From c4243ac9e2713897a63dcdc3a96bf088fdb49866 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 4 Nov 2015 10:03:22 -0800 Subject: armv8/ls2080aqds: Update DDR settings for four chip-select case When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun --- board/freescale/ls2080aqds/ddr.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) (limited to 'board/freescale/ls2080aqds') diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index ae681de35eb..7e67ee03356 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -134,10 +134,18 @@ found: popts->zq_en = 1; if (ddr_freq < 2350) { - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | - DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | - DDR_CDR2_VREF_RANGE_2; + if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) { + /* four chip-selects */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_80ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm); + popts->twot_en = 1; /* enable 2T timing */ + } else { + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | + DDR_CDR1_ODT(DDR_CDR_ODT_60ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) | + DDR_CDR2_VREF_RANGE_2; + } } else { popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_100ohm); -- cgit v1.2.3