From 6d0f6bcf337c5261c08fabe12982178c2c489d76 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Thu, 16 Oct 2008 15:01:15 +0200 Subject: rename CFG_ macros to CONFIG_SYS Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/freescale/mpc8360emds/mpc8360emds.c | 84 +++++++++++++++---------------- board/freescale/mpc8360emds/pci.c | 48 +++++++++--------- 2 files changed, 66 insertions(+), 66 deletions(-) (limited to 'board/freescale/mpc8360emds') diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 5c3b5dbc934..fc0a0e515eb 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -92,8 +92,8 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { int board_early_init_f(void) { - u8 *bcsr = (u8 *)CFG_BCSR; - const immap_t *immr = (immap_t *)CFG_IMMR; + u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* Enable flash write */ bcsr[0xa] &= ~0x04; @@ -124,14 +124,14 @@ void sdram_init(void); phys_size_t initdram(int board_type) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) return -1; /* DDR SDRAM - Main SODIMM */ - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR; #if defined(CONFIG_SPD_EEPROM) msize = spd_sdram(); #else @@ -159,12 +159,12 @@ phys_size_t initdram(int board_type) ************************************************************************/ int fixed_sdram(void) { - volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; u32 msize = 0; u32 ddr_size; u32 ddr_size_log2; - msize = CFG_DDR_SIZE; + msize = CONFIG_SYS_DDR_SIZE; for (ddr_size = msize << 20, ddr_size_log2 = 0; (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) { if (ddr_size & 1) { @@ -173,42 +173,42 @@ int fixed_sdram(void) } im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE); -#if (CFG_DDR_SIZE != 256) +#if (CONFIG_SYS_DDR_SIZE != 256) #warning Currenly any ddr size other than 256 is not supported #endif #ifdef CONFIG_DDR_II - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_mode2 = CFG_DDR_MODE2; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; #else im->ddr.csbnds[0].csbnds = 0x00000007; im->ddr.csbnds[1].csbnds = 0x0008000f; - im->ddr.cs_config[0] = CFG_DDR_CONFIG; - im->ddr.cs_config[1] = CFG_DDR_CONFIG; + im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG; + im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.sdram_cfg = CFG_DDR_CONTROL; + im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; + im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; + im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; #endif udelay(200); im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; return msize; } -#endif /*!CFG_SPD_EEPROM */ +#endif /*!CONFIG_SYS_SPD_EEPROM */ int checkboard(void) { @@ -219,34 +219,34 @@ int checkboard(void) /* * if MPC8360EMDS is soldered with SDRAM */ -#if defined(CFG_BR2_PRELIM) \ - && defined(CFG_OR2_PRELIM) \ - && defined(CFG_LBLAWBAR2_PRELIM) \ - && defined(CFG_LBLAWAR2_PRELIM) +#if defined(CONFIG_SYS_BR2_PRELIM) \ + && defined(CONFIG_SYS_OR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \ + && defined(CONFIG_SYS_LBLAWAR2_PRELIM) /* * Initialize SDRAM memory on the Local Bus. */ void sdram_init(void) { - volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile lbus83xx_t *lbc = &immap->lbus; - uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE; + uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE; /* * Setup SDRAM Base and Option Registers, already done in cpu_init.c */ /*setup mtrpt, lsrt and lbcr for LB bus */ - lbc->lbcr = CFG_LBC_LBCR; - lbc->mrtpr = CFG_LBC_MRTPR; - lbc->lsrt = CFG_LBC_LSRT; + lbc->lbcr = CONFIG_SYS_LBC_LBCR; + lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; + lbc->lsrt = CONFIG_SYS_LBC_LSRT; asm("sync"); /* * Configure the SDRAM controller Machine Mode Register. */ - lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */ - lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */ + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */ asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -254,7 +254,7 @@ void sdram_init(void) /* * We need do 8 times auto refresh operation. */ - lbc->lsdmr = CFG_LBC_LSDMR_2; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; asm("sync"); *sdram_addr = 0xff; /* 1 times */ udelay(100); @@ -274,13 +274,13 @@ void sdram_init(void) udelay(100); /* Mode register write operation */ - lbc->lsdmr = CFG_LBC_LSDMR_4; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; asm("sync"); *(sdram_addr + 0xcc) = 0xff; udelay(100); /* Normal operation */ - lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000; + lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000; asm("sync"); *sdram_addr = 0xff; udelay(100); @@ -294,7 +294,7 @@ void sdram_init(void) #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { - const immap_t *immr = (immap_t *)CFG_IMMR; + const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; ft_cpu_setup(blob, bd); #ifdef CONFIG_PCI diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 4a0d460fadc..935aca26dbb 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -67,7 +67,7 @@ void pci_init_board(void) volatile pcictrl83xx_t *pci_ctrl; volatile pciconf83xx_t *pci_conf; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; @@ -93,7 +93,7 @@ void pci_init_board(void) hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); reg16 = 0xff; pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0), @@ -134,7 +134,7 @@ void pci_init_board(void) u32 val32; u32 dev; - immr = (immap_t *) CFG_IMMR; + immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) & immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; @@ -161,10 +161,10 @@ void pci_init_board(void) /* * Configure PCI Local Access Windows */ - pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR; + pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; - pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR; + pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; /* @@ -172,26 +172,26 @@ void pci_init_board(void) */ /* PCI mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK; + pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI mmio - non-prefetch mem space */ - pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); /* PCI IO space */ - pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; + pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK; + pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ - pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; - pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; + pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK; + pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | @@ -209,31 +209,31 @@ void pci_init_board(void) /* PCI memory prefetch space */ pci_set_region(hose[0].regions + 0, - CFG_PCI_MEM_BASE, - CFG_PCI_MEM_PHYS, - CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); + CONFIG_SYS_PCI_MEM_BASE, + CONFIG_SYS_PCI_MEM_PHYS, + CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH); /* PCI memory space */ pci_set_region(hose[0].regions + 1, - CFG_PCI_MMIO_BASE, - CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM); + CONFIG_SYS_PCI_MMIO_BASE, + CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM); /* PCI IO space */ pci_set_region(hose[0].regions + 2, - CFG_PCI_IO_BASE, - CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO); + CONFIG_SYS_PCI_IO_BASE, + CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); /* System memory space */ pci_set_region(hose[0].regions + 3, - CFG_PCI_SLV_MEM_LOCAL, - CFG_PCI_SLV_MEM_BUS, - CFG_PCI_SLV_MEM_SIZE, + CONFIG_SYS_PCI_SLV_MEM_LOCAL, + CONFIG_SYS_PCI_SLV_MEM_BUS, + CONFIG_SYS_PCI_SLV_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY); hose[0].region_count = 4; pci_setup_indirect(&hose[0], - (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304)); + (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304)); pci_register_hose(hose); -- cgit v1.2.3