From 5ce50206ed24080707946849d3542534fadf8cbf Mon Sep 17 00:00:00 2001
From: Pragnesh Patel
Date: Fri, 29 May 2020 12:14:51 +0530
Subject: riscv: sifive: fu540: enable all cache ways from U-Boot proper

Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
---
 board/sifive/fu540/fu540.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

(limited to 'board/sifive')

diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index fa705dea71d..27ff52f9035 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -15,6 +15,7 @@
 #include <linux/io.h>
 #include <misc.h>
 #include <spl.h>
+#include <asm/arch/cache.h>
 
 /*
  * This define is a value used for error/unknown serial.
@@ -114,7 +115,14 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	/* For now nothing to do here. */
+	int ret;
+
+	/* enable all cache ways */
+	ret = cache_enable_ways();
+	if (ret) {
+		debug("%s: could not enable cache ways\n", __func__);
+		return ret;
+	}
 
 	return 0;
 }
-- 
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