From 79c5c08d7c560aef2d5706501557b7907c2829bb Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 11 Nov 2013 12:09:10 -0500 Subject: omap730p2: Remove board Signed-off-by: Tom Rini --- board/ti/omap730p2/Makefile | 9 - board/ti/omap730p2/README.omap730p2 | 91 ------- board/ti/omap730p2/config.mk | 25 -- board/ti/omap730p2/flash.c | 463 ------------------------------------ board/ti/omap730p2/lowlevel_init.S | 379 ----------------------------- board/ti/omap730p2/omap730p2.c | 255 -------------------- 6 files changed, 1222 deletions(-) delete mode 100644 board/ti/omap730p2/Makefile delete mode 100644 board/ti/omap730p2/README.omap730p2 delete mode 100644 board/ti/omap730p2/config.mk delete mode 100644 board/ti/omap730p2/flash.c delete mode 100644 board/ti/omap730p2/lowlevel_init.S delete mode 100644 board/ti/omap730p2/omap730p2.c (limited to 'board/ti') diff --git a/board/ti/omap730p2/Makefile b/board/ti/omap730p2/Makefile deleted file mode 100644 index 8242f3d69fc..00000000000 --- a/board/ti/omap730p2/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := omap730p2.o flash.o -obj-y += lowlevel_init.o diff --git a/board/ti/omap730p2/README.omap730p2 b/board/ti/omap730p2/README.omap730p2 deleted file mode 100644 index 7c70916120b..00000000000 --- a/board/ti/omap730p2/README.omap730p2 +++ /dev/null @@ -1,91 +0,0 @@ - - u-boot for the TI OMAP730 Perseus2 - - Dave Peverley, MPC-Data Limited - http://www.mpc-data.co.uk - - -Overview : - - As the OMAP730 is similar to the OMAP1610 in many ways, this port was based -on the u-boot port to the OMAP1610 Innovator. Supported features are : - - - Serial terminal support - - Onboard NOR Flash - - Ethernet via the seperate debug board - - Tested on Rev4 and Rev5 boards - - It has also been tested to work correctly when built with a 'standard' GCC -3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain. - - -Hardware Configuration : - - The main dips on the P2 board should be set to 2,3,7 and 9 on with all -others off. On the debug board, dips 1 and 7 should be on with the rest off. -The serial console has been set up to run from the DB9 connector on the -P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit. - - It should be noted that the P2 board has NOR flash that is addressable via -either CS0 or CS3. This mode can be changed via DIP9 on the P2 board. - - -Installing u-boot for the P2 : - - You can simply build u-boot for the Perseus by following the instructions -in the main readme file. The target configuration is "omap730p2_config". -Once u-boot has been built, you should strip the executable so it can be -loaded via CCS (which cant cope with the symbols in the ELF binary) : - $ cp u-boot u-boot.out - $ arm-linux-strip u-boot.out - - The method we've used for installing u-boot the first time on a P2 is -as follows : - -1) Configure TI Code Composer Studio to connect to the P2 board via JTAG - as described in the Users Guide. - -2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU - and run the "init_mmu" GEL script. - -3) Use the "Load Program" option to send the u-boot.out file to the P2 and - run. - - At this point, u-boot should run and you will see the boot menu on your -serial terminal. You can then load the u-boot image to memory : - - # loadb 0x10000000 - - Send the "u-boot.bin" binary via the serial using Kermit. Once loaded -you can self-flash u-boot : - - # protect off 1:0 - # erase 1:0 - # cp.b 0x10000000 0x0 0x20000 - - You should now be able to reset the board and run u-boot from flash. - - -Alternative flash option : - - Sometimes, if you've been silly, you can get the board into a state where -whats in flash has upset the board so much that you can no longer connect -to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode -of the P2 so that you boot from RAM instead of NOR flash. This moves NOR -flash up to 0x0C000000. You can build a special version of u-boot to -utilise this by the following config : - - $ make omap730p2_cs0boot_config - - If you load this up via CCS it will detect flash at its alternate location -and allow you to programme your u-boot image (which, remember must be built -for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work -fine again. - - -Errata : - -1) It's been observed that sometimes the tftp transfer of kernels to the - board can have checksum errors or stall. This appears to be an issue - with the lan91c96.c driver, and can normally be worked around by - resetting the board and trying again. diff --git a/board/ti/omap730p2/config.mk b/board/ti/omap730p2/config.mk deleted file mode 100644 index 86188204ea8..00000000000 --- a/board/ti/omap730p2/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c deleted file mode 100644 index 56f981c47b4..00000000000 --- a/board/ti/omap730p2/flash.c +++ /dev/null @@ -1,463 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - - if (flag) - enable_interrupts(); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag, rc = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = 1; - goto done; - } - } -done: - *addr = (FPW)0x00FF00FF; /* restore read mode */ - if (flag) - enable_interrupts(); - return rc; -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ti/omap730p2/lowlevel_init.S b/board/ti/omap730p2/lowlevel_init.S deleted file mode 100644 index 795c4953726..00000000000 --- a/board/ti/omap730p2/lowlevel_init.S +++ /dev/null @@ -1,379 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003-2004 - * - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited - * (http://www.mpc-data.co.uk) - * - * TODO : Tidy up and change to use system register defines - * from omap730.h where possible. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - /* Save callers address in r11 - r11 must never be modified */ - mov r11, lr - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x1000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Compare physical SDRAM base & current execution location. */ - and r0, pc, #0xF0000000 - /* Compare. */ - cmp r0, #0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bne skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - ldr r0, REG_SDRAM_MRS_LEGACY - ldr r1, SDRAM_MRS_VAL - str r1, [r0] - -skip_sdram: - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS2_CONFIG - ldr r0, REG_TC_EMIFS_CS2_CONFIG - str r1, [r0] /* Chip Select 2 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - - /* 48MHz clock request for UART1 */ - ldr r1, PERSEUS2_CONFIG_BASE - ldrh r0, [r1, #CONFIG_PCC_CONF] - orr r0, r0, #CONF_MOD_UART1_CLK_MODE_R - strh r0, [r1, #CONFIG_PCC_CONF] - - /* Initialize public and private rheas - * - set access factor 2 on both rhea / strobe - * - disable write buffer on strb0, enable write buffer on strb1 - */ - - ldr R0, REG_RHEA_PUB_CTL - ldr R1, REG_RHEA_PRIV_CTL - ldr R2, VAL_RHEA_CTL - strh R2, [R0] - strh R2, [R1] - mov R3, #2 /* disable write buffer on strb0, enable write buffer on strb1 */ - strh R3, [R0, #0x08] /* arm rhea control reg */ - strh R3, [R1, #0x08] - - /* enable IRQ and FIQ */ - - mrs r4, CPSR - bic r4, r4, #IRQ_MASK - bic r4, r4, #FIQ_MASK - msr CPSR, r4 - - /* set TAP CONF to TRI EMULATION */ - - ldr r1, [r0, #CONFIG_MODE2] - bic r1, r1, #0x18 - orr r1, r1, #0x10 - str r1, [r0, #CONFIG_MODE2] - - /* set tdbgen to 1 */ - - ldr r0, PERSEUS2_CONFIG_BASE - ldr r1, [r0, #CONFIG_MODE1] - mov r2, #0x10000 - orr r1, r1, r2 - str r1, [r0, #CONFIG_MODE1] - -#ifdef CONFIG_P2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, r11 - - /* the literal pools origin */ - .ltorg - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_P2_OMAP730 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -REG_SDRAM_MRS_LEGACY: - .word 0xfffecc24 - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* Public and private rhea bridge registers definition */ - -REG_RHEA_PUB_CTL: - .word 0xFFFECA00 - -REG_RHEA_PRIV_CTL: - .word 0xFFFED300 - -/* EMIFF SDRAM Configuration register - - self refresh disable - - auto refresh enabled - - SDRAM type 64 Mb, 16 bits bus 4 banks - - power down enabled - - SDRAM clock disabled - */ -SDRAM_CONFIG_VAL: - .word 0x0C017DF4 - -/* Burst full page length ; cas latency = 3 */ -SDRAM_MRS_VAL: - .word 0x00000037 - -VAL_ARM_CKCTL: - .word 0x6505 -VAL_DPLL1_CTL: - .word 0x3412 - -#ifdef CONFIG_P2_OMAP730 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x0000FFF3 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x00004278 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_ARM_IDLECT1: - .word 0x00000400 -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -VAL_RHEA_CTL: - .word 0xFF22 - -/* Config Register vals */ -PERSEUS2_CONFIG_BASE: - .word 0xFFFE1000 - -.equ CONFIG_PCC_CONF, 0xB4 -.equ CONFIG_MODE1, 0x10 -.equ CONFIG_MODE2, 0x14 -.equ CONF_MOD_UART1_CLK_MODE_R, 0x0A - -/* misc values */ -.equ IRQ_MASK, 0x80 /* IRQ mask value */ -.equ FIQ_MASK, 0x40 /* FIQ mask value */ diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c deleted file mode 100644 index 554019c2070..00000000000 --- a/board/ti/omap730p2/omap730p2.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#if defined(CONFIG_OMAP730) -#include <./configs/omap730.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int test_boot_mode(void); -void spin_up_leds(void); -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define FLASH_ON_CS0 1 -#define FLASH_ON_CS3 0 - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -int test_boot_mode(void) -{ - /* Check for CS0 and CS3 address decode swapping */ - if (*((volatile int *)EMIFS_CONFIG) & 0x00000002) - return(FLASH_ON_CS3); - else - return(FLASH_ON_CS0); -} - -/* Toggle backup LED indication */ -void toggle_backup_led(void) -{ - static int backupLEDState = 0; /* Init variable so that the LED will be ON the first time */ - volatile unsigned int *IOConfReg; - - - IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT); - - if (backupLEDState != 0) { - *IOConfReg &= (0xFFFFEFFF); - backupLEDState = 0; - } else { - *IOConfReg |= (0x00001000); - backupLEDState = 1; - } -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* arch number of OMAP 730 P2 Board - Same as the Innovator! */ - gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - - peripheral_power_enable (); - - /* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */ - toggle_backup_led(); - - /* Hold GSM in reset until needed */ - *((volatile unsigned short *)M_CTL) &= ~1; - - /* - * CSx timings, GPIO Mux ... setup - */ - - /* Flash: CS0 timings setup */ - *((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088; - - /* Ethernet support trough the debug board */ - /* CS1 timings setup */ - *((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3; - *((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000; - - /* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - - return 0; -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ - unsigned int regval; - - regval = *((volatile unsigned int *) EMIFS_CONFIG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_CONFIG) = regval; -} - -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define LAN_RESET_REGISTER 0x0400001c - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (100); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); - -#define ETH_CONTROL_REG 0x0400030b - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (100); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - - /* - * Backup LED Indication - */ - - /* Configure MUXed pin. Mode 6: GPIO_140 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10); - *MuxConfReg &= (0xFFFFFF1F); /* Clear D_MPU_LPG1 */ - *MuxConfReg |= 0x000000C0; /* Set D_MPU_LPG1 to 0x6 */ - - /* Configure GPIO_140 as output */ - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL); - *MuxConfReg &= (0xFFFFEFFF); /* Clear direction (output) for GPIO 140 */ - - /* - * Configure GPIOs for battery charge & feedback - */ - - /* Configure MUXed pin. Mode 6: GPIO_35 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= 0xFFFFFFF1; /* Clear M_CLK_OUT */ - *MuxConfReg |= 0x0000000C; /* Set M_CLK_OUT = 0x6 (GPIOs) */ - - /* Configure MUXed pin. Mode 6: GPIO_72,73,74 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5); - *MuxConfReg &= 0xFFFF1FFF; /* Clear D_DDR */ - *MuxConfReg |= 0x0000C000; /* Set D_DDR = 0x6 (GPIOs) */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL); - *MuxConfReg |= 0x00000100; /* Configure GPIO_72 as input */ - *MuxConfReg &= 0xFFFFFDFF; /* Configure GPIO_73 as output */ - - /* - * Allow battery charge - */ - - MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT); - *MuxConfReg &= (0xFFFFFDFF); /* Clear GPIO_73 pin */ - - /* - * Configure MPU_EXT_NIRQ IO in IO_CONF9 register, - * It is used as the Ethernet controller interrupt - */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9); - *MuxConfReg &= 0x1FFFFFFF; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ - volatile unsigned int *MuxConfReg; - - - /* Set up pins used by UART */ - - /* Start UART clock (48MHz) */ - MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG); - *MuxConfReg &= (0xFFFFFFF7); - *MuxConfReg |= (0x00000008); - - /* Get the UART pin in mode0 */ - MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3); - *MuxConfReg &= (0xFF1FFFFF); - *MuxConfReg &= (0xF1FFFFFF); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif -- cgit v1.2.3 From 39245c8699c68f85a5aaa3153d954370920d09c0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 7 Nov 2013 11:42:57 -0500 Subject: am33xx: Stop modifying certain EMIF4D registers Based on the definitive guide to EMIF configuration[1] certain registers that we have been modifying (and are documented registers) should be left in their reset values rather than modified. This has been tested on AM335x GP EVM and Beaglebone White. [1]: http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips Cc: Enric Balletbo i Serra Cc: Javier Martinez Canillas Cc: Heiko Schocher Cc: Lars Poeschel Signed-off-by: Tom Rini Tested-by: Matt Porter --- arch/arm/cpu/armv7/am33xx/ddr.c | 7 ------- arch/arm/include/asm/arch-am33xx/ddr_defs.h | 31 ++++++----------------------- board/compulab/cm_t335/spl.c | 4 ---- board/isee/igep0033/board.c | 4 ---- board/phytec/pcm051/board.c | 8 -------- board/siemens/dxr2/board.c | 4 ---- board/siemens/pxm2/board.c | 5 ----- board/siemens/rut/board.c | 5 ----- board/ti/am335x/board.c | 17 ---------------- board/ti/ti814x/evm.c | 5 ----- board/ti/ti816x/evm.c | 17 ---------------- 11 files changed, 6 insertions(+), 101 deletions(-) (limited to 'board/ti') diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c74abf..5b0454c3eab 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -89,15 +89,12 @@ void config_ddr_phy(const struct emif_regs *regs, int nr) void config_cmd_ctrl(const struct cmd_control *cmd, int nr) { writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio); - writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff); writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout); writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio); - writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff); writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout); writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio); - writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff); writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout); } @@ -121,10 +118,6 @@ void config_ddr_data(const struct ddr_data *data, int nr) &(ddr_data_reg[nr]+i)->dt0fwsratio0); writel(data->datawrsratio0, &(ddr_data_reg[nr]+i)->dt0wrsratio0); - writel(data->datauserank0delay, - &(ddr_data_reg[nr]+i)->dt0rdelays0); - writel(data->datadldiff0, - &(ddr_data_reg[nr]+i)->dt0dldiff0); } } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index f56d1e07cc8..2278358ab20 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -18,7 +18,6 @@ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) #define VTP_CTRL_START_EN (0x1) -#define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 #define PHY_EN_DYN_PWRDN (0x1 << 20) @@ -29,7 +28,6 @@ #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a -#define MT47H128M16RT25E_DLL_LOCK_DIFF 0x0 #define MT47H128M16RT25E_RATIO 0x80 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 #define MT47H128M16RT25E_RD_DQS 0x12 @@ -38,7 +36,6 @@ #define MT47H128M16RT25E_PHY_GATELVL 0x00 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 -#define MT47H128M16RT25E_PHY_RANK0_DELAY 0x1 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B /* Micron MT41J128M16JT-125 */ @@ -49,7 +46,6 @@ #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 #define MT41J128MJT125_EMIF_SDREF 0x0000093B #define MT41J128MJT125_ZQ_CFG 0x50074BE4 -#define MT41J128MJT125_DLL_LOCK_DIFF 0x1 #define MT41J128MJT125_RATIO 0x40 #define MT41J128MJT125_INVERT_CLKOUT 0x1 #define MT41J128MJT125_RD_DQS 0x3B @@ -72,7 +68,6 @@ #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 -#define MT41J256M8HX15E_DLL_LOCK_DIFF 0x1 #define MT41J256M8HX15E_RATIO 0x40 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 #define MT41J256M8HX15E_RD_DQS 0x3B @@ -89,7 +84,6 @@ #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 -#define MT41K256M16HA125E_DLL_LOCK_DIFF 0x1 #define MT41K256M16HA125E_RATIO 0x80 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 #define MT41K256M16HA125E_RD_DQS 0x38 @@ -106,7 +100,6 @@ #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 -#define MT41J512M8RH125_DLL_LOCK_DIFF 0x1 #define MT41J512M8RH125_RATIO 0x80 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 #define MT41J512M8RH125_RD_DQS 0x3B @@ -123,7 +116,6 @@ #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 -#define K4B2G1646EBIH9_DLL_LOCK_DIFF 0x1 #define K4B2G1646EBIH9_RATIO 0x80 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 #define K4B2G1646EBIH9_RD_DQS 0x35 @@ -155,18 +147,15 @@ void config_ddr_phy(const struct emif_regs *regs, int nr); struct ddr_cmd_regs { unsigned int resv0[7]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv1[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv1[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv2[8]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv3[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv3[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv4[8]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv5[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv5[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv6[3]; }; @@ -203,24 +192,21 @@ struct ddr_regs { unsigned int cm0configclk; /* offset 0x010 */ unsigned int resv1[2]; unsigned int cm0csratio; /* offset 0x01C */ - unsigned int resv2[2]; - unsigned int cm0dldiff; /* offset 0x028 */ + unsigned int resv2[3]; unsigned int cm0iclkout; /* offset 0x02C */ unsigned int resv3[4]; unsigned int cm1config; /* offset 0x040 */ unsigned int cm1configclk; /* offset 0x044 */ unsigned int resv4[2]; unsigned int cm1csratio; /* offset 0x050 */ - unsigned int resv5[2]; - unsigned int cm1dldiff; /* offset 0x05C */ + unsigned int resv5[3]; unsigned int cm1iclkout; /* offset 0x060 */ unsigned int resv6[4]; unsigned int cm2config; /* offset 0x074 */ unsigned int cm2configclk; /* offset 0x078 */ unsigned int resv7[2]; unsigned int cm2csratio; /* offset 0x084 */ - unsigned int resv8[2]; - unsigned int cm2dldiff; /* offset 0x090 */ + unsigned int resv8[3]; unsigned int cm2iclkout; /* offset 0x094 */ unsigned int resv9[12]; unsigned int dt0rdsratio0; /* offset 0x0C8 */ @@ -249,17 +235,14 @@ struct cmd_control { unsigned long cmd0csratio; unsigned long cmd0csforce; unsigned long cmd0csdelay; - unsigned long cmd0dldiff; unsigned long cmd0iclkout; unsigned long cmd1csratio; unsigned long cmd1csforce; unsigned long cmd1csdelay; - unsigned long cmd1dldiff; unsigned long cmd1iclkout; unsigned long cmd2csratio; unsigned long cmd2csforce; unsigned long cmd2csdelay; - unsigned long cmd2dldiff; unsigned long cmd2iclkout; }; @@ -273,8 +256,6 @@ struct ddr_data { unsigned long datagiratio0; unsigned long datafwsratio0; unsigned long datawrsratio0; - unsigned long datauserank0delay; - unsigned long datadldiff0; }; /** diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c index b62e58a7ebc..99f3a869bbc 100644 --- a/board/compulab/cm_t335/spl.c +++ b/board/compulab/cm_t335/spl.c @@ -25,20 +25,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J128MJT125_WR_DQS, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 0b8356dc47b..6a8ca2b4c39 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -35,20 +35,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = K4B2G1646EBIH9_WR_DQS, .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE, .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = K4B2G1646EBIH9_RATIO, - .cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd1csratio = K4B2G1646EBIH9_RATIO, - .cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, .cmd2csratio = K4B2G1646EBIH9_RATIO, - .cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF, .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT, }; diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index bd1bb70939d..6a27e56d11a 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -55,20 +55,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J256M8HX15E_WR_DQS, .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE, .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J256M8HX15E_RATIO, - .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd1csratio = MT41J256M8HX15E_RATIO, - .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT, .cmd2csratio = MT41J256M8HX15E_RATIO, - .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF, .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT, }; @@ -94,20 +90,16 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 1773ab77d00..3a5e11dc816 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -140,13 +140,9 @@ struct emif_regs dxr2_ddr3_emif_reg_data = { }; struct ddr_data dxr2_ddr3_data = { - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control dxr2_ddr3_cmd_ctrl_data = { - .cmd0dldiff = 0, - .cmd1dldiff = 0, - .cmd2dldiff = 0, }; /* pass values from eeprom */ dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index 094b4d6d368..0a25b4b40cc 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -58,19 +58,14 @@ struct ddr_data pxm2_ddr3_data = { .datawdsratio0 = 0, .datafwsratio0 = 0x8020080, .datawrsratio0 = 0x4010040, - .datauserank0delay = 1, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control pxm2_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x80, - .cmd0dldiff = 0, .cmd0iclkout = 0, .cmd1csratio = 0x80, - .cmd1dldiff = 0, .cmd1iclkout = 0, .cmd2csratio = 0x80, - .cmd2dldiff = 0, .cmd2iclkout = 0, }; diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 0cf17ef5b6a..77592dbba88 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -63,19 +63,14 @@ struct ddr_data rut_ddr3_data = { .datawdsratio0 = 0x85, .datafwsratio0 = 0x100, .datawrsratio0 = 0xc1, - .datauserank0delay = 1, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x40, - .cmd0dldiff = 0, .cmd0iclkout = 1, .cmd1csratio = 0x40, - .cmd1dldiff = 0, .cmd1iclkout = 1, .cmd2csratio = 0x40, - .cmd2dldiff = 0, .cmd2iclkout = 1, }; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57fedab340a..1459fae253f 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -107,21 +107,16 @@ static const struct ddr_data ddr2_data = { (MT47H128M16RT25E_PHY_WR_DATA<<20) | (MT47H128M16RT25E_PHY_WR_DATA<<10) | (MT47H128M16RT25E_PHY_WR_DATA<<0)), - .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr2_cmd_ctrl_data = { .cmd0csratio = MT47H128M16RT25E_RATIO, - .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd1csratio = MT47H128M16RT25E_RATIO, - .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, .cmd2csratio = MT47H128M16RT25E_RATIO, - .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, }; @@ -139,7 +134,6 @@ static const struct ddr_data ddr3_data = { .datawdsratio0 = MT41J128MJT125_WR_DQS, .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_beagleblack_data = { @@ -147,7 +141,6 @@ static const struct ddr_data ddr3_beagleblack_data = { .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct ddr_data ddr3_evm_data = { @@ -155,48 +148,38 @@ static const struct ddr_data ddr3_evm_data = { .datawdsratio0 = MT41J512M8RH125_WR_DQS, .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, - .datadldiff0 = PHY_DLL_LOCK_DIFF, }; static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41J128MJT125_RATIO, - .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd1csratio = MT41J128MJT125_RATIO, - .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, .cmd2csratio = MT41J128MJT125_RATIO, - .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, }; static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, - .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd1csratio = MT41K256M16HA125E_RATIO, - .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, .cmd2csratio = MT41K256M16HA125E_RATIO, - .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; static const struct cmd_control ddr3_evm_cmd_ctrl_data = { .cmd0csratio = MT41J512M8RH125_RATIO, - .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd1csratio = MT41J512M8RH125_RATIO, - .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, .cmd2csratio = MT41J512M8RH125_RATIO, - .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, }; diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index e406326a11e..0b76a779059 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -33,15 +33,12 @@ static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; #ifdef CONFIG_SPL_BUILD static const struct cmd_control evm_ddr2_cctrl_data = { .cmd0csratio = 0x80, - .cmd0dldiff = 0x04, .cmd0iclkout = 0x00, .cmd1csratio = 0x80, - .cmd1dldiff = 0x04, .cmd1iclkout = 0x00, .cmd2csratio = 0x80, - .cmd2dldiff = 0x04, .cmd2iclkout = 0x00, }; @@ -77,8 +74,6 @@ static const struct ddr_data evm_ddr2_data = { .datagiratio0 = ((0<<10) | (0<<0)), .datafwsratio0 = ((0x90<<10) | (0x90<<0)), .datawrsratio0 = ((0x50<<10) | (0x50<<0)), - .datauserank0delay = 1, - .datadldiff0 = 0x4, }; void set_uart_mux_conf(void) diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 74d35e936d5..a53859e52e4 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -59,21 +59,16 @@ static struct ddr_data ddr2_data = { .datagiratio0 = ((0x0<<10) | (0x0<<0)), .datafwsratio0 = ((0x13A<<10) | (0x13A<<0)), .datawrsratio0 = ((0x8A<<10) | (0x8A<<0)), - .datauserank0delay = 0x1, - .datadldiff0 = 0x0, /* depend on cpu rev, set later */ }; static struct cmd_control ddr2_ctrl = { .cmd0csratio = 0x80, - .cmd0dldiff = 0x04, /* reset value is 0x4 */ .cmd0iclkout = 0x00, .cmd1csratio = 0x80, - .cmd1dldiff = 0x04, /* reset value is 0x4 */ .cmd1iclkout = 0x00, .cmd2csratio = 0x80, - .cmd2dldiff = 0x04, /* reset value is 0x4 */ .cmd2iclkout = 0x00, }; @@ -150,21 +145,16 @@ static struct ddr_data ddr3_data = { .datagiratio0 = ((0x20<<10) | 0x20<<0), .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), - .datauserank0delay = 0x1, - .datadldiff0 = 0x0, /* depend on cpu rev, set later */ }; static const struct cmd_control ddr3_ctrl = { .cmd0csratio = 0x100, - .cmd0dldiff = 0x004, /* reset value is 0x4 */ .cmd0iclkout = 0x001, .cmd1csratio = 0x100, - .cmd1dldiff = 0x004, /* reset value is 0x4 */ .cmd1iclkout = 0x001, .cmd2csratio = 0x100, - .cmd2dldiff = 0x004, /* reset value is 0x4 */ .cmd2iclkout = 0x001, }; @@ -198,11 +188,6 @@ void sdram_init(void) config_dmm(&evm_lisa_map_regs); #ifdef CONFIG_TI816X_EVM_DDR2 - ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - if (CONFIG_TI816X_USE_EMIF0) { ddr2_emif0_regs.emif_ddr_phy_ctlr_1 = (get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B); @@ -217,8 +202,6 @@ void sdram_init(void) #endif #ifdef CONFIG_TI816X_EVM_DDR3 - ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF); - if (CONFIG_TI816X_USE_EMIF0) config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0); -- cgit v1.2.3 From afdc6321316ca5a6bfc7b916328f45ab4720007e Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 11 Nov 2013 16:56:42 +0200 Subject: ARM: omap5_uevm: Add SATA support The uevm has a SATA port. Inititialize the SATA controller. Signed-off-by: Roger Quadros --- board/ti/omap5_uevm/evm.c | 7 +++++++ include/configs/omap5_uevm.h | 10 ++++++++++ 2 files changed, 17 insertions(+) (limited to 'board/ti') diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c index bb3a699cf72..af854dac1ad 100644 --- a/board/ti/omap5_uevm/evm.c +++ b/board/ti/omap5_uevm/evm.c @@ -20,6 +20,7 @@ #include #include #include +#include #define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000) #define DIE_ID_REG_OFFSET 0x200 @@ -67,6 +68,12 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + omap_sata_init(); + return 0; +} + int board_eth_init(bd_t *bis) { return 0; diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 4d3a8002982..2f128b8a690 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -69,4 +69,14 @@ /* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + #endif /* __CONFIG_OMAP5_EVM_H */ -- cgit v1.2.3 From 21914ee62a62501354a84f234ad73e7a92c29ae1 Mon Sep 17 00:00:00 2001 From: Roger Quadros Date: Mon, 11 Nov 2013 16:56:44 +0200 Subject: ARM: dra7_evm: Add SATA support The evm has a SATA port. Enable SATA configuration and inititialize the SATA controller. Signed-off-by: Roger Quadros --- board/ti/dra7xx/evm.c | 7 +++++++ include/configs/dra7xx_evm.h | 11 +++++++++++ 2 files changed, 18 insertions(+) (limited to 'board/ti') diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 9657c75f235..9ae88c57a41 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "mux_data.h" @@ -77,6 +78,12 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + omap_sata_init(); + return 0; +} + /** * @brief misc_init_r - Configure EVM board specific configurations * such as power configurations, ethernet initialization as phase2 of diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 8a69c7d0a6c..48b47cbd0b5 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -83,4 +83,15 @@ #define CONFIG_OMAP_USB_PHY #define CONFIG_OMAP_USB2PHY2_HOST +/* SATA */ +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_CMD_SCSI +#define CONFIG_LIBATA +#define CONFIG_SCSI_AHCI +#define CONFIG_SCSI_AHCI_PLAT +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ + CONFIG_SYS_SCSI_MAX_LUN) + #endif /* __CONFIG_DRA7XX_EVM_H */ -- cgit v1.2.3 From 675cc77a3ae45e8b0ec17128563264d4a509f628 Mon Sep 17 00:00:00 2001 From: Hardik Patel Date: Wed, 27 Nov 2013 21:16:21 +0530 Subject: pandaboard: 1/1] ARM:OMAP4+: panda-es: Support Rev B3 Elpida DDR2 RAM Signed-off-by: Hardik Patel --- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 4 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 4 ++ board/ti/panda/panda.c | 60 +++++++++++++++++++++++++++++ 3 files changed, 66 insertions(+), 2 deletions(-) (limited to 'board/ti') diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index 811e7764c1b..6903696e1b9 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -32,7 +32,7 @@ #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { +const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .sdram_config_init = 0x80000eb9, .sdram_config = 0x80001ab9, .ref_ctrl = 0x0000030c, @@ -46,7 +46,7 @@ static const struct emif_regs emif_regs_elpida_200_mhz_2cs = { .emif_ddr_phy_ctlr_1 = 0x049ff808 }; -static const struct emif_regs emif_regs_elpida_380_mhz_1cs = { +const struct emif_regs emif_regs_elpida_380_mhz_1cs = { .sdram_config_init = 0x80000eb1, .sdram_config = 0x80001ab1, .ref_ctrl = 0x000005cd, diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index 39c531632e0..ce8217f6979 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -16,6 +16,10 @@ DECLARE_GLOBAL_DATA_PTR; +extern const struct emif_regs emif_regs_elpida_200_mhz_2cs; +extern const struct emif_regs emif_regs_elpida_380_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_1cs; +extern const struct emif_regs emif_regs_elpida_400_mhz_2cs; struct omap_sysinfo { char *board_string; }; diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c index c104024b100..cda09a91259 100644 --- a/board/ti/panda/panda.c +++ b/board/ti/panda/panda.c @@ -122,6 +122,66 @@ int get_board_revision(void) return board_id; } +/** + * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES + * + * + * Detect if we are running on B3 version of ES panda board, + * This can be done by reading the level of GPIO 171 and checking the + * processor revisions. + * GPIO171: 1 => Panda ES Rev B3 + * + * Return : return 1 if Panda ES Rev B3 , else return 0 + */ +u8 is_panda_es_rev_b3(void) +{ + int processor_rev = omap_revision(); + int ret = 0; + + if ((processor_rev >= OMAP4460_ES1_0 && + processor_rev <= OMAP4460_ES1_1)) { + + /* Setup the mux for the common board ID pins (gpio 171) */ + writew((IEN | M3), + (*ctrl)->control_padconf_core_base + UNIPRO_TX0); + + /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */ + ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO); + } + return ret; +} + +#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +/* + * emif_get_reg_dump() - emif_get_reg_dump strong function + * + * @emif_nr - emif base + * @regs - reg dump of timing values + * + * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c + */ +void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) +{ + u32 omap4_rev = omap_revision(); + + /* Same devices and geometry on both EMIFs */ + if (omap4_rev == OMAP4430_ES1_0) + *regs = &emif_regs_elpida_380_mhz_1cs; + else if (omap4_rev == OMAP4430_ES2_0) + *regs = &emif_regs_elpida_200_mhz_2cs; + else if (omap4_rev == OMAP4430_ES2_3) + *regs = &emif_regs_elpida_400_mhz_1cs; + else if (omap4_rev < OMAP4470_ES1_0) { + if(is_panda_es_rev_b3()) + *regs = &emif_regs_elpida_400_mhz_1cs; + else + *regs = &emif_regs_elpida_400_mhz_2cs; + } + else + *regs = &emif_regs_elpida_400_mhz_1cs; +} +#endif + /** * @brief misc_init_r - Configure Panda board specific configurations * such as power configurations, ethernet initialization as phase2 of -- cgit v1.2.3 From 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 Mon Sep 17 00:00:00 2001 From: Albert ARIBAUD Date: Thu, 7 Nov 2013 14:21:46 +0100 Subject: arm: keep all sections in ELF file Current LDS files /DISCARD/ a lot of sections when linking ELF files, causing diagnostic tools such as readelf or objdump to produce partial output. Keep all section at link stage, filter only at objcopy time so that .bin remains minimal. Signed-off-by: Albert ARIBAUD Reviewed-by: Benoît Thébaudeau --- Makefile | 2 +- arch/arm/config.mk | 3 +++ arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds | 16 +++++++++------- arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds | 16 +++++++++------- arch/arm/cpu/ixp/u-boot.lds | 15 +++++++++------ arch/arm/cpu/u-boot-spl.lds | 15 +++++++++------ arch/arm/cpu/u-boot.lds | 18 ++++++++++-------- board/actux1/u-boot.lds | 15 +++++++++------ board/actux2/u-boot.lds | 15 +++++++++------ board/actux3/u-boot.lds | 15 +++++++++------ board/dvlhost/u-boot.lds | 15 +++++++++------ board/freescale/mx31ads/u-boot.lds | 18 +++++++++--------- board/ti/am335x/u-boot.lds | 15 +++++++++------ board/vpac270/u-boot-spl.lds | 18 +++++++++--------- 14 files changed, 113 insertions(+), 83 deletions(-) (limited to 'board/ti') diff --git a/Makefile b/Makefile index 1f499c5ec87..af0ad5744e2 100644 --- a/Makefile +++ b/Makefile @@ -393,7 +393,7 @@ $(obj)u-boot.hex: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ $(obj)u-boot.srec: $(obj)u-boot - $(OBJCOPY) -O srec $< $@ + $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ diff --git a/arch/arm/config.mk b/arch/arm/config.mk index bdabcf407e2..fd3e5fb661d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -103,3 +103,6 @@ ALL-y += checkarmreloc # such usage by requiring word relocations. PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations) endif + +# limit ourselves to the sections we want in the .bin. +OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds index 40bcc3132f8..80fb9bdc8d1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds index 4927736b9bb..76b499d87f1 100644 --- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds +++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds @@ -51,11 +51,13 @@ SECTIONS _end = .; - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index c8d2e126ae4..676ae2c4f9a 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -79,10 +79,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 36cc54a292e..4880d0f78ac 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -51,12 +51,15 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } #if defined(CONFIG_SPL_MAX_SIZE) diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 23bf0306550..9463a33dcb3 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -91,12 +91,14 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - /DISCARD/ : { *(.ARM.exidx*) } - /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } + .dynsym _end : { *(.dynsym) } + .hash : { *(.hash) } + .got.plt : { *(.got.plt) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds index a656fa99d16..12e018f316a 100644 --- a/board/actux1/u-boot.lds +++ b/board/actux1/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds index 7a1717640ab..300273bf7aa 100644 --- a/board/actux2/u-boot.lds +++ b/board/actux2/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds index aadfdd2f570..9c97c533dcc 100644 --- a/board/actux3/u-boot.lds +++ b/board/actux3/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds index 40c9c8038bb..057d94b62a6 100644 --- a/board/dvlhost/u-boot.lds +++ b/board/dvlhost/u-boot.lds @@ -87,10 +87,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds index 3acc4ca5483..6cfca2dab63 100644 --- a/board/freescale/mx31ads/u-boot.lds +++ b/board/freescale/mx31ads/u-boot.lds @@ -90,13 +90,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds index a173f620ef9..9f96a43898c 100644 --- a/board/ti/am335x/u-boot.lds +++ b/board/ti/am335x/u-boot.lds @@ -108,10 +108,13 @@ SECTIONS KEEP(*(.__bss_end)); } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds index 7eac4975ba1..08c78b3dbb0 100644 --- a/board/vpac270/u-boot-spl.lds +++ b/board/vpac270/u-boot-spl.lds @@ -62,13 +62,13 @@ SECTIONS __bss_end = .; } - /DISCARD/ : { *(.bss*) } - /DISCARD/ : { *(.dynsym) } - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynsym*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.hash*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } + .dynsym _end : { *(.dynsym) } + .dynbss : { *(.dynbss) } + .dynstr : { *(.dynstr*) } + .dynamic : { *(.dynamic*) } + .hash : { *(.hash*) } + .plt : { *(.plt*) } + .interp : { *(.interp*) } + .gnu : { *(.gnu*) } + .ARM.exidx : { *(.ARM.exidx*) } } -- cgit v1.2.3