From ab5cda9f88c3eaf9cf599adc3a3375906c4ed904 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Mon, 7 Jul 2008 18:02:08 -0500 Subject: Remove LBC_CACHE_BASE from 8544 DS The 8544 DS doesn't have any cacheable Local Bus memories set up. By mapping space for some anyway, we were allowing speculative loads into unmapped space, which would cause an exception (annoying, even if ultimately harmless). Removing LBC_CACHE_BASE, and using LBC_NONCACHE_BASE for the LBC LAW solves the problem. Signed-off-by: Andy Fleming --- board/freescale/mpc8544ds/law.c | 2 +- board/freescale/mpc8544ds/tlb.c | 12 ++---------- 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c index a82dedea3b4..54cf36bd456 100644 --- a/board/freescale/mpc8544ds/law.c +++ b/board/freescale/mpc8544ds/law.c @@ -30,7 +30,7 @@ struct law_entry law_table[] = { SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_CACHE_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1), SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2), diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index 61fc60986c4..40e049951bc 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -79,21 +79,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), -#ifdef CFG_LBC_CACHE_BASE /* - * TLB 5: 64M Cacheable, non-guarded - */ - SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), -#endif - /* - * TLB 6: 64M Non-cacheable, guarded + * TLB 5: 64M Non-cacheable, guarded * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF */ SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_64M, 1), }; int num_tlb_entries = ARRAY_SIZE(tlb_table); -- cgit v1.2.3 From 0ec436d2f95076d9e46ae594db6e9b1d8732840d Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 11 Jul 2008 15:33:04 -0400 Subject: sbc8560: properly set cs0_bnds for 512MB The sbc8560 board ships with 512MB of memory installed, but the current cs0_bnds is hard coded for 256MB. Set the value based on CFG_SDRAM_SIZE. Signed-off-by: Paul Gortmaker --- board/sbc8560/sbc8560.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'board') diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 2946ca10557..3b6b541cff6 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -421,7 +421,11 @@ long int fixed_sdram (void) #ifndef CFG_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR); +#if (CFG_SDRAM_SIZE == 512) + ddr->cs0_bnds = 0x0000000f; +#else ddr->cs0_bnds = 0x00000007; +#endif ddr->cs1_bnds = 0x0010001f; ddr->cs2_bnds = 0x00000000; ddr->cs3_bnds = 0x00000000; -- cgit v1.2.3 From d04e76edf92f7f89696989e8702b97e020455af3 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 11 Jul 2008 15:33:06 -0400 Subject: sbc8560: add in ft_board_setup() Add in for the sbc8560, the ft_board_setup() routine, based on what is in use for the Freescale MPC8560ADS board. Signed-off-by: Paul Gortmaker --- board/sbc8560/sbc8560.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'board') diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 3b6b541cff6..d9e598c2995 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include long int fixed_sdram (void); @@ -456,3 +458,29 @@ long int fixed_sdram (void) return CFG_SDRAM_SIZE * 1024 * 1024; } #endif /* !defined(CONFIG_SPD_EEPROM) */ + + +#if defined(CONFIG_OF_BOARD_SETUP) +void +ft_board_setup(void *blob, bd_t *bd) +{ + int node, tmp[2]; +#ifdef CONFIG_PCI + const char *path; +#endif + + ft_cpu_setup(blob, bd); + + node = fdt_path_offset(blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI + path = fdt_getprop(blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose.last_busno - hose.first_busno; + do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif -- cgit v1.2.3 From e5852787f0c3c442a276262f13d91ca450605ac0 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 14 Jul 2008 14:07:01 -0500 Subject: MPC8544DS: Report board id, board version and fpga version. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/mpc8544ds.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 8c4b04097e5..c39ce117231 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -49,7 +49,10 @@ int checkboard (void) if ((uint)&gur->porpllsr != 0xe00e0000) { printf("immap size error %lx\n",(ulong)&gur->porpllsr); } - printf ("Board: MPC8544DS\n"); + printf ("Board: MPC8544DS, System ID: 0x%02x, " + "System Version: 0x%02x, FPGA Version: 0x%02x\n", + in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER), + in8(PIXIS_BASE + PIXIS_PVER)); lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ -- cgit v1.2.3 From 630d9bfcb5f6d3a43f251901a6b480994dcb6ea3 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 14 Jul 2008 14:07:03 -0500 Subject: MPC8544DS: Add ATI Video card support Add support for using a PCIe ATI Video card on PCIe2. Signed-off-by: Kumar Gala --- board/freescale/mpc8544ds/u-boot.lds | 1 + include/configs/MPC8544DS.h | 24 ++++++++++++++++++++++-- 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'board') diff --git a/board/freescale/mpc8544ds/u-boot.lds b/board/freescale/mpc8544ds/u-boot.lds index 785a00616bd..c66c69fcbe4 100644 --- a/board/freescale/mpc8544ds/u-boot.lds +++ b/board/freescale/mpc8544ds/u-boot.lds @@ -71,6 +71,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) + drivers/bios_emulator/atibios.o (.text) *(.text) *(.fixup) *(.got1) diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 2a12c051b82..8f4fbf1c7a8 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -224,7 +224,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port - controlled on board with jumper J8 * open - index 2 @@ -312,6 +312,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if defined(CONFIG_PCI) +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CFG_PCIE2_IO_PHYS + +/*PCI video card used*/ +/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CFG_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -380,7 +400,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #if CFG_MONITOR_BASE > 0xfff80000 #define CFG_ENV_ADDR 0xfff80000 #else -#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x70000) #endif #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ -- cgit v1.2.3