From 5d267ec67901d9e5fd6e535eec84bd9176501403 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 11 Apr 2017 15:02:13 +0800 Subject: arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033 Since commit ce412b7, RGMII TX clock internal delay is not enabled for AR8033 unconditionally. On LS1021ATWR board, the third port eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to be enabled. This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX clock internal delay for AR8033 on the third port. Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/ls1021atwr/ls1021atwr.c | 1 + 1 file changed, 1 insertion(+) (limited to 'board') diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d96fd774d36..ff32d5cb28e 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; num++; #endif if (!num) { -- cgit v1.2.3 From 99fe76d02313473f97892eab3e6fa564f1acfea4 Mon Sep 17 00:00:00 2001 From: Santan Kumar Date: Thu, 13 Apr 2017 15:31:09 +0530 Subject: armv8: ls2080ardb: Add phy number for serdes1 protocol 0x4b Signed-off-by: Santan Kumar Signed-off-by: Priyanka Jain Reviewed-by: York Sun --- board/freescale/ls2080ardb/eth_ls2080rdb.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'board') diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 799799c251c..ba584c8a768 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -61,6 +61,13 @@ int board_eth_init(bd_t *bis) wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3); wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4); + break; + case 0x4B: + wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3); + wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4); + break; default: printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n", -- cgit v1.2.3 From e1b09290596ddc4604253a54a4fc313fc11770c9 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 14 Apr 2017 14:48:21 +0800 Subject: armv8: ls1043aqds: Integrate FSL PPA The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/ls1043aqds/ls1043aqds.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 2df63e468d8..8fbd3a74bde 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -325,6 +326,10 @@ int board_init(void) config_serdes_mux(); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + return 0; } -- cgit v1.2.3 From 2ac2e20ef839935b4e8e8723165e73f40922d1e1 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 14 Apr 2017 14:48:23 +0800 Subject: armv8: ls1046aqds: Integrate FSL PPA The PPA is a EL3 firmware, which support PSCI, hotplug, power-management features etc. Signed-off-by: Hou Zhiqiang Reviewed-by: York Sun --- board/freescale/ls1046aqds/ls1046aqds.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 58ce75acf6c..057a11daa85 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -267,6 +268,10 @@ int board_init(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + #ifdef CONFIG_SECURE_BOOT /* * In case of Secure Boot, the IBR configures the SMMU -- cgit v1.2.3 From fedebf0d08a7aa152f8f27de1d40eb036557c11b Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 20 Apr 2017 16:04:23 -0700 Subject: armv8: layerscape: Fix DDR size calcuation for SPL build Commit 088454cd dropped return value from initram(), setting gd->ram_size directly. Three boards were missed for SPL boot. Signed-off-by: York Sun --- board/freescale/ls1043aqds/ddr.c | 4 +++- board/freescale/ls1046aqds/ddr.c | 4 +++- board/freescale/ls1046ardb/ddr.c | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 2643f5bf4aa..b22d3784dce 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -113,7 +113,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index d37af34a9c9..5fcfa0f7018 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -97,7 +97,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index a16f7bc83a9..ae5046cab69 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -101,7 +101,9 @@ int fsl_initdram(void) phys_size_t dram_size; #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) - return fsl_ddr_sdram_size(); + gd->ram_size = fsl_ddr_sdram_size(); + + return 0; #else puts("Initializing DDR....using SPD\n"); -- cgit v1.2.3