From 4057bddaa230de0d77ec6357fd556ea192ab1412 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:15 +0300 Subject: board: lx2160aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/eth_lx2160aqds.c | 12 +++++++++++- board/freescale/lx2160a/lx2160a.c | 5 +++++ 2 files changed, 16 insertions(+), 1 deletion(-) (limited to 'board') diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 0e928ebd868..3b7830343d1 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -25,6 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_ETH #define EMI_NONE 0 #define EMI1 1 /* Mdio Bus 1 */ #define EMI2 2 /* Mdio Bus 2 */ @@ -439,9 +440,11 @@ static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, } #endif +#endif /* !CONFIG_DM_ETH */ int board_eth_init(bd_t *bis) { +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) struct memac_mdio_info mdio_info; struct memac_mdio_controller *regs; @@ -564,6 +567,7 @@ int board_eth_init(bd_t *bis) cpu_eth_init(bis); #endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */ #ifdef CONFIG_PHY_AQUANTIA /* @@ -577,7 +581,12 @@ int board_eth_init(bd_t *bis) gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; #endif + +#ifdef CONFIG_DM_ETH + return 0; +#else return pci_eth_init(bis); +#endif } #if defined(CONFIG_RESET_PHY_R) @@ -589,6 +598,7 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) { @@ -837,4 +847,4 @@ int fdt_fixup_board_phy(void *fdt) return ret; } #endif // CONFIG_FSL_MC_ENET - +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 0d94107def4..4be9882994e 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -584,6 +584,9 @@ int board_init(void) sec_init(); #endif +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif return 0; } @@ -629,7 +632,9 @@ void fdt_fixup_board_enet(void *fdt) if (get_mc_boot_status() == 0 && (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); +#ifndef CONFIG_DM_ETH fdt_fixup_board_phy(fdt); +#endif } else { fdt_status_fail(fdt, offset); } -- cgit v1.2.3 From f49613f4aa19c41051b9a5436898d7a2e459b3e4 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 27 Apr 2020 15:21:16 +0300 Subject: board: lx2160aqds: implement board_fit_config_name_match In case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS for the current SERDES protocol configuration. Signed-off-by: Ioana Ciornei Reviewed-by: Razvan Ionut Cirjan Reviewed-by: Priyanka Jain --- board/freescale/lx2160a/eth_lx2160aqds.c | 109 +++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) (limited to 'board') diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 3b7830343d1..d90b5c3e3a2 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -848,3 +848,112 @@ int fdt_fixup_board_phy(void *fdt) } #endif // CONFIG_FSL_MC_ENET #endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 3, true}, + {1, 7, true}, + {1, 19, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 11, true}, + + /* Serdes block #3 */ + {3, 2, false}, + {3, 3, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; + u32 srds_s1, srds_s2, srds_s3; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK; + srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2) || + !protocol_supported(3, srds_s3)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + get_str_protocol(3, srds_s3, srds_s3_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s", + srds_s1_str, srds_s2_str, srds_s3_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif -- cgit v1.2.3 From b62526282ab2e505148d8c962dfb888f155ec7e9 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:48 +0300 Subject: arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Signed-off-by: Priyanka Jain --- arch/arm/dts/Makefile | 2 + arch/arm/dts/fsl-ls1088a-qds-21-x.dts | 16 +++ arch/arm/dts/fsl-ls1088a-qds-29-x.dts | 16 +++ arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 30 +++++ arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 18 +++ arch/arm/dts/fsl-ls1088a-qds.dts | 123 +------------------- arch/arm/dts/fsl-ls1088a-qds.dtsi | 186 +++++++++++++++++++++++++++++++ board/freescale/ls1088a/eth_ls1088aqds.c | 87 +++++++++++++++ 8 files changed, 358 insertions(+), 120 deletions(-) create mode 100644 arch/arm/dts/fsl-ls1088a-qds-21-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-29-x.dts create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi create mode 100644 arch/arm/dts/fsl-ls1088a-qds.dtsi (limited to 'board') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f28fc371c38..d6f799635d8 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -379,6 +379,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2088a-rdb-qspi.dtb \ fsl-ls1088a-rdb.dtb \ fsl-ls1088a-qds.dtb \ + fsl-ls1088a-qds-21-x.dtb \ + fsl-ls1088a-qds-29-x.dtb \ fsl-ls1028a-rdb.dtb \ fsl-ls1028a-qds-duart.dtb \ fsl-ls1028a-qds-lpuart.dtb \ diff --git a/arch/arm/dts/fsl-ls1088a-qds-21-x.dts b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts new file mode 100644 index 00000000000..a8779645119 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-21-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 21.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-21.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 21-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-29-x.dts b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts new file mode 100644 index 00000000000..29c4ec59fe5 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-29-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES protocol 29.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls1088a-qds-sd1-29.dtsi" + +/ { + model = "NXP Layerscape 1088a QDS Board (DTS 29-x)"; + compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi new file mode 100644 index 00000000000..e0a6c04835b --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-id"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi new file mode 100644 index 00000000000..65e95300ab5 --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1088AQDS device tree source for SERDES block #1 - protocol 29 (0x1d) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls1088a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dts b/arch/arm/dts/fsl-ls1088a-qds.dts index 4f37a28992d..8e64e713aaa 100644 --- a/arch/arm/dts/fsl-ls1088a-qds.dts +++ b/arch/arm/dts/fsl-ls1088a-qds.dts @@ -1,132 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * NXP ls1088a QDS board device tree source + * NXP ls1088a QDS default board device tree source * - * Copyright 2017 NXP + * Copyright 2020 NXP */ /dts-v1/; -#include "fsl-ls1088a.dtsi" +#include "fsl-ls1088a-qds.dtsi" / { model = "NXP Layerscape 1088a QDS Board"; compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; - aliases { - spi0 = &qspi; - spi1 = &dspi; - }; -}; - -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - - i2c-mux@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x3>; - - rtc@51 { - compatible = "pcf2127-rtc"; - reg = <0x51>; - }; - }; - }; -}; - -&ifc { - #address-cells = <2>; - #size-cells = <1>; - /* NOR, NAND Flashes and FPGA on board */ - ranges = <0 0 0x5 0x80000000 0x08000000 - 2 0 0x5 0x30000000 0x00010000 - 3 0 0x5 0x20000000 0x00010000>; - status = "okay"; - - nor@0,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "cfi-flash"; - reg = <0x0 0x0 0x8000000>; - bank-width = <2>; - device-width = <1>; - }; - - nand@2,0 { - compatible = "fsl,ifc-nand"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x1 0x0 0x10000>; - }; - - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus", "fsl,ls1088aqds-fpga", - "fsl,fpga-qixis"; - reg = <0x2 0x0 0x0000100>; - bank-width = <1>; - device-width = <1>; - ranges = <0 2 0 0x100>; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; - - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <1>; - }; - - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3500000>; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs512s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; - - s25fs512s1: flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <1>; - }; -}; - -&sata { - status = "okay"; }; diff --git a/arch/arm/dts/fsl-ls1088a-qds.dtsi b/arch/arm/dts/fsl-ls1088a-qds.dtsi new file mode 100644 index 00000000000..a7d0edcf0aa --- /dev/null +++ b/arch/arm/dts/fsl-ls1088a-qds.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP ls1088a QDS common board device tree source + * + * Copyright 2017-2020 NXP + */ + +#include "fsl-ls1088a.dtsi" + +/ { + aliases { + spi0 = &qspi; + spi1 = &dspi; + }; +}; + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + u-boot,dm-pre-reloc; + + fpga@66 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-mfd"; + reg = <0x66>; + + mux-mdio@54 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mdio-mux-i2creg"; + reg = <0x54>; + #mux-control-cells = <1>; + mux-reg-masks = <0x54 0xe0>; // reg 0x54, bits 7:5 + mdio-parent-bus = <&emdio1>; + + mdio@00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + mdio@20 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x20>; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + emdio1_slot1: mdio@40 { /* I/O Slot #1 */ + reg = <0x40>; + device-name = "emdio1_slot1"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emdio1_slot3: mdio@60 { /* I/O Slot #3 */ + reg = <0x60>; + device-name = "emdio1_slot3"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + rtc@51 { + compatible = "pcf2127-rtc"; + reg = <0x51>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0 0 0x5 0x80000000 0x08000000 + 2 0 0x5 0x30000000 0x00010000 + 3 0 0x5 0x20000000 0x00010000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + nand@2,0 { + compatible = "fsl,ifc-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1 0x0 0x10000>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus", "fsl,ls1088aqds-fpga", + "fsl,fpga-qixis"; + reg = <0x2 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 2 0 0x100>; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <1000000>; /* input clock */ + }; + + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <1>; + }; + + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3500000>; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs512s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + + s25fs512s1: flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <1>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 54ef75347f6..c0bcf712992 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -742,3 +742,90 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 21, true}, + {1, 29, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + char expected_dts[100]; + char srds_s1_str[2]; + u32 srds_s1, cfg; + + cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & + FSL_CHASSIS3_SRDS1_PRTCL_MASK; + cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT; + srds_s1 = serdes_get_number(FSL_SRDS_1, cfg); + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + + sprintf(expected_dts, "fsl-ls1088a-qds-%s-x", srds_s1_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif -- cgit v1.2.3 From 791ec1b9e0adaf00750256497c567b74dde3b176 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Fri, 15 May 2020 09:56:49 +0300 Subject: board: ls1088aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- board/freescale/ls1088a/eth_ls1088aqds.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'board') diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index c0bcf712992..7456f67f3d6 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -24,6 +24,7 @@ #include "ls1088a_qixis.h" +#ifndef CONFIG_DM_ETH #ifdef CONFIG_FSL_MC_ENET #define SFP_TX 0 @@ -735,6 +736,7 @@ int board_eth_init(bd_t *bis) error = pci_eth_init(bis); return error; } +#endif // !CONFIG_DM_ETH #if defined(CONFIG_RESET_PHY_R) void reset_phy(void) -- cgit v1.2.3 From 8cbef912ee8e73fccf2543428e73ecd25d386dba Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:35 +0300 Subject: board: ls2080aqds: transition to DM_ETH In case CONFIG_DM_ETH is enabled, no hardcoding is necessary for DPAA2 Ethernet devices. Compile out any unnecessary setup when CONFIG_DM_ETH is activated. Also, force the PCI devices to be enumerated at probe time. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- board/freescale/ls2080aqds/eth.c | 15 ++++++++++++--- board/freescale/ls2080aqds/ls2080aqds.c | 4 ++++ 2 files changed, 16 insertions(+), 3 deletions(-) (limited to 'board') diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index bbb70a859a1..2b1b106b073 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -24,6 +24,8 @@ #define MC_BOOT_ENV_VAR "mcinitcmd" +#ifndef CONFIG_DM_ETH + #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks. * Bank 1 -> Lanes A, B, C, D, E, F, G, H @@ -889,10 +891,11 @@ void ls2080a_handle_phy_interface_xsgmii(int i) } } #endif +#endif // !CONFIG_DM_ETH int board_eth_init(bd_t *bis) { - int error; +#ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & @@ -906,6 +909,7 @@ int board_eth_init(bd_t *bis) struct memac_mdio_info *memac_mdio1_info; unsigned int i; char *env_hwconfig; + int error; env_hwconfig = env_get("hwconfig"); @@ -970,8 +974,13 @@ int board_eth_init(bd_t *bis) sgmii_configure_repeater(2); } #endif - error = pci_eth_init(bis); - return error; +#endif // !CONFIG_DM_ETH + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif } #if defined(CONFIG_RESET_PHY_R) diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 4034bdee284..1c91c5b7f05 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -251,6 +251,10 @@ int board_init(void) ppa_init(); #endif +#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) + pci_init(); +#endif + return 0; } -- cgit v1.2.3 From 020ed9c666748b103e0740622ca4128a2bd40f29 Mon Sep 17 00:00:00 2001 From: Ioana Ciornei Date: Mon, 18 May 2020 14:48:36 +0300 Subject: arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei Reviewed-by: Priyanka Jain --- arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-ls2080a-qds-42-x.dts | 16 ++++++ arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 48 ++++++++++++++++ arch/arm/dts/fsl-ls2080a-qds.dts | 72 +----------------------- arch/arm/dts/fsl-ls2080a-qds.dtsi | 77 +++++++++++++++++++++++++ board/freescale/ls2080aqds/eth.c | 97 ++++++++++++++++++++++++++++++++ 6 files changed, 241 insertions(+), 70 deletions(-) create mode 100644 arch/arm/dts/fsl-ls2080a-qds-42-x.dts create mode 100644 arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi create mode 100644 arch/arm/dts/fsl-ls2080a-qds.dtsi (limited to 'board') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d6f799635d8..2404eaa5ee0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ fsl-ls2088a-rdb-qspi.dtb \ diff --git a/arch/arm/dts/fsl-ls2080a-qds-42-x.dts b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts new file mode 100644 index 00000000000..bd46c395d45 --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-42-x.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080AQDS device tree source for SERDES protocol 42.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-ls2080a-qds-sd1-42.dtsi" + +/ { + model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)"; + compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi new file mode 100644 index 00000000000..ccbb5de1eae --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a) + * + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac2 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac3 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac4 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac5 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac6 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac7 { + status = "okay"; + phy-connection-type = "xfi"; +}; + +&dpmac8 { + status = "okay"; + phy-connection-type = "xfi"; +}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dts b/arch/arm/dts/fsl-ls2080a-qds.dts index f91a48d9fdd..a1196f92928 100644 --- a/arch/arm/dts/fsl-ls2080a-qds.dts +++ b/arch/arm/dts/fsl-ls2080a-qds.dts @@ -1,13 +1,13 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Freescale ls2080a QDS board device tree source + * Freescale ls2080a QDS defaul board device tree source * * Copyright 2013-2015 Freescale Semiconductor, Inc. */ /dts-v1/; -#include "fsl-ls2080a.dtsi" +#include "fsl-ls2080a-qds.dtsi" / { model = "Freescale Layerscape 2080a QDS Board"; @@ -18,71 +18,3 @@ spi1 = &dspi; }; }; - -&i2c0 { - status = "okay"; - pca9547@77 { - compatible = "nxp,pca9547"; - reg = <0x77>; - #address-cells = <1>; - #size-cells = <0>; - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x00>; - rtc@68 { - compatible = "dallas,ds3232"; - reg = <0x68>; - }; - }; - }; -}; - -&dspi { - bus-num = <0>; - status = "okay"; - - dflash0: n25q128a { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <0>; - }; - dflash1: sst25wf040b { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <1>; - }; - dflash2: en25s64 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <3000000>; - spi-cpol; - spi-cpha; - reg = <2>; - }; -}; - -&qspi { - status = "okay"; - - s25fs256s0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; - reg = <0>; - }; -}; - -&sata { - status = "okay"; -}; diff --git a/arch/arm/dts/fsl-ls2080a-qds.dtsi b/arch/arm/dts/fsl-ls2080a-qds.dtsi new file mode 100644 index 00000000000..cb7851f2cc0 --- /dev/null +++ b/arch/arm/dts/fsl-ls2080a-qds.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Freescale ls2080a QDS common device tree source + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 NXP + */ + +#include "fsl-ls2080a.dtsi" + +&i2c0 { + status = "okay"; + pca9547@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00>; + rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; + }; + }; +}; + +&dspi { + bus-num = <0>; + status = "okay"; + + dflash0: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + dflash1: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; +}; + +&qspi { + status = "okay"; + + s25fs256s0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&sata { + status = "okay"; +}; diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 2b1b106b073..0d6eec377f8 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -989,3 +989,100 @@ void reset_phy(void) mc_env_boot(); } #endif /* CONFIG_RESET_PHY_R */ + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 42, true}, + + /* Serdes block #2 */ + {2, 65, false}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + printf("expected_dts %s\n", expected_dts); + sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + printf("this is not!\n"); + return -1; +} + +#endif -- cgit v1.2.3