From 3c41728d80f7a6178dd4ec91c28347d9768ab200 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 9 Jul 2020 15:26:06 +0800 Subject: imx8m: Refactor the OPTEE memory removal Current codes assume the OPTEE address is at the end of first DRAM bank. Adjust the process to allow OPTEE in the middle of first bank. When OPTEE memory is removed from first bank, it may split the first bank to two banks, adjust the MMU table for the split case, Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge i.MX8MP evk to default to avoid issue. Signed-off-by: Ye Li Signed-off-by: Silvano di Ninno Tested-by: Silvano di Ninno Signed-off-by: Peng Fan --- configs/imx8mp_evk_defconfig | 1 - 1 file changed, 1 deletion(-) (limited to 'configs') diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index dcfc336634d..f49116c9c55 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -16,7 +16,6 @@ CONFIG_TARGET_IMX8MP_EVK=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_NR_DRAM_BANKS=2 CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_FIT=y -- cgit v1.2.3 From 26a6ed1b2e0d07c263d19bd48706a7be05f8c18d Mon Sep 17 00:00:00 2001 From: Niel Fourie Date: Tue, 19 May 2020 14:01:43 +0200 Subject: arm: imx6q: pcm058: Convert pcm058 to use DM with DTs Convert pcm058 support to use device trees and the driver model. Add rudimentary boot scripts to the environment, expand README. Signed-off-by: Niel Fourie Cc: Stefano Babic --- arch/arm/dts/Makefile | 1 + .../arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi | 42 +++ arch/arm/mach-imx/mx6/Kconfig | 4 + board/phytec/pcm058/README | 51 ++++ board/phytec/pcm058/pcm058.c | 325 ++------------------- configs/pcm058_defconfig | 42 ++- include/configs/pcm058.h | 69 ++--- 7 files changed, 178 insertions(+), 356 deletions(-) create mode 100644 arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d839cb49b33..cee10f533f5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -678,6 +678,7 @@ dtb-y += \ imx6q-nitrogen6x.dtb \ imx6q-novena.dtb \ imx6q-pico.dtb \ + imx6q-phytec-mira-rdk-nand.dtb \ imx6q-sabreauto.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ diff --git a/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi new file mode 100644 index 00000000000..8555be16966 --- /dev/null +++ b/arch/arm/dts/imx6q-phytec-mira-rdk-nand-u-boot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 + * Niel Fourie, DENX Software Engineering, lusus@denx.de. + */ +#include "imx6qdl-u-boot.dtsi" + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio6 { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&ecspi1 { + u-boot,dm-spl; +}; + +&pinctrl_ecspi1 { + u-boot,dm-spl; +}; + +&m25p80 { + u-boot,dm-spl; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index fa6e1112e62..fdee0d4f641 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -511,6 +511,10 @@ config TARGET_PCM058 bool "Phytec PCM058 i.MX6 Quad" select BOARD_LATE_INIT select SUPPORT_SPL + select MX6Q + select DM + select OF_CONTROL + imply CMD_DM config TARGET_PFLA02 bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad" diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README index 33271356451..02be0994fcd 100644 --- a/board/phytec/pcm058/README +++ b/board/phytec/pcm058/README @@ -33,3 +33,54 @@ is present, then the RBL tries to load SPL from the SD Card, if not, RBL loads from SPI-NOR. The SPL tries then to load from the same device where SPL was loaded (SD or SPI). Booting from NAND is not supported. + +Flashing U-Boot onto an SD card +------------------------------- + +After a successful build, the generated SPL and U-boot binaries can be copied +to an SD card. Adjust the SD card device as necessary: + +$ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1 + +This is equivalent to separately copying the SPL and U-boot using: + +$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 +$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 + +The default bootscripts expect a kernel fit-image file named "fitImage" in the +first partition and Linux ext4 rootfs in the second partition. + +Flashing U-boot to the SPI Flash, for booting Linux from NAND +------------------------------------------------------------- + +The SD card created above can also be used to install the SPL and U-boot into +the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot. + +Then, clear the SPI flash: + +=> sf probe +=> sf erase 0x0 0x1000000 + +Load the SPL from raw MMC into memory and copy to the SPI. The SPL is maximum +392*512-byte blocks in size therefore 0x188 blocks, totaling 0x31000 bytes: + +=> mmc read ${loadaddr} 0x2 0x188 +=> sf write ${loadaddr} 0x400 0x31000 + +Load the U-boot binary into memory and copy to the SPI. U-boot should fit into +640KiB, so 0x500 512-byte blocks, totalling 0xA0000 bytes: + +=> mmc read ${loadaddr} 0x18a 0x500 +=> sf write ${loadaddr} 0x40000 0xA0000 + +The default NAND bootscripts expect a single MTD partition named "rootfs", +which in turn contains the UBI volumes "fit" (which contains the kernel fit- +image) and "root" (which contains a ubifs root filesystem). + +The "bootm_size" variable in the environment +-------------------------------------------- + +By default, U-boot relocates the device tree towards the upper end of the RAM, +which kernels using CONFIG_HIGHMEM=y may not be able to access during early +boot. With the bootm_size variable set to 0x30000000, U-boot relocates the +device tree to below this address instead. diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c index 096425c5dfe..79c666588f4 100644 --- a/board/phytec/pcm058/pcm058.c +++ b/board/phytec/pcm058/pcm058.c @@ -12,60 +12,14 @@ #include #include #include -#include -#include -#include #include #include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - -#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - -#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) - -#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14) -#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31) -#define USER_LED IMX_GPIO_NR(1, 4) #define IMX6Q_DRIVE_STRENGTH 0x30 int dram_init(void) @@ -74,229 +28,16 @@ int dram_init(void) return 0; } -void board_turn_off_led(void) -{ - gpio_direction_output(USER_LED, 0); -} - -static iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -static iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -#ifdef CONFIG_CMD_NAND -/* NAND */ -static iomux_v3_cfg_t const nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), -}; -#endif - -static struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -static struct fsl_esdhc_cfg usdhc_cfg[] = { - {.esdhc_base = USDHC1_BASE_ADDR, - .max_bus_width = 4}, -#ifndef CONFIG_CMD_NAND - {USDHC4_BASE_ADDR}, -#endif -}; - -static iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ -}; - -#if !defined(CONFIG_CMD_NAND) && !defined(CONFIG_SPL_BUILD) -static iomux_v3_cfg_t const usdhc4_pads[] = { - MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; -#endif - int board_mmc_get_env_dev(int devno) { return devno - 1; } -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret = 0; - - switch (cfg->esdhc_base) { - case USDHC1_BASE_ADDR: - ret = !gpio_get_value(USDHC1_CD_GPIO); - break; - case USDHC4_BASE_ADDR: - ret = 1; /* eMMC/uSDHC4 is always present */ - break; - } - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ -#ifndef CONFIG_SPL_BUILD - int ret; - int i; - - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { - switch (i) { - case 0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - break; -#ifndef CONFIG_CMD_NAND - case 1: - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); - break; -#endif - default: - printf("Warning: you configured more USDHC controllers" - "(%d) then supported by the board (%d)\n", - i + 1, CONFIG_SYS_FSL_USDHC_NUM); - return -EINVAL; - } - - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); - if (ret) - return ret; - } - - return 0; -#else - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned reg = readl(&psrc->sbmr1) >> 11; - /* - * Upon reading BOOT_CFG register the following map is done: - * Bit 11 and 12 of BOOT_CFG register can determine the current - * mmc port - * 0x1 SD1 - * 0x2 SD2 - * 0x3 SD4 - */ - - switch (reg & 0x3) { - case 0x0: - imx_iomux_v3_setup_multiple_pads( - usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); - gpio_direction_input(USDHC1_CD_GPIO); - usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - usdhc_cfg[0].max_bus_width = 4; - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; - break; - } - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -#endif -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); -} - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - gpio_direction_output(ENET_PHY_RESET_GPIO, 0); - mdelay(10); - gpio_set_value(ENET_PHY_RESET_GPIO, 1); - mdelay(30); -} - -static void setup_spi(void) -{ - gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0"); - gpio_direction_output(IMX_GPIO_NR(3, 19), 1); - - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - - enable_spi_clk(true, 0); -} - #ifdef CONFIG_CMD_NAND static void setup_gpmi_nand(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); @@ -325,48 +66,17 @@ static void setup_gpmi_nand(void) } #endif -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - if (bus != 0 || (cs != 0)) - return -EINVAL; - - return IMX_GPIO_NR(3, 19); -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - - return cpu_eth_init(bis); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - - return 0; -} - int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); -#endif - -#ifdef CONFIG_MXC_SPI - setup_spi(); -#endif - #ifdef CONFIG_CMD_NAND setup_gpmi_nand(); #endif return 0; } - #ifdef CONFIG_CMD_BMODE /* * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 @@ -535,11 +245,6 @@ void board_boot_order(u32 *spl_boot_list) void board_init_f(ulong dummy) { -#ifdef CONFIG_CMD_NAND - /* Enable NAND */ - setup_gpmi_nand(); -#endif - /* setup clock gating */ ccgr_init(); @@ -549,23 +254,33 @@ void board_init_f(ulong dummy) /* setup AXI */ gpr_init(); - board_early_init_f(); - /* setup GP timer */ timer_init(); - setup_spi(); - - /* UART clocks enabled and gd valid - init serial console */ - preloader_console_init(); - /* DDR initialization */ spl_dram_init(); /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); - /* load/boot image from boot device */ - board_init_r(NULL, 0); + /* Enable device tree and early DM support*/ + spl_early_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +/* + * Manually probe the SPI bus devices, as this does not happen when the + * SPI Flash is probed, which then fails to find the bus. + */ +void spl_board_init(void) +{ + struct udevice *udev; + int ret = uclass_get_device_by_name(UCLASS_SPI, "spi@2008000", &udev); + + if (ret) { + printf("SPI bus probe failed, err = %d\n", ret); + }; } #endif diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 64947e8355d..c491cbf9a0c 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -7,9 +7,12 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 +CONFIG_MX6_OCRAM_256KB=y CONFIG_TARGET_PCM058=y CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 @@ -26,10 +29,11 @@ CONFIG_BOOTDELAY=3 # CONFIG_USE_BOOTCOMMAND is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a CONFIG_SPL_DMA=y CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_SPL_YMODEM_SUPPORT=y @@ -38,33 +42,51 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:16m(uboot),1m(env),-(rootfs)" +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:-(rootfs)" CONFIG_CMD_UBI=y # CONFIG_SPL_PARTITION_UUIDS is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-phytec-mira-rdk-nand" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y +CONFIG_NAND_MXS_DT=y +CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=20000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +# CONFIG_PINCONF_RECURSIVE is not set +CONFIG_SPL_PINCTRL=y +CONFIG_SPL_PINCONF=y +# CONFIG_SPL_PINCONF_RECURSIVE is not set +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_SERIAL=y +CONFIG_MXC_UART=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y -CONFIG_OF_LIBFDT=y +# CONFIG_SPL_WDT is not set diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index 7c27ebb811d..4f03699117b 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -3,7 +3,6 @@ * Copyright (C) Stefano Babic */ - #ifndef __PCM058_CONFIG_H #define __PCM058_CONFIG_H @@ -13,48 +12,13 @@ #include "mx6_common.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -/* Early setup */ - - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#ifndef CONFIG_SPL_BUILD /* Enable NAND support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -68,10 +32,33 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - /* Environment organization */ - +#define ENV_MMC \ + "mmcdev=0\0" \ + "mmcpart=2\0" \ + "fitpart=1\0" \ + "mmcrootfstype=ext4\0" \ + "fitname=fitImage\0" \ + "mmcloadfit=load mmc ${mmcdev}:${fitpart} ${loadaddr} ${fitname}\0" \ + "mmcargs=setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcpart} " \ + "rootfstype=${mmcrootfstype} ${optargs}\0" \ + "mmcboot=run mmcloadfit;run mmcargs;bootm ${loadaddr}\0" + +#define ENV_NAND \ + "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ + "nandroot=ubi0:root ubi.mtd=rootfs\0" \ + "nandrootfstype=ubifs\0" \ + "nandargs=setenv bootargs root=${nandroot} " \ + "rootfstype=${nandrootfstype} ${mtdparts} ${optargs}\0" \ + "nandloadfit=ubi part rootfs;ubi readvol ${loadaddr} fit\0" \ + "nandboot=run nandloadfit;run nandargs;bootm ${loadaddr}\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x30000000\0" \ + "optargs=rw rootwait\0" \ + ENV_MMC \ + ENV_NAND + +#define CONFIG_BOOTCOMMAND "run mmcboot;run nandboot" #endif -- cgit v1.2.3 From 08556f829f48225388c2bb6d7b9d02ab60cc9e56 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 8 Jul 2020 07:39:59 +0200 Subject: imx6: aristainetos: sync defconfig with 2020.10 as patch gpio: search for gpio label if gpio is not found through bank name is now in mainline, but functionality is disabled, we need to enable CONFIG_DM_GPIO_LOOKUP_LABEL for the aristainetos boards. Signed-off-by: Heiko Schocher --- configs/aristainetos2_defconfig | 3 ++- configs/aristainetos2b_defconfig | 3 ++- configs/aristainetos2bcsl_defconfig | 3 ++- configs/aristainetos2c_defconfig | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) (limited to 'configs') diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 01990bd9704..7e902127e1a 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -10,6 +10,7 @@ CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set # CONFIG_CMD_NANDBCB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -53,7 +54,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y @@ -61,6 +61,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index 318b81e331c..3c605c2121b 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -51,7 +52,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y @@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig index 0ff67a44cbe..6cd095fb852 100644 --- a/configs/aristainetos2bcsl_defconfig +++ b/configs/aristainetos2bcsl_defconfig @@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -51,7 +52,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y @@ -59,6 +59,7 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index ffd4360159f..4f6b9b94019 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -51,7 +52,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y @@ -62,6 +62,7 @@ CONFIG_APBH_DMA=y CONFIG_APBH_DMA_BURST=y CONFIG_APBH_DMA_BURST8=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_LED=y -- cgit v1.2.3 From 949feef062f21d19ecc76b48fdeb8f3099e16df6 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 10 Jul 2020 09:49:32 +0200 Subject: arm: Add extra boot device (UART) to run Ymodem u-boot.img boot on XEA (imx28) This commit enables imx28 based XEA board's u-boot.sb (SPL) to download u-boot proper (u-boot.img) via Ymodem protocol. This is extremely useful in the recovery scenario where u-boot.sb is downloaded via uuu utility to SDRAM [*], and then one can upload u-boot proper via serial console to fully debrick the device. Note - debricking procedure of imx28 devices: - NXP's original USB based tools (like mxsldr or uuu) expect single u-boot.sb which is a relic of the old U-Boot (~2013) without SPL and U-Boot proper distinction. [*] On Host: ------------ cat << EOF > imx28_xea.lst uuu_version 1.3.0 SDPS: boot -f /srv/tftp/xea/u-boot.sb SDPU: done EOF Please start picocom: sudo picocom -b 115200 -s "sz -vv" /dev/ttyUSB1 sudo ./uuu/uuu -V imx28_xea.lst On the U-boot console one shall see: Trying to boot from UART CCC Then please press CTRL+A, S and type u-boot.img Signed-off-by: Lukasz Majewski Acked-by: Peng Fan --- board/liebherr/xea/xea.c | 1 + configs/imx28_xea_defconfig | 1 + 2 files changed, 2 insertions(+) (limited to 'configs') diff --git a/board/liebherr/xea/xea.c b/board/liebherr/xea/xea.c index 8159f3a2d9e..4062c6fb82b 100644 --- a/board/liebherr/xea/xea.c +++ b/board/liebherr/xea/xea.c @@ -116,6 +116,7 @@ void board_boot_order(u32 *spl_boot_list) { spl_boot_list[0] = BOOT_DEVICE_MMC1; spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; } int spl_start_uboot(void) diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index b879de5042d..38f3fa6871c 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_MMC_TINY=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_SPL=y CONFIG_CMD_ASKENV=y -- cgit v1.2.3 From 45032991194239991726cafe4dfa6a72ddf45956 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 13 Jul 2020 11:59:36 -0300 Subject: imx6: Remove unneeded CONFIG_DM_MDIO As explained in the CONFIG_DM_MDIO text inside drivers/net/Kconfig: "Useful in particular for systems that support DM_ETH and have a stand-alone MDIO hardware block shared by multiple Ethernet interfaces." i.MX6 has a single FEC instance, so there is no need to select CONFIG_DM_MDIO. Remove it from the i.MX6 defconfig files. Signed-off-by: Fabio Estevam --- configs/apalis_imx6_defconfig | 1 - configs/colibri_imx6_defconfig | 1 - configs/dh_imx6_defconfig | 1 - configs/mx6sabreauto_defconfig | 1 - configs/mx6sabresd_defconfig | 1 - 5 files changed, 5 deletions(-) (limited to 'configs') diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 34d939a0e91..e162f0a5e85 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -74,7 +74,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 11cd1da26e2..ffa773b581c 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -73,7 +73,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index d91ff77a4a6..e643ade2e6c 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -77,7 +77,6 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 56fe307e638..106c967652b 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -76,7 +76,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 24bc8630f10..f88c629fbfa 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -83,7 +83,6 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y -- cgit v1.2.3 From ab8b4e818cbc3846672c13b12f1d75daccfac519 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 16 Jul 2020 15:11:18 +0200 Subject: mx6memcal: fix build Commit 4503299 has a side effect on this board, and build is broken. Adjust mx6memcal_defconfig to build it again. Signed-off-by: Stefano Babic --- configs/mx6memcal_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'configs') diff --git a/configs/mx6memcal_defconfig b/configs/mx6memcal_defconfig index 57e44a14bac..01a0fff6e0f 100644 --- a/configs/mx6memcal_defconfig +++ b/configs/mx6memcal_defconfig @@ -39,6 +39,7 @@ CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_CMD_CACHE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_NET is not set +CONFIG_DM=y # CONFIG_MMC is not set CONFIG_FSL_USDHC=y CONFIG_USB=y @@ -47,4 +48,5 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y -CONFIG_REGEX=y +CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set -- cgit v1.2.3