From 536c5c7a331d417d416dc04271b6f146db41cab0 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:26:59 -0700 Subject: imx: imx6sx-sdb: Enable DM QSPI driver To support DM QSPI driver - Add spi0 and spi1 alias for qspi1 and qspi2. - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI/QSPI relavent configurations - Remove iomux settings of qspi2 in board codes which is not needed for DM driver. - Add sf default settings. So running "sf probe" can detect the flash Signed-off-by: Ye Li --- configs/mx6sxsabresd_defconfig | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'configs') diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index dcac6f435c4..4c235c1af05 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -15,6 +15,7 @@ CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_PCI=y @@ -37,8 +38,14 @@ CONFIG_DM_GPIO=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_FSL_QSPI=y CONFIG_PHYLIB=y CONFIG_MII=y CONFIG_PCI=y -- cgit v1.2.3 From 0925ee21851287d48279bb43e4a0876b2005a5f2 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:27:00 -0700 Subject: imx: imx6sx-sabreauto: convert to use DM QSPI driver To support DM QSPI driver: - Add -u-boot.dtsi to modify n25q256a@0 and n25q256a@1 compatible string to "spi-flash" and add "num-cs" property. - Enable DM SPI and DM SPI FLASH configurations - Remove iomux settings of qspi1 in board codes which is not needed for DM driver. Signed-off-by: Ye Li --- arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi | 16 ++++++++++ arch/arm/dts/imx6sx-sabreauto.dts | 40 +++++++++++++++++++++++++ board/freescale/mx6sxsabreauto/mx6sxsabreauto.c | 24 --------------- configs/mx6sxsabreauto_defconfig | 2 ++ 4 files changed, 58 insertions(+), 24 deletions(-) create mode 100644 arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi (limited to 'configs') diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi new file mode 100644 index 00000000000..f5c68d707c3 --- /dev/null +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi1 { + num-cs = <2>; + + flash0: n25q256a@0 { + compatible = "spi-flash"; + }; + + flash1: n25q256a@1 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts index a4c2627f974..9643d1fe064 100644 --- a/arch/arm/dts/imx6sx-sabreauto.dts +++ b/arch/arm/dts/imx6sx-sabreauto.dts @@ -96,6 +96,29 @@ }; }; +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + &iomuxc { imx6x-sabreauto { pinctrl_i2c2_1: i2c2grp-1 { @@ -112,6 +135,23 @@ >; }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 975af2c8956..6e606dae3e9 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -218,32 +218,8 @@ int board_early_init_f(void) } #ifdef CONFIG_FSL_QSPI - -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - MX6_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_SCLK__QSPI1_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_SCLK__QSPI1_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); - /* Set the clock */ enable_qspi_clk(0); diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 359b9b6b563..0e15bd6ae88 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -36,6 +36,8 @@ CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_STMICRO=y -- cgit v1.2.3 From 3b82335015cc695b760c90f904ea85bae53c0597 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 19:30:53 -0700 Subject: imx: imx7d-sdb: Add DM QSPI support On iMX7D SabreSD board, the QSPI has pins conflict with EPDC (default). To use QSPI, users have to rework the board (de-populate R388-R391, R396-R399 populate R392-R395, R299, R300). So we add new DTS file and new defconfig dedicated for QSPI. Other changes to support the DM QSPI: - Add QSPI node and alias spi0. - Modify spi4 (spi-gpio) node and add alias spi5 for it to avoid req conflict - Add EPDC node in imx7d.dtsi and disable it in imx7d-sdb-qspi.dts to align with kernel and also present the conflict. - Add -u-boot.dtsi to modify compatible string of mx25l51245g@0 to "spi-flash" - Remove iomux settings of qspi in board codes which is not needed for DM driver. Signed-off-by: Ye Li --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi | 10 ++++ arch/arm/dts/imx7d-sdb-qspi.dts | 44 ++++++++++++++++ arch/arm/dts/imx7d-sdb.dts | 6 ++- arch/arm/dts/imx7d.dtsi | 12 +++++ arch/arm/dts/imx7s.dtsi | 22 ++++++-- board/freescale/mx7dsabresd/mx7dsabresd.c | 16 ------ configs/mx7dsabresd_qspi_defconfig | 83 +++++++++++++++++++++++++++++++ include/configs/mx7dsabresd.h | 4 +- 9 files changed, 175 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi create mode 100644 arch/arm/dts/imx7d-sdb-qspi.dts create mode 100644 configs/mx7dsabresd_qspi_defconfig (limited to 'configs') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ebfa2272627..68e5c4f66c4 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -445,7 +445,8 @@ dtb-$(CONFIG_MX6UL) += \ dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ - imx7d-sdb.dtb + imx7d-sdb.dtb \ + imx7d-sdb-qspi.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb diff --git a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi new file mode 100644 index 00000000000..2ce6961096f --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&qspi1 { + flash0: mx25l51245g@0 { + compatible = "spi-flash"; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts new file mode 100644 index 00000000000..9bb4c743c14 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-qspi.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include "imx7d-sdb.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + ddrsmp=<0>; + + flash0: mx25l51245g@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25l51245g"; + spi-max-frequency = <29000000>; + /* take off one dummy cycle */ + spi-nor,ddr-quad-read-dummy = <5>; + reg = <0>; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index bafcc791668..76aa69a35b3 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -11,11 +11,15 @@ model = "Freescale i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + aliases { + spi5 = &soft_spi; + }; + memory { reg = <0x80000000 0x80000000>; }; - spi4 { + soft_spi: soft-spi { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index f6dee41a05d..30b058934bf 100644 --- a/arch/arm/dts/imx7d.dtsi +++ b/arch/arm/dts/imx7d.dtsi @@ -86,6 +86,18 @@ }; }; +&aips2 { + epdc: epdc@306f0000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x306f0000 0x10000>; + clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; + clock-names = "epdc_axi", "epdc_pix"; + epdc-ram = <&gpr 0x4 30>; + status = "disabled"; + }; +}; + &aips3 { usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 4d42335c0de..5067b9f7e7c 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -82,10 +82,11 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; + spi0 = &qspi1; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; }; cpus { @@ -1072,6 +1073,19 @@ status = "disabled"; }; + qspi1: qspi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + sdma: sdma@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 90e2d1a92ae..191b59a6d43 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -36,9 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ PAD_CTL_DSE_3P3V_49OHM) -#define QSPI_PAD_CTRL \ - (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) - #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) #define SPI_PAD_CTRL \ @@ -278,21 +275,8 @@ int board_phy_config(struct phy_device *phydev) #endif #ifdef CONFIG_FSL_QSPI -static iomux_v3_cfg_t const quadspi_pads[] = { - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), -}; - int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); - /* Set the clock */ set_clk_qspi(); diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig new file mode 100644 index 00000000000..a79880482f8 --- /dev/null +++ b/configs/mx7dsabresd_qspi_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +# CONFIG_CMD_BMODE is not set +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_GPIO=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_ESDHC=y +CONFIG_FSL_QSPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SOFT_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 11fcc9f158b..87241ef4bfd 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -225,9 +225,7 @@ #endif #ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_MACRONIX -#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 -- cgit v1.2.3 From 1a8c01995fa7a5086a51f3cf0d11e54ef07beefe Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 27 Jun 2018 20:23:17 -0700 Subject: imx: imx6ul_evk: Enable DM driver for iMX6UL EVK u-boot Convert the codes and configurations to enable DM drivers in u-boot for modules: i2c, PMIC, regulator, USB, Ethernet, SD/MMC, GPIO and QSPI This patch does not change SPL, so it still uses non-DM driver for UART, GPIO and SD/MMC. Signed-off-by: Ye Li --- board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c | 208 +++++----------------- configs/mx6ul_14x14_evk_defconfig | 17 +- configs/mx6ul_9x9_evk_defconfig | 20 ++- include/configs/mx6ul_14x14_evk.h | 13 +- 4 files changed, 82 insertions(+), 176 deletions(-) (limited to 'configs') diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 1c9ffdaa16e..595ad76bbec 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -59,158 +59,47 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define IOX_SDI IMX_GPIO_NR(5, 10) -#define IOX_STCP IMX_GPIO_NR(5, 7) -#define IOX_SHCP IMX_GPIO_NR(5, 11) -#define IOX_OE IMX_GPIO_NR(5, 8) - -static iomux_v3_cfg_t const iox_pads[] = { - /* IOX_SDI */ - MX6_PAD_BOOT_MODE0__GPIO5_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_SHCP */ - MX6_PAD_BOOT_MODE1__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_STCP */ - MX6_PAD_SNVS_TAMPER7__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* IOX_nOE */ - MX6_PAD_SNVS_TAMPER8__GPIO5_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -/* - * HDMI_nRST --> Q0 - * ENET1_nRST --> Q1 - * ENET2_nRST --> Q2 - * CAN1_2_STBY --> Q3 - * BT_nPWD --> Q4 - * CSI_RST --> Q5 - * CSI_PWDN --> Q6 - * LCD_nPWREN --> Q7 - */ -enum qn { - HDMI_NRST, - ENET1_NRST, - ENET2_NRST, - CAN1_2_STBY, - BT_NPWD, - CSI_RST, - CSI_PWDN, - LCD_NPWREN, -}; - -enum qn_func { - qn_reset, - qn_enable, - qn_disable, -}; - -enum qn_level { - qn_low = 0, - qn_high = 1, -}; - -static enum qn_level seq[3][2] = { - {0, 1}, {1, 1}, {0, 0} -}; - -static enum qn_func qn_output[8] = { - qn_reset, qn_reset, qn_reset, qn_enable, qn_disable, qn_reset, - qn_disable, qn_disable -}; +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) -static void iox74lv_init(void) +#ifdef CONFIG_DM_PMIC +int power_init_board(void) { - int i; + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; - gpio_direction_output(IOX_OE, 0); + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][0]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); - - for (i = 7; i >= 0; i--) { - gpio_direction_output(IOX_SHCP, 0); - gpio_direction_output(IOX_SDI, seq[qn_output[i]][1]); - udelay(500); - gpio_direction_output(IOX_SHCP, 1); - udelay(500); - } - gpio_direction_output(IOX_STCP, 0); - udelay(500); - /* - * shift register will be output to pins - */ - gpio_direction_output(IOX_STCP, 1); -}; + /* SW1B step ramp up time from 2us to 4us/25mV */ + reg = 0x40; + pmic_reg_write(dev, PFUZE3000_SW1BCONF, reg); -#ifdef CONFIG_SYS_I2C_MXC -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -/* I2C1 for PMIC and EEPROM */ -static struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | PC, - .gp = IMX_GPIO_NR(1, 28), - }, - .sda = { - .i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | PC, - .gp = IMX_GPIO_NR(1, 29), - }, -}; + /* SW1B mode to APS/PFM */ + reg = 0xc; + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); -#ifdef CONFIG_POWER -#define I2C_PMIC 0 -int power_init_board(void) -{ - if (is_mx6ul_9x9_evk()) { - struct pmic *pfuze; - int ret; - unsigned int reg, rev_id; - - ret = power_pfuze3000_init(I2C_PMIC); - if (ret) - return ret; - - pfuze = pmic_get("PFUZE3000"); - ret = pmic_probe(pfuze); - if (ret) - return ret; - - pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); - pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); - printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", - reg, rev_id); - - /* disable Low Power Mode during standby mode */ - pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); - - /* SW1B step ramp up time from 2us to 4us/25mV */ - reg = 0x40; - pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, reg); - - /* SW1B mode to APS/PFM */ - reg = 0xc; - pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, reg); - - /* SW1B standby voltage set to 0.975V */ - reg = 0xb; - pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, reg); - } + /* SW1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); return 0; } #endif -#endif int dram_init(void) { @@ -294,25 +183,8 @@ static void setup_iomux_uart(void) } #ifdef CONFIG_FSL_QSPI - -#define QSPI_PAD_CTRL1 \ - (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ - PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) - -static iomux_v3_cfg_t const quadspi_pads[] = { - MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), - MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), -}; - static int board_qspi_init(void) { - /* Set the iomux */ - imx_iomux_v3_setup_multiple_pads(quadspi_pads, - ARRAY_SIZE(quadspi_pads)); /* Set the clock */ enable_qspi_clk(0); @@ -349,6 +221,7 @@ int board_mmc_getcd(struct mmc *mmc) ret = 1; #else imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); gpio_direction_input(USDHC2_CD_GPIO); /* @@ -393,6 +266,7 @@ int board_mmc_init(bd_t *bis) case 0: imx_iomux_v3_setup_multiple_pads( usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); gpio_direction_input(USDHC1_CD_GPIO); usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); @@ -408,6 +282,7 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); #endif + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); gpio_direction_output(USDHC2_PWR_GPIO, 0); udelay(500); gpio_direction_output(USDHC2_PWR_GPIO, 1); @@ -430,11 +305,13 @@ int board_mmc_init(bd_t *bis) #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { - MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; /* At default the 3v3 enables the MIC2026 for VBUS power */ @@ -468,6 +345,7 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif #ifdef CONFIG_FEC_MXC /* @@ -606,11 +484,13 @@ static int setup_lcd(void) imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); udelay(500); gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); return 0; @@ -629,21 +509,15 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - imx_iomux_v3_setup_multiple_pads(iox_pads, ARRAY_SIZE(iox_pads)); - - iox74lv_init(); - -#ifdef CONFIG_SYS_I2C_MXC - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); -#endif - #ifdef CONFIG_FEC_MXC setup_fec(CONFIG_FEC_ENET_DEV); #endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 038f3a63546..64ddc4f0c75 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y @@ -30,11 +31,18 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y @@ -45,8 +53,15 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 5e020734197..af8939f76a8 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL=y @@ -30,11 +31,18 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_FSL_ESDHC=y @@ -45,8 +53,18 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_FSL_QSPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO=y -CONFIG_OF_LIBFDT=y +CONFIG_DM_ETH=y diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 3ad2518dce9..c8c088e6655 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -38,17 +38,14 @@ /* I2C configs */ #ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif -/* PMIC only for 9X9 EVK */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#ifdef CONFIG_DM_GPIO +#define CONFIG_DM_74X164 #endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -166,6 +163,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_FSL_QSPI_AHB #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 @@ -190,12 +188,13 @@ #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x2 #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE ENET2_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" #endif -#define CONFIG_ETHPRIME "FEC" #endif #define CONFIG_IMX_THERMAL -- cgit v1.2.3 From b8babd8050f6780bb67e90d9402f9f19e0d63045 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Fri, 31 Aug 2018 12:08:43 +0200 Subject: imx: missing CONFIG_MII in mx7dsabresd_qspi_defconfig CONFIG_CMD_MII is set without CONFIG_MII, build is broken. Signed-off-by: Stefano Babic --- configs/mx7dsabresd_qspi_defconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'configs') diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index a79880482f8..53894e66f14 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -53,6 +53,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_EON=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_BAR=y +CONFIG_MII=y CONFIG_PHYLIB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y -- cgit v1.2.3