From 3c74e32a98187c792edcea3e0e39150de5a8dda6 Mon Sep 17 00:00:00 2001 From: wdenk Date: Sun, 22 Feb 2004 23:46:08 +0000 Subject: * Patch by Travis Sawyer, 09 Feb 2004: o 440GX: - Fix PCI Indirect access for type 1 config cycles with ppc440. - Add phymode for 440 enet - fix pci pre init o XPedite1K: - Change board_pre_init to board_early_init_f - Add user flash to bus controller setup - Fix pci pre init - Fix is_pci_host to check GPIO for monarch bit - Force xpedite1k to pci conventional mode (via #define option) * Patch by Brad Kemp, 4 Feb 2004: - handle the machine check that is generated during the PCI scans on 82xx processors. - define the registers used in the IMMR by the PCI subsystem. * Patch by Pierre Aubert, 03 Feb 2004: cpu/mpc5xxx/start.S: copy MBAR into SPR311 * Patch by Jeff Angielski, 03 Feb 2004: Fix copy & paste error in cpu/mpc8260/pci.c * Patch by Reinhard Meyer, 24 Jan 2004: Fix typo in cpu/mpc5xxx/pci_mpc5200.c --- cpu/mpc5xxx/pci_mpc5200.c | 2 +- cpu/mpc5xxx/start.S | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'cpu/mpc5xxx') diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c index 0c2114a818c..94c157f6e88 100644 --- a/cpu/mpc5xxx/pci_mpc5200.c +++ b/cpu/mpc5xxx/pci_mpc5200.c @@ -115,7 +115,7 @@ void pci_mpc5xxx_init (struct pci_controller *hose) /* Map MBAR to PCI space */ *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR; - *(vu_long *)MPC5XXX_PCI_TBATR1 = CFG_MBAR | 1; + *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1; /* Map RAM to PCI space */ *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3); diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 26811e11ad7..6f0b269b46c 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -145,6 +145,8 @@ lowboot_reentry: lis r3, CFG_MBAR@h ori r3, r3, CFG_MBAR@l #if defined(CONFIG_MPC5200) + /* MBAR is mirrored into the MBAR SPR */ + mtspr MBAR,r3 rlwinm r3, r3, 16, 16, 31 #endif #if defined(CONFIG_MGT5100) -- cgit v1.2.3