From 23780398b587ac8bc912971c60cd816bd1afeb12 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 26 May 2022 13:36:17 -0400 Subject: imx6: Update CONFIG_SPL_STACK defaults in Kconfig Update the Kconfig entry to have the correct defaults for i.MX6 platforms, and move the existing large comment from imx6_spl.h to doc/imx/common/imx6.txt so that it's not lost. Signed-off-by: Tom Rini --- doc/imx/common/imx6.txt | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'doc') diff --git a/doc/imx/common/imx6.txt b/doc/imx/common/imx6.txt index 9007cfbf587..c5554d8d6b3 100644 --- a/doc/imx/common/imx6.txt +++ b/doc/imx/common/imx6.txt @@ -162,3 +162,34 @@ icorem6qdl> nand write ${loadaddr} uboot ${filesize} NAND write: device 0 offset 0x200000, size 0x8fd26 589094 bytes written: OK icorem6qdl> + +SPL Stack size and location notes +--------------------------------- + +If we have CONFIG_MX6_OCRAM_256KB then see Figure 8.4.1 in IMX6DQ Reference +manuals: + - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF + - BOOT ROM stack is at 0x0093FFB8 + - if icache/dcache is enabled (eFuse/strapping controlled) then the + IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to + fit between 0x00907000 and 0x00938000. + - Additionally the BOOT ROM loads what they consider the firmware image + which consists of a 4K header in front of us that contains the IVT, DCD + and some padding thus 'our' max size is really 0x00908000 - 0x00938000 + or 192KB + - Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the + SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + boot media (given that boot media specific offset is configured properly). +and if we don't, see Figure 8-3 in IMX6SDL Reference manuals: + - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF + - BOOT ROM stack is at 0x0091FFB8 + - if icache/dcache is enabled (eFuse/strapping controlled) then the + IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to + fit between 0x00907000 and 0x00918000. + - Additionally the BOOT ROM loads what they consider the firmware image + which consists of a 4K header in front of us that contains the IVT, DCD + and some padding thus 'our' max size is really 0x00908000 - 0x00918000 + or 64KB + - Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + boot media (given that boot media specific offset is configured properly). -- cgit v1.2.3