From 77024aa7d9a06153d0be007439b0179157da5b86 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 28 Nov 2022 01:02:24 -0600 Subject: clk: sunxi: Add DE2 display-related clocks/resets Add clock/reset definitions for display-related peripherals, including the display engine, TCONs, and DSI and HDMI encoders, so those drivers can be converted to DM clock consumers instead of directly manipulating the CCU registers. Signed-off-by: Samuel Holland --- drivers/clk/sunxi/clk_h3.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/clk/sunxi/clk_h3.c') diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c index 17ab3b5c278..213ab510ed5 100644 --- a/drivers/clk/sunxi/clk_h3.c +++ b/drivers/clk/sunxi/clk_h3.c @@ -32,6 +32,11 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)), [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)), + [CLK_BUS_TCON0] = GATE(0x064, BIT(3)), + [CLK_BUS_TCON1] = GATE(0x064, BIT(4)), + [CLK_BUS_HDMI] = GATE(0x064, BIT(11)), + [CLK_BUS_DE] = GATE(0x064, BIT(12)), + [CLK_BUS_PIO] = GATE(0x068, BIT(5)), [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), @@ -55,6 +60,12 @@ static struct ccu_clk_gate h3_gates[] = { [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)), [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)), [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)), + + [CLK_DE] = GATE(0x104, BIT(31)), + [CLK_TCON0] = GATE(0x118, BIT(31)), + + [CLK_HDMI] = GATE(0x150, BIT(31)), + [CLK_HDMI_DDC] = GATE(0x154, BIT(31)), }; static struct ccu_reset h3_resets[] = { @@ -79,6 +90,12 @@ static struct ccu_reset h3_resets[] = { [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)), [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)), + [RST_BUS_TCON0] = RESET(0x2c4, BIT(3)), + [RST_BUS_TCON1] = RESET(0x2c4, BIT(4)), + [RST_BUS_HDMI0] = RESET(0x2c4, BIT(10)), + [RST_BUS_HDMI1] = RESET(0x2c4, BIT(11)), + [RST_BUS_DE] = RESET(0x2c4, BIT(12)), + [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)), [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), -- cgit v1.2.3