From 89a54abf1bd1a8a9ebbea9808199ec8ee3d902bd Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Wed, 21 Sep 2016 10:25:56 +0800 Subject: ddr: altera: Configuring SDRAM extra cycles timing parameters To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen --- drivers/ddr/altera/sdram.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/ddr/altera') diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c index 7e4606de28a..e74c5b039ec 100644 --- a/drivers/ddr/altera/sdram.c +++ b/drivers/ddr/altera/sdram.c @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg) debug("Configuring DRAMODT\n"); writel(cfg->dram_odt, &sdr_ctrl->dram_odt); + + debug("Configuring EXTRATIME1\n"); + writel(cfg->extratime1, &sdr_ctrl->extratime1); } /** -- cgit v1.2.3