From 4697abea62a3b02c9c346b94d7eae2e4a1c6cfd0 Mon Sep 17 00:00:00 2001
From: maxims@google.com
Date: Wed, 18 Jan 2017 13:44:55 -0800
Subject: aspeed: Add drivers common to all Aspeed SoCs

Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.

Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.

Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)
Reviewed-by: Simon Glass <sjg@chromium.org>
---
 drivers/sysreset/Makefile       |  1 +
 drivers/sysreset/sysreset_ast.c | 55 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_ast.c

(limited to 'drivers/sysreset')

diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile
index fa75cc52de7..37638a8eea4 100644
--- a/drivers/sysreset/Makefile
+++ b/drivers/sysreset/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o
 obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o
 obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
+obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
diff --git a/drivers/sysreset/sysreset_ast.c b/drivers/sysreset/sysreset_ast.c
new file mode 100644
index 00000000000..a0ab12851d4
--- /dev/null
+++ b/drivers/sysreset/sysreset_ast.c
@@ -0,0 +1,55 @@
+/*
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+#include <asm/arch/wdt.h>
+#include <linux/err.h>
+
+/* Number of Watchdog Timer ticks before reset */
+#define AST_WDT_RESET_TIMEOUT	10
+#define AST_WDT_FOR_RESET	0
+
+static int ast_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct ast_wdt *wdt = ast_get_wdt(AST_WDT_FOR_RESET);
+	u32 reset_mode = 0;
+
+	if (IS_ERR(wdt))
+		return PTR_ERR(wdt);
+
+	switch (type) {
+	case SYSRESET_WARM:
+		reset_mode = WDT_CTRL_RESET_CPU;
+		break;
+	case SYSRESET_COLD:
+		reset_mode = WDT_CTRL_RESET_CHIP;
+		break;
+	default:
+		return -EPROTONOSUPPORT;
+	}
+
+	/* Clear reset mode bits */
+	clrsetbits_le32(&wdt->ctrl,
+			(WDT_CTRL_RESET_MODE_MASK << WDT_CTRL_RESET_MODE_SHIFT),
+			(reset_mode << WDT_CTRL_RESET_MODE_SHIFT));
+	wdt_start(wdt, AST_WDT_RESET_TIMEOUT);
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops ast_sysreset = {
+	.request	= ast_sysreset_request,
+};
+
+U_BOOT_DRIVER(sysreset_ast) = {
+	.name	= "ast_sysreset",
+	.id	= UCLASS_SYSRESET,
+	.ops	= &ast_sysreset,
+};
-- 
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