From a69214dc719862b8433608d7e914e51464dfd14c Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Tue, 29 Apr 2014 14:37:56 -0700 Subject: video: mxc_ipuv3_fb: stash frame buffer pointer in global data. This patch updates the i.MX video driver to store the frame-buffer address in the fb_base field of the global data structure *gd. By doing this, you can find the frame buffer address using the 'bdinfo' command: U-Boot > bdinfo arch_number = 0x00000EB9 ... FB base = 0x4F35F1C0 This is very useful when debugging display connections. Signed-off-by: Eric Nelson Acked-by: Otavio Salvador Acked-by: Marek Vasut --- drivers/video/mxc_ipuv3_fb.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/video/mxc_ipuv3_fb.c b/drivers/video/mxc_ipuv3_fb.c index 3e21fb23067..f75d77064ea 100644 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -24,6 +25,8 @@ #include "mxcfb.h" #include "ipu_regs.h" +DECLARE_GLOBAL_DATA_PTR; + static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); @@ -415,6 +418,8 @@ static int mxcfb_map_video_memory(struct fb_info *fbi) fbi->screen_size = fbi->fix.smem_len; + gd->fb_base = fbi->fix.smem_start; + /* Clear the screen */ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); -- cgit v1.2.3 From 1161f98db687a1cb263cbacdc7eb548a0354218d Mon Sep 17 00:00:00 2001 From: Wu, Josh Date: Mon, 10 Mar 2014 16:40:41 +0800 Subject: at91: video: atmel_hlcdfb.c: fix bad timing configuration The right correspondance between LCD margins and LCD timings is: * upper margin -> vertical back porch * lower margin -> vertical front porch * left margin -> horizontal back porch * right margin -> horizontal front porch Signed-off-by: Josh Wu --- drivers/video/atmel_hlcdfb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index 853303b5e53..bb4d7d8c147 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -128,12 +128,12 @@ void lcd_ctrl_init(void *lcdbase) value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); lcdc_writel(®s->lcdc_lcdcfg1, value); - value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); - value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); + value = LCDC_LCDCFG2_VBPW(panel_info.vl_upper_margin); + value |= LCDC_LCDCFG2_VFPW(panel_info.vl_lower_margin - 1); lcdc_writel(®s->lcdc_lcdcfg2, value); - value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); - value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); + value = LCDC_LCDCFG3_HBPW(panel_info.vl_left_margin - 1); + value |= LCDC_LCDCFG3_HFPW(panel_info.vl_right_margin - 1); lcdc_writel(®s->lcdc_lcdcfg3, value); /* Display size */ -- cgit v1.2.3 From 5146fc2b37a3098f0973b2f2339e069adfc7d272 Mon Sep 17 00:00:00 2001 From: Jesper B. Christensen Date: Fri, 25 Apr 2014 15:46:17 +0200 Subject: i2c: zynq: Fixed compilation errors when using DEBUG Signed-off-by: Jesper B. Christensen Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index f1f65131a2a..b3264af4526 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -142,7 +142,7 @@ static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(zynq_i2c)); + zynq_i2c_debug_status(zynq_i2c); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -235,7 +235,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c); #endif return 0; } -- cgit v1.2.3 From 8e2615752ee6d5daf8ce2e1e599a0512750f24b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 20:09:58 +0900 Subject: bd_info: remove bi_barudrate member from struct bd_info gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada Cc: Tom Rini Cc: Simon Glass Cc: Wolfgang Denk Cc: Heiko Schocher Acked-by: Michal Simek (For microblaze) --- arch/arm/include/asm/u-boot.h | 1 - arch/arm/lib/board.c | 1 - arch/avr32/include/asm/u-boot.h | 1 - arch/avr32/lib/board.c | 1 - arch/blackfin/include/asm/u-boot.h | 1 - arch/blackfin/lib/board.c | 2 -- arch/m68k/include/asm/u-boot.h | 1 - arch/m68k/lib/board.c | 1 - arch/microblaze/include/asm/u-boot.h | 1 - arch/microblaze/lib/board.c | 1 - arch/mips/include/asm/u-boot.h | 1 - arch/mips/lib/board.c | 1 - arch/nds32/include/asm/u-boot.h | 1 - arch/nds32/lib/board.c | 1 - arch/nios2/include/asm/u-boot.h | 1 - arch/nios2/lib/board.c | 1 - arch/openrisc/include/asm/u-boot.h | 1 - arch/openrisc/lib/board.c | 1 - arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/include/asm/u-boot.h | 1 - arch/powerpc/lib/board.c | 1 - arch/sh/include/asm/u-boot.h | 1 - arch/sh/lib/board.c | 1 - arch/sparc/include/asm/u-boot.h | 1 - arch/sparc/lib/board.c | 1 - board/muas3001/muas3001.c | 4 +++- board/mvblue/mvblue.c | 5 ++--- common/board_f.c | 9 --------- common/cmd_bdinfo.c | 28 ++++++++++++++-------------- drivers/serial/serial.c | 10 +++------- include/asm-generic/u-boot.h | 1 - 31 files changed, 23 insertions(+), 61 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index cb81232b832..43cc4946838 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -27,7 +27,6 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ unsigned long bi_arm_freq; /* arm frequency */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 92e85c4db51..9b473b5eaba 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -445,7 +445,6 @@ void board_init_f(ulong bootflag) post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif - gd->bd->bi_baudrate = gd->baudrate; /* Ram ist board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index bff17d5ed26..6aef8087490 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -7,7 +7,6 @@ #define __ASM_U_BOOT_H__ 1 typedef struct bd_info { - unsigned int bi_baudrate; unsigned char bi_phy_id[4]; unsigned long bi_board_number; void *bi_boot_params; diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 28c2ec09efd..7680102f523 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -220,7 +220,6 @@ void board_init_f(ulong board_type) */ bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; bd->bi_dram[0].size = sdram_size; - bd->bi_baudrate = gd->baudrate; memcpy(new_gd, gd, sizeof(gd_t)); diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index fc36ced519e..acaeee9053e 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -13,7 +13,6 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 62342014a47..87842557dfd 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -69,7 +69,6 @@ static int display_banner(void) static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - gd->bd->bi_baudrate = gd->baudrate; return 0; } @@ -92,7 +91,6 @@ static void display_global_data(void) printf(" |-env_valid: %lx\n", gd->env_valid); printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); printf(" \\-bd: %p\n", gd->bd); - printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); printf(" |-bi_memstart: %lx\n", bd->bi_memstart); printf(" |-bi_memsize: %lx\n", bd->bi_memsize); diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 99de31aff5f..983cb2d9671 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -44,7 +44,6 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* vco Freq in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index e75b6a98dd5..318ca01ea7f 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -342,7 +342,6 @@ board_init_f (ulong bootflag) bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ #endif - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index ab3f23202d6..54d415ebb5b 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -24,7 +24,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ ulong bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index fafeeaebd63..600c80ab766 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -78,7 +78,6 @@ void board_init_f(ulong not_used) memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); gd->bd = bd; gd->baudrate = CONFIG_BAUDRATE; - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 0eb170ded8e..4909a2a5c4b 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -23,7 +23,6 @@ #else /* !CONFIG_SYS_GENERIC_BOARD */ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 3200d87e30a..3feb0207120 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -204,7 +204,6 @@ void board_init_f(ulong bootflag) */ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */ bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ memcpy(id, (void *)gd, sizeof(gd_t)); diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index 8170d28f7c2..44e72d414b9 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -23,7 +23,6 @@ #include typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 2d4c6231a37..4c06a4866b1 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -255,7 +255,6 @@ void board_init_f(ulong bootflag) addr_sp &= ~0x07; debug("New Stack Pointer is: %08lx\n", addr_sp); - gd->bd->bi_baudrate = gd->baudrate; /* Ram isn't board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index 6849b4ae9f2..51f6c30ef76 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -23,7 +23,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c index bb1a8a73407..f24218ff1c1 100644 --- a/arch/nios2/lib/board.c +++ b/arch/nios2/lib/board.c @@ -92,7 +92,6 @@ void board_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h index 5c288a85ffc..cdb8ff996ed 100644 --- a/arch/openrisc/include/asm/u-boot.h +++ b/arch/openrisc/include/asm/u-boot.h @@ -16,7 +16,6 @@ #define _U_BOOT_H_ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 391d1e19c51..234668538ca 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -84,7 +84,6 @@ void board_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { WATCHDOG_RESET(); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 0cc21c7f680..ed80a841804 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -674,7 +674,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_CPM2 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", - "current-speed", bd->bi_baudrate, 1); + "current-speed", gd->baudrate, 1); do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index f4d4a6b3003..e1b566fa568 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -64,7 +64,6 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 8b03d3aa07b..57b4a09b04e 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -547,7 +547,6 @@ void board_init_f(ulong bootflag) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index 81d51612824..ea37c244970 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -20,7 +20,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 8498153d4ea..1eb7afb89e5 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -155,7 +155,6 @@ void sh_generic_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 66cf4b023d6..5f12e581316 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -40,7 +40,6 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index c778ba26e73..b311a946c05 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -173,7 +173,6 @@ void board_init_f(ulong bootflag) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 42b0a035c7d..08eb5e82903 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -286,6 +286,8 @@ int board_early_init_r (void) } #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +DECLARE_GLOBAL_DATA_PTR; + /* * update "memory" property in the blob */ @@ -314,7 +316,7 @@ void ft_blob_update (void *blob, bd_t *bd) /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); if (nodeoffset >= 0) { - speed = cpu_to_be32 (bd->bi_baudrate); + speed = cpu_to_be32 (gd->baudrate); ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed, sizeof (unsigned long)); if (ret < 0) diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index 69abb06251e..63503e89da1 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -58,7 +58,6 @@ int checkboard (void) u32 BoardType = get_BoardType (); char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; char *p; - bd_t *bd = gd->bd; hw_watchdog_reset (); @@ -71,8 +70,8 @@ int checkboard (void) if ((p = getenv ("console_nr")) != NULL) { unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; + gd->baudrate &= ~3; + gd->baudrate |= con_nr & 3; } return 0; } diff --git a/common/board_f.c b/common/board_f.c index cbdf06f812e..aea6bff5551 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -708,14 +708,6 @@ static int init_post(void) } #endif -static int setup_baud_rate(void) -{ - /* Ick, can we get rid of this line? */ - gd->bd->bi_baudrate = gd->baudrate; - - return 0; -} - static int setup_dram_config(void) { /* Ram is board specific, so move it to board code ... */ @@ -954,7 +946,6 @@ static init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET setup_board_part2, #endif - setup_baud_rate, display_new_sp, #ifdef CONFIG_SYS_EXTBDINFO setup_board_extra, diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 238cadb1e1f..f283a1616e9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -148,7 +148,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("ethspeed", bd->bi_ethspeed); #endif printf("IP addr = %s\n", getenv("ipaddr")); - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); print_num("relocaddr", gd->relocaddr); board_detail(); return 0; @@ -176,7 +176,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -198,7 +198,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -231,7 +231,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); return 0; } @@ -277,7 +277,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -304,7 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -324,7 +324,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -344,7 +344,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -368,7 +368,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) print_num("TLB addr", gd->arch.tlb_addr); #endif @@ -406,7 +406,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -440,7 +440,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); print_mhz("ethspeed", bd->bi_ethspeed); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -490,7 +490,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -512,7 +512,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -530,7 +530,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %d bps\n", gd->baudrate); return 0; } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c4fb59cfb31..fd61a5e5458 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) - gd->bd->bi_baudrate = baudrate; -#endif serial_setbrg(); @@ -502,12 +499,11 @@ int uart_post_test(int flags) unsigned char c; int ret, saved_baud, b; struct serial_device *saved_dev, *s; - bd_t *bd = gd->bd; /* Save current serial state */ ret = 0; saved_dev = serial_current; - saved_baud = bd->bi_baudrate; + saved_baud = gd->baudrate; for (s = serial_devices; s; s = s->next) { /* If this driver doesn't support loop back, skip it */ @@ -530,7 +526,7 @@ int uart_post_test(int flags) /* Test every available baud rate */ for (b = 0; b < ARRAY_SIZE(bauds); ++b) { - bd->bi_baudrate = bauds[b]; + gd->baudrate = bauds[b]; serial_setbrg(); /* @@ -572,7 +568,7 @@ int uart_post_test(int flags) done: /* Restore previous serial state */ serial_current = saved_dev; - bd->bi_baudrate = saved_baud; + gd->baudrate = saved_baud; serial_reinit_all(); serial_setbrg(); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index c18e4ca27a3..62cb1eabc1f 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -66,7 +66,6 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ -- cgit v1.2.3 From d57dee5787ad96d2c80bf36f443276592d39ee21 Mon Sep 17 00:00:00 2001 From: Karicheri, Muralidharan Date: Wed, 9 Apr 2014 15:38:46 -0400 Subject: serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri --- README | 4 ++++ drivers/serial/ns16550.c | 6 ++++++ include/ns16550.h | 1 + 3 files changed, 11 insertions(+) (limited to 'drivers') diff --git a/README b/README index 80a1bfaad2a..61c2caca316 100644 --- a/README +++ b/README @@ -751,6 +751,10 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. + CONFIG_SERIAL_HW_FLOW_CONTROL + + Define this variable to enable hw flow control in serial driver. + Current user of this option is drivers/serial/nsl16550.c driver - Console Interface: Depending on board, define exactly one serial port diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8a134549433..f26979dbe15 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -33,6 +33,12 @@ #if defined(CONFIG_K2HK_EVM) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#undef UART_MCRVAL +#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL +#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) +#else +#define UART_MCRVAL (UART_MCR_RTS) +#endif #endif #ifndef CONFIG_SYS_NS16550_IER diff --git a/include/ns16550.h b/include/ns16550.h index 51cb5b4a66d..17f829f6f9b 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -100,6 +100,7 @@ typedef struct NS16550 *NS16550_t; #define UART_MCR_OUT1 0x04 /* Out 1 */ #define UART_MCR_OUT2 0x08 /* Out 2 */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ #define UART_MCR_DMA_EN 0x04 #define UART_MCR_TX_DFR 0x08 -- cgit v1.2.3 From 02aa4c538838edc918ff4e7e9e4121259552ef70 Mon Sep 17 00:00:00 2001 From: Xiaobo Xie Date: Fri, 11 Apr 2014 16:03:11 +0800 Subject: AR8035/phy: Enable autonegotiation function for ar8035 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before, but used "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8035 to enable autonegotiation. Then removed the genphy_config_aneg() function. Signed-off-by: Xie Xiaobo --- drivers/net/phy/atheros.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index abd4e5b463e..d509e30d359 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -31,9 +31,7 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); - genphy_config_aneg(phydev); - - phy_reset(phydev); + phydev->supported = phydev->drv->features; return 0; } -- cgit v1.2.3 From 597fe041a85fe3b1bf6044adf5e132f7a5457000 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 11 Apr 2014 16:14:17 +0800 Subject: net/phy: enable get_phy_id redefinable As some PHYs have non-standard PHY ID registers, PHY Id can't be read correctly by current get_phy_id function, so we enable get_phy_id redefinable to permit specific PHY driver having own specific get_phy_id function. Signed-off-by: Shengzhou Liu --- drivers/net/phy/phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index c691fbbbc61..230ed97dd12 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,7 @@ #include #include #include +#include /* Generic PHY support and helper functions */ @@ -577,7 +578,7 @@ static struct phy_device *phy_device_create(struct mii_dev *bus, int addr, * Description: Reads the ID registers of the PHY at @addr on the * @bus, stores it in @phy_id and returns zero on success. */ -static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) { int phy_reg; -- cgit v1.2.3 From da384a9d7628c77140023e7c095f79ecfe5a4e2d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 18 Apr 2014 19:09:48 +0900 Subject: net: rename and refactor eth_rand_ethaddr() function Some functions in include/net.h are ported from include/linux/etherdevice.h of Linux Kernel. For ex. is_zero_ether_addr() is_multicast_ether_addr() is_broadcast_ether_addr() is_valid_ether_addr(); So, we should use the same function name as that of Linux Kernel, eth_rand_addr(), for consistency. Besides, eth_rand_addr() has been implemented as an inline function. So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR. Signed-off-by: Masahiro Yamada Acked-by: Joe Hershberger --- board/buffalo/lsxl/lsxl.c | 2 +- drivers/net/dm9000x.c | 2 +- drivers/net/ftmac110.c | 2 +- include/net.h | 36 +++++++++++++++++++----------------- net/eth.c | 22 ---------------------- 5 files changed, 22 insertions(+), 42 deletions(-) (limited to 'drivers') diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index eca1683a6fe..659a124b227 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -231,7 +231,7 @@ static void rescue_mode(void) printf("Entering rescue mode..\n"); #ifdef CONFIG_RANDOM_MACADDR if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - eth_random_enetaddr(enetaddr); + eth_random_addr(enetaddr); if (eth_setenv_enetaddr("ethaddr", enetaddr)) { printf("Failed to set ethernet address\n"); set_led(LED_ALARM_BLINKING); diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index b68d808c742..4de9d41642e 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -345,7 +345,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) if (!is_valid_ether_addr(dev->enetaddr)) { #ifdef CONFIG_RANDOM_MACADDR printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); printf("MAC: %pM\n", dev->enetaddr); #else printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 8eee272cf14..98c4f09629b 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -425,7 +425,7 @@ int ftmac110_initialize(bd_t *bis) dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( diff --git a/include/net.h b/include/net.h index 0802fad8761..735b0b9d26f 100644 --- a/include/net.h +++ b/include/net.h @@ -130,23 +130,6 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr); -#ifdef CONFIG_RANDOM_MACADDR -/* - * The u-boot policy does not allow hardcoded ethernet addresses. Under the - * following circumstances a random generated address is allowed: - * - in emergency cases, where you need a working network connection to set - * the ethernet address. - * Eg. you want a rescue boot and don't have a serial port to access the - * CLI to set environment variables. - * - * In these cases, we generate a random locally administered ethernet address. - * - * Args: - * enetaddr - returns 6 byte hardware address - */ -extern void eth_random_enetaddr(uchar *enetaddr); -#endif - extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(void *packet, int length); /* Send a packet */ @@ -674,6 +657,25 @@ static inline int is_valid_ether_addr(const u8 *addr) return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); } +/** + * eth_random_addr - Generate software assigned random Ethernet address + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Generate a random Ethernet address (MAC) that is not multicast + * and has the local assigned bit set. + */ +static inline void eth_random_addr(uchar *addr) +{ + int i; + unsigned int seed = get_timer(0); + + for (i = 0; i < 6; i++) + addr[i] = rand_r(&seed); + + addr[0] &= 0xfe; /* clear multicast bit */ + addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ +} + /* Convert an IP address to a string */ extern void ip_to_string(IPaddr_t x, char *s); diff --git a/net/eth.c b/net/eth.c index 32bd10c8290..99386e3e631 100644 --- a/net/eth.c +++ b/net/eth.c @@ -63,28 +63,6 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } -#ifdef CONFIG_RANDOM_MACADDR -void eth_random_enetaddr(uchar *enetaddr) -{ - uint32_t rval; - - srand(get_timer(0)); - - rval = rand(); - enetaddr[0] = rval & 0xff; - enetaddr[1] = (rval >> 8) & 0xff; - enetaddr[2] = (rval >> 16) & 0xff; - - rval = rand(); - enetaddr[3] = rval & 0xff; - enetaddr[4] = (rval >> 8) & 0xff; - enetaddr[5] = (rval >> 16) & 0xff; - - /* make sure it's local and unicast */ - enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01; -} -#endif - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on -- cgit v1.2.3 From bafd67d3d0f39a19c1e32146cde8b1f4ccd6d666 Mon Sep 17 00:00:00 2001 From: Manish Badarkhe Date: Thu, 24 Apr 2014 08:55:07 +0530 Subject: tps6586x: staticize funtions Make funtions static which are locally used in file. Signed-off-by: Manish Badarkhe --- drivers/power/tps6586x.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/power/tps6586x.c b/drivers/power/tps6586x.c index 704c2439b14..d29d969533d 100644 --- a/drivers/power/tps6586x.c +++ b/drivers/power/tps6586x.c @@ -32,7 +32,7 @@ enum { }; #define MAX_I2C_RETRY 3 -int tps6586x_read(int reg) +static int tps6586x_read(int reg) { int i; uchar data; @@ -61,7 +61,7 @@ exit: return retval; } -int tps6586x_write(int reg, uchar *data, uint len) +static int tps6586x_write(int reg, uchar *data, uint len) { int i; int retval = -1; -- cgit v1.2.3 From 15e82e5309ed706fa2878aed3b225aa48ae960c7 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Mon, 28 Apr 2014 20:14:05 +0100 Subject: net/designware: call phy_connect_dev() to properly setup phylib device This sets up the linkage from the phydev back to the ethernet device. This symptom of not doing this which I noticed was: Waiting for PHY auto negotiation to complete.... rather than: dwmac.1c50000 Waiting for PHY auto negotiation to complete.... Signed-off-by: Ian Campbell Cc: Alexey Brodkin --- drivers/net/designware.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index c45593bcc09..78751b2600c 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -390,6 +390,8 @@ static int dw_phy_init(struct eth_device *dev) if (!phydev) return -1; + phy_connect_dev(phydev, dev); + phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; -- cgit v1.2.3 From b625b9aef383be4366670e8d22b13d48ef8aa870 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:23:43 +0100 Subject: fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/esd/pmc440/fpga.c | 2 +- board/matrix_vision/mvsmr/fpga.c | 2 +- drivers/fpga/spartan2.c | 40 ++++++++++++++++++++-------------------- drivers/fpga/xilinx.c | 14 +++++++------- include/spartan2.h | 32 ++++++++++++++++---------------- include/xilinx.h | 2 +- 6 files changed, 46 insertions(+), 46 deletions(-) (limited to 'drivers') diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index b7b62dd94db..cef20508827 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { }; #endif -Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = { +xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { ngcc_fpga_pre_config_fn, ngcc_fpga_pgm_fn, ngcc_fpga_clk_fn, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index 88035a9e9e3..639bc7c75b9 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -27,7 +27,7 @@ Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { }; Xilinx_desc spartan3 = { - Xilinx_Spartan2, + xilinx_spartan2, slave_serial, XILINX_XC3S200_SIZE, (void *) &fpga_fns, diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eab1b51e55..bd317095c65 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,29 +31,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan2_ss_load (desc, buf, bsize); + ret_val = spartan2_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan2_sp_load (desc, buf, bsize); + ret_val = spartan2_sp_load(desc, buf, bsize); break; default: @@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan2_ss_dump (desc, buf, bsize); + ret_val = spartan2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan2_sp_dump (desc, buf, bsize); + ret_val = spartan2_sp_dump(desc, buf, bsize); break; default: @@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_info( Xilinx_desc *desc ) +int spartan2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -248,10 +248,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -296,10 +296,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -439,7 +439,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 2e0db535d47..47bbf395140 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,11 +149,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Loader...\n", __FUNCTION__); - ret_val = Spartan2_load (desc, buf, bsize); + ret_val = spartan2_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -206,11 +206,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Reader...\n", __FUNCTION__); - ret_val = Spartan2_dump (desc, buf, bsize); + ret_val = spartan2_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -262,7 +262,7 @@ int xilinx_info (Xilinx_desc * desc) if (xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: printf ("Spartan-II\n"); break; case Xilinx_Spartan3: @@ -316,9 +316,9 @@ int xilinx_info (Xilinx_desc * desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) - Spartan2_info (desc); + spartan2_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-II devices.\n", diff --git a/include/spartan2.h b/include/spartan2.h index 087a27d3cc0..a9fc68acc89 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,9 +10,9 @@ #include -extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan2_info(Xilinx_desc *desc); +int spartan2_load(Xilinx_desc *desc, const void *image, size_t size); +int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int spartan2_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { @@ -29,7 +29,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Parallel_fns; +} xilinx_spartan2_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -40,7 +40,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Serial_fns; +} xilinx_spartan2_slave_serial_fns; /* Device Image Sizes *********************************************************************/ @@ -63,36 +63,36 @@ typedef struct { *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } #endif /* _SPARTAN2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 00a585e5fc3..9d870b2d848 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -26,7 +26,7 @@ typedef enum { /* typedef Xilinx_iface */ typedef enum { /* typedef Xilinx_Family */ min_xilinx_type, /* low range check value */ - Xilinx_Spartan2, /* Spartan-II Family */ + xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ Xilinx_Virtex2, /* Virtex2 Family */ Xilinx_Spartan3, /* Spartan-III Family */ -- cgit v1.2.3 From 2a6e3869f25093cd4032a3cd64ee455afbd668bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:28:42 +0100 Subject: fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 4 ++-- board/astro/mcf5373l/fpga.c | 4 ++-- board/balloon3/balloon3.c | 2 +- board/esd/pmc440/fpga.c | 4 ++-- board/matrix_vision/mvsmr/fpga.c | 2 +- board/spear/x600/fpga.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 2 +- drivers/fpga/spartan3.c | 40 ++++++++++++++++++------------------ drivers/fpga/xilinx.c | 14 ++++++------- include/spartan3.h | 38 +++++++++++++++++----------------- include/xilinx.h | 2 +- 11 files changed, 57 insertions(+), 57 deletions(-) (limited to 'drivers') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 0c08c0640ef..56fde200e79 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -26,7 +26,7 @@ * Spartan2 code is used to download our Spartan 3 :) code is compatible. * Just take care about the file size */ -Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { +xilinx_spartan3_slave_parallel_fns fpga_fns = { fpga_pre_fn, fpga_pgm_fn, fpga_init_fn, @@ -43,7 +43,7 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { }; Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Spartan3, + {xilinx_spartan3, slave_parallel, 1196128l/8, (void *)&fpga_fns, diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index c679ad7f65c..152ff1f58c9 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -363,7 +363,7 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) * relocated at runtime. * FIXME: relocation not yet working for coldfire, see below! */ -Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { +xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_pre_config_fn, xilinx_pgm_fn, xilinx_clk_fn, @@ -375,7 +375,7 @@ Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { }; Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Spartan3, + {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, (void *)&xilinx_fns, diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 04e0574658a..4aa66052da9 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = { +xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index cef20508827..18a1b63088d 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USE_SP_CODE #ifdef USE_SP_CODE -Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { fpga_post_config_fn, }; #else -Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index 639bc7c75b9..b2074552439 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -16,7 +16,7 @@ #include "fpga.h" #include "mvsmr.h" -Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { +xilinx_spartan3_slave_serial_fns fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index c06c9947777..c26eba42845 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int cookie) return assert_write; } -static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { +static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index c32d554ea42..a36176494e4 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -190,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { +xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 3edc5c2c66a..e40abbfb946 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,29 +35,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan3_ss_load (desc, buf, bsize); + ret_val = spartan3_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan3_sp_load (desc, buf, bsize); + ret_val = spartan3_sp_load(desc, buf, bsize); break; default: @@ -68,19 +68,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan3_ss_dump (desc, buf, bsize); + ret_val = spartan3_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan3_sp_dump (desc, buf, bsize); + ret_val = spartan3_sp_dump(desc, buf, bsize); break; default: @@ -91,7 +91,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_info( Xilinx_desc *desc ) +int spartan3_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,10 +100,10 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -254,10 +254,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -302,10 +302,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -457,7 +457,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 47bbf395140..7d93d641f6a 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -159,11 +159,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Loader...\n", __FUNCTION__); - ret_val = Spartan3_load (desc, buf, bsize); + ret_val = spartan3_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -216,11 +216,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Reader...\n", __FUNCTION__); - ret_val = Spartan3_dump (desc, buf, bsize); + ret_val = spartan3_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -265,7 +265,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan2: printf ("Spartan-II\n"); break; - case Xilinx_Spartan3: + case xilinx_spartan3: printf ("Spartan-III\n"); break; case Xilinx_Virtex2: @@ -325,9 +325,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) - Spartan3_info (desc); + spartan3_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-III devices.\n", diff --git a/include/spartan3.h b/include/spartan3.h index 72e7c0ddd00..93ca8a40bc3 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,9 +10,9 @@ #include -extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan3_info(Xilinx_desc *desc); +int spartan3_load(Xilinx_desc *desc, const void *image, size_t size); +int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int spartan3_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { @@ -29,7 +29,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Spartan3_Slave_Parallel_fns; +} xilinx_spartan3_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -42,7 +42,7 @@ typedef struct { Xilinx_post_fn post; Xilinx_bwr_fn bwr; /* block write function */ Xilinx_abort_fn abort; -} Xilinx_Spartan3_Slave_Serial_fns; +} xilinx_spartan3_slave_serial_fns; /* Device Image Sizes *********************************************************************/ @@ -73,46 +73,46 @@ typedef struct { *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } #endif /* _SPARTAN3_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 9d870b2d848..365c0c358eb 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -29,7 +29,7 @@ typedef enum { /* typedef Xilinx_Family */ xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ Xilinx_Virtex2, /* Virtex2 Family */ - Xilinx_Spartan3, /* Spartan-III Family */ + xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ } Xilinx_Family; /* end, typedef Xilinx_Family */ -- cgit v1.2.3 From d9071ce0a8cd684589c9c35e4d7c604a9cbd7d62 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:33:36 +0100 Subject: fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/gen860t/fpga.c | 4 ++-- drivers/fpga/virtex2.c | 34 +++++++++++++++++----------------- drivers/fpga/xilinx.c | 14 +++++++------- include/virtex2.h | 34 +++++++++++++++++----------------- include/xilinx.h | 2 +- 5 files changed, 44 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index b7984dd0fec..48a4222ac41 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Note that these are pointers to code that is in Flash. They will be * relocated at runtime. */ -Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { +xilinx_virtex2_slave_selectmap_fns fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -57,7 +57,7 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { }; Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Virtex2, + {xilinx_virtex2, slave_selectmap, XILINX_XC2V3000_SIZE, (void *) &fpga_fns, diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b5a895d41a7..1cd9046a248 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,25 +84,25 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Virtex2_ss_load (desc, buf, bsize); + ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Virtex2_ssm_load (desc, buf, bsize); + ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: @@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Virtex2_ss_dump (desc, buf, bsize); + ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Virtex2_ssm_dump (desc, buf, bsize); + ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: @@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_info (Xilinx_desc * desc) +int virtex2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", __FUNCTION__, __LINE__, fn); @@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -404,13 +404,13 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 7d93d641f6a..6953535f082 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -169,11 +169,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Loader...\n", __FUNCTION__); - ret_val = Virtex2_load (desc, buf, bsize); + ret_val = virtex2_load(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -226,11 +226,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined( CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Reader...\n", __FUNCTION__); - ret_val = Virtex2_dump (desc, buf, bsize); + ret_val = virtex2_dump(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -268,7 +268,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan3: printf ("Spartan-III\n"); break; - case Xilinx_Virtex2: + case xilinx_virtex2: printf ("Virtex-II\n"); break; case xilinx_zynq: @@ -334,9 +334,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) - Virtex2_info (desc); + virtex2_info(desc); #else /* just in case */ printf ("%s: No support for Virtex-II devices.\n", diff --git a/include/virtex2.h b/include/virtex2.h index 2e9a4f52da3..1e6624ca962 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,9 @@ #include -extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Virtex2_info(Xilinx_desc *desc); +int virtex2_load(Xilinx_desc *desc, const void *image, size_t size); +int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int virtex2_info(Xilinx_desc *desc); /* * Slave SelectMap Implementation function table. @@ -32,7 +32,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Virtex2_Slave_SelectMap_fns; +} xilinx_virtex2_slave_selectmap_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -40,7 +40,7 @@ typedef struct { Xilinx_clk_fn clk; Xilinx_rdata_fn rdata; Xilinx_wdata_fn wdata; -} Xilinx_Virtex2_Slave_Serial_fns; +} xilinx_virtex2_slave_serial_fns; /* Device Image Sizes (in bytes) *********************************************************************/ @@ -60,39 +60,39 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } #endif /* _VIRTEX2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 365c0c358eb..fa89fb68351 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -28,7 +28,7 @@ typedef enum { /* typedef Xilinx_Family */ min_xilinx_type, /* low range check value */ xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ - Xilinx_Virtex2, /* Virtex2 Family */ + xilinx_virtex2, /* Virtex2 Family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ -- cgit v1.2.3 From f8c1be9816a60d1f627954fe202b502917c69863 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 12:49:21 +0100 Subject: fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 2 +- board/astro/mcf5373l/fpga.c | 2 +- board/balloon3/balloon3.c | 2 +- board/esd/pmc440/fpga.c | 2 +- board/gen860t/fpga.c | 2 +- board/matrix_vision/mvsmr/fpga.c | 2 +- board/spear/x600/fpga.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 2 +- board/xilinx/zynq/board.c | 14 +++++++------- drivers/fpga/spartan2.c | 26 +++++++++++++------------- drivers/fpga/spartan3.c | 26 +++++++++++++------------- drivers/fpga/virtex2.c | 22 +++++++++++----------- drivers/fpga/xilinx.c | 14 +++++++------- drivers/fpga/zynqpl.c | 6 +++--- include/spartan2.h | 6 +++--- include/spartan3.h | 6 +++--- include/virtex2.h | 6 +++--- include/xilinx.h | 10 +++++----- include/zynqpl.h | 6 +++--- 19 files changed, 79 insertions(+), 79 deletions(-) (limited to 'drivers') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 56fde200e79..7d6e1e462c9 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -42,7 +42,7 @@ xilinx_spartan3_slave_parallel_fns fpga_fns = { fpga_post_fn, }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { {xilinx_spartan3, slave_parallel, 1196128l/8, diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 152ff1f58c9..9dc82c5737c 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -374,7 +374,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_fastwr_fn }; -Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 4aa66052da9..aa108ca1539 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -207,7 +207,7 @@ xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, +xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, (void *)&balloon3_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index 18a1b63088d..f876da855b1 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -57,7 +57,7 @@ xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { ngcc_fpga_post_config_fn }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC( #ifdef USE_SP_CODE slave_parallel, diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 48a4222ac41..dd0ef707d6d 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -56,7 +56,7 @@ xilinx_virtex2_slave_selectmap_fns fpga_fns = { fpga_post_config_fn }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { {xilinx_virtex2, slave_selectmap, XILINX_XC2V3000_SIZE, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index b2074552439..518992578c1 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -26,7 +26,7 @@ xilinx_spartan3_slave_serial_fns fpga_fns = { 0 }; -Xilinx_desc spartan3 = { +xilinx_desc spartan3 = { xilinx_spartan2, slave_serial, XILINX_XC3S200_SIZE, diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index c26eba42845..b256222e186 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -173,7 +173,7 @@ static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { fpga_post_config_fn, }; -static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) }; diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index a36176494e4..b4a0a72bd0f 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -200,7 +200,7 @@ xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, +xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, (void *)&mt_ventoux_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 485a5e4a249..c8cc2bc9344 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -14,15 +14,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FPGA -Xilinx_desc fpga; +xilinx_desc fpga; /* It can be done differently */ -Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index bd317095c65..0796729436c 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,17 +31,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(xilinx_desc *desc ); */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(Xilinx_desc *desc) +int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,7 +96,7 @@ int spartan2_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -248,7 +248,7 @@ static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -296,7 +296,7 @@ static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; @@ -439,7 +439,7 @@ static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index e40abbfb946..1304b4c646e 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,17 +35,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(xilinx_desc *desc ); */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(Xilinx_desc *desc) +int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,7 +100,7 @@ int spartan3_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -254,7 +254,7 @@ static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -302,7 +302,7 @@ static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; @@ -457,7 +457,7 @@ static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 1cd9046a248..a582bf2d798 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,13 +84,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(Xilinx_desc *desc) +int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ int virtex2_info(Xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -352,7 +352,7 @@ static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -404,13 +404,13 @@ static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 6953535f082..b0e9cb35a31 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -31,7 +31,7 @@ #endif /* Local Static Functions */ -static int xilinx_validate (Xilinx_desc * desc, char *fn); +static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ @@ -43,7 +43,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; const fpga_desc *desc; - Xilinx_desc *xdesc; + xilinx_desc *xdesc; dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ @@ -94,7 +94,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return FPGA_FAIL; } } else { - printf("%s: Please fill correct device ID to Xilinx_desc\n", + printf("%s: Please fill correct device ID to xilinx_desc\n", __func__); } printf(" part number = \"%s\"\n", buffer); @@ -141,7 +141,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return fpga_load(devnum, dataptr, swapsize); } -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -198,7 +198,7 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -255,7 +255,7 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_info (Xilinx_desc * desc) +int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; @@ -369,7 +369,7 @@ int xilinx_info (Xilinx_desc * desc) /* ------------------------------------------------------------------------- */ -static int xilinx_validate (Xilinx_desc * desc, char *fn) +static int xilinx_validate(xilinx_desc *desc, char *fn) { int ret_val = false; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 923a1586d8b..b4d0e2278c9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(Xilinx_desc *desc) +int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +358,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } diff --git a/include/spartan2.h b/include/spartan2.h index a9fc68acc89..33b25e6b8b9 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,9 +10,9 @@ #include -int spartan2_load(Xilinx_desc *desc, const void *image, size_t size); -int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int spartan2_info(Xilinx_desc *desc); +int spartan2_load(xilinx_desc *desc, const void *image, size_t size); +int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int spartan2_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/spartan3.h b/include/spartan3.h index 93ca8a40bc3..e06b99bff55 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,9 +10,9 @@ #include -int spartan3_load(Xilinx_desc *desc, const void *image, size_t size); -int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int spartan3_info(Xilinx_desc *desc); +int spartan3_load(xilinx_desc *desc, const void *image, size_t size); +int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int spartan3_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/virtex2.h b/include/virtex2.h index 1e6624ca962..dd47965aad3 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,9 @@ #include -int virtex2_load(Xilinx_desc *desc, const void *image, size_t size); -int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_info(Xilinx_desc *desc); +int virtex2_load(xilinx_desc *desc, const void *image, size_t size); +int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int virtex2_info(xilinx_desc *desc); /* * Slave SelectMap Implementation function table. diff --git a/include/xilinx.h b/include/xilinx.h index fa89fb68351..5900c837440 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -34,20 +34,20 @@ typedef enum { /* typedef Xilinx_Family */ max_xilinx_type /* insert all new types before this */ } Xilinx_Family; /* end, typedef Xilinx_Family */ -typedef struct { /* typedef Xilinx_desc */ +typedef struct { /* typedef xilinx_desc */ Xilinx_Family family; /* part type */ Xilinx_iface iface; /* interface type */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ char *name; /* device name in bitstream */ -} Xilinx_desc; /* end, typedef Xilinx_desc */ +} xilinx_desc; /* end, typedef xilinx_desc */ /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); -extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int xilinx_info(Xilinx_desc *desc); +int xilinx_load(xilinx_desc *desc, const void *image, size_t size); +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int xilinx_info(xilinx_desc *desc); /* Board specific implementation specific function types *********************************************************************/ diff --git a/include/zynqpl.h b/include/zynqpl.h index c81446e9860..fdee69110ce 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,9 +12,9 @@ #include -extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); -extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int zynq_info(Xilinx_desc *desc); +int zynq_load(xilinx_desc *desc, const void *image, size_t size); +int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int zynq_info(xilinx_desc *desc); #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b -- cgit v1.2.3 From 14cfc4f3735d9704cb6a630ef302be596d380684 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 13:07:57 +0100 Subject: fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 1 + board/astro/mcf5373l/fpga.c | 3 +- drivers/fpga/spartan2.c | 12 +++- drivers/fpga/spartan3.c | 12 +++- drivers/fpga/virtex2.c | 12 +++- drivers/fpga/xilinx.c | 159 ++------------------------------------------ drivers/fpga/zynqpl.c | 13 ++-- include/spartan2.h | 28 ++++---- include/spartan3.h | 36 +++++----- include/virtex2.h | 28 ++++---- include/xilinx.h | 7 ++ include/zynqpl.h | 16 ++--- 12 files changed, 104 insertions(+), 223 deletions(-) (limited to 'drivers') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 7d6e1e462c9..65a4812c35b 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -48,6 +48,7 @@ xilinx_desc fpga[CONFIG_FPGA_COUNT] = { 1196128l/8, (void *)&fpga_fns, 0, + &spartan3_op, "3s200aft256"} }; diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 81ec1920657..1d044d96a56 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -379,7 +379,8 @@ xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { slave_serial, XILINX_XC3S4000_SIZE, (void *)&xilinx_fns, - 0} + 0, + &spartan3_op} }; /* Initialize the fpga. Return 1 on success, 0 on failure. */ diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 0796729436c..70540561403 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(xilinx_desc *desc) +static int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan2_op = { + .load = spartan2_load, + .dump = spartan2_dump, + .info = spartan2_info, +}; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1304b4c646e..5c9412c2f63 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(xilinx_desc *desc) +static int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan3_op = { + .load = spartan3_load, + .dump = spartan3_dump, + .info = spartan3_info, +}; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index a582bf2d798..e092147edd1 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(xilinx_desc *desc) +static int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) } /* vim: set ts=4 tw=78: */ + +struct xilinx_fpga_op virtex2_op = { + .load = virtex2_load, + .dump = virtex2_dump, + .info = virtex2_info, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index b0e9cb35a31..8837f5c122e 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -19,17 +19,6 @@ #include #include -#if 0 -#define FPGA_DEBUG -#endif - -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local Static Functions */ static int xilinx_validate(xilinx_desc *desc, char *fn); @@ -143,116 +132,22 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Loader...\n", - __FUNCTION__); - ret_val = spartan2_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Loader...\n", - __FUNCTION__); - ret_val = spartan3_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Loader...\n", - __FUNCTION__); - ret_val = virtex2_load(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Loader...\n", - __func__); - ret_val = zynq_load(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->load(desc, buf, bsize); } int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Reader...\n", - __FUNCTION__); - ret_val = spartan2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Reader...\n", - __FUNCTION__); - ret_val = spartan3_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Reader...\n", - __FUNCTION__); - ret_val = virtex2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Reader...\n", - __func__); - ret_val = zynq_dump(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->dump(desc, buf, bsize); } int xilinx_info(xilinx_desc *desc) @@ -315,47 +210,7 @@ int xilinx_info(xilinx_desc *desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - spartan2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - spartan3_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - virtex2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - zynq_info(desc); -#else - /* just in case */ - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - ; - } + desc->operations->info(desc); } else printf ("No Device Function Table.\n"); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index b4d0e2278c9..dcd34951ad6 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(xilinx_desc *desc) +static int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -152,8 +152,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) return 0; } - -int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +357,13 @@ int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } + +struct xilinx_fpga_op zynq_op = { + .load = zynq_load, + .dump = zynq_dump, + .info = zynq_info, +}; diff --git a/include/spartan2.h b/include/spartan2.h index 25db6e7a60d..2aca954e73a 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,10 +10,6 @@ #include -int spartan2_load(xilinx_desc *desc, const void *image, size_t size); -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int spartan2_info(xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { xilinx_pre_fn pre; @@ -42,6 +38,8 @@ typedef struct { xilinx_post_fn post; } xilinx_spartan2_slave_serial_fns; +extern struct xilinx_fpga_op spartan2_op; + /* Device Image Sizes *********************************************************************/ /* Spartan-II (2.5V) */ @@ -63,36 +61,36 @@ typedef struct { *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op } #endif /* _SPARTAN2_H_ */ diff --git a/include/spartan3.h b/include/spartan3.h index 56698ac9c72..d6d67a6e560 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,10 +10,6 @@ #include -int spartan3_load(xilinx_desc *desc, const void *image, size_t size); -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int spartan3_info(xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { xilinx_pre_fn pre; @@ -44,6 +40,8 @@ typedef struct { xilinx_abort_fn abort; } xilinx_spartan3_slave_serial_fns; +extern struct xilinx_fpga_op spartan3_op; + /* Device Image Sizes *********************************************************************/ /* Spartan-III (1.2V) */ @@ -73,46 +71,48 @@ typedef struct { *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ + &spartan3_op } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ + &spartan3_op } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op } #endif /* _SPARTAN3_H_ */ diff --git a/include/virtex2.h b/include/virtex2.h index d39286c7ab9..7b7825f513e 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,7 @@ #include -int virtex2_load(xilinx_desc *desc, const void *image, size_t size); -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_info(xilinx_desc *desc); +extern struct xilinx_fpga_op virtex2_op; /* * Slave SelectMap Implementation function table. @@ -60,39 +58,39 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op } #endif /* _VIRTEX2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index b72aece7c90..9801267c593 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -40,9 +40,16 @@ typedef struct { /* typedef xilinx_desc */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ + struct xilinx_fpga_op *operations; /* operations */ char *name; /* device name in bitstream */ } xilinx_desc; /* end, typedef xilinx_desc */ +struct xilinx_fpga_op { + int (*load)(xilinx_desc *, const void *, size_t); + int (*dump)(xilinx_desc *, const void *, size_t); + int (*info)(xilinx_desc *); +}; + /* Generic Xilinx Functions *********************************************************************/ int xilinx_load(xilinx_desc *desc, const void *image, size_t size); diff --git a/include/zynqpl.h b/include/zynqpl.h index fdee69110ce..8a9ec3297fb 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,9 +12,7 @@ #include -int zynq_load(xilinx_desc *desc, const void *image, size_t size); -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int zynq_info(xilinx_desc *desc); +extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b @@ -33,21 +31,21 @@ int zynq_info(xilinx_desc *desc); /* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" } #define XILINX_XC7Z015_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" } +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" } #define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" } #define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" } #define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" } #define XILINX_XC7Z100_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" } +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" } #endif /* _ZYNQPL_H_ */ -- cgit v1.2.3 From 42a74a08eb4ef976f3b29a0b2bdefe0e509af8f5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 25 Apr 2014 13:51:58 +0200 Subject: fpga: zynq: Remove sparse warnings Warnings: drivers/fpga/zynqpl.c:150:32: warning: Using plain integer as NULL pointer drivers/fpga/zynqpl.c:152:16: warning: Using plain integer as NULL pointer Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index dcd34951ad6..0a134e524c4 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -147,9 +147,9 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } /* Loop can be huge - support CTRL + C */ if (ctrlc()) - return 0; + return NULL; } - return 0; + return NULL; } static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) -- cgit v1.2.3 From a0735a34f8ab2d7060b6f8c16d3cccf78b137283 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 12 Mar 2014 17:09:26 +0530 Subject: fpga: zynq: Use helper functions for zynq dma Use zynq_dma_xfer_init, zynq_align_dma_buffer, zynq_dma_transfer helper function performing dma transfers so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 201 +++++++++++++++++++++++++++++--------------------- 1 file changed, 115 insertions(+), 86 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 0a134e524c4..ef6d1caca41 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -152,70 +152,52 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) return NULL; } -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 i, control, isr_status, status, swap, diff; - u32 *buf_start; + unsigned long ts; + u32 isr_status; - /* Detect if we are going working with partial or full bitstream */ - if (bsize != desc->size) { - printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; - } - - buf_start = check_data((u8 *)buf, bsize, &swap); - if (!buf_start) - return FPGA_FAIL; - - /* Check if data is postpone from start */ - diff = (u32)buf_start - (u32)buf; - if (diff) { - printf("%s: Bitstream is not validated yet (diff %x)\n", - __func__, diff); - return FPGA_FAIL; - } + /* Set up the transfer */ + writel((u32)srcbuf, &devcfg_base->dma_src_addr); + writel(dstbuf, &devcfg_base->dma_dst_addr); + writel(srclen, &devcfg_base->dma_src_len); + writel(dstlen, &devcfg_base->dma_dst_len); - if ((u32)buf < SZ_1M) { - printf("%s: Bitstream has to be placed up to 1MB (%x)\n", - __func__, (u32)buf); - return FPGA_FAIL; - } + isr_status = readl(&devcfg_base->int_sts); - if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { - u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + /* Polling the PCAP_INIT status for Set */ + ts = get_timer(0); + while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { + if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { + debug("%s: Error: isr = 0x%08X\n", __func__, + isr_status); + debug("%s: Write count = 0x%08X\n", __func__, + readl(&devcfg_base->write_count)); + debug("%s: Read count = 0x%08X\n", __func__, + readl(&devcfg_base->read_count)); - /* - * This might be dangerous but permits to flash if - * ARCH_DMA_MINALIGN is greater than header size - */ - if (new_buf > buf_start) { - debug("%s: Aligned buffer is after buffer start\n", - __func__); - new_buf -= ARCH_DMA_MINALIGN; + return FPGA_FAIL; } + if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { + printf("%s: Timeout wait for DMA to complete\n", + __func__); + return FPGA_FAIL; + } + isr_status = readl(&devcfg_base->int_sts); + } - printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, - (u32)buf_start, (u32)new_buf, swap); - - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); - - swap = SWAP_DONE; - buf = new_buf; - } else if (swap != SWAP_DONE) { - /* For bitstream which are aligned */ - u32 *new_buf = (u32 *)buf; + debug("%s: DMA transfer is done\n", __func__); - printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, - swap); + /* Clear out the DMA status */ + writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - for (i = 0; i < (bsize/4); i++) - new_buf[i] = load_word(&buf_start[i], swap); + return FPGA_SUCCESS; +} - swap = SWAP_DONE; - } +static int zynq_dma_xfer_init(u32 partialbit) +{ + u32 status, control, isr_status; + unsigned long ts; /* Clear loopback bit */ clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK); @@ -297,6 +279,83 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status); } + return FPGA_SUCCESS; +} + +static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) +{ + u32 *new_buf; + u32 i; + + if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { + new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, + (u32)buf, (u32)new_buf, swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + + buf = new_buf; + } else if (swap != SWAP_DONE) { + /* For bitstream which are aligned */ + u32 *new_buf = (u32 *)buf; + + printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__, + swap); + + for (i = 0; i < (len/4); i++) + new_buf[i] = load_word(&buf[i], swap); + } + + return buf; +} + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + unsigned long ts; /* Timestamp */ + u32 partialbit = 0; + u32 isr_status, swap, diff; + u32 *buf_start; + + /* Detect if we are going working with partial or full bitstream */ + if (bsize != desc->size) { + printf("%s: Working with partial bitstream\n", __func__); + partialbit = 1; + } + + buf_start = check_data((u8 *)buf, bsize, &swap); + if (!buf_start) + return FPGA_FAIL; + + /* Check if data is postpone from start */ + diff = (u32)buf_start - (u32)buf; + if (diff) { + printf("%s: Bitstream is not validated yet (diff %x)\n", + __func__, diff); + return FPGA_FAIL; + } + + if ((u32)buf < SZ_1M) { + printf("%s: Bitstream has to be placed up to 1MB (%x)\n", + __func__, (u32)buf); + return FPGA_FAIL; + } + + if (zynq_dma_xfer_init(partialbit)) + return FPGA_FAIL; + + buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); + debug("%s: Source = 0x%08X\n", __func__, (u32)buf); debug("%s: Size = %zu\n", __func__, bsize); @@ -304,37 +363,10 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) flush_dcache_range((u32)buf, (u32)buf + roundup(bsize, ARCH_DMA_MINALIGN)); - /* Set up the transfer */ - writel((u32)buf | 1, &devcfg_base->dma_src_addr); - writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr); - writel(bsize >> 2, &devcfg_base->dma_src_len); - writel(0, &devcfg_base->dma_dst_len); + if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0)) + return FPGA_FAIL; isr_status = readl(&devcfg_base->int_sts); - - /* Polling the PCAP_INIT status for Set */ - ts = get_timer(0); - while (!(isr_status & DEVCFG_ISR_DMA_DONE)) { - if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) { - debug("%s: Error: isr = 0x%08X\n", __func__, - isr_status); - debug("%s: Write count = 0x%08X\n", __func__, - readl(&devcfg_base->write_count)); - debug("%s: Read count = 0x%08X\n", __func__, - readl(&devcfg_base->read_count)); - - return FPGA_FAIL; - } - if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) { - printf("%s: Timeout wait for DMA to complete\n", - __func__); - return FPGA_FAIL; - } - isr_status = readl(&devcfg_base->int_sts); - } - - debug("%s: DMA transfer is done\n", __func__); - /* Check FPGA configuration completion */ ts = get_timer(0); while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) { @@ -348,9 +380,6 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) debug("%s: FPGA config done\n", __func__); - /* Clear out the DMA status */ - writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts); - if (!partialbit) zynq_slcr_devcfg_enable(); -- cgit v1.2.3 From 31081859855e606ca06131c3a14e099e043d39f0 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Thu, 13 Mar 2014 11:57:34 +0530 Subject: fpga: zynq: Use helper function zynq_validate_bitstream Use helper function zynq_validate_bitstream so that the code can be reused easily for different cases of dma transfer. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index ef6d1caca41..c066f21d79f 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -320,20 +320,20 @@ static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap) return buf; } -static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf, + size_t bsize, u32 blocksize, u32 *swap, + u32 *partialbit) { - unsigned long ts; /* Timestamp */ - u32 partialbit = 0; - u32 isr_status, swap, diff; u32 *buf_start; + u32 diff; /* Detect if we are going working with partial or full bitstream */ if (bsize != desc->size) { printf("%s: Working with partial bitstream\n", __func__); - partialbit = 1; + *partialbit = 1; } + buf_start = check_data((u8 *)buf, blocksize, swap); - buf_start = check_data((u8 *)buf, bsize, &swap); if (!buf_start) return FPGA_FAIL; @@ -351,7 +351,25 @@ static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_FAIL; } - if (zynq_dma_xfer_init(partialbit)) + if (zynq_dma_xfer_init(*partialbit)) + return FPGA_FAIL; + + return 0; +} + + +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +{ + unsigned long ts; /* Timestamp */ + u32 partialbit = 0; + u32 isr_status, swap; + + /* + * send bsize inplace of blocksize as it was not a bitstream + * in chunks + */ + if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap, + &partialbit)) return FPGA_FAIL; buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap); -- cgit v1.2.3 From 0b2e13d9ccbe56e32dc674cf896b2fb55684368c Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Mon, 14 Apr 2014 18:42:06 +0800 Subject: powerpc/85xx: Add T4240RDB board support T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h] --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 + board/freescale/t4rdb/Makefile | 12 + board/freescale/t4rdb/ddr.c | 118 ++++++ board/freescale/t4rdb/ddr.h | 78 ++++ board/freescale/t4rdb/eth.c | 146 +++++++ board/freescale/t4rdb/law.c | 28 ++ board/freescale/t4rdb/pci.c | 23 ++ board/freescale/t4rdb/t4240rdb.c | 125 ++++++ board/freescale/t4rdb/t4_pbi.cfg | 31 ++ board/freescale/t4rdb/t4_rcw.cfg | 7 + board/freescale/t4rdb/t4rdb.h | 18 + board/freescale/t4rdb/tlb.c | 111 ++++++ boards.cfg | 1 + drivers/mmc/fsl_esdhc.c | 2 +- include/configs/T4240RDB.h | 752 +++++++++++++++++++++++++++++++++++ 15 files changed, 1453 insertions(+), 1 deletion(-) create mode 100644 board/freescale/t4rdb/Makefile create mode 100644 board/freescale/t4rdb/ddr.c create mode 100644 board/freescale/t4rdb/ddr.h create mode 100644 board/freescale/t4rdb/eth.c create mode 100644 board/freescale/t4rdb/law.c create mode 100644 board/freescale/t4rdb/pci.c create mode 100644 board/freescale/t4rdb/t4240rdb.c create mode 100644 board/freescale/t4rdb/t4_pbi.cfg create mode 100644 board/freescale/t4rdb/t4_rcw.cfg create mode 100644 board/freescale/t4rdb/t4rdb.h create mode 100644 board/freescale/t4rdb/tlb.c create mode 100644 include/configs/T4240RDB.h (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index f1813151346..1a3cb339874 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_BASE(1, 307), SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile new file mode 100644 index 00000000000..f7f7fc01774 --- /dev/null +++ b/board/freescale/t4rdb/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += ddr.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c new file mode 100644 index 00000000000..5a43c1bc78f --- /dev/null +++ b/board/freescale/t4rdb/ddr.c @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data\n" + "rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h new file mode 100644 index 00000000000..7b854767e7a --- /dev/null +++ b/board/freescale/t4rdb/ddr.h @@ -0,0 +1,78 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c new file mode 100644 index 00000000000..d220475b5a8 --- /dev/null +++ b/board/freescale/t4rdb/eth.c @@ -0,0 +1,146 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "t4rdb.h" + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + if (srds_prtcl_s1 == 28) { + /* SGMII */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); + } else { + puts("Invalid SerDes1 protocol for T4240RDB\n"); + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + if (srds_prtcl_s2 == 56) { + /* SGMII && XFI */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); + } else { + puts("Invalid SerDes2 protocol for T4240RDB\n"); + } + + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c new file mode 100644 index 00000000000..1f5876885c0 --- /dev/null +++ b/board/freescale/t4rdb/law.c @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c new file mode 100644 index 00000000000..6387a20caec --- /dev/null +++ b/board/freescale/t4rdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c new file mode 100644 index 00000000000..5448c86c482 --- /dev/null +++ b/board/freescale/t4rdb/t4240rdb.c @@ -0,0 +1,125 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t4rdb.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sRDB, ", cpu->name); + + puts("SERDES Reference Clocks:\n"); + printf(" SERDES1=100MHz SERDES2=156.25MHz\n" + " SERDES3=100MHz SERDES4=100MHz\n"); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * = + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int rcwsrc; + + /* RCW section SW3[4] */ + rcwsrc = 0x0; + puts("RCW source = "); + switch (rcwsrc & 0x1) { + case 0x1: + puts("SDHC/eMMC\n"); + break; + default: + puts("I2C normal addressing\n"); + break; + } +} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg new file mode 100644 index 00000000000..c9f8ced2a3b --- /dev/null +++ b/board/freescale/t4rdb/t4_pbi.cfg @@ -0,0 +1,31 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#slow mdio clock +095fc030 00008148 +095fd030 00808148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg new file mode 100644 index 00000000000..13408bd01fb --- /dev/null +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 28_56_2_10 +16070019 18101916 00000000 00000000 +70701050 00448c00 6c020000 f5000000 +00000000 ee0000ee 00000000 000287fc +00000000 50000000 00000000 00000028 diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h new file mode 100644 index 00000000000..fb25d43291e --- /dev/null +++ b/board/freescale/t4rdb/t4rdb.h @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T4RDB_H__ +#define __T4RDB_H__ + +#undef CONFIG_SYS_NUM_FM1_DTSEC +#undef CONFIG_SYS_NUM_FM2_DTSEC +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c new file mode 100644 index 00000000000..4b50bcd09b0 --- /dev/null +++ b/board/freescale/t4rdb/tlb.c @@ -0,0 +1,111 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 512K SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_512K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 9d90550794c..b7c6da95a29 100644 --- a/boards.cfg +++ b/boards.cfg @@ -983,6 +983,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4c3b93d413d..50cba64d99a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h new file mode 100644 index 00000000000..b1a8053a539 --- /dev/null +++ b/include/configs/T4240RDB.h @@ -0,0 +1,752 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T4240 RDB board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_T4240RDB +#define CONFIG_PHYS_64BIT + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#endif + +#define CONFIG_DDR_ECC + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x54 +#define SPD_EEPROM_ADDRESS3 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_CORTINA +#define CONFIG_CORTINA_FW_ADDR 0xefe00000 +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define CONFIG_PHY_TERANETICS +#define SGMII_PHY_ADDR1 0x0 +#define SGMII_PHY_ADDR2 0x1 +#define SGMII_PHY_ADDR3 0x2 +#define SGMII_PHY_ADDR4 0x3 +#define SGMII_PHY_ADDR5 0x4 +#define SGMII_PHY_ADDR6 0x5 +#define SGMII_PHY_ADDR7 0x6 +#define SGMII_PHY_ADDR8 0x7 +#define FM1_10GEC1_PHY_ADDR 0x10 +#define FM1_10GEC2_PHY_ADDR 0x11 +#define FM2_10GEC1_PHY_ADDR 0x12 +#define FM2_10GEC2_PHY_ADDR 0x13 +#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR +#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR +#endif + + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define __USB_PHY_TYPE utmi + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#define CTRL_INTLV_PREFERED 3way_4KB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240rdb/t4240rdb.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#ifdef CONFIG_SECURE_BOOT +/* Secure Boot target was not getting build for T4240 because of + * increased binary size. So the size is being reduced by removing USB + * which is anyways not used in Secure Environment. + */ +#undef CONFIG_CMD_USB +#endif + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 3a7ed5aa232da1d2836b5d3962e59e685307122e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Tue, 22 Apr 2014 18:21:37 +0800 Subject: powerpc/fman/memac: use default MDIO_HOLD value Current driver uses a Maximum value for MDIO_HOLD when doing 10G MDIO access, this is due to an errata A-006260 on T4 rev1.0 which is fixed on rev2.0, so remove the maximum value to use the default value for rev2.0. Signed-off-by: Shaohui Xie --- drivers/net/fm/memac_phy.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c index 2f4bc11a6c2..de9c0e9cd28 100644 --- a/drivers/net/fm/memac_phy.c +++ b/drivers/net/fm/memac_phy.c @@ -29,10 +29,8 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) @@ -76,10 +74,8 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, c45 = 0; /* clause 22 */ dev_addr = regnum & 0x1f; clrbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - } else { + } else setbits_be32(®s->mdio_stat, MDIO_STAT_ENC); - setbits_be32(®s->mdio_stat, MDIO_STAT_HOLD_15_CLK); - } /* Wait till the bus is free */ while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY) -- cgit v1.2.3 From 5122dfae5d3cd68e0b6e5e08597df91ba79770aa Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 25 Apr 2014 16:31:22 +0800 Subject: powerpc/85xx: add T4080 SoC support The T4080 SoC is a low-power version of the T4160. T4080 combines 4 dual-threaded Power Architecture e6500 cores with single cluster and two memory complexes. Signed-off-by: Shengzhou Liu --- arch/powerpc/cpu/mpc85xx/Makefile | 2 ++ arch/powerpc/cpu/mpc85xx/cpu.c | 24 ++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 9 ++++++++- arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 1 + arch/powerpc/include/asm/config_mpc85xx.h | 16 +++++++++++----- arch/powerpc/include/asm/fsl_errata.h | 2 ++ arch/powerpc/include/asm/immap_85xx.h | 6 ++++-- arch/powerpc/include/asm/processor.h | 1 + drivers/net/fm/Makefile | 1 + 11 files changed, 57 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 409478539ec..ad26b432f18 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o obj-$(CONFIG_PPC_P5040) += p5040_ids.o obj-$(CONFIG_PPC_T4240) += t4240_ids.o obj-$(CONFIG_PPC_T4160) += t4240_ids.o +obj-$(CONFIG_PPC_T4080) += t4240_ids.o obj-$(CONFIG_PPC_B4420) += b4860_ids.o obj-$(CONFIG_PPC_B4860) += b4860_ids.o obj-$(CONFIG_PPC_T1040) += t1040_ids.o @@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o obj-$(CONFIG_PPC_P5040) += p5040_serdes.o obj-$(CONFIG_PPC_T4240) += t4240_serdes.o obj-$(CONFIG_PPC_T4160) += t4240_serdes.o +obj-$(CONFIG_PPC_T4080) += t4240_serdes.o obj-$(CONFIG_PPC_B4420) += b4860_serdes.o obj-$(CONFIG_PPC_B4860) += b4860_serdes.o obj-$(CONFIG_BSC9132) += bsc9132_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 12e8e10d483..684d4007e48 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -77,6 +77,30 @@ int checkcpu (void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); +#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) + if (SVR_SOC_VER(svr) == SVR_T4080) { + ccsr_rcpm_t *rcpm = + (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + + setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || + FSL_CORENET_DEVDISR2_DTSEC1_9); + setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); + setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); + + /* It needs SW to disable core4~7 as HW design sake on T4080 */ + for (i = 4; i < 8; i++) + cpu_disable(i); + + /* request core4~7 into PH20 state, prior to entering PCL10 + * state, all cores in cluster should be placed in PH20 state. + */ + setbits_be32(&rcpm->pcph20setr, 0xf0); + + /* put the 2nd cluster into PCL10 state */ + setbits_be32(&rcpm->clpcl10setr, 1 << 1); + } +#endif + if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 36ef23232ed..7e2746412bd 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -462,10 +462,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); int enable_cluster_l2(void) { int i = 0; - u32 cluster; + u32 cluster, svr = get_svr(); ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache; + /* only the L2 of first cluster should be enabled as expected on T4080, + * but there is no EOC in the first cluster as HW sake, so return here + * to skip enabling L2 cache of the 2nd cluster. + */ + if (SVR_SOC_VER(svr) == SVR_T4080) + return 0; + cluster = in_be32(&gur->tp_cluster[i].lower); if (cluster & TP_CLUSTER_EOC) return 0; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index d516d4e4a62..3236f6a5da6 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info) * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0 * it uses 6. */ -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) if (SVR_MAJ(get_svr()) >= 2) mem_pll_rat *= 2; #endif diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c index ff55e3c357c..1f99a0a8978 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c @@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = { {18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}}, {} }; -#elif defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080) static const struct serdes_config serdes1_cfg_tbl[] = { /* SerDes 1 */ {1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 35795c4fbe7..dfedc536ffb 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -62,6 +62,7 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), CPU_TYPE_ENTRY(T4160, T4160, 0), + CPU_TYPE_ENTRY(T4080, T4080, 4), CPU_TYPE_ENTRY(B4860, B4860, 0), CPU_TYPE_ENTRY(G4860, G4860, 0), CPU_TYPE_ENTRY(G4060, G4060, 0), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0d6eb491f1a..8a7d4d8a1dc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -595,7 +595,8 @@ #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR -#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define CONFIG_E6500 #define CONFIG_SYS_PPC64 /* 64-bit core */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ @@ -611,13 +612,18 @@ #define CONFIG_SYS_NUM_FM2_10GEC 2 #define CONFIG_NUM_DDR_CONTROLLERS 3 #else -#define CONFIG_MAX_CPUS 8 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } -#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_NUM_FM2_DTSEC 7 +#define CONFIG_SYS_NUM_FM2_DTSEC 8 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#if defined(CONFIG_PPC_T4160) +#define CONFIG_MAX_CPUS 8 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#elif defined(CONFIG_PPC_T4080) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1 } +#endif #endif #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 #define CONFIG_SYS_FSL_NUM_LAWS 32 diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index d820121ee3a..64da4bb3bae 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -16,6 +16,7 @@ static inline bool has_erratum_a006379(void) u32 svr = get_svr(); if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || + ((SVR_SOC_VER(svr) == SVR_T4080) && SVR_MAJ(svr) <= 1) || ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || @@ -49,6 +50,7 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T4240: case SVR_T4160: + case SVR_T4080: return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 741b8618d11..eff573b5ade 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1748,7 +1748,8 @@ typedef struct ccsr_gur { /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */ #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 @@ -1848,7 +1849,8 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 #endif -#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) +#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \ + defined(CONFIG_PPC_T4080) #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 72f30feee62..a6f121e113a 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1111,6 +1111,7 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_T4080 0x824102 #define SVR_C291 0x850000 #define SVR_C292 0x850020 #define SVR_C293 0x850030 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index ee5d7689377..5ae3b167a93 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -32,5 +32,6 @@ obj-$(CONFIG_PPC_T2080) += t2080.o obj-$(CONFIG_PPC_T2081) += t2080.o obj-$(CONFIG_PPC_T4240) += t4240.o obj-$(CONFIG_PPC_T4160) += t4240.o +obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o -- cgit v1.2.3 From ca721fb292c0d17c586caf1993a22a10f6fffd9c Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Wed, 30 Apr 2014 16:45:31 +0800 Subject: qe: disable qe when qe-ucode fails to be uploaded for "deep sleep" when qe-ucode fails to be uploaded, "deep sleep" will hang. if there is no qe-ucode, disable qe module for platforms which support "deep sleep" Signed-off-by: Zhao Qiang --- drivers/qe/qe.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index b1da75ec4d9..9c5fbd1d694 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -14,6 +14,8 @@ #include "asm/immap_qe.h" #include "qe.h" +#define MPC85xx_DEVDISR_QE_DISABLE 0x1 + qe_map_t *qe_immr = NULL; static qe_snum_t snums[QE_NUM_OF_SNUM]; @@ -317,7 +319,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) size_t calc_size = sizeof(struct qe_firmware); size_t length; const struct qe_header *hdr; - +#ifdef CONFIG_DEEP_SLEEP + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif if (!firmware) { printf("Invalid address\n"); return -EINVAL; @@ -330,6 +334,9 @@ int qe_upload_firmware(const struct qe_firmware *firmware) if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') || (hdr->magic[2] != 'F')) { printf("Not a microcode\n"); +#ifdef CONFIG_DEEP_SLEEP + setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE); +#endif return -EPERM; } -- cgit v1.2.3 From fab356a0b87d57d474d6e87408f1ede98a503150 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 May 2014 17:46:26 +0200 Subject: mvtwsi: Fix clock programming The TWSI_FREQUENCY macro was wrong in 2 ways: 1) It was casting the result of the calculations to an u8, while i2c clk rates are often >= 100Khz which won't fit in a u8, drop the cast. 2) It had an extra factor of 2 in the divider which neither the datasheet nor the Linux driver have. The comment for the default value was wrongly saying that m lives in bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct shift by 3 used in i2c_init(). While at it remove the unused twsi_actual_speed variable. Signed-off-by: Hans de Goede --- drivers/i2c/mvtwsi.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 90c83879182..b44944378a9 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -216,7 +216,7 @@ static int twsi_stop(int status) */ #define TWSI_FREQUENCY(m, n) \ - ((u8) (CONFIG_SYS_TCLK / (10 * (m + 1) * 2 * (1 << n)))) + (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) /* * These are required to be reprogrammed before enabling the controller @@ -225,10 +225,8 @@ static int twsi_stop(int status) * twsi_slave_address left uninitialized lest checkpatch.pl complains. */ -/* Baudrate generator: m (bits 7..4) =4, n (bits 3..0) =4 */ +/* Baudrate generator: m (bits 6..3) = 8, n (bits 2..0) = 4 */ static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default frequency corresponding to default m=4, n=4 */ -static u8 twsi_actual_speed = TWSI_FREQUENCY(4, 4); /* Default slave address is 0 (so is an uninitialized static) */ static u8 twsi_slave_address; @@ -279,7 +277,6 @@ void i2c_init(int requested_speed, int slaveadd) } /* save baud rate and slave for later calls to twsi_reset */ twsi_baud_rate = baud; - twsi_actual_speed = highest_speed; twsi_slave_address = slaveadd; /* reset controller */ twsi_reset(); -- cgit v1.2.3 From 2072e7262965bb48d7fffb1e283101e6ed8b21a8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 May 2014 17:46:27 +0200 Subject: mvtwsi: Remove unnecessary twsi_baud_rate and twsi_slave_address globals These are used only once, so their is no need to have them global. This also stops mvtwsi from using any bss vars making it easier to use before dram init (to talk to the pmic to set the dram voltage). Signed-off-by: Hans de Goede --- drivers/i2c/mvtwsi.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index b44944378a9..5ba0e038624 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -218,25 +218,13 @@ static int twsi_stop(int status) #define TWSI_FREQUENCY(m, n) \ (CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n))) -/* - * These are required to be reprogrammed before enabling the controller - * because a reset loses them. - * Default values come from the spec, but a twsi_reset will change them. - * twsi_slave_address left uninitialized lest checkpatch.pl complains. - */ - -/* Baudrate generator: m (bits 6..3) = 8, n (bits 2..0) = 4 */ -static u8 twsi_baud_rate = 0x44; /* baudrate at controller reset */ -/* Default slave address is 0 (so is an uninitialized static) */ -static u8 twsi_slave_address; - /* * Reset controller. * Called at end of i2c_init unsuccessful i2c transactions. * Controller reset also resets the baud rate and slave address, so * re-establish them. */ -static void twsi_reset(void) +static void twsi_reset(u8 baud_rate, u8 slave_address) { /* ensure controller will be enabled by any twsi*() function */ twsi_control_flags = MVTWSI_CONTROL_TWSIEN; @@ -245,9 +233,9 @@ static void twsi_reset(void) /* wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); /* set baud rate */ - writel(twsi_baud_rate, &twsi->baudrate); + writel(baud_rate, &twsi->baudrate); /* set slave address even though we don't use it */ - writel(twsi_slave_address, &twsi->slave_address); + writel(slave_address, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); /* assert STOP but don't care for the result */ (void) twsi_stop(0); @@ -275,11 +263,8 @@ void i2c_init(int requested_speed, int slaveadd) } } } - /* save baud rate and slave for later calls to twsi_reset */ - twsi_baud_rate = baud; - twsi_slave_address = slaveadd; /* reset controller */ - twsi_reset(); + twsi_reset(baud, slaveadd); } /* -- cgit v1.2.3 From ffc8667acf5c01e2b1ab7b7bb640ddaf2d1f2784 Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Wed, 16 Apr 2014 16:40:52 +0800 Subject: net: phy/vitesse: Add support for VSC8664 phy module This patch adds support for VSC8664 PHY module which can be found on Freescale's T4240RDB boards. Signed-off-by: Chunhe Lan Reviewed-by: York Sun --- drivers/net/phy/vitesse.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'drivers') diff --git a/drivers/net/phy/vitesse.c b/drivers/net/phy/vitesse.c index 3a55d271a53..c58fe50b720 100644 --- a/drivers/net/phy/vitesse.c +++ b/drivers/net/phy/vitesse.c @@ -58,6 +58,14 @@ #define MIIM_VSC8514_18G_QSGMII 0x80e0 #define MIIM_VSC8514_18G_CMDSTAT 0x8000 +/* Vitesse VSC8664 Control/Status Register */ +#define MIIM_VSC8664_SERDES_AND_SIGDET 0x13 +#define MIIM_VSC8664_ADDITIONAL_DEV 0x16 +#define MIIM_VSC8664_EPHY_CON 0x17 +#define MIIM_VSC8664_LED_CON 0x1E + +#define PHY_EXT_PAGE_ACCESS_EXTENDED 0x0001 + /* CIS8201 */ static int vitesse_config(struct phy_device *phydev) { @@ -244,6 +252,33 @@ static int vsc8514_config(struct phy_device *phydev) return 0; } +static int vsc8664_config(struct phy_device *phydev) +{ + u32 val; + + /* Enable MAC interface auto-negotiation */ + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON); + val |= (1 << 13); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_EPHY_CON, val); + + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, + PHY_EXT_PAGE_ACCESS_EXTENDED); + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET); + val |= (1 << 11); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_SERDES_AND_SIGDET, val); + phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0); + + /* Enable LED blink */ + val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON); + val &= ~(1 << 2); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8664_LED_CON, val); + + genphy_config_aneg(phydev); + + return 0; +} + static struct phy_driver VSC8211_driver = { .name = "Vitesse VSC8211", .uid = 0xfc4b0, @@ -334,6 +369,16 @@ static struct phy_driver VSC8662_driver = { .shutdown = &genphy_shutdown, }; +static struct phy_driver VSC8664_driver = { + .name = "Vitesse VSC8664", + .uid = 0x70660, + .mask = 0xffff0, + .features = PHY_GBIT_FEATURES, + .config = &vsc8664_config, + .startup = &vitesse_startup, + .shutdown = &genphy_shutdown, +}; + /* Vitesse bought Cicada, so we'll put these here */ static struct phy_driver cis8201_driver = { .name = "CIS8201", @@ -366,6 +411,7 @@ int phy_vitesse_init(void) phy_register(&VSC8574_driver); phy_register(&VSC8514_driver); phy_register(&VSC8662_driver); + phy_register(&VSC8664_driver); phy_register(&cis8201_driver); phy_register(&cis8204_driver); -- cgit v1.2.3 From f1a96ec1a9920854c3308a062caca0b339bd1e3b Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Wed, 7 May 2014 10:50:20 +0800 Subject: fsl/pci: Add workaround for erratum A-005434 By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are mapped to 0xF, which is local memory. But for BSC9132, 0xF is CCSR, 0x0 is local memory. Signed-off-by: Minghuan Lian Signed-off-by: Chunhe Lan Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + drivers/pci/fsl_pci_init.c | 9 +++++++-- 3 files changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 9d8acd0aa17..3d37a7614f9 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 check_erratum_a007212(); #endif +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + puts("Work-around for Erratum A-005434 enabled\n"); +#endif return 0; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8a7d4d8a1dc..e124b07b25d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -591,6 +591,7 @@ #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_ERRATUM_A005125 +#define CONFIG_SYS_FSL_ERRATUM_A005434 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 #define CONFIG_ESDHC_HC_BLK_ADDR diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 6317fb13241..3a41b0ec173 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -49,8 +49,13 @@ static void set_inbound_window(volatile pit_t *pi, u64 size) { u32 sz = (__ilog2_u64(size) - 1); - u32 flag = PIWAR_EN | PIWAR_LOCAL | - PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; +#ifdef CONFIG_SYS_FSL_ERRATUM_A005434 + u32 flag = 0; +#else + u32 flag = PIWAR_LOCAL; +#endif + + flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP; out_be32(&pi->pitar, r->phys_start >> 12); out_be32(&pi->piwbar, r->bus_start >> 12); -- cgit v1.2.3 From 15231f6dd14b592e2bdef33f6aea1ca1d88fd1bf Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Thu, 8 May 2014 17:05:26 +0530 Subject: drivers/usb : Define usb control register mask for w1c bits Define and use CONTROL_REGISTER_W1C_MASK to make sure that w1c bits of usb control register do not get reset while writing any other bit Signed-off-by: Nikhil Badola Signed-off-by: Ramneek Mehresh Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 15 ++++++++++----- include/usb/ehci-fsl.h | 2 ++ 2 files changed, 12 insertions(+), 5 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 6cb4d986685..45062e699bd 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -104,15 +104,20 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) - setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); - setbits_be32(&ehci->control, UTMI_PHY_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_UTMI); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); - setbits_be32(&ehci->control, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + USB_EN); } else { - setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI); - clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN); + clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, + PHY_CLK_SEL_ULPI); + clrsetbits_be32(&ehci->control, UTMI_PHY_EN | + CONTROL_REGISTER_W1C_MASK, USB_EN); udelay(1000); /* delay required for PHY Clk to appear */ if (!usb_phy_clk_valid(ehci)) return -EINVAL; diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index c9ee1d5bf62..dd77ad63254 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -11,6 +11,8 @@ #include +#define CONTROL_REGISTER_W1C_MASK 0x00020000 /* W1C: PHY_CLK_VALID */ + /* Global offsets */ #define FSL_SKIP_PCI 0x100 -- cgit v1.2.3