From 4ed4aa20de50661de89dbe7896595e2b0bf44d5c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 12 Nov 2013 14:25:29 +0100 Subject: net: gem: Check if phy was correctly detected As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek --- drivers/net/zynq_gem.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers') diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 6a017a81027..381bca459e1 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -339,6 +339,11 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) phy_config(phydev); phy_startup(phydev); + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return -1; + } + switch (phydev->speed) { case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, -- cgit v1.2.3 From 8475c869c30cbeef1695396b43bc240cc0d35f5a Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:10 +0100 Subject: s5p: gpio: change gpio coding method for s5p gpio. Old s5p gpio coding method was not clean and was not working properly for all parts and banks. New method is clean and easy to extend. Gpio coding mask: 0x000000ff - pin number 0x00ffff00 - bank offset 0xff000000 - part number Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- arch/arm/include/asm/arch-exynos/gpio.h | 245 +++++++++---------------------- arch/arm/include/asm/arch-s5pc1xx/gpio.h | 47 ++++-- board/samsung/trats2/trats2.c | 8 +- drivers/gpio/s5p_gpio.c | 15 +- include/configs/s5p_goni.h | 4 +- include/configs/s5pc210_universal.h | 12 +- include/configs/trats.h | 4 +- 7 files changed, 132 insertions(+), 203 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index 2a19852153b..d6868fa25dd 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -247,180 +247,81 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 - -#define exynos4_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \ - EXYNOS4_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \ - EXYNOS4_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX) - -#define exynos4x12_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \ - EXYNOS4X12_GPIO_PART1_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \ - EXYNOS4X12_GPIO_PART2_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX) - -#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos4x12_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \ - EXYNOS4X12_GPIO_PART3_BASE)->bank)) \ - - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX) - -#define exynos5_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \ - EXYNOS5_GPIO_PART1_BASE)->bank)) \ - - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \ - EXYNOS5_GPIO_PART2_BASE)->bank)) \ - - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX) - -#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \ - EXYNOS5_GPIO_PART3_BASE)->bank)) \ - - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX) - - -/* EXYNOS5420 */ -#define exynos5420_gpio_part1_get_nr(bank, pin) \ - ((((((unsigned int) &(((struct exynos5420_gpio_part1 *)\ - EXYNOS5420_GPIO_PART1_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) - -#define EXYNOS5420_GPIO_PART1_MAX ((sizeof(struct exynos5420_gpio_part1) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part2_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part2 *)\ - EXYNOS5420_GPIO_PART2_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART1_MAX) - -#define EXYNOS5420_GPIO_PART2_MAX ((sizeof(struct exynos5420_gpio_part2) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part3_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part3 *)\ - EXYNOS5420_GPIO_PART3_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART2_MAX) - -#define EXYNOS5420_GPIO_PART3_MAX ((sizeof(struct exynos5420_gpio_part3) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define exynos5420_gpio_part4_get_nr(bank, pin) \ - (((((((unsigned int) &(((struct exynos5420_gpio_part4 *)\ - EXYNOS5420_GPIO_PART4_BASE)->bank)) \ - - EXYNOS5420_GPIO_PART4_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) + EXYNOS5420_GPIO_PART3_MAX) - -#define EXYNOS5420_GPIO_PART4_MAX ((sizeof(struct exynos5420_gpio_part4) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -#define EXYNOS5420_GPIO_PART5_MAX ((sizeof(struct exynos5420_gpio_part5) \ - / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK) - -static inline unsigned int s5p_gpio_base(int nr) +#define S5P_GPIO_PART_SHIFT (24) +#define S5P_GPIO_PART_MASK (0xff) +#define S5P_GPIO_BANK_SHIFT (8) +#define S5P_GPIO_BANK_MASK (0xffff) +#define S5P_GPIO_PIN_MASK (0xff) + +#define S5P_GPIO_SET_PART(x) \ + (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) + +#define S5P_GPIO_GET_PART(x) \ + (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + +#define S5P_GPIO_SET_PIN(x) \ + ((x) & S5P_GPIO_PIN_MASK) + +#define EXYNOS4_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos4_gpio_part##part *) \ + EXYNOS4_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS4_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define EXYNOS4X12_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos4x12_gpio_part##part *) \ + EXYNOS4X12_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS4X12_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define EXYNOS5_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ + EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS5_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define EXYNOS5420_GPIO_SET_BANK(part, bank) \ + ((((unsigned)&(((struct exynos5420_gpio_part##part *) \ + EXYNOS5420_GPIO_PART##part##_BASE)->bank) \ + - EXYNOS5420_GPIO_PART##part##_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define exynos4_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS4_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) + +#define exynos4x12_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS4X12_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) + +#define exynos5420_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS5420_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) + +#define exynos5_gpio_get(part, bank, pin) \ + (S5P_GPIO_SET_PART(part) | \ + EXYNOS5_GPIO_SET_BANK(part, bank) | \ + S5P_GPIO_SET_PIN(pin)) + +static inline unsigned int s5p_gpio_base(int gpio) { - if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { - if (nr < EXYNOS5420_GPIO_PART1_MAX) - return EXYNOS5420_GPIO_PART1_BASE; - else if (nr < EXYNOS5420_GPIO_PART2_MAX) - return EXYNOS5420_GPIO_PART2_BASE; - else if (nr < EXYNOS5420_GPIO_PART3_MAX) - return EXYNOS5420_GPIO_PART3_BASE; - else - return EXYNOS5420_GPIO_PART4_BASE; - } else { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return EXYNOS5_GPIO_PART1_BASE; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART2_BASE; - else - return EXYNOS5_GPIO_PART3_BASE; - } - } else if (cpu_is_exynos4()) { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return EXYNOS4_GPIO_PART1_BASE; - else - return EXYNOS4_GPIO_PART2_BASE; + unsigned gpio_part = S5P_GPIO_GET_PART(gpio); + + switch (gpio_part) { + case 1: + return samsung_get_base_gpio_part1(); + case 2: + return samsung_get_base_gpio_part2(); + case 3: + return samsung_get_base_gpio_part3(); + case 4: + return samsung_get_base_gpio_part4(); + default: + return 0; } - - return 0; -} - -static inline unsigned int s5p_gpio_part_max(int nr) -{ - if (cpu_is_exynos5()) { - if (proid_is_exynos5420()) { - if (nr < EXYNOS5420_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5420_GPIO_PART2_MAX) - return EXYNOS5420_GPIO_PART1_MAX; - else if (nr < EXYNOS5420_GPIO_PART3_MAX) - return EXYNOS5420_GPIO_PART2_MAX; - else if (nr < EXYNOS5420_GPIO_PART4_MAX) - return EXYNOS5420_GPIO_PART3_MAX; - else - return EXYNOS5420_GPIO_PART4_MAX; - } else { - if (nr < EXYNOS5_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS5_GPIO_PART2_MAX) - return EXYNOS5_GPIO_PART1_MAX; - else - return EXYNOS5_GPIO_PART2_MAX; - } - } else if (cpu_is_exynos4()) { - if (proid_is_exynos4412()) { - if (nr < EXYNOS4X12_GPIO_PART1_MAX) - return 0; - else if (nr < EXYNOS4X12_GPIO_PART2_MAX) - return EXYNOS4X12_GPIO_PART1_MAX; - else - return EXYNOS4X12_GPIO_PART2_MAX; - } else { - if (nr < EXYNOS4_GPIO_PART1_MAX) - return 0; - else - return EXYNOS4_GPIO_PART1_MAX; - } - } - - return 0; } #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index ac60fe63863..da8df74a10a 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -125,20 +125,45 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* GPIO pins per bank */ #define GPIO_PER_BANK 8 -static inline unsigned int s5p_gpio_base(int nr) -{ - return S5PC110_GPIO_BASE; -} +#define S5P_GPIO_PART_SHIFT (24) +#define S5P_GPIO_PART_MASK (0xff) +#define S5P_GPIO_BANK_SHIFT (8) +#define S5P_GPIO_BANK_MASK (0xffff) +#define S5P_GPIO_PIN_MASK (0xff) + +#define S5P_GPIO_SET_PART(x) \ + (((x) & S5P_GPIO_PART_MASK) << S5P_GPIO_PART_SHIFT) + +#define S5P_GPIO_GET_PART(x) \ + (((x) >> S5P_GPIO_PART_SHIFT) & S5P_GPIO_PART_MASK) + +#define S5P_GPIO_SET_PIN(x) \ + ((x) & S5P_GPIO_PIN_MASK) -static inline unsigned int s5p_gpio_part_max(int nr) +#define S5PC100_SET_BANK(bank) \ + (((unsigned)&(((struct s5pc100_gpio *) \ + S5PC100_GPIO_BASE)->bank) - S5PC100_GPIO_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define S5PC110_SET_BANK(bank) \ + ((((unsigned)&(((struct s5pc110_gpio *) \ + S5PC110_GPIO_BASE)->bank) - S5PC110_GPIO_BASE) \ + & S5P_GPIO_BANK_MASK) << S5P_GPIO_BANK_SHIFT) + +#define s5pc100_gpio_get(bank, pin) \ + (S5P_GPIO_SET_PART(0) | \ + S5PC100_SET_BANK(bank) | \ + S5P_GPIO_SET_PIN(pin)) + +#define s5pc110_gpio_get(bank, pin) \ + (S5P_GPIO_SET_PART(0) | \ + S5PC110_SET_BANK(bank) | \ + S5P_GPIO_SET_PIN(pin)) + +static inline unsigned int s5p_gpio_base(int nr) { - return 0; + return samsung_get_base_gpio(); } - -#define s5pc110_gpio_get_nr(bank, pin) \ - ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\ - - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \ - * GPIO_PER_BANK) + pin) #endif /* Pin configurations */ diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index be15357e69f..1e96fdc6af9 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -144,17 +144,17 @@ static void board_init_i2c(void) int get_soft_i2c_scl_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_part2_get_nr(m2, 1); /* I2C9 */ + return exynos4x12_gpio_get(2, m2, 1); /* I2C9 */ else - return exynos4x12_gpio_part1_get_nr(f1, 4); /* I2C8 */ + return exynos4x12_gpio_get(1, f1, 4); /* I2C8 */ } int get_soft_i2c_sda_pin(void) { if (I2C_ADAP_HWNR) - return exynos4x12_gpio_part2_get_nr(m2, 0); /* I2C9 */ + return exynos4x12_gpio_get(2, m2, 0); /* I2C9 */ else - return exynos4x12_gpio_part1_get_nr(f1, 5); /* I2C8 */ + return exynos4x12_gpio_get(1, f1, 5); /* I2C8 */ } #endif diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c index 7eeb96d19ff..11a0472c695 100644 --- a/drivers/gpio/s5p_gpio.c +++ b/drivers/gpio/s5p_gpio.c @@ -9,6 +9,11 @@ #include #include +#define S5P_GPIO_GET_BANK(x) ((x >> S5P_GPIO_BANK_SHIFT) \ + & S5P_GPIO_BANK_MASK) + +#define S5P_GPIO_GET_PIN(x) (x & S5P_GPIO_PIN_MASK) + #define CON_MASK(x) (0xf << ((x) << 2)) #define CON_SFR(x, v) ((v) << ((x) << 2)) @@ -124,17 +129,15 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode) struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned gpio) { - int bank; - unsigned g = gpio - s5p_gpio_part_max(gpio); + unsigned bank = S5P_GPIO_GET_BANK(gpio); + unsigned base = s5p_gpio_base(gpio); - bank = g / GPIO_PER_BANK; - bank *= sizeof(struct s5p_gpio_bank); - return (struct s5p_gpio_bank *) (s5p_gpio_base(gpio) + bank); + return (struct s5p_gpio_bank *)(base + bank); } int s5p_gpio_get_pin(unsigned gpio) { - return gpio % GPIO_PER_BANK; + return S5P_GPIO_GET_PIN(gpio); } /* Common GPIO API */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 0590d201cea..4cdf937a60c 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -208,8 +208,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get_nr(j4, 3) -#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get_nr(j4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL s5pc110_gpio_get(j4, 3) +#define CONFIG_SOFT_I2C_GPIO_SDA s5pc110_gpio_get(j4, 0) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index d9e4c5683f8..02a1c99a831 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -229,8 +229,8 @@ /* * I2C Settings */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(1, b, 7) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(1, b, 6) #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ @@ -253,10 +253,10 @@ */ #define CONFIG_SOFT_SPI #define CONFIG_SOFT_SPI_MODE SPI_MODE_3 -#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_part2_get_nr(y3, 1) -#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_part2_get_nr(y3, 3) -#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_part2_get_nr(y3, 0) -#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_part2_get_nr(y4, 3) +#define CONFIG_SOFT_SPI_GPIO_SCLK exynos4_gpio_get(2, y3, 1) +#define CONFIG_SOFT_SPI_GPIO_MOSI exynos4_gpio_get(2, y3, 3) +#define CONFIG_SOFT_SPI_GPIO_MISO exynos4_gpio_get(2, y3, 0) +#define CONFIG_SOFT_SPI_GPIO_CS exynos4_gpio_get(2, y4, 3) #define SPI_DELAY udelay(1) #undef SPI_INIT diff --git a/include/configs/trats.h b/include/configs/trats.h index fdd8b460b0d..9a927837963 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -287,8 +287,8 @@ #include /* I2C FG */ -#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part2_get_nr(y4, 1) -#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part2_get_nr(y4, 0) +#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_get(2, y4, 1) +#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_get(2, y4, 0) #define CONFIG_POWER #define CONFIG_POWER_I2C -- cgit v1.2.3 From 7f39b0678275c773301da15d3a7cc1ea7ca87171 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:11 +0100 Subject: trats2: Code cleanup. Remove wrong and unused env variables Trats2 is not as GT-I8800. Signed-off-by: Przemyslaw Marczak Acked-by: Jaehoon Chung Cc: Piotr Wilczek Signed-off-by: Minkyu Kang --- board/samsung/trats2/trats2.c | 12 ++---------- drivers/power/battery/bat_trats2.c | 2 +- include/power/max77686_pmic.h | 2 ++ 3 files changed, 5 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index 1e96fdc6af9..feb6c4cccd2 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -72,15 +72,12 @@ static void check_hw_revision(void) int checkboard(void) { puts("Board:\tTRATS2\n"); + printf("HW Revision:\t0x%04x\n", board_rev); + return 0; } #endif -static void show_hw_revision(void) -{ - printf("HW Revision:\t0x%04x\n", board_rev); -} - u32 get_board_rev(void) { return board_rev; @@ -618,11 +615,6 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - setenv("model", "GT-I8800"); - setenv("board", "TRATS2"); - - show_hw_revision(); - return 0; } #endif diff --git a/drivers/power/battery/bat_trats2.c b/drivers/power/battery/bat_trats2.c index f2648329d4d..94015aa41a1 100644 --- a/drivers/power/battery/bat_trats2.c +++ b/drivers/power/battery/bat_trats2.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include static struct battery battery_trats; diff --git a/include/power/max77686_pmic.h b/include/power/max77686_pmic.h index 16e90160894..c2a772a8951 100644 --- a/include/power/max77686_pmic.h +++ b/include/power/max77686_pmic.h @@ -8,6 +8,8 @@ #ifndef __MAX77686_H_ #define __MAX77686_H_ +#include + enum { MAX77686_REG_PMIC_ID = 0x0, MAX77686_REG_PMIC_INTSRC, -- cgit v1.2.3 From 679549d1802f0ee8e66576ecfc766d30b4040983 Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:12 +0100 Subject: samsung: common: Add file for common functions, draw_logo() cleanup. Changes: new file: - board/samsung/common/misc.c depends on: CONFIG_MISC_COMMON - move draw_logo() to misc.c configs: trats, trats2, universal: - enable CONFIG_MISC_COMMON, - enable CONFIG_MISC_INIT_R, - add misc_init_r() and call draw_logo() in it. Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- board/samsung/common/Makefile | 1 + board/samsung/common/misc.c | 41 ++++++++++++++++++++++++++++++++ board/samsung/trats/trats.c | 11 +++++++++ board/samsung/trats2/trats2.c | 4 ++++ board/samsung/universal_c210/universal.c | 11 +++++++++ drivers/video/exynos_fb.c | 28 ---------------------- include/configs/s5pc210_universal.h | 5 ++++ include/configs/trats.h | 5 ++++ include/configs/trats2.h | 6 ++++- include/samsung/misc.h | 8 +++++++ 10 files changed, 91 insertions(+), 29 deletions(-) create mode 100644 board/samsung/common/misc.c create mode 100644 include/samsung/misc.h (limited to 'drivers') diff --git a/board/samsung/common/Makefile b/board/samsung/common/Makefile index 22bd6b197e5..7d2bb8c4a2f 100644 --- a/board/samsung/common/Makefile +++ b/board/samsung/common/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o obj-$(CONFIG_THOR_FUNCTION) += thor.o obj-$(CONFIG_CMD_USB_MASS_STORAGE) += ums.o +obj-$(CONFIG_MISC_COMMON) += misc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_BOARD_COMMON) += board.o diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c new file mode 100644 index 00000000000..f6be8917928 --- /dev/null +++ b/board/samsung/common/misc.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2013 Samsung Electronics + * Przemyslaw Marczak + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_CMD_BMP +void draw_logo(void) +{ + int x, y; + ulong addr; + + addr = panel_info.logo_addr; + if (!addr) { + error("There is no logo data."); + return; + } + + if (panel_info.vl_width >= panel_info.logo_width) { + x = ((panel_info.vl_width - panel_info.logo_width) >> 1); + } else { + x = 0; + printf("Warning: image width is bigger than display width\n"); + } + + if (panel_info.vl_height >= panel_info.logo_height) { + y = ((panel_info.vl_height - panel_info.logo_height) >> 1); + } else { + y = 0; + printf("Warning: image height is bigger than display height\n"); + } + + bmp_display(addr, x, y); +} +#endif /* CONFIG_CMD_BMP */ diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index 640a193dc21..a644b608cdb 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -786,3 +786,14 @@ void init_panel_info(vidinfo_t *vid) setenv("lcdinfo", "lcd=s6e8ax0"); } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index feb6c4cccd2..4834f9010d7 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -615,6 +615,10 @@ void init_panel_info(vidinfo_t *vid) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif return 0; } #endif diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index 3feef3f7777..2b8c69be1d0 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -511,3 +511,14 @@ int board_init(void) return 0; } + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_BMP + if (panel_info.logo_on) + draw_logo(); +#endif + return 0; +} +#endif diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 7d4c6e092df..00a0a11ed4e 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -62,31 +62,6 @@ static void exynos_lcd_init(vidinfo_t *vid) lcd_set_flush_dcache(1); } -#ifdef CONFIG_CMD_BMP -static void draw_logo(void) -{ - int x, y; - ulong addr; - - if (panel_width >= panel_info.logo_width) { - x = ((panel_width - panel_info.logo_width) >> 1); - } else { - x = 0; - printf("Warning: image width is bigger than display width\n"); - } - - if (panel_height >= panel_info.logo_height) { - y = ((panel_height - panel_info.logo_height) >> 1) - 4; - } else { - y = 0; - printf("Warning: image height is bigger than display height\n"); - } - - addr = panel_info.logo_addr; - bmp_display(addr, x, y); -} -#endif - void __exynos_cfg_lcd_gpio(void) { } @@ -323,9 +298,6 @@ void lcd_enable(void) if (panel_info.logo_on) { memset((void *) gd->fb_base, 0, panel_width * panel_height * (NBITS(panel_info.vl_bpix) >> 3)); -#ifdef CONFIG_CMD_BMP - draw_logo(); -#endif } lcd_panel_on(&panel_info); diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 02a1c99a831..6b98bed7b4f 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -269,6 +269,11 @@ void universal_spi_sda(int bit); int universal_spi_read(void); #endif +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* * LCD Settings */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 9a927837963..7a9c60b3491 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -306,6 +306,11 @@ #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD diff --git a/include/configs/trats2.h b/include/configs/trats2.h index 83633b074d5..b4ca1ff8570 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -277,7 +277,6 @@ #define CONFIG_EFI_PARTITION #define CONFIG_PARTITION_UUIDS -#define CONFIG_MISC_INIT_R #define CONFIG_BOARD_EARLY_INIT_F /* I2C */ @@ -318,6 +317,11 @@ int get_soft_i2c_sda_pin(void); #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_USB_CABLE_CHECK +/* Common misc for Samsung */ +#define CONFIG_MISC_COMMON + +#define CONFIG_MISC_INIT_R + /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD diff --git a/include/samsung/misc.h b/include/samsung/misc.h new file mode 100644 index 00000000000..8ea92236f9b --- /dev/null +++ b/include/samsung/misc.h @@ -0,0 +1,8 @@ +#ifndef __SAMSUNG_MISC_COMMON_H__ +#define __SAMSUNG_MISC_COMMON_H__ + +#ifdef CONFIG_CMD_BMP +void draw_logo(void); +#endif + +#endif /* __SAMSUNG_MISC_COMMON_H__ */ -- cgit v1.2.3 From f831b3fe0f532a4f877b2e5877183e16b64cb11a Mon Sep 17 00:00:00 2001 From: Przemyslaw Marczak Date: Wed, 22 Jan 2014 11:24:15 +0100 Subject: video: exynos: fimd: add support for various display color modes Now fimd BPP color mode depends on vl_bpp value in struct "panel_info". There is only 16BPP mode check, default mode is 24BPP. Other fimd modes are usually unneeded and also needs some fimd driver modifications and tests. Signed-off-by: Przemyslaw Marczak Signed-off-by: Minkyu Kang --- drivers/video/exynos_fimd.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index f962c4f0a6e..cebbba7581e 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -73,18 +73,19 @@ static void exynos_fimd_set_par(unsigned int win_id) /* DATAPATH is DMA */ cfg |= EXYNOS_WINCON_DATAPATH_DMA; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_WSWP_ENABLE; - else /* To get output console on LCD */ - cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; + cfg |= EXYNOS_WINCON_HAWSWP_ENABLE; /* dma burst is 16 */ cfg |= EXYNOS_WINCON_BURSTLEN_16WORD; - if (pvid->logo_on) /* To get proprietary LOGO */ - cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; - else /* To get output console on LCD */ + switch (pvid->vl_bpix) { + case 4: cfg |= EXYNOS_WINCON_BPPMODE_16BPP_565; + break; + default: + cfg |= EXYNOS_WINCON_BPPMODE_24BPP_888; + break; + } writel(cfg, (unsigned int)&fimd_ctrl->wincon0 + EXYNOS_WINCON(win_id)); -- cgit v1.2.3 From aceea941b65130459eae1e6faec14768d1ce9d24 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Sat, 25 Jan 2014 12:53:32 +0530 Subject: driver/fsl_pci:Update print to display PCIe generation Current print only display width of PCIe device. Add print to display PCIe generation supported by the device. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- drivers/pci/fsl_pci_init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 2085cd6b9b2..6317fb13241 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -510,8 +510,8 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info) /* Print the negotiated PCIe link width */ pci_hose_read_config_word(hose, dev, pci_lsr, &temp16); - printf("x%d, regs @ 0x%lx\n", (temp16 & 0x3f0 ) >> 4, - pci_info->regs); + printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4, + (temp16 & 0xf), pci_info->regs); hose->current_busno++; /* Start scan with secondary */ pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); -- cgit v1.2.3 From 5b7672fc49af1b771a7e318522b010fd5b11c4ab Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 27 Jan 2014 15:55:20 +0530 Subject: boards/t1040qds: Adds ethernet support for T1040 Enable entherent for T1040QDS. It enables FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 Define MDIO related configs Added eth.c file Update t1040.c to support RGMII and SGMII Update t1040qds.c to support ethernet Define the PHY address Signed-off-by: Arpit Goel Signed-off-by: Bhupesh Sharma Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Prabhakar Kushwaha [York Sun: remove dash from commit message] Signed-off-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 11 + board/freescale/t1040qds/Makefile | 1 + board/freescale/t1040qds/eth.c | 492 ++++++++++++++++++++++++++++++++++ board/freescale/t1040qds/t1040qds.c | 1 + drivers/net/fm/t1040.c | 56 ++++ include/configs/T1040QDS.h | 5 +- 6 files changed, 563 insertions(+), 3 deletions(-) create mode 100644 board/freescale/t1040qds/eth.c (limited to 'drivers') diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 68c3c824533..9d08321f5d3 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1759,6 +1759,17 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 +#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 +#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 +#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 +#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile index 93af9eb6a06..c7470d7cbb2 100644 --- a/board/freescale/t1040qds/Makefile +++ b/board/freescale/t1040qds/Makefile @@ -9,3 +9,4 @@ obj-y += ddr.o obj-$(CONFIG_PCI) += pci.o obj-y += law.o obj-y += tlb.o +obj-y += eth.o diff --git a/board/freescale/t1040qds/eth.c b/board/freescale/t1040qds/eth.c new file mode 100644 index 00000000000..3077b4ae2c5 --- /dev/null +++ b/board/freescale/t1040qds/eth.c @@ -0,0 +1,492 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * The RGMII PHYs are provided by the two on-board PHY connected to + * dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board + * PHY or by the standard four-port SGMII riser card (VSC). + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "../common/qixis.h" + +#include "t1040qds_qixis.h" + +#ifdef CONFIG_FMAN_ENET + /* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks. + * Bank 1 -> Lanes A, B, C, D + * Bank 2 -> Lanes E, F, G, H + */ + + /* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here + * means that the mapping must be determined dynamically, or that the lane + * maps to something other than a board slot. + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs + * housed. + */ +static int riser_phy_addr[] = { + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR, +}; + +/* Slot2 does not have EMI connections */ +#define EMI_NONE 0xFFFFFFFF +#define EMI1_RGMII0 0 +#define EMI1_RGMII1 1 +#define EMI1_SLOT1 2 +#define EMI1_SLOT3 3 +#define EMI1_SLOT4 4 +#define EMI1_SLOT5 5 +#define EMI1_SLOT6 6 +#define EMI1_SLOT7 7 +#define EMI2 8 + +static int mdio_mux[NUM_FM_PORTS]; + +static const char * const mdio_names[] = { + "T1040_QDS_MDIO0", + "T1040_QDS_MDIO1", + "T1040_QDS_MDIO2", + "T1040_QDS_MDIO3", + "T1040_QDS_MDIO4", + "T1040_QDS_MDIO5", + "T1040_QDS_MDIO6", + "T1040_QDS_MDIO7", +}; + +struct t1040_qds_mdio { + u8 muxval; + struct mii_dev *realbus; +}; + +static const char *t1040_qds_mdio_name_for_muxval(u8 muxval) +{ + return mdio_names[muxval]; +} + +struct mii_dev *mii_dev_for_muxval(u8 muxval) +{ + struct mii_dev *bus; + const char *name = t1040_qds_mdio_name_for_muxval(muxval); + + if (!name) { + printf("No bus for muxval %x\n", muxval); + return NULL; + } + + bus = miiphy_get_dev_by_name(name); + + if (!bus) { + printf("No bus by name %s\n", name); + return NULL; + } + + return bus; +} + +static void t1040_qds_mux_mdio(u8 muxval) +{ + u8 brdcfg4; + if (muxval <= 7) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= ~BRDCFG4_EMISEL_MASK; + brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); + QIXIS_WRITE(brdcfg[4], brdcfg4); + } +} + +static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct t1040_qds_mdio *priv = bus->priv; + + t1040_qds_mux_mdio(priv->muxval); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int t1040_qds_mdio_reset(struct mii_dev *bus) +{ + struct t1040_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int t1040_qds_mdio_init(char *realbusname, u8 muxval) +{ + struct t1040_qds_mdio *pmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate t1040_qds MDIO bus\n"); + return -1; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate t1040_qds private data\n"); + free(bus); + return -1; + } + + bus->read = t1040_qds_mdio_read; + bus->write = t1040_qds_mdio_write; + bus->reset = t1040_qds_mdio_reset; + sprintf(bus->name, t1040_qds_mdio_name_for_muxval(muxval)); + + pmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!pmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(pmdio); + return -1; + } + + pmdio->muxval = muxval; + bus->priv = pmdio; + + return mdio_register(bus); +} + +/* + * Initialize the lane_to_slot[] array. + * + * On the T1040QDS board the mapping is controlled by ?? register. + */ +static void initialize_lane_to_slot(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL) + >> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + + QIXIS_WRITE(cms[0], 0x07); + + switch (serdes1_prtcl) { + case 0x60: + case 0x66: + case 0x67: + case 0x69: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + break; + case 0x86: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + case 0x87: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x89: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[7] = 7; + break; + case 0x8d: + lane_to_slot[1] = 7; + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + lane_to_slot[5] = 3; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0x8F: + case 0x85: + lane_to_slot[1] = 7; + lane_to_slot[2] = 6; + lane_to_slot[3] = 5; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA5: + lane_to_slot[1] = 7; + lane_to_slot[6] = 3; + lane_to_slot[7] = 3; + break; + case 0xA7: + lane_to_slot[1] = 7; + lane_to_slot[7] = 7; + break; + case 0xAA: + lane_to_slot[1] = 7; + lane_to_slot[6] = 7; + lane_to_slot[7] = 7; + break; + case 0x40: + lane_to_slot[2] = 7; + lane_to_slot[3] = 7; + break; + default: + printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n", + serdes1_prtcl); + break; + } +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used, and we recalculate the offset anyway. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + * + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + phy_interface_t intf = fm_info_get_enet_if(port); + char phy[16]; + + /* The RGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_RGMII) { + sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + + /* The SGMII PHY is identified by the MAC connected to it */ + if (intf == PHY_INTERFACE_MODE_SGMII) { + int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 + + port); + u8 slot; + if (lane < 0) + return; + slot = lane_to_slot[lane]; + if (slot) { + /* Slot housing a SGMII riser card */ + sprintf(phy, "phy_s%x_%02x", slot, + (fm_info_get_phy_address(port - FM1_DTSEC1)- + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1)); + fdt_set_phy_handle(fdt, compat, addr, phy); + } + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i, lane, idx; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + idx = i - FM1_DTSEC1; + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + + switch (mdio_mux[i]) { + case EMI1_SLOT3: + fdt_status_okay_by_alias(fdt, "emi1_slot3"); + break; + case EMI1_SLOT5: + fdt_status_okay_by_alias(fdt, "emi1_slot5"); + break; + case EMI1_SLOT6: + fdt_status_okay_by_alias(fdt, "emi1_slot6"); + break; + case EMI1_SLOT7: + fdt_status_okay_by_alias(fdt, "emi1_slot7"); + break; + } + break; + case PHY_INTERFACE_MODE_RGMII: + if (i == FM1_DTSEC4) + fdt_status_okay_by_alias(fdt, "emi1_rgmii0"); + + if (i == FM1_DTSEC5) + fdt_status_okay_by_alias(fdt, "emi1_rgmii1"); + break; + default: + break; + } + } +} +#endif /* #ifdef CONFIG_FMAN_ENET */ + +static void set_brdcfg9_for_gtx_clk(void) +{ + u8 brdcfg9; + brdcfg9 = QIXIS_READ(brdcfg[9]); + brdcfg9 |= (1 << 5); + QIXIS_WRITE(brdcfg[9], brdcfg9); +} + +void t1040_handle_phy_interface_sgmii(int i) +{ + int lane, idx, slot; + idx = i - FM1_DTSEC1; + lane = serdes_get_first_lane(FSL_SRDS_1, + SGMII_FM1_DTSEC1 + idx); + + if (lane < 0) + return; + slot = lane_to_slot[lane]; + + switch (slot) { + case 1: + mdio_mux[i] = EMI1_SLOT1; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 3: + if (FM1_DTSEC4 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC5 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + + mdio_mux[i] = EMI1_SLOT3; + + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 4: + mdio_mux[i] = EMI1_SLOT4; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 5: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT5; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 6: + /* Slot housing a SGMII riser card? */ + fm_info_set_phy_address(i, riser_phy_addr[0]); + mdio_mux[i] = EMI1_SLOT6; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + case 7: + if (FM1_DTSEC1 == i) + fm_info_set_phy_address(i, riser_phy_addr[0]); + if (FM1_DTSEC2 == i) + fm_info_set_phy_address(i, riser_phy_addr[1]); + if (FM1_DTSEC3 == i) + fm_info_set_phy_address(i, riser_phy_addr[2]); + + mdio_mux[i] = EMI1_SLOT7; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); + break; + default: + break; + } + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} +void t1040_handle_phy_interface_rgmii(int i) +{ + fm_info_set_phy_address(i, i == FM1_DTSEC5 ? + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR : + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 : + EMI1_RGMII0; + fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); +} + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + unsigned int i; + + printf("Initializing Fman\n"); + set_brdcfg9_for_gtx_clk(); + + initialize_lane_to_slot(); + + /* Initialize the mdio_mux array so we can recognize empty elements */ + for (i = 0; i < NUM_FM_PORTS; i++) + mdio_mux[i] = EMI_NONE; + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + /* Register the muxing front-ends to the MDIO buses */ + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); + t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); + + /* + * Program on board RGMII PHY addresses. If the SGMII Riser + * card used, we'll override the PHY address later. For any DTSEC that + * is RGMII, we'll also override its PHY address later. We assume that + * DTSEC4 and DTSEC5 are used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_QSGMII: + break; + case PHY_INTERFACE_MODE_SGMII: + t1040_handle_phy_interface_sgmii(i); + break; + + case PHY_INTERFACE_MODE_RGMII: + /* Only DTSEC4 and DTSEC5 can be routed to RGMII */ + t1040_handle_phy_interface_rgmii(i); + break; + default: + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c index de3ea5c2aa2..3dec4473e52 100644 --- a/board/freescale/t1040qds/t1040qds.c +++ b/board/freescale/t1040qds/t1040qds.c @@ -223,6 +223,7 @@ void ft_board_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); #endif } diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 83cf081f3d3..bcc871d8420 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -12,5 +12,61 @@ phy_interface_t fman_port_enet_if(enum fm_port port) { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + /* handle RGMII first */ + if ((port == FM1_DTSEC2) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if ((port == FM1_DTSEC4) && + ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == + FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == + FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + if (port == FM1_DTSEC5) { + if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) + return PHY_INTERFACE_MODE_RGMII; + else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == + FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) + return PHY_INTERFACE_MODE_MII; + else + return PHY_INTERFACE_MODE_NONE; + } + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_QSGMII; + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + return PHY_INTERFACE_MODE_NONE; } diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 8234a828dda..75ea125f539 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -611,9 +611,8 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 -#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -- cgit v1.2.3 From 1b4175d6fa12b8012c119889ad5cc1e65c3cf6ba Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Sat, 18 Jan 2014 12:28:30 +0530 Subject: driver/ifc:Change accessor function to take care of endianness IFC registers can be of type Little Endian or big Endian depending upon Freescale SoC. Here SoC defines the register type of IFC IP. So update acessor functions with common IFC acessor functions to take care both type of endianness. Signed-off-by: Prabhakar Kushwaha Acked-by: York Sun --- README | 6 + arch/powerpc/include/asm/config_mpc85xx.h | 3 + drivers/mtd/nand/fsl_ifc_nand.c | 243 +++++++++++++++--------------- drivers/mtd/nand/fsl_ifc_spl.c | 60 ++++---- include/fsl_ifc.h | 42 ++++-- 5 files changed, 190 insertions(+), 164 deletions(-) (limited to 'drivers') diff --git a/README b/README index 176de61a331..6cdf355446f 100644 --- a/README +++ b/README @@ -472,6 +472,12 @@ The following options need to be configured: Board config to use DDR3. It can be enabled for SoCs with Freescale DDR3 controllers. + CONFIG_SYS_FSL_IFC_BE + Defines the IFC controller register space as Big Endian + + CONFIG_SYS_FSL_IFC_LE + Defines the IFC controller register space as Little Endian + CONFIG_SYS_FSL_PBL_PBI It enables addition of RCW (Power on reset configuration) in built image. Please refer doc/README.pblimage for more details diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 32e19be82fa..56587aebc0b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -22,6 +22,9 @@ #define FSL_DDR_VER_4_7 47 #define FSL_DDR_VER_5_0 50 +/* IP endianness */ +#define CONFIG_SYS_FSL_IFC_BE + /* Number of TLB CAM entries we have on FSL Book-E chips */ #if defined(CONFIG_E500MC) #define CONFIG_SYS_NUM_TLBCAMS 64 diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 1808a7ffba8..be5a16a1ba9 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -230,8 +230,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) ctrl->page = page_addr; /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, page_addr); - out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); + ifc_out32(&ifc->ifc_nand.row0, page_addr); + ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column); buf_num = page_addr & priv->bufnum_mask; @@ -294,23 +294,23 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int i; /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read/write seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status); if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER) printf("%s: Flash Time Out Error\n", __func__); @@ -324,7 +324,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) int sector_end = sector + chip->ecc.steps - 1; for (i = sector / 4; i <= sector_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = sector; i <= sector_end; i++) { errors = check_read_ecc(mtd, ctrl, eccstat, i); @@ -364,30 +364,30 @@ static void fsl_ifc_do_read(struct nand_chip *chip, /* Program FIR/IFC_NAND_FCR0 for Small/Large page */ if (mtd->writesize > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT)); if (oob) - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT); else - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } } @@ -408,7 +408,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, switch (command) { /* READ0 read the entire buffer to use hardware ECC. */ case NAND_CMD_READ0: { - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); set_addr(mtd, 0, page_addr, 0); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -424,7 +424,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* READOOB reads only the OOB because no ECC is performed. */ case NAND_CMD_READOOB: - out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column); set_addr(mtd, column, page_addr, 1); ctrl->read_bytes = mtd->writesize + mtd->oobsize; @@ -441,19 +441,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, if (command == NAND_CMD_PARAM) timing = IFC_FIR_OP_RBCD; - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (timing << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - command << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, column); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (timing << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + command << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, column); /* * although currently it's 8 bytes for READID, we always read * the maximum 256 bytes(for PARAM) */ - out_be32(&ifc->ifc_nand.nand_fbcr, 256); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 256); ctrl->read_bytes = 256; set_addr(mtd, 0, 0, 0); @@ -468,16 +468,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* ERASE2 uses the block and page address from ERASE1 */ case NAND_CMD_ERASE2: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); ctrl->read_bytes = 0; fsl_ifc_run_command(mtd); return; @@ -494,17 +494,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) | (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_WBCD << + IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT)); } else { nand_fcr0 = ((NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT) | @@ -513,18 +514,18 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | - (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | - (IFC_FIR_OP_RDSTAT << + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) | + (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) | - (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); + (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT)); if (column >= mtd->writesize) nand_fcr0 |= @@ -539,7 +540,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, column -= mtd->writesize; ctrl->oob = 1; } - out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); + ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0); set_addr(mtd, column, page_addr, ctrl->oob); return; } @@ -547,21 +548,21 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ case NAND_CMD_PAGEPROG: if (ctrl->oob) - out_be32(&ifc->ifc_nand.nand_fbcr, - ctrl->index - ctrl->column); + ifc_out32(&ifc->ifc_nand.nand_fbcr, + ctrl->index - ctrl->column); else - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); fsl_ifc_run_command(mtd); return; case NAND_CMD_STATUS: - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -572,10 +573,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command, return; case NAND_CMD_RESET: - out_be32(&ifc->ifc_nand.nand_fir0, - IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT); fsl_ifc_run_command(mtd); return; @@ -647,8 +648,8 @@ static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd) * next byte. */ if (ctrl->index < ctrl->read_bytes) { - data = in_be16((uint16_t *)&ctrl-> - addr[ctrl->index]); + data = ifc_in16((uint16_t *)&ctrl-> + addr[ctrl->index]); ctrl->index += 2; return (uint8_t)data; } @@ -727,12 +728,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) return NAND_STATUS_FAIL; /* Use READ_STATUS command, but wait for the device to be ready */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << - IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.nand_fbcr, 1); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS << + IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 1); set_addr(mtd, 0, 0, 0); ctrl->read_bytes = 1; @@ -741,7 +742,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ctrl->status != IFC_NAND_EVTER_STAT_OPC) return NAND_STATUS_FAIL; - nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr); + nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr); /* Chip sometimes reporting write protect even when it's not */ nand_fsr = nand_fsr | NAND_STATUS_WP; @@ -784,17 +785,17 @@ static void fsl_ifc_ctrl_init(void) ifc_ctrl->regs = IFC_BASE_ADDR; /* clear event registers */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); - out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U); + ifc_out32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U); /* Enable error and event for any detected errors */ - out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, - IFC_NAND_EVTER_EN_OPC_EN | - IFC_NAND_EVTER_EN_PGRDCMPL_EN | - IFC_NAND_EVTER_EN_FTOER_EN | - IFC_NAND_EVTER_EN_WPER_EN); + ifc_out32(&ifc_ctrl->regs->ifc_nand.nand_evter_en, + IFC_NAND_EVTER_EN_OPC_EN | + IFC_NAND_EVTER_EN_PGRDCMPL_EN | + IFC_NAND_EVTER_EN_FTOER_EN | + IFC_NAND_EVTER_EN_WPER_EN); - out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0); } static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) @@ -810,50 +811,50 @@ static void fsl_ifc_sram_init(void) cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; /* Save CSOR and CSOR_ext */ - csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); - csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = ifc_in32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); /* chage PageSize 8K and SpareSize 1K*/ csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); /* READID */ - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); - out_be32(&ifc->ifc_nand.row3, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.row3, 0x0); - out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0); /* Program ROW0/COL0 */ - out_be32(&ifc->ifc_nand.row0, 0x0); - out_be32(&ifc->ifc_nand.col0, 0x0); + ifc_out32(&ifc->ifc_nand.row0, 0x0); + ifc_out32(&ifc->ifc_nand.col0, 0x0); /* set the chip select for NAND Transaction */ - out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + ifc_out32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); /* start read seq */ - out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for NAND Machine complete flag or timeout */ end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); while (end_tick > get_ticks()) { - ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); /* Restore CSOR and CSOR_ext */ - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); - out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + ifc_out32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); } static int fsl_ifc_chip_init(int devnum, u8 *addr) @@ -883,8 +884,8 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { phys_addr_t phys_addr = virt_to_phys(addr); - cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); - csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); + cspr = ifc_in32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr); + csor = ifc_in32(&ifc_ctrl->regs->csor_cs[priv->bank].csor); if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND && (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) { @@ -1004,7 +1005,7 @@ static int fsl_ifc_chip_init(int devnum, u8 *addr) nand->ecc.mode = NAND_ECC_SOFT; } - ver = in_be32(&ifc_ctrl->regs->ifc_rev); + ver = ifc_in32(&ifc_ctrl->regs->ifc_rev); if (ver == FSL_IFC_V1_1_0) fsl_ifc_sram_init(); diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index 6b43496f0ed..2f82f7c5c61 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -60,7 +60,7 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) bufnum_end = bufnum + bufperpage - 1; do { - status = in_be32(&ifc->ifc_nand.nand_evter_stat); + status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); } while (!(status & IFC_NAND_EVTER_STAT_OPC)); if (status & IFC_NAND_EVTER_STAT_FTOER) { @@ -70,14 +70,14 @@ static inline void nand_wait(uchar *buf, int bufnum, int page_size) } for (i = bufnum / 4; i <= bufnum_end / 4; i++) - eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]); + eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); for (i = bufnum; i <= bufnum_end; i++) { if (check_read_ecc(buf, eccstat, i, page_size)) break; } - out_be32(&ifc->ifc_nand.nand_evter_stat, status); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); } static inline int bad_block(uchar *marker, int port_size) @@ -140,38 +140,38 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) blk_size = pages_per_blk * page_size; /* Open Full SRAM mapping for spare are access */ - out_be32(&ifc->ifc_nand.ncfgr, 0x0); + ifc_out32(&ifc->ifc_nand.ncfgr, 0x0); /* Clear Boot events */ - out_be32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); + ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff); /* Program FIR/FCR for Large/Small page */ if (page_size > 512) { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | - (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) | + (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT)); } else { - out_be32(&ifc->ifc_nand.nand_fir0, - (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | - (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | - (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | - (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); - out_be32(&ifc->ifc_nand.nand_fir1, 0x0); - - out_be32(&ifc->ifc_nand.nand_fcr0, - NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); + ifc_out32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) | + (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT)); + ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0); + + ifc_out32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT); } /* Program FBCR = 0 for full page read */ - out_be32(&ifc->ifc_nand.nand_fbcr, 0); + ifc_out32(&ifc->ifc_nand.nand_fbcr, 0); /* Read and copy u-boot on SDRAM from NAND device, In parallel * check for Bad block if found skip it and read continue to @@ -184,11 +184,11 @@ static int nand_load(uint32_t offs, unsigned int uboot_size, void *vdst) bufnum = pg_no & bufnum_mask; sram_addr = bufnum * page_size * 2; - out_be32(&ifc->ifc_nand.row0, pg_no); - out_be32(&ifc->ifc_nand.col0, 0); + ifc_out32(&ifc->ifc_nand.row0, pg_no); + ifc_out32(&ifc->ifc_nand.col0, 0); /* start read */ - out_be32(&ifc->ifc_nand.nandseq_strt, - IFC_NAND_SEQ_STRT_FIR_STRT); + ifc_out32(&ifc->ifc_nand.nandseq_strt, + IFC_NAND_SEQ_STRT_FIR_STRT); /* wait for read to complete */ nand_wait(&buf[sram_addr], bufnum, page_size); diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index be6c10715b1..58a6efdfe05 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -12,6 +12,20 @@ #include #include + +#ifdef CONFIG_SYS_FSL_IFC_LE +#define ifc_in32(a) in_le32(a) +#define ifc_out32(a, v) out_le32(a, v) +#define ifc_in16(a) in_le16(a) +#elif defined(CONFIG_SYS_FSL_IFC_BE) +#define ifc_in32(a) in_be32(a) +#define ifc_out32(a, v) out_be32(a, v) +#define ifc_in16(a) in_be16(a) +#else +#error Neither CONFIG_SYS_FSL_IFC_LE nor CONFIG_SYS_FSL_IFC_BE is defined +#endif + + /* * CSPR - Chip Select Property Register */ @@ -773,20 +787,22 @@ extern void init_early_memctl_regs(void); #define IFC_BASE_ADDR ((struct fsl_ifc *)CONFIG_SYS_IFC_ADDR) -#define get_ifc_cspr_ext(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) -#define get_ifc_cspr(i) (in_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) -#define get_ifc_csor_ext(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) -#define get_ifc_csor(i) (in_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) -#define get_ifc_amask(i) (in_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) -#define get_ifc_ftim(i, j) (in_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) - -#define set_ifc_cspr_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) -#define set_ifc_cspr(i, v) (out_be32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) -#define set_ifc_csor_ext(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) -#define set_ifc_csor(i, v) (out_be32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) -#define set_ifc_amask(i, v) (out_be32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) +#define get_ifc_cspr_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext)) +#define get_ifc_cspr(i) (ifc_in32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr)) +#define get_ifc_csor_ext(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext)) +#define get_ifc_csor(i) (ifc_in32(&(IFC_BASE_ADDR)->csor_cs[i].csor)) +#define get_ifc_amask(i) (ifc_in32(&(IFC_BASE_ADDR)->amask_cs[i].amask)) +#define get_ifc_ftim(i, j) (ifc_in32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j])) + +#define set_ifc_cspr_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) +#define set_ifc_cspr(i, v) (ifc_out32(&(IFC_BASE_ADDR)->cspr_cs[i].cspr, v)) +#define set_ifc_csor_ext(i, v) \ + (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor_ext, v)) +#define set_ifc_csor(i, v) (ifc_out32(&(IFC_BASE_ADDR)->csor_cs[i].csor, v)) +#define set_ifc_amask(i, v) (ifc_out32(&(IFC_BASE_ADDR)->amask_cs[i].amask, v)) #define set_ifc_ftim(i, j, v) \ - (out_be32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + (ifc_out32(&(IFC_BASE_ADDR)->ftim_cs[i].ftim[j], v)) enum ifc_chip_sel { IFC_CS0, -- cgit v1.2.3 From a73ca4789fddce35936dd8decb1522f08b6cb620 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 24 Jan 2014 12:46:06 -0700 Subject: mmc: tegra: support Tegra124 Tegra124's MMC controller is very similar to earlier SoC generations, and can be supported by the same driver. However, there are some non-backwards-compatible HW differences, and hence a new DT compatible value must be used to describe the HW. This patch updates the driver to support that new compatible value. That said, the HW differences are only relevant when enabling certain high-performance transfer modes. Since the driver is currently very simple and doesn't enable those modes, we don't actually need to address any of these HW differences in the code yet, hence the simple nature of this patch. Signed-off-by: Stephen Warren Acked-by: Pantelis Antoniou Tested-by: Thierry Reding Acked-by: Simon Glass Signed-off-by: Tom Warren --- drivers/mmc/tegra_mmc.c | 9 +++++++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 3 files changed, 11 insertions(+) (limited to 'drivers') diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index e1817e24f6d..3d1ce1263c8 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -668,6 +668,15 @@ void tegra_mmc_init(void) const void *blob = gd->fdt_blob; debug("%s entry\n", __func__); + /* See if any Tegra124 MMC controllers are present */ + count = fdtdec_find_aliases_for_id(blob, "sdhci", + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS); + debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count); + if (process_nodes(blob, node_list, count)) { + printf("%s: Error processing T30 mmc node(s)!\n", __func__); + return; + } + /* See if any Tegra30 MMC controllers are present */ count = fdtdec_find_aliases_for_id(blob, "sdhci", COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS); diff --git a/include/fdtdec.h b/include/fdtdec.h index 433d6a7c025..19bab794481 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -59,6 +59,7 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ + COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */ COMPAT_NVIDIA_TEGRA20_SFLASH, /* Tegra 2 SPI flash controller */ diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 207314fa72f..1fecab3fbc3 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -32,6 +32,7 @@ static const char * const compat_names[COMPAT_COUNT] = { COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"), COMPAT(NVIDIA_TEGRA20_PWM, "nvidia,tegra20-pwm"), COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"), + COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"), COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"), COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"), COMPAT(NVIDIA_TEGRA20_SFLASH, "nvidia,tegra20-sflash"), -- cgit v1.2.3 From 6f9b93723a39dc6d6231c842bb0166bd6258ee53 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 21 Nov 2013 16:15:51 +0100 Subject: net: axi_emac: Check if phy was correctly detected As tsec and fm drivers checking phydev->link ensure that u-boot don't try access device if link is not ready. Signed-off-by: Michal Simek --- drivers/net/xilinx_axi_emac.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers') diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index bb5044b31f5..262b67b6cf9 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -261,6 +261,10 @@ static int setup_phy(struct eth_device *dev) phydev->dev->name); return 0; } + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return 0; + } switch (phydev->speed) { case 1000: -- cgit v1.2.3 From 8c3bd6b596300d0ade265329f44832e89ef54a22 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 21 Jan 2014 07:29:47 +0100 Subject: serial: uartlite: Reset RX/TX in init Just to be sure that there is no pending data. Signed-off-by: Michal Simek --- drivers/serial/serial_xuartlite.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c index e6139943ba2..988438e7547 100644 --- a/drivers/serial/serial_xuartlite.c +++ b/drivers/serial/serial_xuartlite.c @@ -18,10 +18,14 @@ #define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ #define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define ULITE_CONTROL_RST_TX 0x01 +#define ULITE_CONTROL_RST_RX 0x02 + struct uartlite { unsigned int rx_fifo; unsigned int tx_fifo; unsigned int status; + unsigned int control; }; static struct uartlite *userial_ports[4] = { @@ -75,8 +79,16 @@ static int uartlite_serial_tstc(const int port) static int uartlite_serial_init(const int port) { - if (userial_ports[port]) + struct uartlite *regs = userial_ports[port]; + + if (regs) { + out_be32(®s->control, 0); + out_be32(®s->control, + ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX); + in_be32(®s->control); return 0; + } + return -1; } -- cgit v1.2.3 From e6252fab2d6989025bfb97e33abca03b5cb10ff1 Mon Sep 17 00:00:00 2001 From: Inha Song Date: Tue, 4 Feb 2014 14:57:25 +0900 Subject: serial: s5p: set automatically clears after resetting Rx FIFO This patch fix the u-boot shell problem on TRATS2 board. - If hold the key while booting is in progress, white spaces are written in u-boot shell. Set Automatically clears after resetting Rx FIFO. Signed-off-by: Inha Song Signed-off-by: Jaehoon Chung Acked-by: Lukasz Majewski Tested-by: Lukasz Majewski Signed-off-by: Minkyu Kang --- drivers/serial/serial_s5p.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 89f5d68dd08..98c62b4c147 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -100,8 +100,8 @@ static int serial_init_dev(const int dev_index) { struct s5p_uart *const uart = s5p_get_base_uart(dev_index); - /* enable FIFOs */ - writel(0x1, &uart->ufcon); + /* enable FIFOs, auto clear Rx FIFO */ + writel(0x3, &uart->ufcon); writel(0, &uart->umcon); /* 8N1 */ writel(0x3, &uart->ulcon); -- cgit v1.2.3 From 16b7a29fc6fac16431051de06d62da689360c40a Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:41 +0100 Subject: usb:gadget:ums: Replace malloc calls with memalign to fix cache buffer alignment Calls to malloc() have been replaced by memalign. It now provides proper buffer alignment. Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/f_mass_storage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index b1fe8bd3a80..f896169743c 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2515,7 +2515,7 @@ static struct fsg_common *fsg_common_init(struct fsg_common *common, buffhds_first_it: bh->inreq_busy = 0; bh->outreq_busy = 0; - bh->buf = kmalloc(FSG_BUFLEN, GFP_KERNEL); + bh->buf = memalign(CONFIG_SYS_CACHELINE_SIZE, FSG_BUFLEN); if (unlikely(!bh->buf)) { rc = -ENOMEM; goto error_release; @@ -2622,7 +2622,7 @@ usb_copy_descriptors(struct usb_descriptor_header **src) bytes += (*tmp)->bLength; bytes += (n_desc + 1) * sizeof(*tmp); - mem = kmalloc(bytes, GFP_KERNEL); + mem = memalign(CONFIG_SYS_CACHELINE_SIZE, bytes); if (!mem) return NULL; -- cgit v1.2.3 From 716662bd194f72cdf9bf05e0f57d9f6944dc953a Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:42 +0100 Subject: usb:udc:samsung: Remove redundant cache operation from Samsung UDC driver A set of cache operations (both invalidation and flush) were redundant in the S3C HS OTG Samsung driver: 1. s3c_udc_ep0_zlp - to transmit EP0's ZLP packets one don't need to flush the cache (since it is the zero length transmission) 2. s3c_udc_pre_setup and s3c_ep0_complete_out - cache invalidation is not needed when the buffer for OUT EP0 transmission is setup, since no data has yet arrived. Cache cleanups presented above don't contribute much to transmission speed up, hence shall be regarded as cosmetic changes. 3. setdma_rx - here the s3c UDC driver's internal buffers were invalidated. This call is not needed anymore since we reuse the buffers passed from gadgets. This is a key contribution to transmission speed improvement. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurements: Base values (without improvement): Transmission speed: 9.51 MiB/s After the change: Transmission speed: 10.15 MiB/s Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 1cbf8f60a7a..cbc8734af3b 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -29,10 +29,6 @@ static inline void s3c_udc_ep0_zlp(struct s3c_udc *dev) { u32 ep_ctrl; - flush_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1), ®->in_endp[EP0_CON].dieptsiz); @@ -52,10 +48,6 @@ void s3c_udc_pre_setup(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Setup packets.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -82,10 +74,6 @@ static inline void s3c_ep0_complete_out(void) debug_cond(DEBUG_IN_EP, "%s : Prepare Complete Out packet.\n", __func__); - invalidate_dcache_range((unsigned long) usb_ctrl_dma_addr, - (unsigned long) usb_ctrl_dma_addr - + DMA_BUFFER_SIZE); - writel(DOEPT_SIZ_PKT_CNT(1) | sizeof(struct usb_ctrlrequest), ®->out_endp[EP0_CON].doeptsiz); writel(usb_ctrl_dma_addr, ®->out_endp[EP0_CON].doepdma); @@ -115,11 +103,6 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_num], - (unsigned long) ep->dev->dma_buf[ep_num] - + ROUND(ep->ep.maxpacket, - CONFIG_SYS_CACHELINE_SIZE)); - if (length == 0) pktcnt = 1; else -- cgit v1.2.3 From 9c9822188cf2d7eeee7ae4f64a231a2d013df690 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:43 +0100 Subject: usb:udc:samsung: Allow burst transfers for non EP0 endpints This patch removed obscure restriction on the HW setting of DMA transfers. Before this change each transaction sent up to 512 bytes (with packet count equal to 1) for non EP0 transfer. Now it is possible to setup DMA transaction up to DMA_BUFFER_SIZE. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 20.74 MiB/s Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index cbc8734af3b..7c7176bfd3c 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -97,18 +97,17 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) u32 ep_num = ep_index(ep); buf = req->req.buf + req->req.actual; - - length = min(req->req.length - req->req.actual, (int)ep->ep.maxpacket); + length = min(req->req.length - req->req.actual, + ep_num ? DMA_BUFFER_SIZE : ep->ep.maxpacket); ep->len = length; ep->dma_buf = buf; - if (length == 0) + if (ep_num == EP0_CON || length == 0) pktcnt = 1; else pktcnt = (length - 1)/(ep->ep.maxpacket) + 1; - pktcnt = 1; ctrl = readl(®->out_endp[ep_num].doepctl); writel(the_controller->dma_addr[ep_index(ep)+1], -- cgit v1.2.3 From e0059eaef18dbdc65ee420a337aecfa555e8d493 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:44 +0100 Subject: usb:udc:samsung: Zero copy approach for data passed to Samsung's UDC driver The Samsung's UDC driver is not anymore copying data from USB requests to aligned internal buffers. Now it works directly in data allocated in the upper layers like UMS, DFU, THOR. This change is possible since those gadgets now must take care to allocate buffers aligned to cache line (CONFIG_SYS_CACHELINE_SIZE). This can be achieved by using DEFINE_CACHE_ALIGN_BUFFER() or ALLOC_CACHE_ALIGN_BUFFER() macros. Those take care to allocate buffer aligned to cache line in both starting address and its size. Sometimes it is enough to just use memalign() with size being a multiplication of cache line size. Test condition - test HW + measurement: Trats - Exynos4210 rev.1 - test HW Trats2 - Exynos4412 rev.1 400 MiB compressed rootfs image download with `thor 0 mmc 0` Measurement: Transmission speed: 27.04 MiB/s Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/s3c_udc_otg.c | 19 +++++----- drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 63 ++++++++++++++++--------------- include/usb/s3c_udc.h | 5 +-- 3 files changed, 43 insertions(+), 44 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c index ba17a04265e..63d4487a9bb 100644 --- a/drivers/usb/gadget/s3c_udc_otg.c +++ b/drivers/usb/gadget/s3c_udc_otg.c @@ -843,7 +843,7 @@ static struct s3c_udc memory = { int s3c_udc_probe(struct s3c_plat_otg_data *pdata) { struct s3c_udc *dev = &memory; - int retval = 0, i; + int retval = 0; debug("%s: %p\n", __func__, pdata); @@ -864,16 +864,15 @@ int s3c_udc_probe(struct s3c_plat_otg_data *pdata) the_controller = dev; - for (i = 0; i < S3C_MAX_ENDPOINTS+1; i++) { - dev->dma_buf[i] = memalign(CONFIG_SYS_CACHELINE_SIZE, - DMA_BUFFER_SIZE); - dev->dma_addr[i] = (dma_addr_t) dev->dma_buf[i]; - invalidate_dcache_range((unsigned long) dev->dma_buf[i], - (unsigned long) (dev->dma_buf[i] - + DMA_BUFFER_SIZE)); + usb_ctrl = memalign(CONFIG_SYS_CACHELINE_SIZE, + ROUND(sizeof(struct usb_ctrlrequest), + CONFIG_SYS_CACHELINE_SIZE)); + if (!usb_ctrl) { + error("No memory available for UDC!\n"); + return -ENOMEM; } - usb_ctrl = dev->dma_buf[0]; - usb_ctrl_dma_addr = dev->dma_addr[0]; + + usb_ctrl_dma_addr = (dma_addr_t) usb_ctrl; udc_reinit(dev); diff --git a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c index 7c7176bfd3c..06dfeed9051 100644 --- a/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/s3c_udc_otg_xfer_dma.c @@ -110,8 +110,7 @@ static int setdma_rx(struct s3c_ep *ep, struct s3c_request *req) ctrl = readl(®->out_endp[ep_num].doepctl); - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->out_endp[ep_num].doepdma); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); writel(DEPCTL_EPENA|DEPCTL_CNAK|ctrl, ®->out_endp[ep_num].doepctl); @@ -134,7 +133,6 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) u32 *buf, ctrl = 0; u32 length, pktcnt; u32 ep_num = ep_index(ep); - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; buf = req->req.buf + req->req.actual; length = req->req.length - req->req.actual; @@ -144,10 +142,10 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) ep->len = length; ep->dma_buf = buf; - memcpy(p, ep->dma_buf, length); - flush_dcache_range((unsigned long) p , - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(ep->len, CONFIG_SYS_CACHELINE_SIZE)); if (length == 0) pktcnt = 1; @@ -160,8 +158,7 @@ int setdma_tx(struct s3c_ep *ep, struct s3c_request *req) while (readl(®->grstctl) & TX_FIFO_FLUSH) ; - writel(the_controller->dma_addr[ep_index(ep)+1], - ®->in_endp[ep_num].diepdma); + writel((unsigned long) ep->dma_buf, ®->in_endp[ep_num].diepdma); writel(DIEPT_SIZ_PKT_CNT(pktcnt) | DIEPT_SIZ_XFER_SIZE(length), ®->in_endp[ep_num].dieptsiz); @@ -194,7 +191,6 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) struct s3c_ep *ep = &dev->ep[ep_num]; struct s3c_request *req = NULL; u32 ep_tsr = 0, xfer_size = 0, is_short = 0; - u32 *p = the_controller->dma_buf[ep_index(ep)+1]; if (list_empty(&ep->queue)) { debug_cond(DEBUG_OUT_EP != 0, @@ -214,10 +210,23 @@ static void complete_rx(struct s3c_udc *dev, u8 ep_num) xfer_size = ep->len - xfer_size; - invalidate_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); - - memcpy(ep->dma_buf, p, ep->len); + /* + * NOTE: + * + * Please be careful with proper buffer allocation for USB request, + * which needs to be aligned to CONFIG_SYS_CACHELINE_SIZE, not only + * with starting address, but also its size shall be a cache line + * multiplication. + * + * This will prevent from corruption of data allocated immediatelly + * before or after the buffer. + * + * For armv7, the cache_v7.c provides proper code to emit "ERROR" + * message to warn users. + */ + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + + ROUND(xfer_size, CONFIG_SYS_CACHELINE_SIZE)); req->req.actual += min(xfer_size, req->req.length - req->req.actual); is_short = (xfer_size < ep->ep.maxpacket); @@ -711,19 +720,14 @@ static int write_fifo_ep0(struct s3c_ep *ep, struct s3c_request *req) int s3c_fifo_read(struct s3c_ep *ep, u32 *cp, int max) { - u32 bytes; - - bytes = sizeof(struct usb_ctrlrequest); - - invalidate_dcache_range((unsigned long) ep->dev->dma_buf[ep_index(ep)], - (unsigned long) ep->dev->dma_buf[ep_index(ep)] - + DMA_BUFFER_SIZE); + invalidate_dcache_range((unsigned long)cp, (unsigned long)cp + + ROUND(max, CONFIG_SYS_CACHELINE_SIZE)); debug_cond(DEBUG_EP0 != 0, - "%s: bytes=%d, ep_index=%d %p\n", __func__, - bytes, ep_index(ep), ep->dev->dma_buf[ep_index(ep)]); + "%s: bytes=%d, ep_index=%d 0x%p\n", __func__, + max, ep_index(ep), cp); - return bytes; + return max; } /** @@ -855,14 +859,12 @@ static int s3c_ep0_write(struct s3c_udc *dev) return 1; } -u16 g_status; - int s3c_udc_get_status(struct s3c_udc *dev, struct usb_ctrlrequest *crq) { u8 ep_num = crq->wIndex & 0x7F; + u16 g_status = 0; u32 ep_ctrl; - u32 *p = the_controller->dma_buf[1]; debug_cond(DEBUG_SETUP != 0, "%s: *** USB_REQ_GET_STATUS\n", __func__); @@ -900,12 +902,13 @@ int s3c_udc_get_status(struct s3c_udc *dev, return 1; } - memcpy(p, &g_status, sizeof(g_status)); + memcpy(usb_ctrl, &g_status, sizeof(g_status)); - flush_dcache_range((unsigned long) p, - (unsigned long) p + DMA_BUFFER_SIZE); + flush_dcache_range((unsigned long) usb_ctrl, + (unsigned long) usb_ctrl + + ROUND(sizeof(g_status), CONFIG_SYS_CACHELINE_SIZE)); - writel(the_controller->dma_addr[1], ®->in_endp[EP0_CON].diepdma); + writel(usb_ctrl_dma_addr, ®->in_endp[EP0_CON].diepdma); writel(DIEPT_SIZ_PKT_CNT(1) | DIEPT_SIZ_XFER_SIZE(2), ®->in_endp[EP0_CON].dieptsiz); diff --git a/include/usb/s3c_udc.h b/include/usb/s3c_udc.h index 734c6cd2f7c..6dead2fb46d 100644 --- a/include/usb/s3c_udc.h +++ b/include/usb/s3c_udc.h @@ -19,7 +19,7 @@ /*-------------------------------------------------------------------------*/ /* DMA bounce buffer size, 16K is enough even for mass storage */ -#define DMA_BUFFER_SIZE (4096*4) +#define DMA_BUFFER_SIZE (16*SZ_1K) #define EP0_FIFO_SIZE 64 #define EP_FIFO_SIZE 512 @@ -81,9 +81,6 @@ struct s3c_udc { struct s3c_plat_otg_data *pdata; - void *dma_buf[S3C_MAX_ENDPOINTS+1]; - dma_addr_t dma_addr[S3C_MAX_ENDPOINTS+1]; - int ep0state; struct s3c_ep ep[S3C_MAX_ENDPOINTS]; -- cgit v1.2.3 From 84c13e6f61ecf73d2d477c055a6dc96630f3e4b4 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:45 +0100 Subject: usb:gadget:f_thor: Allocate request up to THOR_PACKET_SIZE not ep->maxpacket Now it is possible to allocate static request - which receives data from the host (OUT transaction) to the size of THOR packet. Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/f_thor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index c4c9909155a..780729a20c2 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -614,7 +614,7 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) { struct usb_request *req; - req = alloc_ep_req(ep, ep->maxpacket); + req = alloc_ep_req(ep, THOR_PACKET_SIZE); debug("%s: ep:%p req:%p\n", __func__, ep, req); if (!req) -- cgit v1.2.3 From fc2d5d04e1ebfd5ed5bc031938573d3a19413b7b Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Wed, 5 Feb 2014 10:10:46 +0100 Subject: usb:gadget:f_thor: cosmetic: Remove debug memset Apparently debug memset (with a 0x55 value) has been overlooked in the f_thor code. Signed-off-by: Lukasz Majewski Cc: Marek Vasut --- drivers/usb/gadget/f_thor.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers') diff --git a/drivers/usb/gadget/f_thor.c b/drivers/usb/gadget/f_thor.c index 780729a20c2..f5c0224f213 100644 --- a/drivers/usb/gadget/f_thor.c +++ b/drivers/usb/gadget/f_thor.c @@ -623,8 +623,6 @@ static struct usb_request *thor_start_ep(struct usb_ep *ep) memset(req->buf, 0, req->length); req->complete = thor_rx_tx_complete; - memset(req->buf, 0x55, req->length); - return req; } -- cgit v1.2.3 From c8d4b2f8266fac1bcbf9101838939054b8a23011 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:14:28 +0100 Subject: ARM: IXP: Remove the IXP architecture support The architecture is unmaintained and dead, remove it. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- MAKEALL | 2 - README | 1 - arch/arm/cpu/ixp/Makefile | 12 - arch/arm/cpu/ixp/config.mk | 16 - arch/arm/cpu/ixp/cpu.c | 100 ------ arch/arm/cpu/ixp/interrupts.c | 66 ---- arch/arm/cpu/ixp/start.S | 430 ----------------------- arch/arm/cpu/ixp/timer.c | 101 ------ arch/arm/cpu/ixp/u-boot.lds | 91 ----- arch/arm/include/asm/arch-ixp/ixp425.h | 548 ------------------------------ arch/arm/include/asm/arch-ixp/ixp425pci.h | 174 ---------- arch/arm/include/asm/global_data.h | 3 - drivers/i2c/soft_i2c.c | 3 - 13 files changed, 1547 deletions(-) delete mode 100644 arch/arm/cpu/ixp/Makefile delete mode 100644 arch/arm/cpu/ixp/config.mk delete mode 100644 arch/arm/cpu/ixp/cpu.c delete mode 100644 arch/arm/cpu/ixp/interrupts.c delete mode 100644 arch/arm/cpu/ixp/start.S delete mode 100644 arch/arm/cpu/ixp/timer.c delete mode 100644 arch/arm/cpu/ixp/u-boot.lds delete mode 100644 arch/arm/include/asm/arch-ixp/ixp425.h delete mode 100644 arch/arm/include/asm/arch-ixp/ixp425pci.h (limited to 'drivers') diff --git a/MAKEALL b/MAKEALL index 562071a03e3..63838ce4f04 100755 --- a/MAKEALL +++ b/MAKEALL @@ -398,8 +398,6 @@ LIST_at91="$(targets_by_soc at91)" LIST_pxa="$(targets_by_cpu pxa)" -LIST_ixp="$(targets_by_cpu ixp)" - ######################################################################### ## SPEAr Systems ######################################################################### diff --git a/README b/README index 176de61a331..8ea097d0e65 100644 --- a/README +++ b/README @@ -141,7 +141,6 @@ Directory Hierarchy: /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm926ejs Files specific to ARM 926 CPUs /arm1136 Files specific to ARM 1136 CPUs - /ixp Files specific to Intel XScale IXP CPUs /pxa Files specific to Intel XScale PXA CPUs /sa1100 Files specific to Intel StrongARM SA1100 CPUs /lib Architecture specific library files diff --git a/arch/arm/cpu/ixp/Makefile b/arch/arm/cpu/ixp/Makefile deleted file mode 100644 index 4e66523c035..00000000000 --- a/arch/arm/cpu/ixp/Makefile +++ /dev/null @@ -1,12 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -extra-y = start.o - -obj-y += cpu.o -obj-$(CONFIG_USE_IRQ) += interrupts.o -obj-y += timer.o diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk deleted file mode 100644 index 894861fb4ff..00000000000 --- a/arch/arm/cpu/ixp/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger -# -# SPDX-License-Identifier: GPL-2.0+ -# - -BIG_ENDIAN = y - -PLATFORM_RELFLAGS += -mbig-endian - -PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100 - -PLATFORM_LDFLAGS += -EB -USE_PRIVATE_LIBGCC = yes diff --git a/arch/arm/cpu/ixp/cpu.c b/arch/arm/cpu/ixp/cpu.c deleted file mode 100644 index 4387c18d3d4..00000000000 --- a/arch/arm/cpu/ixp/cpu.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * CPU specific code - */ - -#include -#include -#include -#include -#include - -static void cache_flush(void); - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo (void) -{ - unsigned long id; - int speed = 0; - - asm ("mrc p15, 0, %0, c0, c0, 0":"=r" (id)); - - puts("CPU: Intel IXP425 at "); - switch ((id & 0x000003f0) >> 4) { - case 0x1c: - speed = 533; - break; - - case 0x1d: - speed = 400; - break; - - case 0x1f: - speed = 266; - break; - } - - if (speed) - printf("%d MHz\n", speed); - else - puts("unknown revision\n"); - - return 0; -} -#endif /* CONFIG_DISPLAY_CPUINFO */ - -int cleanup_before_linux (void) -{ - /* - * this function is called just before we call linux - * it prepares the processor for linux - * - * just disable everything that can disturb booting linux - */ - - disable_interrupts (); - - /* turn off I-cache */ - icache_disable(); - dcache_disable(); - - /* flush I-cache */ - cache_flush(); - - return 0; -} - -/* flush I/D-cache */ -static void cache_flush (void) -{ - unsigned long i = 0; - - asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i)); -} - -/* FIXME */ -/* -void pci_init(void) -{ - return; -} -*/ - -int cpu_eth_init(bd_t *bis) -{ -#ifdef CONFIG_IXP4XX_NPE - npe_initialize(bis); -#endif - return 0; -} diff --git a/arch/arm/cpu/ixp/interrupts.c b/arch/arm/cpu/ixp/interrupts.c deleted file mode 100644 index 7694c6a6ccb..00000000000 --- a/arch/arm/cpu/ixp/interrupts.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct _irq_handler { - void *m_data; - void (*m_func)( void *data); -}; - -static struct _irq_handler IRQ_HANDLER[N_IRQS]; - -static void default_isr(void *data) -{ - printf("default_isr(): called for IRQ %d, Interrupt Status=%x PR=%x\n", - (int)data, *IXP425_ICIP, *IXP425_ICIH); -} - -static int next_irq(void) -{ - return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1); -} - -void do_irq (struct pt_regs *pt_regs) -{ - int irq = next_irq(); - - IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data); -} - -void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data) -{ - if (irq >= N_IRQS || !handle_irq) - return; - - IRQ_HANDLER[irq].m_data = data; - IRQ_HANDLER[irq].m_func = handle_irq; -} - -int arch_interrupt_init (void) -{ - int i; - - /* install default interrupt handlers */ - for (i = 0; i < N_IRQS; i++) - irq_install_handler(i, default_isr, (void *)i); - - /* configure interrupts for IRQ mode */ - *IXP425_ICLR = 0x00000000; - - return (0); -} diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S deleted file mode 100644 index 82c868a1749..00000000000 --- a/arch/arm/cpu/ixp/start.S +++ /dev/null @@ -1,430 +0,0 @@ -/* vi: set ts=8 sw=8 noet: */ -/* - * u-boot - Startup Code for XScale IXP - * - * Copyright (C) 2003 Kyle Harris - * - * Based on startup code example contained in the - * Intel IXP4xx Programmer's Guide and past u-boot Start.S - * samples. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MMU_Control_M 0x001 /* Enable MMU */ -#define MMU_Control_A 0x002 /* Enable address alignment faults */ -#define MMU_Control_C 0x004 /* Enable cache */ -#define MMU_Control_W 0x008 /* Enable write-buffer */ -#define MMU_Control_P 0x010 /* Compatability: 32 bit code */ -#define MMU_Control_D 0x020 /* Compatability: 32 bit data */ -#define MMU_Control_L 0x040 /* Compatability: */ -#define MMU_Control_B 0x080 /* Enable Big-Endian */ -#define MMU_Control_S 0x100 /* Enable system protection */ -#define MMU_Control_R 0x200 /* Enable ROM protection */ -#define MMU_Control_I 0x1000 /* Enable Instruction cache */ -#define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */ -#define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L) - - -/* - * Macro definitions - */ - /* Delay a bit */ - .macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc - .endm - - /* wait for coprocessor write complete */ - .macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 - .endm - -.globl _start -_start: - ldr pc, _reset - ldr pc, _undefined_instruction - ldr pc, _software_interrupt - ldr pc, _prefetch_abort - ldr pc, _data_abort - ldr pc, _not_used - ldr pc, _irq - ldr pc, _fiq - -_reset: .word reset -_undefined_instruction: .word undefined_instruction -_software_interrupt: .word software_interrupt -_prefetch_abort: .word prefetch_abort -_data_abort: .word data_abort -_not_used: .word not_used -_irq: .word irq -_fiq: .word fiq - - .balignl 16,0xdeadbeef - - -/* - * Startup Code (reset vector) - * - * do important init only if we don't start from memory! - * - relocate armboot to ram - * - setup stack - * - jump to second stage - */ - -.globl _TEXT_BASE -_TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -/* - * These are defined in the board-specific linker script. - * Subtracting _start from them lets the linker put their - * relative position in the executable instead of leaving - * them null. - */ -.globl _bss_start_ofs -_bss_start_ofs: - .word __bss_start - _start - -.globl _bss_end_ofs -_bss_end_ofs: - .word __bss_end - _start - -.globl _end_ofs -_end_ofs: - .word _end - _start - -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de -#endif - -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de - -/* - * the actual reset code - */ - -reset: - /* disable mmu, set big-endian */ - mov r0, #0xf8 - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* disable write buffer coalescing */ - mrc p15, 0, r0, c1, c0, 1 - orr r0, r0, #1 - mcr p15, 0, r0, c1, c0, 1 - CPWAIT r0 - - /* set EXP CS0 to the optimum timing */ - ldr r1, =CONFIG_SYS_EXP_CS0 - ldr r2, =IXP425_EXP_CS0 - str r1, [r2] - - /* make sure flash is visible at 0 */ - mov r1, #CONFIG_SYS_SDR_CONFIG - ldr r2, =IXP425_SDR_CONFIG - str r1, [r2] - - /* disable refresh cycles */ - mov r1, #0 - ldr r3, =IXP425_SDR_REFRESH - str r1, [r3] - - /* send nop command */ - mov r1, #3 - ldr r4, =IXP425_SDR_IR - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* set SDRAM internal refresh val */ - ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT - str r1, [r3] - DELAY_FOR 0x4000, r0 - - /* send precharge-all command to close all open banks */ - mov r1, #2 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* provide 8 auto-refresh cycles */ - mov r1, #4 - mov r5, #8 -111: str r1, [r4] - DELAY_FOR 0x100, r0 - subs r5, r5, #1 - bne 111b - - /* set mode register in sdram */ - mov r1, #CONFIG_SYS_SDR_MODE_CONFIG - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* send normal operation command */ - mov r1, #6 - str r1, [r4] - DELAY_FOR 0x4000, r0 - - /* invalidate I & D caches & BTB */ - mcr p15, 0, r0, c7, c7, 0 - CPWAIT r0 - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* drain write and fill buffers */ - mcr p15, 0, r0, c7, c10, 4 - CPWAIT r0 - - /* remove flash mirror at 0x00000000 */ - ldr r2, =IXP425_EXP_CFG0 - ldr r1, [r2] - bic r1, r1, #0x80000000 - str r1, [r2] - - /* invalidate I & Data TLB */ - mcr p15, 0, r0, c8, c7, 0 - CPWAIT r0 - - /* enable I cache */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #MMU_Control_I - mcr p15, 0, r0, c1, c0, 0 - CPWAIT r0 - - mrs r0,cpsr /* set the cpu to SVC32 mode */ - bic r0,r0,#0x1f /* (superviser mode, M=10011) */ - orr r0,r0,#0x13 - msr cpsr,r0 - - bl _main - -/*------------------------------------------------------------------------------*/ - - .globl c_runtime_cpu_setup -c_runtime_cpu_setup: - - bx lr - -/****************************************************************************/ -/* */ -/* Interrupt handling */ -/* */ -/****************************************************************************/ - -/* IRQ stack frame */ - -#define S_FRAME_SIZE 72 - -#define S_OLD_R0 68 -#define S_PSR 64 -#define S_PC 60 -#define S_LR 56 -#define S_SP 52 - -#define S_IP 48 -#define S_FP 44 -#define S_R10 40 -#define S_R9 36 -#define S_R8 32 -#define S_R7 28 -#define S_R6 24 -#define S_R5 20 -#define S_R4 16 -#define S_R3 12 -#define S_R2 8 -#define S_R1 4 -#define S_R0 0 - -#define MODE_SVC 0x13 - - /* use bad_save_user_regs for abort/prefetch/undef/swi ... */ - - .macro bad_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - - ldr r2, IRQ_STACK_START_IN - ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ - add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ - - add r5, sp, #S_SP - mov r1, lr - stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */ - mov r0, sp - .endm - - - /* use irq_save_user_regs / irq_restore_user_regs for */ - /* IRQ/FIQ handling */ - - .macro irq_save_user_regs - sub sp, sp, #S_FRAME_SIZE - stmia sp, {r0 - r12} /* Calling r0-r12 */ - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ /* Calling SP, LR */ - str lr, [r8, #0] /* Save calling PC */ - mrs r6, spsr - str r6, [r8, #4] /* Save CPSR */ - str r0, [r8, #8] /* Save OLD_R0 */ - mov r0, sp - .endm - - .macro irq_restore_user_regs - ldmia sp, {r0 - lr}^ @ Calling r0 - lr - mov r0, r0 - ldr lr, [sp, #S_PC] @ Get PC - add sp, sp, #S_FRAME_SIZE - subs pc, lr, #4 @ return & move spsr_svc into cpsr - .endm - - .macro get_bad_stack - ldr r13, IRQ_STACK_START_IN @ setup our mode stack - - str lr, [r13] @ save caller lr / spsr - mrs lr, spsr - str lr, [r13, #4] - - mov r13, #MODE_SVC @ prepare SVC-Mode - msr spsr_c, r13 - mov lr, pc - movs pc, lr - .endm - - .macro get_irq_stack @ setup IRQ stack - ldr sp, IRQ_STACK_START - .endm - - .macro get_fiq_stack @ setup FIQ stack - ldr sp, FIQ_STACK_START - .endm - - -/****************************************************************************/ -/* */ -/* exception handlers */ -/* */ -/****************************************************************************/ - - .align 5 -undefined_instruction: - get_bad_stack - bad_save_user_regs - bl do_undefined_instruction - - .align 5 -software_interrupt: - get_bad_stack - bad_save_user_regs - bl do_software_interrupt - - .align 5 -prefetch_abort: - get_bad_stack - bad_save_user_regs - bl do_prefetch_abort - - .align 5 -data_abort: - get_bad_stack - bad_save_user_regs - bl do_data_abort - - .align 5 -not_used: - get_bad_stack - bad_save_user_regs - bl do_not_used - -#ifdef CONFIG_USE_IRQ - - .align 5 -irq: - get_irq_stack - irq_save_user_regs - bl do_irq - irq_restore_user_regs - - .align 5 -fiq: - get_fiq_stack - irq_save_user_regs /* someone ought to write a more */ - bl do_fiq /* effiction fiq_save_user_regs */ - irq_restore_user_regs - -#else - - .align 5 -irq: - get_bad_stack - bad_save_user_regs - bl do_irq - - .align 5 -fiq: - get_bad_stack - bad_save_user_regs - bl do_fiq - -#endif - -/****************************************************************************/ -/* */ -/* Reset function: Use Watchdog to reset */ -/* */ -/****************************************************************************/ - - .align 5 -.globl reset_cpu - -reset_cpu: - ldr r1, =0x482e - ldr r2, =IXP425_OSWK - str r1, [r2] - ldr r1, =0x0fff - ldr r2, =IXP425_OSWT - str r1, [r2] - ldr r1, =0x5 - ldr r2, =IXP425_OSWE - str r1, [r2] - b reset_endless - -reset_endless: - b reset_endless diff --git a/arch/arm/cpu/ixp/timer.c b/arch/arm/cpu/ixp/timer.c deleted file mode 100644 index 38e2e2879c8..00000000000 --- a/arch/arm/cpu/ixp/timer.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * (C) Copyright 2010 - * Michael Schwingen, michael@schwingen.org - * - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * The IXP42x time-stamp timer runs at 2*OSC_IN (66.666MHz when using a - * 33.333MHz crystal). - */ -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, CONFIG_IXP425_TIMER_CLK); - return tick; -} - -static inline unsigned long long time_to_tick(unsigned long long time) -{ - time *= CONFIG_IXP425_TIMER_CLK; - do_div(time, CONFIG_SYS_HZ); - return time; -} - -static inline unsigned long long us_to_tick(unsigned long long us) -{ - us = us * CONFIG_IXP425_TIMER_CLK + 999999; - do_div(us, 1000000); - return us; -} - -unsigned long long get_ticks(void) -{ - ulong now = readl(IXP425_OSTS_B); - - if (readl(IXP425_OSST) & IXP425_OSST_TIMER_TS_PEND) { - /* rollover of timestamp timer register */ - gd->arch.timestamp += (0xFFFFFFFF - gd->arch.lastinc) + now + 1; - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - } else { - /* move stamp forward with absolut diff ticks */ - gd->arch.timestamp += (now - gd->arch.lastinc); - } - gd->arch.lastinc = now; - return gd->arch.timestamp; -} - - -void reset_timer_masked(void) -{ - /* capture current timestamp counter */ - gd->arch.lastinc = readl(IXP425_OSTS_B); - /* start "advancing" time stamp from 0 */ - gd->arch.timestamp = 0; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - - tmp = get_ticks() + us_to_tick(usec); - - while (get_ticks() < tmp) - ; -} - -int timer_init(void) -{ - writel(IXP425_OSST_TIMER_TS_PEND, IXP425_OSST); - return 0; -} diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds deleted file mode 100644 index 676ae2c4f9a..00000000000 --- a/arch/arm/cpu/ixp/u-boot.lds +++ /dev/null @@ -1,91 +0,0 @@ -/* - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.__image_copy_start) - arch/arm/cpu/ixp/start.o(.text*) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - - .image_copy_end : - { - *(.__image_copy_end) - } - - .rel_dyn_start : - { - *(.__rel_dyn_start) - } - - .rel.dyn : { - *(.rel*) - } - - .rel_dyn_end : - { - *(.__rel_dyn_end) - } - - _end = .; - -/* - * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c - * __bss_base and __bss_limit are for linker only (overlay ordering) - */ - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - .dynsym _end : { *(.dynsym) } - .dynbss : { *(.dynbss) } - .dynstr : { *(.dynstr*) } - .dynamic : { *(.dynamic*) } - .hash : { *(.hash*) } - .plt : { *(.plt*) } - .interp : { *(.interp*) } - .gnu : { *(.gnu*) } - .ARM.exidx : { *(.ARM.exidx*) } -} diff --git a/arch/arm/include/asm/arch-ixp/ixp425.h b/arch/arm/include/asm/arch-ixp/ixp425.h deleted file mode 100644 index c2e9c820495..00000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425.h +++ /dev/null @@ -1,548 +0,0 @@ -/* - * include/asm-arm/arch-ixp425/ixp425.h - * - * Register definitions for IXP425 - * - * Copyright (C) 2002 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#ifndef _ASM_ARM_IXP425_H_ -#define _ASM_ARM_IXP425_H_ - -#define BIT(x) (1<<(x)) - -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 -#ifdef UBOOT_REG_FIX -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# endif -#endif /* UBOOT_REG_FIX */ - -/* - * - * IXP425 Memory map: - * - * Phy Phy Size Map Size Virt Description - * ========================================================================= - * - * 0x00000000 0x10000000 SDRAM 1 - * - * 0x10000000 0x10000000 SDRAM 2 - * - * 0x20000000 0x10000000 SDRAM 3 - * - * 0x30000000 0x10000000 SDRAM 4 - * - * The above four are aliases to the same memory location (0x00000000) - * - * 0x48000000 0x4000000 PCI Memory - * - * 0x50000000 0x10000000 Not Mapped EXP BUS - * - * 0x6000000 0x00004000 0x4000 0xFFFEB000 QMgr - * - * 0xC0000000 0x100 0x1000 0xFFFDD000 PCI CFG - * - * 0xC4000000 0x100 0x1000 0xFFFDE000 EXP CFG - * - * 0xC8000000 0xC000 0xC000 0xFFFDF000 PERIPHERAL - * - * 0xCC000000 0x100 0x1000 Not Mapped SDRAM CFG - */ - -/* - * SDRAM - */ -#define IXP425_SDRAM_BASE (0x00000000) -#define IXP425_SDRAM_BASE_ALT (0x10000000) - - -/* - * PCI Configuration space - */ -#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000) -#define IXP425_PCI_CFG_REGION_SIZE (0x00001000) - -/* - * Expansion BUS Configuration registers - */ -#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000) -#define IXP425_EXP_CFG_REGION_SIZE (0x00001000) - -/* - * Peripheral space - */ -#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000) -#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000) - -/* - * SDRAM configuration registers - */ -#define IXP425_SDRAM_CFG_BASE_PHYS (0xCC000000) - -/* - * Q Manager space .. not static mapped - */ -#define IXP425_QMGR_BASE_PHYS (0x60000000) -#define IXP425_QMGR_REGION_SIZE (0x00004000) - -/* - * Expansion BUS - * - * Expansion Bus 'lives' at either base1 or base 2 depending on the value of - * Exp Bus config registers: - * - * Setting bit 31 of IXP425_EXP_CFG0 puts SDRAM at zero, - * and The expansion bus to IXP425_EXP_BUS_BASE2 - */ -#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000) -#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000) - -#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS - -#define IXP425_EXP_BUS_REGION_SIZE (0x08000000) -#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000) - -#define IXP425_EXP_BUS_CS0_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x00000000) -#define IXP425_EXP_BUS_CS1_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x01000000) -#define IXP425_EXP_BUS_CS2_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x02000000) -#define IXP425_EXP_BUS_CS3_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x03000000) -#define IXP425_EXP_BUS_CS4_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x04000000) -#define IXP425_EXP_BUS_CS5_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x05000000) -#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000) -#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000) - -#define IXP425_FLASH_WRITABLE (0x2) -#define IXP425_FLASH_DEFAULT (0xbcd23c40) -#define IXP425_FLASH_WRITE (0xbcd23c42) - -#define IXP425_EXP_CS0_OFFSET 0x00 -#define IXP425_EXP_CS1_OFFSET 0x04 -#define IXP425_EXP_CS2_OFFSET 0x08 -#define IXP425_EXP_CS3_OFFSET 0x0C -#define IXP425_EXP_CS4_OFFSET 0x10 -#define IXP425_EXP_CS5_OFFSET 0x14 -#define IXP425_EXP_CS6_OFFSET 0x18 -#define IXP425_EXP_CS7_OFFSET 0x1C -#define IXP425_EXP_CFG0_OFFSET 0x20 -#define IXP425_EXP_CFG1_OFFSET 0x24 -#define IXP425_EXP_CFG2_OFFSET 0x28 -#define IXP425_EXP_CFG3_OFFSET 0x2C - -/* - * Expansion Bus Controller registers. - */ -#ifndef __ASSEMBLY__ -#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x))) -#else -#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x)) -#endif - -#define IXP425_EXP_CS0 IXP425_EXP_REG(IXP425_EXP_CS0_OFFSET) -#define IXP425_EXP_CS1 IXP425_EXP_REG(IXP425_EXP_CS1_OFFSET) -#define IXP425_EXP_CS2 IXP425_EXP_REG(IXP425_EXP_CS2_OFFSET) -#define IXP425_EXP_CS3 IXP425_EXP_REG(IXP425_EXP_CS3_OFFSET) -#define IXP425_EXP_CS4 IXP425_EXP_REG(IXP425_EXP_CS4_OFFSET) -#define IXP425_EXP_CS5 IXP425_EXP_REG(IXP425_EXP_CS5_OFFSET) -#define IXP425_EXP_CS6 IXP425_EXP_REG(IXP425_EXP_CS6_OFFSET) -#define IXP425_EXP_CS7 IXP425_EXP_REG(IXP425_EXP_CS7_OFFSET) - -#define IXP425_EXP_CFG0 IXP425_EXP_REG(IXP425_EXP_CFG0_OFFSET) -#define IXP425_EXP_CFG1 IXP425_EXP_REG(IXP425_EXP_CFG1_OFFSET) -#define IXP425_EXP_CFG2 IXP425_EXP_REG(IXP425_EXP_CFG2_OFFSET) -#define IXP425_EXP_CFG3 IXP425_EXP_REG(IXP425_EXP_CFG3_OFFSET) - -/* - * SDRAM Controller registers. - */ -#define IXP425_SDR_CONFIG_OFFSET 0x00 -#define IXP425_SDR_REFRESH_OFFSET 0x04 -#define IXP425_SDR_IR_OFFSET 0x08 - -#define IXP425_SDRAM_REG(x) (IXP425_SDRAM_CFG_BASE_PHYS+(x)) - -#define IXP425_SDR_CONFIG IXP425_SDRAM_REG(IXP425_SDR_CONFIG_OFFSET) -#define IXP425_SDR_REFRESH IXP425_SDRAM_REG(IXP425_SDR_REFRESH_OFFSET) -#define IXP425_SDR_IR IXP425_SDRAM_REG(IXP425_SDR_IR_OFFSET) - -/* - * UART registers - */ -#define IXP425_UART1 0 -#define IXP425_UART2 0x1000 - -#define IXP425_UART_RBR_OFFSET 0x00 -#define IXP425_UART_THR_OFFSET 0x00 -#define IXP425_UART_DLL_OFFSET 0x00 -#define IXP425_UART_IER_OFFSET 0x04 -#define IXP425_UART_DLH_OFFSET 0x04 -#define IXP425_UART_IIR_OFFSET 0x08 -#define IXP425_UART_FCR_OFFSET 0x00 -#define IXP425_UART_LCR_OFFSET 0x0c -#define IXP425_UART_MCR_OFFSET 0x10 -#define IXP425_UART_LSR_OFFSET 0x14 -#define IXP425_UART_MSR_OFFSET 0x18 -#define IXP425_UART_SPR_OFFSET 0x1c -#define IXP425_UART_ISR_OFFSET 0x20 - -#define IXP425_UART_CFG_BASE_PHYS (0xc8000000) - -#define RBR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_RBR_OFFSET) -#define THR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_THR_OFFSET) -#define DLL(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLL_OFFSET) -#define IER(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IER_OFFSET) -#define DLH(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_DLH_OFFSET) -#define IIR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_IIR_OFFSET) -#define FCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_FCR_OFFSET) -#define LCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LCR_OFFSET) -#define MCR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MCR_OFFSET) -#define LSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_LSR_OFFSET) -#define MSR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_MSR_OFFSET) -#define SPR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_SPR_OFFSET) -#define ISR(x) __REG(IXP425_UART_CFG_BASE_PHYS+(x)+IXP425_UART_ISR_OFFSET) - -#define IER_DMAE (1 << 7) /* DMA Requests Enable */ -#define IER_UUE (1 << 6) /* UART Unit Enable */ -#define IER_NRZE (1 << 5) /* NRZ coding Enable */ -#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */ -#define IER_MIE (1 << 3) /* Modem Interrupt Enable */ -#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */ -#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */ -#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */ - -#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */ -#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */ -#define IIR_TOD (1 << 3) /* Time Out Detected */ -#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */ -#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */ -#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */ - -#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */ -#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */ -#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */ -#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */ -#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */ -#define FCR_ITL_1 (0) -#define FCR_ITL_8 (FCR_ITL1) -#define FCR_ITL_16 (FCR_ITL2) -#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1) - -#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */ -#define LCR_SB (1 << 6) /* Set Break */ -#define LCR_STKYP (1 << 5) /* Sticky Parity */ -#define LCR_EPS (1 << 4) /* Even Parity Select */ -#define LCR_PEN (1 << 3) /* Parity Enable */ -#define LCR_STB (1 << 2) /* Stop Bit */ -#define LCR_WLS1 (1 << 1) /* Word Length Select */ -#define LCR_WLS0 (1 << 0) /* Word Length Select */ - -#define LSR_FIFOE (1 << 7) /* FIFO Error Status */ -#define LSR_TEMT (1 << 6) /* Transmitter Empty */ -#define LSR_TDRQ (1 << 5) /* Transmit Data Request */ -#define LSR_BI (1 << 4) /* Break Interrupt */ -#define LSR_FE (1 << 3) /* Framing Error */ -#define LSR_PE (1 << 2) /* Parity Error */ -#define LSR_OE (1 << 1) /* Overrun Error */ -#define LSR_DR (1 << 0) /* Data Ready */ - -#define MCR_LOOP (1 << 4) */ -#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ -#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ -#define MCR_RTS (1 << 1) /* Request to Send */ -#define MCR_DTR (1 << 0) /* Data Terminal Ready */ - -#define MSR_DCD (1 << 7) /* Data Carrier Detect */ -#define MSR_RI (1 << 6) /* Ring Indicator */ -#define MSR_DSR (1 << 5) /* Data Set Ready */ -#define MSR_CTS (1 << 4) /* Clear To Send */ -#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */ -#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */ -#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ -#define MSR_DCTS (1 << 0) /* Delta Clear To Send */ - -#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS -/* - * Peripheral Space Registers - */ -#define IXP425_UART1_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x0000) -#define IXP425_UART2_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x1000) -#define IXP425_PMU_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x2000) -#define IXP425_INTC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x3000) -#define IXP425_GPIO_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x4000) -#define IXP425_TIMER_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x5000) -#define IXP425_NPEA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x6000) -#define IXP425_NPEB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x7000) -#define IXP425_NPEC_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x8000) -#define IXP425_EthA_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0x9000) -#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000) -#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000) - -/* - * UART Register Definitions , Offsets only as there are 2 UARTS. - * IXP425_UART1_BASE , IXP425_UART2_BASE. - */ - -#undef UART_NO_RX_INTERRUPT - -#define IXP425_UART_XTAL 14745600 - -/* - * Constants to make it easy to access Interrupt Controller registers - */ -#define IXP425_ICPR_OFFSET 0x00 /* Interrupt Status */ -#define IXP425_ICMR_OFFSET 0x04 /* Interrupt Enable */ -#define IXP425_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */ -#define IXP425_ICIP_OFFSET 0x0C /* IRQ Status */ -#define IXP425_ICFP_OFFSET 0x10 /* FIQ Status */ -#define IXP425_ICHR_OFFSET 0x14 /* Interrupt Priority */ -#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */ -#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */ - -#define N_IRQS 32 -#define IXP425_TIMER_2_IRQ 11 - -/* - * Interrupt Controller Register Definitions. - */ -#ifndef __ASSEMBLY__ -#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x))) -#else -#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x)) -#endif - -#define IXP425_ICPR IXP425_INTC_REG(IXP425_ICPR_OFFSET) -#define IXP425_ICMR IXP425_INTC_REG(IXP425_ICMR_OFFSET) -#define IXP425_ICLR IXP425_INTC_REG(IXP425_ICLR_OFFSET) -#define IXP425_ICIP IXP425_INTC_REG(IXP425_ICIP_OFFSET) -#define IXP425_ICFP IXP425_INTC_REG(IXP425_ICFP_OFFSET) -#define IXP425_ICHR IXP425_INTC_REG(IXP425_ICHR_OFFSET) -#define IXP425_ICIH IXP425_INTC_REG(IXP425_ICIH_OFFSET) -#define IXP425_ICFH IXP425_INTC_REG(IXP425_ICFH_OFFSET) - -/* - * Constants to make it easy to access GPIO registers - */ -#define IXP425_GPIO_GPOUTR_OFFSET 0x00 -#define IXP425_GPIO_GPOER_OFFSET 0x04 -#define IXP425_GPIO_GPINR_OFFSET 0x08 -#define IXP425_GPIO_GPISR_OFFSET 0x0C -#define IXP425_GPIO_GPIT1R_OFFSET 0x10 -#define IXP425_GPIO_GPIT2R_OFFSET 0x14 -#define IXP425_GPIO_GPCLKR_OFFSET 0x18 -#define IXP425_GPIO_GPDBSELR_OFFSET 0x1C - -/* - * GPIO Register Definitions. - * [Only perform 32bit reads/writes] - */ -#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x))) - -#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET) -#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET) -#define IXP425_GPIO_GPINR IXP425_GPIO_REG(IXP425_GPIO_GPINR_OFFSET) -#define IXP425_GPIO_GPISR IXP425_GPIO_REG(IXP425_GPIO_GPISR_OFFSET) -#define IXP425_GPIO_GPIT1R IXP425_GPIO_REG(IXP425_GPIO_GPIT1R_OFFSET) -#define IXP425_GPIO_GPIT2R IXP425_GPIO_REG(IXP425_GPIO_GPIT2R_OFFSET) -#define IXP425_GPIO_GPCLKR IXP425_GPIO_REG(IXP425_GPIO_GPCLKR_OFFSET) -#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET) - -#define IXP425_GPIO_GPITR(line) (((line) >= 8) ? \ - IXP425_GPIO_GPIT2R : IXP425_GPIO_GPIT1R) - -/* - * Macros to make it easy to access the GPIO registers - */ -#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line)) -#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line)) -#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line)) -#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line)) -#define GPIO_INT_ACT_LOW_SET(line) \ - *IXP425_GPIO_GPITR(line) = \ - (*IXP425_GPIO_GPITR(line) & \ - ~(0x7 << (((line) & 0x7) * 3))) | \ - (0x1 << (((line) & 0x7) * 3)) \ - -/* - * Constants to make it easy to access Timer Control/Status registers - */ -#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */ -#define IXP425_OST1_OFFSET 0x04 /* Timer 1 Timestamp */ -#define IXP425_OSRT1_OFFSET 0x08 /* Timer 1 Reload */ -#define IXP425_OST2_OFFSET 0x0C /* Timer 2 Timestamp */ -#define IXP425_OSRT2_OFFSET 0x10 /* Timer 2 Reload */ -#define IXP425_OSWT_OFFSET 0x14 /* Watchdog Timer */ -#define IXP425_OSWE_OFFSET 0x18 /* Watchdog Enable */ -#define IXP425_OSWK_OFFSET 0x1C /* Watchdog Key */ -#define IXP425_OSST_OFFSET 0x20 /* Timer Status */ - -/* - * Operating System Timer Register Definitions. - */ - -#ifndef __ASSEMBLY__ -#define IXP425_TIMER_REG(x) ((volatile u32 *)(IXP425_TIMER_BASE_PHYS+(x))) -#else -#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x)) -#endif - -/* _B to avoid collision: also defined in npe/include/... */ -#define IXP425_OSTS_B IXP425_TIMER_REG(IXP425_OSTS_OFFSET) -#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET) -#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET) -#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET) -#define IXP425_OSRT2 IXP425_TIMER_REG(IXP425_OSRT2_OFFSET) -#define IXP425_OSWT IXP425_TIMER_REG(IXP425_OSWT_OFFSET) -#define IXP425_OSWE IXP425_TIMER_REG(IXP425_OSWE_OFFSET) -#define IXP425_OSWK IXP425_TIMER_REG(IXP425_OSWK_OFFSET) -#define IXP425_OSST IXP425_TIMER_REG(IXP425_OSST_OFFSET) - -/* - * Timer register values and bit definitions - */ -#define IXP425_OST_ENABLE BIT(0) -#define IXP425_OST_ONE_SHOT BIT(1) -/* Low order bits of reload value ignored */ -#define IXP425_OST_RELOAD_MASK (0x3) -#define IXP425_OST_DISABLED (0x0) -#define IXP425_OSST_TIMER_1_PEND BIT(0) -#define IXP425_OSST_TIMER_2_PEND BIT(1) -#define IXP425_OSST_TIMER_TS_PEND BIT(2) -#define IXP425_OSST_TIMER_WDOG_PEND BIT(3) -#define IXP425_OSST_TIMER_WARM_RESET BIT(4) - -/* - * Constants to make it easy to access PCI Control/Status registers - */ -#define PCI_NP_AD_OFFSET 0x00 -#define PCI_NP_CBE_OFFSET 0x04 -#define PCI_NP_WDATA_OFFSET 0x08 -#define PCI_NP_RDATA_OFFSET 0x0c -#define PCI_CRP_AD_CBE_OFFSET 0x10 -#define PCI_CRP_WDATA_OFFSET 0x14 -#define PCI_CRP_RDATA_OFFSET 0x18 -#define PCI_CSR_OFFSET 0x1c -#define PCI_ISR_OFFSET 0x20 -#define PCI_INTEN_OFFSET 0x24 -#define PCI_DMACTRL_OFFSET 0x28 -#define PCI_AHBMEMBASE_OFFSET 0x2c -#define PCI_AHBIOBASE_OFFSET 0x30 -#define PCI_PCIMEMBASE_OFFSET 0x34 -#define PCI_AHBDOORBELL_OFFSET 0x38 -#define PCI_PCIDOORBELL_OFFSET 0x3C -#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40 -#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44 -#define PCI_ATPDMA0_LENADDR_OFFSET 0x48 -#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C -#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50 -#define PCI_ATPDMA1_LENADDR_OFFSET 0x54 - -/* - * PCI Control/Status Registers - */ -#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x))) - -#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET) -#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET) -#define PCI_NP_WDATA IXP425_PCI_CSR(PCI_NP_WDATA_OFFSET) -#define PCI_NP_RDATA IXP425_PCI_CSR(PCI_NP_RDATA_OFFSET) -#define PCI_CRP_AD_CBE IXP425_PCI_CSR(PCI_CRP_AD_CBE_OFFSET) -#define PCI_CRP_WDATA IXP425_PCI_CSR(PCI_CRP_WDATA_OFFSET) -#define PCI_CRP_RDATA IXP425_PCI_CSR(PCI_CRP_RDATA_OFFSET) -#define PCI_CSR IXP425_PCI_CSR(PCI_CSR_OFFSET) -#define PCI_ISR IXP425_PCI_CSR(PCI_ISR_OFFSET) -#define PCI_INTEN IXP425_PCI_CSR(PCI_INTEN_OFFSET) -#define PCI_DMACTRL IXP425_PCI_CSR(PCI_DMACTRL_OFFSET) -#define PCI_AHBMEMBASE IXP425_PCI_CSR(PCI_AHBMEMBASE_OFFSET) -#define PCI_AHBIOBASE IXP425_PCI_CSR(PCI_AHBIOBASE_OFFSET) -#define PCI_PCIMEMBASE IXP425_PCI_CSR(PCI_PCIMEMBASE_OFFSET) -#define PCI_AHBDOORBELL IXP425_PCI_CSR(PCI_AHBDOORBELL_OFFSET) -#define PCI_PCIDOORBELL IXP425_PCI_CSR(PCI_PCIDOORBELL_OFFSET) -#define PCI_ATPDMA0_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET) -#define PCI_ATPDMA0_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET) -#define PCI_ATPDMA0_LENADDR IXP425_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET) -#define PCI_ATPDMA1_AHBADDR IXP425_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET) -#define PCI_ATPDMA1_PCIADDR IXP425_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET) -#define PCI_ATPDMA1_LENADDR IXP425_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET) - -/* - * PCI register values and bit definitions - */ - -/* CSR bit definitions */ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/* ISR (Interrupt status) Register bit definitions */ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/* INTEN (Interrupt Enable) Register bit definitions */ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/* - * Shift value for byte enable on NP cmd/byte enable register - */ -#define IXP425_PCI_NP_CBE_BESL 4 - -/* - * PCI commands supported by NP access unit - */ -#define NP_CMD_IOREAD 0x2 -#define NP_CMD_IOWRITE 0x3 -#define NP_CMD_CONFIGREAD 0xa -#define NP_CMD_CONFIGWRITE 0xb -#define NP_CMD_MEMREAD 0x6 -#define NP_CMD_MEMWRITE 0x7 - -#if 0 -#ifndef __ASSEMBLY__ -extern int ixp425_pci_read(u32 addr, u32 cmd, u32* data); -extern int ixp425_pci_write(u32 addr, u32 cmd, u32 data); -extern void ixp425_pci_init(void *); -#endif -#endif - -/* - * Constants for CRP access into local config space - */ -#define CRP_AD_CBE_BESL 20 -#define CRP_AD_CBE_WRITE BIT(16) - -/* - * Clock Speed Definitions. - */ -#define IXP425_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */ - - -#endif diff --git a/arch/arm/include/asm/arch-ixp/ixp425pci.h b/arch/arm/include/asm/arch-ixp/ixp425pci.h deleted file mode 100644 index f4998839363..00000000000 --- a/arch/arm/include/asm/arch-ixp/ixp425pci.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * IXP PCI Init - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _IXP425PCI_H -#define _IXP425PCI_H - -#define OK 0 -#define ERROR -1 - -struct pci_controller; -extern void pci_ixp_init(struct pci_controller *hose); - -/* Mask definitions*/ -#define IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK 0x0000000f - -#define PCI_NP_CBE_BESL (4) -#define PCI_NP_AD_FUNCSL (8) - -/*Register addressing definitions for PCI controller configuration - and status registers*/ - -#define PCI_CSR_BASE (0xC0000000) -/* -#define PCI_NP_AD_OFFSET (0x00) -#define PCI_NP_CBE_OFFSET (0x04) -#define PCI_NP_WDATA_OFFSET (0x08) -#define PCI_NP_RDATA_OFFSET (0x0C) -#define PCI_CRP_OFFSET (0x10) -#define PCI_CRP_WDATA_OFFSET (0x14) -#define PCI_CRP_RDATA_OFFSET (0x18) -#define PCI_CSR_OFFSET (0x1C) -#define PCI_ISR_OFFSET (0x20) -#define PCI_INTEN_OFFSET (0x24) -#define PCI_DMACTRL_OFFSET (0x28) -#define PCI_AHBMEMBASE_OFFSET (0x2C) -#define PCI_AHBIOBASE_OFFSET (0x30) -#define PCI_PCIMEMBASE_OFFSET (0x34) -#define PCI_AHBDOORBELL_OFFSET (0x38) -#define PCI_PCIDOORBELL_OFFSET (0x3C) -#define PCI_ATPDMA0_AHBADDR (0x40) -#define PCI_ATPDMA0_PCIADDR (0x44) -#define PCI_ATPDMA0_LENADDR (0x48) -#define PCI_ATPDMA1_AHBADDR (0x4C) -#define PCI_ATPDMA1_PCIADDR (0x50) -#define PCI_ATPDMA1_LENADDR (0x54) -#define PCI_PTADMA0_AHBADDR (0x58) -#define PCI_PTADMA0_PCIADDR (0x5C) -#define PCI_PTADMA0_LENADDR (0x60) -#define PCI_PTADMA1_AHBADDR (0x64) -#define PCI_PTADMA1_PCIADDR (0x68) -#define PCI_PTADMA1_LENADDR (0x6C) -*/ -/*Non prefetch registers bit definitions*/ -/* -#define NP_CMD_INTACK (0x0) -#define NP_CMD_SPECIAL (0x1) -#define NP_CMD_IOREAD (0x2) -#define NP_CMD_IOWRITE (0x3) -#define NP_CMD_MEMREAD (0x6) -#define NP_CMD_MEMWRITE (0x7) -#define NP_CMD_CONFIGREAD (0xa) -#define NP_CMD_CONFIGWRITE (0xb) -*/ - -/*Configuration Port register bit definitions*/ -#define PCI_CRP_WRITE BIT(16) - -/*ISR (Interrupt status) Register bit definitions*/ -#define PCI_ISR_PSE BIT(0) -#define PCI_ISR_PFE BIT(1) -#define PCI_ISR_PPE BIT(2) -#define PCI_ISR_AHBE BIT(3) -#define PCI_ISR_APDC BIT(4) -#define PCI_ISR_PADC BIT(5) -#define PCI_ISR_ADB BIT(6) -#define PCI_ISR_PDB BIT(7) - -/*INTEN (Interrupt Enable) Register bit definitions*/ -#define PCI_INTEN_PSE BIT(0) -#define PCI_INTEN_PFE BIT(1) -#define PCI_INTEN_PPE BIT(2) -#define PCI_INTEN_AHBE BIT(3) -#define PCI_INTEN_APDC BIT(4) -#define PCI_INTEN_PADC BIT(5) -#define PCI_INTEN_ADB BIT(6) -#define PCI_INTEN_PDB BIT(7) - -/*PCI configuration regs.*/ - -#define PCI_CFG_VENDOR_ID 0x00 -#define PCI_CFG_DEVICE_ID 0x02 -#define PCI_CFG_COMMAND 0x04 -#define PCI_CFG_STATUS 0x06 -#define PCI_CFG_REVISION 0x08 -#define PCI_CFG_PROGRAMMING_IF 0x09 -#define PCI_CFG_SUBCLASS 0x0a -#define PCI_CFG_CLASS 0x0b -#define PCI_CFG_CACHE_LINE_SIZE 0x0c -#define PCI_CFG_LATENCY_TIMER 0x0d -#define PCI_CFG_HEADER_TYPE 0x0e -#define PCI_CFG_BIST 0x0f -#define PCI_CFG_BASE_ADDRESS_0 0x10 -#define PCI_CFG_BASE_ADDRESS_1 0x14 -#define PCI_CFG_BASE_ADDRESS_2 0x18 -#define PCI_CFG_BASE_ADDRESS_3 0x1c -#define PCI_CFG_BASE_ADDRESS_4 0x20 -#define PCI_CFG_BASE_ADDRESS_5 0x24 -#define PCI_CFG_CIS 0x28 -#define PCI_CFG_SUB_VENDOR_ID 0x2c -#define PCI_CFG_SUB_SYSTEM_ID 0x2e -#define PCI_CFG_EXPANSION_ROM 0x30 -#define PCI_CFG_RESERVED_0 0x34 -#define PCI_CFG_RESERVED_1 0x38 -#define PCI_CFG_DEV_INT_LINE 0x3c -#define PCI_CFG_DEV_INT_PIN 0x3d -#define PCI_CFG_MIN_GRANT 0x3e -#define PCI_CFG_MAX_LATENCY 0x3f -#define PCI_CFG_SPECIAL_USE 0x41 -#define PCI_CFG_MODE 0x43 - -#define PCI_CMD_IO_ENABLE 0x0001 /* IO access enable */ -#define PCI_CMD_MEM_ENABLE 0x0002 /* memory access enable */ -#define PCI_CMD_MASTER_ENABLE 0x0004 /* bus master enable */ -#define PCI_CMD_MON_ENABLE 0x0008 /* monitor special cycles enable */ -#define PCI_CMD_WI_ENABLE 0x0010 /* write and invalidate enable */ -#define PCI_CMD_SNOOP_ENABLE 0x0020 /* palette snoop enable */ -#define PCI_CMD_PERR_ENABLE 0x0040 /* parity error enable */ -#define PCI_CMD_WC_ENABLE 0x0080 /* wait cycle enable */ -#define PCI_CMD_SERR_ENABLE 0x0100 /* system error enable */ -#define PCI_CMD_FBTB_ENABLE 0x0200 /* fast back to back enable */ - - -/*CSR Register bit definitions*/ -#define PCI_CSR_HOST BIT(0) -#define PCI_CSR_ARBEN BIT(1) -#define PCI_CSR_ADS BIT(2) -#define PCI_CSR_PDS BIT(3) -#define PCI_CSR_ABE BIT(4) -#define PCI_CSR_DBT BIT(5) -#define PCI_CSR_ASE BIT(8) -#define PCI_CSR_IC BIT(15) - -/*Configuration command bit definitions*/ -#define PCI_CFG_CMD_IOAE BIT(0) -#define PCI_CFG_CMD_MAE BIT(1) -#define PCI_CFG_CMD_BME BIT(2) -#define PCI_CFG_CMD_MWIE BIT(4) -#define PCI_CFG_CMD_SER BIT(8) -#define PCI_CFG_CMD_FBBE BIT(9) -#define PCI_CFG_CMD_MDPE BIT(24) -#define PCI_CFG_CMD_STA BIT(27) -#define PCI_CFG_CMD_RTA BIT(28) -#define PCI_CFG_CMD_RMA BIT(29) -#define PCI_CFG_CMD_SSE BIT(30) -#define PCI_CFG_CMD_DPE BIT(31) - -/*DMACTRL DMA Control and status Register*/ -#define PCI_DMACTRL_APDCEN BIT(0) -#define PCI_DMACTRL_APDC0 BIT(4) -#define PCI_DMACTRL_APDE0 BIT(5) -#define PCI_DMACTRL_APDC1 BIT(6) -#define PCI_DMACTRL_APDE1 BIT(7) -#define PCI_DMACTRL_PADCEN BIT(8) -#define PCI_DMACTRL_PADC0 BIT(12) -#define PCI_DMACTRL_PADE0 BIT(13) -#define PCI_DMACTRL_PADC1 BIT(14) -#define PCI_DMACTRL_PADE1 BIT(15) - -#endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 60e872637fc..63e4ad5a674 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -32,9 +32,6 @@ struct arch_global_data { unsigned long tbl; unsigned long lastinc; unsigned long long timer_reset_value; -#ifdef CONFIG_IXP425 - unsigned long timestamp; -#endif #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) unsigned long tlb_addr; unsigned long tlb_size; diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index dfea54ae733..db9b4026b37 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -29,9 +29,6 @@ #include #endif #endif -#ifdef CONFIG_IXP425 /* only valid for IXP425 */ -#include -#endif #if defined(CONFIG_MPC852T) || defined(CONFIG_MPC866) #include #endif -- cgit v1.2.3 From b1c756782c38cf69ba71bbe51186ad4b98e4cdb3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:15:55 +0100 Subject: ARM: USB: Remove the IXP EHCI driver The driver is no longer used, remove it. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- drivers/usb/host/Makefile | 1 - drivers/usb/host/ehci-ixp4xx.c | 37 ------------------------------------- 2 files changed, 38 deletions(-) delete mode 100644 drivers/usb/host/ehci-ixp4xx.c (limited to 'drivers') diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 14170282dbb..578b097fc95 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -31,7 +31,6 @@ obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o -obj-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o obj-$(CONFIG_USB_EHCI_SPEAR) += ehci-spear.o diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c deleted file mode 100644 index 646e815e71d..00000000000 --- a/drivers/usb/host/ehci-ixp4xx.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2008, Michael Trimarchi - * - * Author: Michael Trimarchi - * This code is based on ehci freescale driver - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include - -#include "ehci.h" -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, - struct ehci_hccr **hccr, struct ehci_hcor **hcor) -{ - *hccr = (struct ehci_hccr *)(0xcd000100); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr - + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - - printf("IXP4XX init hccr %x and hcor %x hc_length %d\n", - (uint32_t)*hccr, (uint32_t)*hcor, - (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); - return 0; -} - -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} -- cgit v1.2.3 From c75692d3625c415e0e3fe982bd72a3300d828465 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:18:20 +0100 Subject: ARM: PCI: Remove the IXP PCI driver The driver is no longer used, remove it. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- doc/driver-model/UDM-pci.txt | 4 - drivers/pci/Makefile | 1 - drivers/pci/pci_ixp.c | 351 ------------------------------------------- 3 files changed, 356 deletions(-) delete mode 100644 drivers/pci/pci_ixp.c (limited to 'drivers') diff --git a/doc/driver-model/UDM-pci.txt b/doc/driver-model/UDM-pci.txt index 059a4329fb9..1dce99de3dc 100644 --- a/doc/driver-model/UDM-pci.txt +++ b/doc/driver-model/UDM-pci.txt @@ -125,10 +125,6 @@ III) Analysis of in-tree drivers Shared driver for indirect PCI bridges, several CONFIG macros - will require significant cleanup. - pci_ixp.c - --------- - Standard driver, specifies all read/write functions separately. - pci_sh4.c --------- Shared init function for SH4 drivers, uses dword for read/write ops. diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 6182a5904db..f0dfb5994cf 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -11,7 +11,6 @@ obj-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o obj-$(CONFIG_PCI_MSC01) += pci_msc01.o obj-$(CONFIG_FTPCI100) += pci_ftpci100.o -obj-$(CONFIG_IXP_PCI) += pci_ixp.o obj-$(CONFIG_SH4_PCI) += pci_sh4.o obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o diff --git a/drivers/pci/pci_ixp.c b/drivers/pci/pci_ixp.c deleted file mode 100644 index d71fda28464..00000000000 --- a/drivers/pci/pci_ixp.c +++ /dev/null @@ -1,351 +0,0 @@ -/* - * IXP PCI Init - * - * (C) Copyright 2011 - * Michael Schwingen, michael@schwingen.org - * (C) Copyright 2004 eslab.whut.edu.cn - * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void non_prefetch_read(unsigned int addr, unsigned int cmd, - unsigned int *data); -static void non_prefetch_write(unsigned int addr, unsigned int cmd, - unsigned int data); - -/*define the sub vendor and subsystem to be used */ -#define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000 - -#define PCI_MEMORY_BUS 0x00000000 -#define PCI_MEMORY_PHY 0x00000000 -#define PCI_MEMORY_SIZE 0x04000000 - -#define PCI_MEM_BUS 0x48000000 -#define PCI_MEM_PHY 0x00000000 -#define PCI_MEM_SIZE 0x04000000 - -#define PCI_IO_BUS 0x00000000 -#define PCI_IO_PHY 0x00000000 -#define PCI_IO_SIZE 0x00010000 - -/* build address value for config sycle */ -static unsigned int pci_config_addr(pci_dev_t bdf, unsigned int reg) -{ - unsigned int bus = PCI_BUS(bdf); - unsigned int dev = PCI_DEV(bdf); - unsigned int func = PCI_FUNC(bdf); - unsigned int addr; - - if (bus) { /* secondary bus, use type 1 config cycle */ - addr = bdf | (reg & ~3) | 1; - } else { - /* - primary bus, type 0 config cycle. address bits 31:28 - specify the device 10:8 specify the function - */ - addr = BIT((31 - dev)) | (func << 8) | (reg & ~3); - } - - return addr; -} - -static int pci_config_status(void) -{ - unsigned int regval; - - regval = readl(PCI_CSR_BASE + PCI_ISR_OFFSET); - if ((regval & PCI_ISR_PFE) == 0) - return OK; - - /* no device present, make sure that the master abort bit is reset */ - writel(PCI_ISR_PFE, PCI_CSR_BASE + PCI_ISR_OFFSET); - return ERROR; -} - -static int pci_ixp_hose_read_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int *val) -{ - unsigned int retval; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_dword: bdf %x, reg %x", bdf, where); - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, NP_CMD_CONFIGREAD, &retval); - *val = retval; - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short *val) -{ - unsigned int n; - unsigned int retval; - unsigned int addr; - unsigned int byteEnables; - int stat; - - debug("pci_ixp_hose_read_config_word: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - - /*Pick out the word we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_read_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char *val) -{ - unsigned int retval; - unsigned int n; - unsigned int byteEnables; - unsigned int addr; - int stat; - - debug("pci_ixp_hose_read_config_byte: bdf %x, reg %x", bdf, where); - n = where % 4; - /*byte enables are 4 bits, active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - - /*Set the address to be read */ - addr = pci_config_addr(bdf, where); - non_prefetch_read(addr, byteEnables | NP_CMD_CONFIGREAD, &retval); - /*Pick out the byte we are interested in */ - *val = retval >> (8 * n); - - stat = pci_config_status(); - if (stat < 0) - *val = -1; - debug("-> val %x, status %x\n", *val, stat); - return stat; -} - -static int pci_ixp_hose_write_config_byte(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned char val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_byte: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = (~BIT(n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_word(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned short val) -{ - unsigned int addr; - unsigned int byteEnables; - unsigned int n; - unsigned int ldata; - int stat; - - debug("pci_ixp_hose_write_config_word: bdf %x, reg %x, val %x", - bdf, where, val); - n = where % 4; - /*byte enables are 4 bits active low, the position of each - bit maps to the byte that it enables */ - byteEnables = - (~(BIT(n) | BIT((n + 1)))) & - IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK; - byteEnables = byteEnables << PCI_NP_CBE_BESL; - ldata = val << (8 * n); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, byteEnables | NP_CMD_CONFIGWRITE, ldata); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static int pci_ixp_hose_write_config_dword(struct pci_controller *hose, - pci_dev_t bdf, int where, unsigned int val) -{ - unsigned int addr; - int stat; - - debug("pci_ixp_hose_write_config_dword: bdf %x, reg %x, val %x", - bdf, where, val); - /*Set the address to be written */ - addr = pci_config_addr(bdf, where); - non_prefetch_write(addr, NP_CMD_CONFIGWRITE, val); - - stat = pci_config_status(); - debug("-> status %x\n", stat); - return stat; -} - -static void non_prefetch_read(unsigned int addr, - unsigned int cmd, unsigned int *data) -{ - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - - /*set up and execute the read */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - - /*The result of the read is now in np_rdata */ - *data = readl(PCI_CSR_BASE + PCI_NP_RDATA_OFFSET); - - return; -} - -static void non_prefetch_write(unsigned int addr, - unsigned int cmd, unsigned int data) -{ - - writel(addr, PCI_CSR_BASE + PCI_NP_AD_OFFSET); - /*set up the write */ - writel(cmd, PCI_CSR_BASE + PCI_NP_CBE_OFFSET); - /*Execute the write by writing to NP_WDATA */ - writel(data, PCI_CSR_BASE + PCI_NP_WDATA_OFFSET); - - return; -} - -static void crp_write(unsigned int offset, unsigned int data) -{ - /* - * The CRP address register bit 16 indicates that we want to do a - * write - */ - writel(PCI_CRP_WRITE | offset, PCI_CSR_BASE + PCI_CRP_AD_CBE_OFFSET); - writel(data, PCI_CSR_BASE + PCI_CRP_WDATA_OFFSET); -} - -void pci_ixp_init(struct pci_controller *hose) -{ - unsigned int csr; - - /* - * Specify that the AHB bus is operating in big endian mode. Set up - * byte lane swapping between little-endian PCI and the big-endian - * AHB bus - */ -#ifdef __ARMEB__ - csr = PCI_CSR_ABE | PCI_CSR_PDS | PCI_CSR_ADS; -#else - csr = PCI_CSR_ABE; -#endif - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - writel(0, PCI_CSR_BASE + PCI_INTEN_OFFSET); - - /* - * We configure the PCI inbound memory windows to be - * 1:1 mapped to SDRAM - */ - crp_write(PCI_CFG_BASE_ADDRESS_0, 0x00000000); - crp_write(PCI_CFG_BASE_ADDRESS_1, 0x01000000); - crp_write(PCI_CFG_BASE_ADDRESS_2, 0x02000000); - crp_write(PCI_CFG_BASE_ADDRESS_3, 0x03000000); - - /* - * Enable CSR window at 64 MiB to allow PCI masters - * to continue prefetching past 64 MiB boundary. - */ - crp_write(PCI_CFG_BASE_ADDRESS_4, 0x04000000); - /* - * Enable the IO window to be way up high, at 0xfffffc00 - */ - crp_write(PCI_CFG_BASE_ADDRESS_5, 0xfffffc01); - - /*Setup PCI-AHB and AHB-PCI address mappings */ - writel(0x00010203, PCI_CSR_BASE + PCI_AHBMEMBASE_OFFSET); - - writel(0x00000000, PCI_CSR_BASE + PCI_AHBIOBASE_OFFSET); - - writel(0x48494a4b, PCI_CSR_BASE + PCI_PCIMEMBASE_OFFSET); - - crp_write(PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM); - - crp_write(PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME); - udelay(1000); - - /* clear error bits in status register */ - writel(PCI_ISR_PSE | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE, - PCI_CSR_BASE + PCI_ISR_OFFSET); - - /* - * Set Initialize Complete in PCI Control Register: allow IXP4XX to - * respond to PCI configuration cycles. - */ - csr |= PCI_CSR_IC; - writel(csr, PCI_CSR_BASE + PCI_CSR_OFFSET); - - hose->first_busno = 0; - hose->last_busno = 0; - - /* System memory space */ - pci_set_region(hose->regions + 0, - PCI_MEMORY_BUS, - PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - PCI_MEM_BUS, - PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM); - /* PCI I/O space */ - pci_set_region(hose->regions + 2, - PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO); - - hose->region_count = 3; - - pci_set_ops(hose, - pci_ixp_hose_read_config_byte, - pci_ixp_hose_read_config_word, - pci_ixp_hose_read_config_dword, - pci_ixp_hose_write_config_byte, - pci_ixp_hose_write_config_word, - pci_ixp_hose_write_config_dword); - - pci_register_hose(hose); - hose->last_busno = pci_hose_scan(hose); -} -- cgit v1.2.3 From 0b2d3f209a33648a9d235af3927c113a7cfa4c29 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:19:47 +0100 Subject: ARM: NET: Remove the IXP NPE ethernet driver This driver is no longer used, remove it. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- Makefile | 1 - drivers/net/npe/IxEthAcc.c | 237 -- drivers/net/npe/IxEthAccCommon.c | 1025 -------- drivers/net/npe/IxEthAccControlInterface.c | 509 ---- drivers/net/npe/IxEthAccDataPlane.c | 2459 ------------------ drivers/net/npe/IxEthAccMac.c | 2617 -------------------- drivers/net/npe/IxEthAccMii.c | 386 --- drivers/net/npe/IxEthDBAPI.c | 424 ---- drivers/net/npe/IxEthDBAPISupport.c | 651 ----- drivers/net/npe/IxEthDBCore.c | 439 ---- drivers/net/npe/IxEthDBEvents.c | 496 ---- drivers/net/npe/IxEthDBFeatures.c | 638 ----- drivers/net/npe/IxEthDBFirewall.c | 242 -- drivers/net/npe/IxEthDBHashtable.c | 618 ----- drivers/net/npe/IxEthDBLearning.c | 125 - drivers/net/npe/IxEthDBMem.c | 625 ----- drivers/net/npe/IxEthDBNPEAdaptor.c | 695 ------ drivers/net/npe/IxEthDBPortUpdate.c | 716 ------ drivers/net/npe/IxEthDBReports.c | 628 ----- drivers/net/npe/IxEthDBSearch.c | 303 --- drivers/net/npe/IxEthDBSpanningTree.c | 83 - drivers/net/npe/IxEthDBUtil.c | 96 - drivers/net/npe/IxEthDBVlan.c | 1155 --------- drivers/net/npe/IxEthDBWiFi.c | 456 ---- drivers/net/npe/IxEthMii.c | 473 ---- drivers/net/npe/IxFeatureCtrl.c | 398 --- drivers/net/npe/IxNpeDl.c | 916 ------- drivers/net/npe/IxNpeDlImageMgr.c | 663 ----- drivers/net/npe/IxNpeDlNpeMgr.c | 907 ------- drivers/net/npe/IxNpeDlNpeMgrUtils.c | 782 ------ drivers/net/npe/IxNpeMh.c | 558 ----- drivers/net/npe/IxNpeMhConfig.c | 584 ----- drivers/net/npe/IxNpeMhReceive.c | 296 --- drivers/net/npe/IxNpeMhSend.c | 283 --- drivers/net/npe/IxNpeMhSolicitedCbMgr.c | 334 --- drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c | 222 -- drivers/net/npe/IxOsalBufferMgt.c | 776 ------ drivers/net/npe/IxOsalIoMem.c | 307 --- drivers/net/npe/IxOsalOsCacheMMU.c | 43 - drivers/net/npe/IxOsalOsMsgQ.c | 55 - drivers/net/npe/IxOsalOsSemaphore.c | 209 -- drivers/net/npe/IxOsalOsServices.c | 227 -- drivers/net/npe/IxOsalOsThread.c | 74 - drivers/net/npe/IxQMgrAqmIf.c | 939 ------- drivers/net/npe/IxQMgrDispatcher.c | 1320 ---------- drivers/net/npe/IxQMgrInit.c | 209 -- drivers/net/npe/IxQMgrQAccess.c | 772 ------ drivers/net/npe/IxQMgrQCfg.c | 519 ---- drivers/net/npe/Makefile | 60 - drivers/net/npe/include/IxAssert.h | 47 - drivers/net/npe/include/IxAtmSch.h | 480 ---- drivers/net/npe/include/IxAtmTypes.h | 385 --- drivers/net/npe/include/IxAtmdAcc.h | 1169 --------- drivers/net/npe/include/IxAtmdAccCtrl.h | 1933 --------------- drivers/net/npe/include/IxAtmm.h | 771 ------ drivers/net/npe/include/IxDmaAcc.h | 236 -- drivers/net/npe/include/IxEthAcc.h | 2488 ------------------- drivers/net/npe/include/IxEthAccDataPlane_p.h | 221 -- drivers/net/npe/include/IxEthAccMac_p.h | 224 -- drivers/net/npe/include/IxEthAccMii_p.h | 73 - drivers/net/npe/include/IxEthAccQueueAssign_p.h | 113 - drivers/net/npe/include/IxEthAcc_p.h | 301 --- drivers/net/npe/include/IxEthDB.h | 2349 ------------------ drivers/net/npe/include/IxEthDBLocks_p.h | 98 - drivers/net/npe/include/IxEthDBLog_p.h | 203 -- drivers/net/npe/include/IxEthDBMessages_p.h | 234 -- drivers/net/npe/include/IxEthDBPortDefs.h | 139 -- drivers/net/npe/include/IxEthDBQoS.h | 130 - drivers/net/npe/include/IxEthDB_p.h | 686 ----- drivers/net/npe/include/IxEthMii.h | 246 -- drivers/net/npe/include/IxEthMii_p.h | 161 -- drivers/net/npe/include/IxEthNpe.h | 671 ----- drivers/net/npe/include/IxFeatureCtrl.h | 718 ------ drivers/net/npe/include/IxHssAcc.h | 1292 ---------- drivers/net/npe/include/IxI2cDrv.h | 843 ------- drivers/net/npe/include/IxNpeA.h | 758 ------ drivers/net/npe/include/IxNpeDl.h | 956 ------- drivers/net/npe/include/IxNpeDlImageMgr_p.h | 339 --- drivers/net/npe/include/IxNpeDlMacros_p.h | 390 --- .../net/npe/include/IxNpeDlNpeMgrEcRegisters_p.h | 869 ------- drivers/net/npe/include/IxNpeDlNpeMgrUtils_p.h | 381 --- drivers/net/npe/include/IxNpeDlNpeMgr_p.h | 236 -- drivers/net/npe/include/IxNpeMh.h | 473 ---- drivers/net/npe/include/IxNpeMhConfig_p.h | 531 ---- drivers/net/npe/include/IxNpeMhMacros_p.h | 272 -- drivers/net/npe/include/IxNpeMhReceive_p.h | 115 - drivers/net/npe/include/IxNpeMhSend_p.h | 139 -- drivers/net/npe/include/IxNpeMhSolicitedCbMgr_p.h | 147 -- .../net/npe/include/IxNpeMhUnsolicitedCbMgr_p.h | 145 -- drivers/net/npe/include/IxNpeMicrocode.h | 272 -- drivers/net/npe/include/IxOsBufLib.h | 31 - drivers/net/npe/include/IxOsBuffMgt.h | 28 - drivers/net/npe/include/IxOsBuffPoolMgt.h | 50 - drivers/net/npe/include/IxOsCacheMMU.h | 36 - drivers/net/npe/include/IxOsPrintf.h | 78 - drivers/net/npe/include/IxOsServices.h | 31 - drivers/net/npe/include/IxOsServicesComponents.h | 110 - drivers/net/npe/include/IxOsServicesEndianess.h | 28 - drivers/net/npe/include/IxOsServicesMemAccess.h | 28 - drivers/net/npe/include/IxOsServicesMemMap.h | 30 - drivers/net/npe/include/IxOsal.h | 1493 ----------- drivers/net/npe/include/IxOsalAssert.h | 57 - drivers/net/npe/include/IxOsalBackward.h | 41 - drivers/net/npe/include/IxOsalBackwardAssert.h | 30 - drivers/net/npe/include/IxOsalBackwardBufferMgt.h | 135 - drivers/net/npe/include/IxOsalBackwardCacheMMU.h | 45 - drivers/net/npe/include/IxOsalBackwardMemMap.h | 117 - drivers/net/npe/include/IxOsalBackwardOsServices.h | 101 - drivers/net/npe/include/IxOsalBackwardOssl.h | 248 -- drivers/net/npe/include/IxOsalBufferMgt.h | 570 ----- drivers/net/npe/include/IxOsalBufferMgtDefault.h | 64 - drivers/net/npe/include/IxOsalConfig.h | 52 - drivers/net/npe/include/IxOsalEndianess.h | 110 - drivers/net/npe/include/IxOsalIoMem.h | 298 --- drivers/net/npe/include/IxOsalMemAccess.h | 470 ---- drivers/net/npe/include/IxOsalOem.h | 73 - drivers/net/npe/include/IxOsalOs.h | 30 - drivers/net/npe/include/IxOsalOsAssert.h | 10 - drivers/net/npe/include/IxOsalOsBufferMgt.h | 72 - drivers/net/npe/include/IxOsalOsIxp400.h | 292 --- .../npe/include/IxOsalOsIxp400CustomizedMapping.h | 380 --- drivers/net/npe/include/IxOsalOsTypes.h | 60 - drivers/net/npe/include/IxOsalOsUtilitySymbols.h | 4 - drivers/net/npe/include/IxOsalTypes.h | 355 --- drivers/net/npe/include/IxOsalUtilitySymbols.h | 27 - drivers/net/npe/include/IxParityENAcc.h | 761 ------ drivers/net/npe/include/IxPerfProfAcc.h | 1334 ---------- drivers/net/npe/include/IxQMgr.h | 2186 ---------------- drivers/net/npe/include/IxQMgrAqmIf_p.h | 903 ------- drivers/net/npe/include/IxQMgrDefines_p.h | 31 - drivers/net/npe/include/IxQMgrDispatcher_p.h | 82 - drivers/net/npe/include/IxQMgrLog_p.h | 100 - drivers/net/npe/include/IxQMgrQAccess_p.h | 72 - drivers/net/npe/include/IxQMgrQCfg_p.h | 98 - drivers/net/npe/include/IxQueueAssignments.h | 492 ---- drivers/net/npe/include/IxSspAcc.h | 1247 ---------- drivers/net/npe/include/IxTimeSyncAcc.h | 759 ------ drivers/net/npe/include/IxTimerCtrl.h | 239 -- drivers/net/npe/include/IxTypes.h | 62 - drivers/net/npe/include/IxUART.h | 434 ---- drivers/net/npe/include/IxVersionId.h | 131 - drivers/net/npe/include/ix_error.h | 42 - drivers/net/npe/include/ix_macros.h | 242 -- drivers/net/npe/include/ix_os_type.h | 41 - drivers/net/npe/include/ix_ossl.h | 136 - drivers/net/npe/include/ix_symbols.h | 82 - drivers/net/npe/include/ix_types.h | 184 -- drivers/net/npe/include/npe.h | 74 - drivers/net/npe/include/os_datatypes.h | 58 - drivers/net/npe/miiphy.c | 101 - drivers/net/npe/npe.c | 680 ----- 151 files changed, 65939 deletions(-) delete mode 100644 drivers/net/npe/IxEthAcc.c delete mode 100644 drivers/net/npe/IxEthAccCommon.c delete mode 100644 drivers/net/npe/IxEthAccControlInterface.c delete mode 100644 drivers/net/npe/IxEthAccDataPlane.c delete mode 100644 drivers/net/npe/IxEthAccMac.c delete mode 100644 drivers/net/npe/IxEthAccMii.c delete mode 100644 drivers/net/npe/IxEthDBAPI.c delete mode 100644 drivers/net/npe/IxEthDBAPISupport.c delete mode 100644 drivers/net/npe/IxEthDBCore.c delete mode 100644 drivers/net/npe/IxEthDBEvents.c delete mode 100644 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100644 drivers/net/npe/miiphy.c delete mode 100644 drivers/net/npe/npe.c (limited to 'drivers') diff --git a/Makefile b/Makefile index 1687e2e90ab..0e07aa59700 100644 --- a/Makefile +++ b/Makefile @@ -227,7 +227,6 @@ LIBS-y += $(CPUDIR)/ ifdef SOC LIBS-y += $(CPUDIR)/$(SOC)/ endif -LIBS-$(CONFIG_IXP4XX_NPE) += drivers/net/npe/ LIBS-$(CONFIG_OF_EMBED) += dts/ LIBS-y += arch/$(ARCH)/lib/ LIBS-y += fs/ diff --git a/drivers/net/npe/IxEthAcc.c b/drivers/net/npe/IxEthAcc.c deleted file mode 100644 index 05a9e053ff0..00000000000 --- a/drivers/net/npe/IxEthAcc.c +++ /dev/null @@ -1,237 +0,0 @@ -/** - * @file IxEthAcc.c - * - * @author Intel Corporation - * @date 20-Feb-2001 - * - * @brief This file contains the implementation of the IXP425 Ethernet Access Component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - - -#include "IxEthAcc.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxFeatureCtrl.h" - -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAcc - *@{ - */ - - -/** - * @brief System-wide information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccInfo ixEthAccDataInfo; -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -/** - * @brief System-wide information - * - * @ingroup IxEthAccPri - * - */ -BOOL ixEthAccServiceInit = false; - -/* global filtering bit mask */ -PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * @brief Per port information data strucure. - * - * @ingroup IxEthAccPri - * - */ - -IxEthAccPortDataInfo ixEthAccPortData[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PUBLIC IxEthAccStatus ixEthAccInit() -{ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* - * Initialize Control plane - */ - if (ixEthDBInit() != IX_ETH_DB_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: EthDB init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - ixEthAccNewSrcMask = (~0); /* want all the bits */ - } - else - { - ixEthAccNewSrcMask = (~IX_ETHACC_NE_NEWSRCMASK); /* want all but the NewSrc bit */ - } - - /* - * Initialize Data plane - */ - if ( ixEthAccInitDataPlane() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: data plane init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - - if ( ixEthAccQMgrQueuesConfig() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: queue config failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MII - */ - if ( ixEthAccMiiInit() != IX_ETH_ACC_SUCCESS ) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mii init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize MAC I/O memory - */ - if (ixEthAccMacMemInit() != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Mac init failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* - * Initialize control plane interface lock - */ - if (ixOsalMutexInit(&ixEthAccControlInterfaceMutex) != IX_SUCCESS) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccInit: Control plane interface lock initialization failed\n", 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - /* initialiasation is complete */ - ixEthAccServiceInit = true; - - return IX_ETH_ACC_SUCCESS; - -} - -PUBLIC void ixEthAccUnload(void) -{ - IxEthAccPortId portId; - - if ( IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - /* check none of the port is still active */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccUnload: port %u still active, bail out\n", portId, 0, 0, 0, 0, 0); - return; - } - } - } - - /* unmap the memory areas */ - ixEthAccMiiUnload(); - ixEthAccMacUnload(); - - /* set all ports as uninitialized */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixEthAccPortData[portId].portInitialized = false; - } - - /* uninitialize the service */ - ixEthAccServiceInit = false; - } -} - -PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId) -{ - - IxEthAccStatus ret=IX_ETH_ACC_SUCCESS; - - if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() ) - { - return(IX_ETH_ACC_FAIL); - } - - /* - * Check for valid port - */ - - if ( ! IX_ETH_ACC_IS_PORT_VALID(portId) ) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Eth port.\n",(INT32) portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if ( IX_ETH_IS_PORT_INITIALIZED(portId) ) - { - /* Already initialized */ - return(IX_ETH_ACC_FAIL); - } - - if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set the port init flag. - */ - - ixEthAccPortData[portId].portInitialized = true; - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* init learning/filtering database structures for this port */ - ixEthDBPortInit(portId); -#endif - - return(ret); -} - - diff --git a/drivers/net/npe/IxEthAccCommon.c b/drivers/net/npe/IxEthAccCommon.c deleted file mode 100644 index 8249737b0c2..00000000000 --- a/drivers/net/npe/IxEthAccCommon.c +++ /dev/null @@ -1,1025 +0,0 @@ -/** - * @file IxEthAccCommon.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation common support routines for the component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* - * Component header files - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxNpeMh.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMii_p.h" - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -extern IxEthAccInfo ixEthAccDataInfo; - -/** - * - * @brief Maximum number of RX queues set to be the maximum number - * of traffic calsses. - * - */ -#define IX_ETHACC_MAX_RX_QUEUES \ - (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \ - - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \ - + 1) - -/** - * - * @brief Maximum number of 128 entry RX queues - * - */ -#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4 - -/** - * - * @brief Data structure template for Default RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - -/** - * - * @brief Data structure template for Small RX Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate = - { - IX_ETH_ACC_RX_FRAME_ETH_Q, /**< Queue ID */ - "Eth Rx Q", - ixEthRxFrameQMCallback, /**< Functional callback */ - (IxQMgrCallbackId) 0, /**< Callback tag */ - IX_QMGR_Q_SIZE64, /**< Allocate Smaller Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL1, /**< Q High water mark - needed by NPE */ - }; - - -/** - * - * @brief Data structure used to register & initialize the Queues - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrStaticInfo[]= -{ - { - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, - "Eth Rx Fr Q 1", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /***< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, - "Eth Rx Fr Q 2", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, - "Eth Rx Fr Q 3", - ixEthRxFreeQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_ENET0_Q, - "Eth Tx Q 1", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_1, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, - - { - IX_ETH_ACC_TX_FRAME_ENET1_Q, - "Eth Tx Q 2", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_2, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - false, /**< Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL64, /**< Q High water mark */ - }, -#ifdef __ixp46X - { - IX_ETH_ACC_TX_FRAME_ENET2_Q, - "Eth Tx Q 3", - ixEthTxFrameQMCallback, - (IxQMgrCallbackId) IX_ETH_PORT_3, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /** Queue Entry Sizes - all Q entries are single ord entries */ - false, /** Disable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE, /** Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /* No queues use almost empty */ - IX_QMGR_Q_WM_LEVEL64, /** Q High water mark - needed used */ - }, -#endif - { - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - "Eth Tx Done Q", - ixEthTxFrameDoneQMCallback, - (IxQMgrCallbackId) 0, - IX_QMGR_Q_SIZE128, /**< Allocate Max Size Q */ - IX_QMGR_Q_ENTRY_SIZE1, /**< Queue Entry Sizes - all Q entries are single word entries */ - true, /**< Enable Q notification at startup */ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback */ - IX_QMGR_Q_WM_LEVEL0, /**< Q Low water mark */ - IX_QMGR_Q_WM_LEVEL2, /**< Q High water mark - needed by NPE */ - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/** - * - * @brief Data structure used to register & initialize the Queues - * - * The structure will be filled at run time depending on the NPE - * image already loaded and the QoS configured in ethDB. - * - */ -IX_ETH_ACC_PRIVATE -IxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]= -{ - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* PlaceHolder for rx queues - * depending on the QoS configured - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - }, - - { /* Null Termination entry - */ - (IxQMgrQId)0, - (char *) NULL, - (IxQMgrCallback) NULL, - (IxQMgrCallbackId) 0, - 0, - 0, - 0, - 0, - 0, - 0 - } - -}; - -/* forward declarations */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes); - -/** - * @fn ixEthAccQMgrQueueSetup(void) - * - * @brief Setup one queue and its event, and register the callback required - * by this component to the QMgr - * - * @internal - */ -IX_ETH_ACC_PRIVATE IxEthAccStatus -ixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes) -{ - /* - * Configure each Q. - */ - if ( ixQMgrQConfig( qInfoDes->qName, - qInfoDes->qId, - qInfoDes->qSize, - qInfoDes->qWords) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - if ( ixQMgrWatermarkSet( qInfoDes->qId, - qInfoDes->AlmostEmptyThreshold, - qInfoDes->AlmostFullThreshold - ) != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set dispatcher priority. - */ - if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId, - IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY) - != IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Register callbacks for each Q. - */ - if ( ixQMgrNotificationCallbackSet(qInfoDes->qId, - qInfoDes->qCallback, - qInfoDes->callbackTag) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - - /* - * Set notification condition for Q - */ - if (qInfoDes->qNotificationEnableAtStartup == true) - { - if ( ixQMgrNotificationEnable(qInfoDes->qId, - qInfoDes->qConditionSource) - != IX_SUCCESS ) - { - return IX_ETH_ACC_FAIL; - } - } - - return(IX_ETH_ACC_SUCCESS); -} - -/** - * @fn ixEthAccQMgrQueuesConfig(void) - * - * @brief Setup all the queues and register all callbacks required - * by this component to the QMgr - * - * The RxFree queues, tx queues, rx queues are configured statically - * - * Rx queues configuration is driven by QoS setup. - * Many Rx queues may be required when QoS is enabled (this depends - * on IxEthDB setup and the images being downloaded). The configuration - * of the rxQueues is done in many steps as follows: - * - * @li select all Rx queues as configured by ethDB for all ports - * @li sort the queues by traffic class - * @li build the priority dependency for all queues - * @li fill the configuration for all rx queues - * @li configure all statically configured queues - * @li configure all dynamically configured queues - * - * @param none - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrQueuesConfig(void) -{ - struct - { - int npeCount; - UINT32 npeId; - IxQMgrQId qId; - IxEthDBProperty trafficClass; - } rxQueues[IX_ETHACC_MAX_RX_QUEUES]; - - UINT32 rxQueue = 0; - UINT32 rxQueueCount = 0; - IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES; - IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS; - IxEthDBPortId ixEthDbPortId = 0; - IxEthAccPortId ixEthAccPortId = 0; - UINT32 ixNpeId = 0; - UINT32 ixHighestNpeId = 0; - UINT32 sortIterations = 0; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - IxEthAccQregInfo *qInfoDes = NULL; - IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY; - UINT32 ixEthDBParameter = 0; - BOOL completelySorted = false; - - /* Fill the corspondance between ports and queues - * This defines the mapping from port to queue Ids. - */ - - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccRxData.rxFreeQueue - = IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q; -#endif - ixEthAccPortData[IX_ETH_PORT_1].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET0_Q; - ixEthAccPortData[IX_ETH_PORT_2].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET1_Q; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].ixEthAccTxData.txQueue - = IX_ETH_ACC_TX_FRAME_ENET2_Q; -#endif - /* Fill the corspondance between ports and NPEs - * This defines the mapping from port to npeIds. - */ - - ixEthAccPortData[IX_ETH_PORT_1].npeId = IX_NPEMH_NPEID_NPEB; - ixEthAccPortData[IX_ETH_PORT_2].npeId = IX_NPEMH_NPEID_NPEC; -#ifdef __ixp46X - ixEthAccPortData[IX_ETH_PORT_3].npeId = IX_NPEMH_NPEID_NPEA; -#endif - /* set the default rx scheduling discipline */ - ixEthAccDataInfo.schDiscipline = FIFO_NO_PRIORITY; - - /* - * Queue Selection step: - * - * The following code selects all the queues and build - * a temporary array which contains for each queue - * - the queue Id, - * - the highest traffic class (in case of many - * priorities configured for the same queue on different - * ports) - * - the number of different Npes which are - * configured to write to this queue. - * - * The output of this loop is a temporary array of RX queues - * in any order. - * - */ -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - for (ixEthAccPortId = 0; - (ixEthAccPortId < IX_ETH_ACC_NUMBER_OF_PORTS) - && (ret == IX_ETH_ACC_SUCCESS); - ixEthAccPortId++) - { - /* map between ethDb and ethAcc port Ids */ - ixEthDbPortId = (IxEthDBPortId)ixEthAccPortId; - - /* map between npeId and ethAcc port Ids */ - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - - /* Iterate thru the different priorities */ - for (ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY; - ixEthDBTrafficClass++) - { - ixEthDBStatus = ixEthDBFeaturePropertyGet( - ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - ixEthDBTrafficClass, - &ixEthDBPropertyType, - (void *)&ixEthDBParameter); - - if (ixEthDBStatus == IX_ETH_DB_SUCCESS) - { - /* This port and QoS class are mapped to - * a RX queue. - */ - if (ixEthDBPropertyType == IX_ETH_DB_INTEGER_PROPERTY) - { - /* remember the highest npe Id supporting ethernet */ - if (ixNpeId > ixHighestNpeId) - { - ixHighestNpeId = ixNpeId; - } - - /* search the queue in the list of queues - * already used by an other port or QoS - */ - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].qId == (IxQMgrQId)ixEthDBParameter) - { - /* found an existing setup, update the number of ports - * for this queue if the port maps to - * a different NPE. - */ - if (rxQueues[rxQueue].npeId != ixNpeId) - { - rxQueues[rxQueue].npeCount++; - rxQueues[rxQueue].npeId = ixNpeId; - } - /* get the highest traffic class for this queue */ - if (rxQueues[rxQueue].trafficClass > ixEthDBTrafficClass) - { - rxQueues[rxQueue].trafficClass = ixEthDBTrafficClass; - } - break; - } - } - if (rxQueue == rxQueueCount) - { - /* new queue not found in the current list, - * add a new entry. - */ - IX_OSAL_ASSERT(rxQueueCount < IX_ETHACC_MAX_RX_QUEUES); - rxQueues[rxQueueCount].qId = ixEthDBParameter; - rxQueues[rxQueueCount].npeCount = 1; - rxQueues[rxQueueCount].npeId = ixNpeId; - rxQueues[rxQueueCount].trafficClass = ixEthDBTrafficClass; - rxQueueCount++; - } - } - else - { - /* unexpected property type (not Integer) */ - ret = IX_ETH_ACC_FAIL; - - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: unexpected property type returned by EthDB\n", 0, 0, 0, 0, 0, 0); - - /* no point to continue to iterate */ - break; - } - } - else - { - /* No Rx queue configured for this port - * and this traffic class. Do nothing. - */ - } - } - - /* notify EthDB that queue initialization is complete and traffic class allocation is frozen */ - ixEthDBFeaturePropertySet(ixEthDbPortId, - IX_ETH_DB_VLAN_QOS, - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE, - NULL /* ignored */); - } - -#else - - ixNpeId = IX_ETH_ACC_PORT_TO_NPE_ID(ixEthAccPortId); - rxQueues[0].qId = 4; - rxQueues[0].npeCount = 1; - rxQueues[0].npeId = ixNpeId; - rxQueues[0].trafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - rxQueueCount++; - -#endif - - /* check there is at least 1 rx queue : there is no point - * to continue if there is no rx queue configured - */ - if ((rxQueueCount == 0) || (ret == IX_ETH_ACC_FAIL)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: no queues configured, bailing out\n", 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - /* Queue sort step: - * - * Re-order the array of queues by decreasing traffic class - * using a bubble sort. (trafficClass 0 is the lowest - * priority traffic, trafficClass 7 is the highest priority traffic) - * - * Primary sort order is traffic class - * Secondary sort order is npeId - * - * Note that a bubble sort algorithm is not very efficient when - * the number of queues grows . However, this is not a very bad choice - * considering the very small number of entries to sort. Also, bubble - * sort is extremely fast when the list is already sorted. - * - * The output of this loop is a sorted array of queues. - * - */ - sortIterations = 0; - do - { - sortIterations++; - completelySorted = true; - for (rxQueue = 0; - rxQueue < rxQueueCount - sortIterations; - rxQueue++) - { - /* compare adjacent elements */ - if ((rxQueues[rxQueue].trafficClass < - rxQueues[rxQueue+1].trafficClass) - || ((rxQueues[rxQueue].trafficClass == - rxQueues[rxQueue+1].trafficClass) - &&(rxQueues[rxQueue].npeId < - rxQueues[rxQueue+1].npeId))) - { - /* swap adjacent elements */ - int npeCount = rxQueues[rxQueue].npeCount; - UINT32 npeId = rxQueues[rxQueue].npeId; - IxQMgrQId qId = rxQueues[rxQueue].qId; - IxEthDBProperty trafficClass = rxQueues[rxQueue].trafficClass; - rxQueues[rxQueue].npeCount = rxQueues[rxQueue+1].npeCount; - rxQueues[rxQueue].npeId = rxQueues[rxQueue+1].npeId; - rxQueues[rxQueue].qId = rxQueues[rxQueue+1].qId; - rxQueues[rxQueue].trafficClass = rxQueues[rxQueue+1].trafficClass; - rxQueues[rxQueue+1].npeCount = npeCount; - rxQueues[rxQueue+1].npeId = npeId; - rxQueues[rxQueue+1].qId = qId; - rxQueues[rxQueue+1].trafficClass = trafficClass; - completelySorted = false; - } - } - } - while (!completelySorted); - - /* Queue traffic class list: - * - * Fill an array of rx queues linked by ascending traffic classes. - * - * If the queues are configured as follows - * qId 6 -> traffic class 0 (lowest) - * qId 7 -> traffic class 0 - * qId 8 -> traffic class 6 - * qId 12 -> traffic class 7 (highest) - * - * Then the output of this loop will be - * - * higherPriorityQueue[6] = 8 - * higherPriorityQueue[7] = 8 - * higherPriorityQueue[8] = 12 - * higherPriorityQueue[12] = Invalid queueId - * higherPriorityQueue[...] = Invalid queueId - * - * Note that this queue ordering does not handle all possibilities - * that could result from different rules associated with different - * ports, and inconsistencies in the rules. In all cases, the - * output of this algorithm is a simple linked list of queues, - * without closed circuit. - - * This list is implemented as an array with invalid values initialized - * with an "invalid" queue id which is the maximum number of queues. - * - */ - - /* - * Initialise the rx queue list. - */ - for (rxQueue = 0; rxQueue < IX_QMGR_MAX_NUM_QUEUES; rxQueue++) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueue] = IX_QMGR_MAX_NUM_QUEUES; - } - - /* build the linked list for this NPE. - */ - for (ixNpeId = 0; - ixNpeId <= ixHighestNpeId; - ixNpeId++) - { - /* iterate thru the sorted list of queues - */ - ixQId = IX_QMGR_MAX_NUM_QUEUES; - for (rxQueue = 0; - rxQueue < rxQueueCount; - rxQueue++) - { - if (rxQueues[rxQueue].npeId == ixNpeId) - { - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - /* iterate thru queues with the same traffic class - * than the current queue. (queues are ordered by descending - * traffic classes and npeIds). - */ - while ((rxQueue < rxQueueCount - 1) - && (rxQueues[rxQueue].trafficClass - == rxQueues[rxQueue+1].trafficClass) - && (ixNpeId == rxQueues[rxQueue].npeId)) - { - rxQueue++; - ixEthAccDataInfo.higherPriorityQueue[rxQueues[rxQueue].qId] = ixQId; - } - ixQId = rxQueues[rxQueue].qId; - } - } - } - - /* point on the first dynamic queue description */ - qInfoDes = ixEthAccQmgrRxQueuesInfo; - - /* update the list of queues with the rx queues */ - for (rxQueue = 0; - (rxQueue < rxQueueCount) && (ret == IX_ETH_ACC_SUCCESS); - rxQueue++) - { - /* Don't utilize more than IX_ETHACC_MAX_LARGE_RX_QUEUES queues - * with the full 128 entries. For the lower priority queues, use - * a smaller number of entries. This ensures queue resources - * remain available for other components. - */ - if( (rxQueueCount > IX_ETHACC_MAX_LARGE_RX_QUEUES) && - (rxQueue < rxQueueCount - IX_ETHACC_MAX_LARGE_RX_QUEUES) ) - { - /* add the small RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxSmallTemplate, sizeof(*qInfoDes)); - } else { - /* add the default RX Queue setup template to the list of queues */ - memcpy(qInfoDes, &ixEthAccQmgrRxDefaultTemplate, sizeof(*qInfoDes)); - } - - /* setup the RxQueue ID */ - qInfoDes->qId = rxQueues[rxQueue].qId; - - /* setup the RxQueue watermark level - * - * Each queue can be filled by many NPEs. To avoid the - * NPEs to write to a full queue, need to set the - * high watermark level for nearly full condition. - * (the high watermark level are a power of 2 - * starting from the top of the queue) - * - * Number of watermark - * ports level - * 1 0 - * 2 1 - * 3 2 - * 4 4 - * 5 4 - * 6 8 - * n approx. 2**ceil(log2(n)) - */ - if (rxQueues[rxQueue].npeCount == 1) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL0; - } - else if (rxQueues[rxQueue].npeCount == 2) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL1; - } - else if (rxQueues[rxQueue].npeCount == 3) - { - qInfoDes->AlmostFullThreshold = IX_QMGR_Q_WM_LEVEL2; - } - else - { - /* reach the maximum number for CSR 2.0 */ - IX_ETH_ACC_WARNING_LOG("ixEthAccQMgrQueuesConfig: maximum number of NPEs per queue reached, bailing out\n", 0, 0, 0, 0, 0, 0); - ret = IX_ETH_ACC_FAIL; - break; - } - - /* move to next queue entry */ - ++qInfoDes; - } - - /* configure the static list (RxFree, Tx and TxDone queues) */ - for (qInfoDes = ixEthAccQmgrStaticInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - /* configure the dynamic list (Rx queues) */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - ret = ixEthAccQMgrQueueSetup(qInfoDes); - } - - return(ret); -} - -/** - * @fn ixEthAccQMgrRxQEntryGet(UINT32 *rxQueueEntries) - * - * @brief Add and return the total number of entries in all Rx queues - * - * @param UINT32 rxQueueEntries[in] number of entries in all queues - * - * @return void - * - * @note Rx queues configuration is driven by Qos Setup. There is a - * variable number of rx queues which are set at initialisation. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries) -{ - UINT32 rxQueueLevel; - IxEthAccQregInfo *qInfoDes;; - - *numRxQueueEntries = 0; - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - qInfoDes->qCallback != (IxQMgrCallback)NULL; - ++qInfoDes) - { - /* retrieve the rx queue level */ - rxQueueLevel = 0; - ixQMgrQNumEntriesGet(qInfoDes->qId, &rxQueueLevel); - (*numRxQueueEntries) += rxQueueLevel; - } -} - -/** - * @fn ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) - * - * @brief Change the callback registered to all rx queues. - * - * @param IxQMgrCallback ixQMgrCallback[in] QMgr callback to register - * - * @return IxEthAccStatus - * - * @note The user may decide to use different Rx mechanisms - * (e.g. receive many frames at the same time , or receive - * one frame at a time, depending on the overall application - * performances). A different QMgr callback is registered. This - * way, there is no excessive pointer checks in the datapath. - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback) -{ - IxEthAccQregInfo *qInfoDes; - IxEthAccStatus ret = IX_ETH_ACC_SUCCESS; - - /* parameter check */ - if (NULL == ixQMgrCallback) - { - ret = IX_ETH_ACC_FAIL; - } - - /* iterate thru rx queues */ - for (qInfoDes = ixEthAccQmgrRxQueuesInfo; - (qInfoDes->qCallback != (IxQMgrCallback) NULL ) - && (ret == IX_ETH_ACC_SUCCESS); - ++qInfoDes) - { - /* register the rx callback for all queues */ - if (ixQMgrNotificationCallbackSet(qInfoDes->qId, - ixQMgrCallback, - qInfoDes->callbackTag - ) != IX_SUCCESS) - { - ret = IX_ETH_ACC_FAIL; - } - } - return(ret); -} - -/** - * @fn ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) - * - * @brief Check the npe exists for this port - * - * @param IxEthAccPortId portId[in] port - * - * @return IxEthAccStatus - * - * @internal - */ -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId) -{ - - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_ENABLED)) - { - return IX_ETH_ACC_SUCCESS; - } - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -/** - * @fn ixEthAccStatsShow(void) - * - * @brief Displays all EthAcc stats - * - * @return void - * - */ -void ixEthAccStatsShow(IxEthAccPortId portId) -{ - ixEthAccMdioShow(); - - printf("\nPort %u\nUnicast MAC : ", portId); - ixEthAccPortUnicastAddressShow(portId); - ixEthAccPortMulticastAddressShow(portId); - printf("\n"); - - ixEthAccDataPlaneShow(); -} - - - diff --git a/drivers/net/npe/IxEthAccControlInterface.c b/drivers/net/npe/IxEthAccControlInterface.c deleted file mode 100644 index dbe32e133c2..00000000000 --- a/drivers/net/npe/IxEthAccControlInterface.c +++ /dev/null @@ -1,509 +0,0 @@ -/** - * @file IxEthAccControlInterface.c - * - * @author Intel Corporation - * @date - * - * @brief IX_ETH_ACC_PUBLIC wrappers for control plane functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" - -PUBLIC IxOsalMutex ixEthAccControlInterfaceMutex; - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: (Mac) cannot enable port %d, service not initialized\n", portId); - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - /* check the context is iinitialized */ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortEnabledQueryPriv(portId, enabled); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeClearPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortPromiscuousModeSetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressSetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastMacAddressGetPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinPriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressJoinAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, IxEthAccMacAddr *macAddr) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeavePriv(portId, macAddr); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMulticastAddressLeaveAllPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortUnicastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC void -ixEthAccPortMulticastAddressShow(IxEthAccPortId portId) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - ixEthAccPortMulticastAddressShowPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId, IxEthAccDuplexMode mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeSetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId, IxEthAccDuplexMode *mode) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortDuplexModeGetPriv(portId, mode); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendPaddingDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxFrameAppendFCSDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccTxSchedulingDisciplineSetPriv(portId, sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccRxSchedulingDisciplineSetPriv(sched); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxEnablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccNpeLoopbackDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortTxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortRxDisablePriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} - -IX_ETH_ACC_PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId) -{ - IxEthAccStatus result; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&ixEthAccControlInterfaceMutex, IX_OSAL_WAIT_FOREVER); - result = ixEthAccPortMacResetPriv(portId); - ixOsalMutexUnlock(&ixEthAccControlInterfaceMutex); - return result; -} diff --git a/drivers/net/npe/IxEthAccDataPlane.c b/drivers/net/npe/IxEthAccDataPlane.c deleted file mode 100644 index c0b82d99b7f..00000000000 --- a/drivers/net/npe/IxEthAccDataPlane.c +++ /dev/null @@ -1,2459 +0,0 @@ -/** - * @file IxEthDataPlane.c - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief This file contains the implementation of the IXPxxx - * Ethernet Access Data plane component - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeMh.h" -#include "IxEthAcc.h" -#include "IxEthDB.h" -#include "IxOsal.h" -#include "IxEthDBPortDefs.h" -#include "IxFeatureCtrl.h" -#include "IxEthAcc_p.h" -#include "IxEthAccQueueAssign_p.h" - -extern PUBLIC IxEthAccMacState ixEthAccMacState[]; -extern PUBLIC UINT32 ixEthAccNewSrcMask; - -/** - * private functions prototype - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask); - -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf); - -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr); - -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority); - -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId); - -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf); - -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, - UINT32 qBuffer); - -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, - UINT32 qBuffer, - UINT32 priority); - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* increment a counter only when stats are enabled */ -#define TX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccTxData.stats.field) -#define RX_STATS_INC(port,field) \ - IX_ETH_ACC_STATS_INC(ixEthAccPortData[port].ixEthAccRxData.stats.field) - -/* always increment the counter (mainly used for unexpected errors) */ -#define TX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccTxData.stats.field++ -#define RX_INC(port,field) \ - ixEthAccPortData[port].ixEthAccRxData.stats.field++ - -PRIVATE IxEthAccDataPlaneStats ixEthAccDataStats; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -extern IxEthAccInfo ixEthAccDataInfo; - -PRIVATE IxOsalFastMutex txWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; -PRIVATE IxOsalFastMutex rxWriteMutex[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/** - * - * @brief Mbuf header conversion macros : they implement the - * different conversions using a temporary value. They also double-check - * that the parameters can be converted to/from NPE format. - * - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MBUF_MBUF_VIRTUAL_TO_PHYSICAL_TRANSLATION((IX_OSAL_MBUF*)ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MBUF_MBUF_PHYSICAL_TO_VIRTUAL_TRANSLATION(temp); } \ - while(0) -#else -#define PTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - IX_OSAL_ENSURE(sizeof(ptrSrc) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(dst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#define PTR_NPE2VIRT(type,src,ptrDst) \ - do { void *temp; \ - IX_OSAL_ENSURE(sizeof(type) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(src) == sizeof(UINT32), "Wrong parameter type"); \ - IX_OSAL_ENSURE(sizeof(ptrDst) == sizeof(UINT32), "Wrong parameter type"); \ - temp = (void *)IX_OSAL_SWAP_BE_SHARED_LONG(src); \ - (ptrDst) = (type)IX_OSAL_MMU_PHYS_TO_VIRT(temp); } \ - while(0) -#endif - -/** - * - * @brief Mbuf payload pointer conversion macros : Wince has its own - * method to convert the buffer pointers - */ -#if defined(__wince) && !defined(IN_KERNEL) -#define DATAPTR_VIRT2NPE(ptrSrc,dst) \ - do { UINT32 temp; \ - temp = (UINT32)IX_OSAL_MBUF_DATA_VIRTUAL_TO_PHYSICAL_TRANSLATION(ptrSrc); \ - (dst) = IX_OSAL_SWAP_BE_SHARED_LONG(temp); } \ - while(0) - -#else -#define DATAPTR_VIRT2NPE(ptrSrc,dst) PTR_VIRT2NPE(IX_OSAL_MBUF_MDATA(ptrSrc),dst) -#endif - - -/* Flush the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_FLUSH(mbufPtr) \ - do { \ - IX_OSAL_CACHE_FLUSH(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Invalidate the shared part of the mbuf header */ -#define IX_ETHACC_NE_CACHE_INVALIDATE(mbufPtr) \ - do { \ - IX_OSAL_CACHE_INVALIDATE(IX_ETHACC_NE_SHARED(mbufPtr), \ - sizeof(IxEthAccNe)); \ - } \ - while(0) - -/* Preload one cache line (shared mbuf headers are aligned - * and their size is 1 cache line) - * - * IX_OSAL_CACHED is defined when the mbuf headers are - * allocated from cached memory. - * - * Other processor on emulation environment may not implement - * preload function - */ -#ifdef IX_OSAL_CACHED - #if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - #define IX_ACC_DATA_CACHE_PRELOAD(ptr) \ - do { /* preload a cache line (Xscale Processor) */ \ - __asm__ (" pld [%0]\n": : "r" (ptr)); \ - } \ - while(0) - #else - /* preload not implemented on different processor */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) - #endif -#else - /* preload not needed if cache is not enabled */ - #define IX_ACC_DATA_CACHE_PRELOAD(mbufPtr) \ - do { /* nothing */ } while (0) -#endif - -/** - * - * @brief function to retrieve the correct pointer from - * a queue entry posted by the NPE - * - * @param qEntry : entry from qmgr queue - * mask : applicable mask for this queue - * (4 most significant bits are used for additional informations) - * - * @return IX_OSAL_MBUF * pointer to mbuf header - * - * @internal - */ -PRIVATE IX_OSAL_MBUF * -ixEthAccEntryFromQConvert(UINT32 qEntry, UINT32 mask) -{ - IX_OSAL_MBUF *mbufPtr; - - if (qEntry != 0) - { - /* mask NPE bits (e.g. priority, port ...) */ - qEntry &= mask; - -#if IX_ACC_DRAM_PHYS_OFFSET != 0 - /* restore the original address pointer (if PHYS_OFFSET is not 0) */ - qEntry |= (IX_ACC_DRAM_PHYS_OFFSET & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); -#endif - /* get the mbuf pointer address from the npe-shared address */ - qEntry -= offsetof(IX_OSAL_MBUF,ix_ne); - - /* phys2virt mbuf */ - mbufPtr = (IX_OSAL_MBUF *)IX_OSAL_MMU_PHYS_TO_VIRT(qEntry); - - /* preload the cacheline shared with NPE */ - IX_ACC_DATA_CACHE_PRELOAD(IX_ETHACC_NE_SHARED(mbufPtr)); - - /* preload the cacheline used by xscale */ - IX_ACC_DATA_CACHE_PRELOAD(mbufPtr); - } - else - { - mbufPtr = NULL; - } - - return mbufPtr; -} - -/* Convert the mbuf header for NPE transmission */ -PRIVATE UINT32 -ixEthAccMbufTxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 qbuf; - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxMBufs); - - /* payload pointer conversion */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : the frame length is the mbuf length - * and the 2 identical lengths are stored in the same - * word. - */ - len = IX_OSAL_MBUF_MLEN(mbuf); - - /* set the length in both length and pktLen 16-bits fields */ - len |= (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next contains 0 */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* get the frame length from the header of the first buffer */ - frmLen = IX_OSAL_MBUF_PKT_LEN(mbuf); - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxMBufs); - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - /* Buffer length and frame length are stored in the same word */ - len = IX_OSAL_MBUF_MLEN(ptr); - len = frmLen | (len << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* get the virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - if (nextPtr != NULL) - { - /* shared pointer of the next buffer is chained */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* move to next buffer */ - ptr = nextPtr; - - /* the frame length field is set only in the first buffer - * and is zeroed in the next buffers - */ - frmLen = 0; - } - while(ptr != NULL); - - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header for NPE reception */ -PRIVATE UINT32 -ixEthAccMbufRxQPrepare(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - UINT32 qbuf; - - if (IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) == NULL) - { - /* "best case" scenario : unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxFreeMBufs); - - /* unchained mbufs : payload pointer */ - DATAPTR_VIRT2NPE(mbuf, IX_ETHACC_NE_DATA(mbuf)); - - /* unchained mbufs : set the buffer length - * and the frame length field is zeroed - */ - len = (IX_OSAL_MBUF_MLEN(mbuf) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(mbuf) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* unchained mbufs : next pointer is null */ - IX_ETHACC_NE_NEXT(mbuf) = 0; - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(mbuf); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(mbuf); - } - else - { - /* chained mbufs */ - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - - do - { - /* chained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxFreeMBufs); - - /* we must save virtual next chain pointer */ - nextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - - if (nextPtr != NULL) - { - /* chaining pointer for NPE */ - PTR_VIRT2NPE(IX_ETHACC_NE_SHARED(nextPtr), - IX_ETHACC_NE_NEXT(ptr)); - } - else - { - IX_ETHACC_NE_NEXT(ptr) = 0; - } - - /* payload pointer */ - DATAPTR_VIRT2NPE(ptr,IX_ETHACC_NE_DATA(ptr)); - - /* buffer length */ - len = (IX_OSAL_MBUF_MLEN(ptr) << IX_ETHNPE_ACC_LENGTH_OFFSET); - IX_ETHACC_NE_LEN(ptr) = IX_OSAL_SWAP_BE_SHARED_LONG(len); - - /* flush shared header after all address conversions */ - IX_ETHACC_NE_CACHE_FLUSH(ptr); - - /* remove shared header cache line */ - IX_ETHACC_NE_CACHE_INVALIDATE(ptr); - - /* next mbuf in the chain */ - ptr = nextPtr; - } - while(ptr != NULL); - } - - /* virt2phys mbuf itself */ - qbuf = (UINT32)IX_OSAL_MMU_VIRT_TO_PHYS( - IX_ETHACC_NE_SHARED(mbuf)); - - /* Ensure the bits which are reserved to exchange information with - * the NPE are cleared - * - * If the mbuf address is not correctly aligned, or from an - * incompatible memory range, there is no point to continue - */ - IX_OSAL_ENSURE(((qbuf & ~IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) == 0), - "Invalid address range"); - - return qbuf; -} - -/* Convert the mbuf header after NPE transmission - * Since there is nothing changed by the NPE, there is no need - * to process anything but the update of internal stats - * when they are enabled -*/ -PRIVATE void -ixEthAccMbufFromTxQ(IX_OSAL_MBUF *mbuf) -{ -#ifndef NDEBUG - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs : update the stats */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedTxDoneMBufs); - } - else - { - /* chained mbufs : walk the chain and update the stats */ - IX_OSAL_MBUF *ptr = mbuf; - - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedTxDoneMBufs); - ptr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr); - } - while (ptr != NULL); - } -#endif -} - -/* Convert the mbuf header after NPE reception */ -PRIVATE void -ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf) -{ - UINT32 len; - - /* endianess swap for tci and flags - note: this is done only once, even for chained buffers */ - IX_ETHACC_NE_FLAGS(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_FLAGS(mbuf)); - IX_ETHACC_NE_VLANTCI(mbuf) = IX_OSAL_SWAP_BE_SHARED_SHORT(IX_ETHACC_NE_VLANTCI(mbuf)); - - /* test for unchained mbufs */ - if (IX_ETHACC_NE_NEXT(mbuf) == 0) - { - /* unchained mbufs */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.unchainedRxMBufs); - - /* get the frame length. it is the same than the buffer length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - len &= IX_ETHNPE_ACC_PKTLENGTH_MASK; - IX_OSAL_MBUF_PKT_LEN(mbuf) = IX_OSAL_MBUF_MLEN(mbuf) = len; - - /* clears the next packet field */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mbuf) = NULL; - } - else - { - IX_OSAL_MBUF *ptr = mbuf; - IX_OSAL_MBUF *nextPtr; - UINT32 frmLen; - - /* convert the frame length */ - frmLen = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(mbuf)); - IX_OSAL_MBUF_PKT_LEN(mbuf) = (frmLen & IX_ETHNPE_ACC_PKTLENGTH_MASK); - - /* chained mbufs */ - do - { - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.chainedRxMBufs); - - /* convert the length */ - len = IX_OSAL_SWAP_BE_SHARED_LONG(IX_ETHACC_NE_LEN(ptr)); - IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET); - - /* get the next pointer */ - PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr); - if (nextPtr != NULL) - { - nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne)); - } - /* set the next pointer */ - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(ptr) = nextPtr; - - /* move to the next buffer */ - ptr = nextPtr; - } - while (ptr != NULL); - } -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the tx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockTxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&txWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - TX_STATS_INC(portId, txOverflow); - } -#endif - ixOsalFastMutexUnlock(&txWriteMutex[portId]); - } - else - { - TX_STATS_INC(portId, txLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* write to qmgr if possible and report an overflow if not possible - * Use a fast lock to protect the queue write. - * This way, the Rx feature is reentrant. - */ -PRIVATE IX_STATUS -ixEthAccQmgrLockRxWrite(IxEthAccPortId portId, UINT32 qBuffer) -{ - IX_STATUS qStatus; - if (ixOsalFastMutexTryLock(&rxWriteMutex[portId]) == IX_SUCCESS) - { - qStatus = ixQMgrQWrite( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - &qBuffer); -#ifndef NDEBUG - if (qStatus != IX_SUCCESS) - { - RX_STATS_INC(portId, rxFreeOverflow); - } -#endif - ixOsalFastMutexUnlock(&rxWriteMutex[portId]); - } - else - { - RX_STATS_INC(portId, rxFreeLock); - qStatus = IX_QMGR_Q_OVERFLOW; - } - return qStatus; -} - -/* - * Set the priority and write to a qmgr queue. - */ -PRIVATE IX_STATUS -ixEthAccQmgrTxWrite(IxEthAccPortId portId, UINT32 qBuffer, UINT32 priority) -{ - /* fill the priority field */ - qBuffer |= (priority << IX_ETHNPE_QM_Q_FIELD_PRIOR_R); - - return ixEthAccQmgrLockTxWrite(portId, qBuffer); -} - -/** - * - * @brief This function will discover the highest priority S/W Tx Q that - * has entries in it - * - * @param portId - (in) the id of the port whose S/W Tx queues are to be searched - * priorityPtr - (out) the priority of the highest priority occupied q will be written - * here - * - * @return IX_ETH_ACC_SUCCESS if an occupied Q is found - * IX_ETH_ACC_FAIL if no Q has entries - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxSwQHighestPriorityGet(IxEthAccPortId portId, - IxEthAccTxPriority *priorityPtr) -{ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline - == FIFO_NO_PRIORITY) - { - if(IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[IX_ETH_ACC_TX_DEFAULT_PRIORITY])) - { - return IX_ETH_ACC_FAIL; - } - else - { - *priorityPtr = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - TX_STATS_INC(portId,txPriority[*priorityPtr]); - return IX_ETH_ACC_SUCCESS; - } - } - else - { - IxEthAccTxPriority highestPriority = IX_ETH_ACC_TX_PRIORITY_7; - while(1) - { - if(!IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccTxData.txQ[highestPriority])) - { - - *priorityPtr = highestPriority; - TX_STATS_INC(portId,txPriority[highestPriority]); - return IX_ETH_ACC_SUCCESS; - - } - if (highestPriority == IX_ETH_ACC_TX_PRIORITY_0) - { - return IX_ETH_ACC_FAIL; - } - highestPriority--; - } - } -} - -/** - * - * @brief This function will take a buffer from a TX S/W Q and attempt - * to add it to the relevant TX H/W Q - * - * @param portId - the port whose TX queue is to be written to - * priority - identifies the queue from which the entry is to be read - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccTxFromSwQ(IxEthAccPortId portId, - IxEthAccTxPriority priority) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus; - - IX_OSAL_ENSURE((UINT32)priority <= (UINT32)7, "Invalid priority"); - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - if (mbuf != NULL) - { - /* - * Add the Tx buffer to the H/W Tx Q - * We do not need to flush here as it is already done - * in TxFrameSubmit(). - */ - qStatus = ixEthAccQmgrTxWrite( - portId, - IX_OSAL_MMU_VIRT_TO_PHYS((UINT32)IX_ETHACC_NE_SHARED(mbuf)), - priority); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txFromSwQOK); - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer - * back on the s/w Q. - * we must put it back on the head of the q to avoid - * reordering packet tx - */ - TX_STATS_INC(portId,txFromSwQDelayed); - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - /*enable Q notification*/ - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS && qStatus != IX_QMGR_WARNING) - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - TX_INC(portId,txUnexpectedError); - - /* recovery attempt */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccTxData.txQ[priority], - mbuf); - - IX_ETH_ACC_FATAL_LOG( - "ixEthAccTxFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - -/** - * - * @brief This function will take a buffer from a RXfree S/W Q and attempt - * to add it to the relevant RxFree H/W Q - * - * @param portId - the port whose RXFree queue is to be written to - * - * @internal - */ -PRIVATE IxEthAccStatus -ixEthAccRxFreeFromSwQ(IxEthAccPortId portId) -{ - IX_OSAL_MBUF *mbuf; - IX_STATUS qStatus = IX_SUCCESS; - - IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - if (mbuf != NULL) - { - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, - IX_OSAL_MMU_VIRT_TO_PHYS( - (UINT32)IX_ETHACC_NE_SHARED(mbuf))); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepFromSwQOK); - /* - * Buffer added to h/w Q. - */ - return IX_SUCCESS; - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * H/W Q overflow, need to save the buffer back on the s/w Q. - */ - RX_STATS_INC(portId,rxFreeRepFromSwQDelayed); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - } - else - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - mbuf); - - IX_ETH_ACC_FATAL_LOG("IxEthAccRxFreeFromSwQ:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - } - else - { - /* sw queue is empty */ - } - return IX_ETH_ACC_FAIL; -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccInitDataPlane() -{ - UINT32 portId; - - /* - * Initialize the service and register callback to other services. - */ - - IX_ETH_ACC_MEMSET(&ixEthAccDataStats, - 0, - sizeof(ixEthAccDataStats)); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - ixOsalFastMutexInit(&txWriteMutex[portId]); - ixOsalFastMutexInit(&rxWriteMutex[portId]); - - IX_ETH_ACC_MEMSET(&ixEthAccPortData[portId], - 0, - sizeof(ixEthAccPortData[portId])); - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = FIFO_NO_PRIORITY; - } - - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback - txCallbackFn, - UINT32 callbackTag) -{ - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - -/* HACK: removing this code to enable NPE-A preliminary testing - * if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - * { - * IX_ETH_ACC_WARNING_LOG("ixEthAccPortTxDoneCallbackRegister: Unavailable Eth %d: Cannot register TxDone Callback.\n",(INT32)portId,0,0,0,0,0); - * return IX_ETH_ACC_SUCCESS ; - * } - */ - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if (txCallbackFn == 0) - /* Check for null function pointer here. */ - { - return (IX_ETH_ACC_INVALID_ARG); - } - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = txCallbackFn; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = callbackTag; - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == true)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxFrameQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - IX_ETH_ACC_FATAL_LOG("ixEthAccPortRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx single-buffer callback\n", 0, 0, 0, 0, 0, 0); - - RX_INC(portId,rxUnexpectedError); - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = false; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortMultiBufferRxCallbackRegister( - IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback - rxCallbackFn, - UINT32 callbackTag) -{ - IxEthAccPortId port; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccPortMultiBufferRxCallbackRegister: Unavailable Eth %d: Cannot register Rx Callback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* Check for null function pointer here. */ - if (rxCallbackFn == NULL) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - /* Check the user is not changing the callback type - * when the port is enabled. - */ - if (ixEthAccMacState[portId].portDisableState == ACTIVE) - { - for (port = 0; port < IX_ETH_ACC_NUMBER_OF_PORTS; port++) - { - if ((ixEthAccMacState[port].portDisableState == ACTIVE) - && (ixEthAccPortData[port].ixEthAccRxData.rxMultiBufferCallbackInUse == false)) - { - /* one of the active ports has a different rx callback type. - * Changing the callback type when the port is enabled - * is not safe - */ - return (IX_ETH_ACC_INVALID_ARG); - } - } - } - - /* update the callback pointer : this is done before - * registering the new qmgr callback - */ - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = rxCallbackFn; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = callbackTag; - - /* update the qmgr callback for rx queues */ - if (ixEthAccQMgrRxCallbacksRegister(ixEthRxMultiBufferQMCallback) - != IX_ETH_ACC_SUCCESS) - { - /* unexpected qmgr error */ - RX_INC(portId,rxUnexpectedError); - - IX_ETH_ACC_FATAL_LOG("ixEthAccPortMultiBufferRxCallbackRegister: unexpected QMgr error, " \ - "could not register Rx multi-buffer callback\n", 0, 0, 0, 0, 0, 0); - - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackInUse = true; - - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortTxFrameSubmit(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - IxEthAccTxPriority highestPriority; - IxQMgrQStatus txQStatus; - -#ifndef NDEBUG - if (buffer == NULL) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG("ixEthAccPortTxFrameSubmit: Unavailable Eth %d: Cannot submit Tx Frame.\n", - (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - if ((UINT32)priority > (UINT32)IX_ETH_ACC_TX_PRIORITY_7) - { - return (IX_ETH_ACC_INVALID_ARG); - } -#endif - - /* - * Need to Flush the MBUF and its contents (data) as it may be - * read from the NPE. Convert virtual addresses to physical addresses also. - */ - qBuffer = ixEthAccMbufTxQPrepare(buffer); - - /* - * If no fifo priority set on Xscale ... - */ - if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_NO_PRIORITY) - { - /* - * Add The Tx Buffer to the H/W Tx Q if possible - * (the priority is passed to the NPE, because - * the NPE is able to reorder the frames - * before transmission to the underlying hardware) - */ - qStatus = ixEthAccQmgrTxWrite(portId, - qBuffer, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - - if (qStatus == IX_SUCCESS) - { - TX_STATS_INC(portId,txQOK); - - /* - * "best case" scenario : Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in the sw Q. - * (use the default priority queue regardless of - * input parameter) - */ - priority = IX_ETH_ACC_TX_DEFAULT_PRIORITY; - } - else - { - /* unexpected qmgr error */ - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - } - else if (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY) - { - - /* - * For priority transmission, put the frame directly on the H/W queue - * if the H/W queue is empty, otherwise, put it in a S/W Q - */ - ixQMgrQStatusGet(IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), &txQStatus); - if((txQStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) != 0) - { - /*The tx queue is empty, check whether there are buffers on the s/w queues*/ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - - /* the queue was empty, 1 buffer is already supplied - * but is likely to be immediately transmitted and the - * hw queue is likely to be empty again, so submit - * more from the sw queues - */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - ixEthAccTxFromSwQ(portId, highestPriority); - /* - * and force the buffer supplied to be placed - * on a priority queue - */ - qStatus = IX_QMGR_Q_OVERFLOW; - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - /*there are no buffers in the s/w queues, submit directly*/ - qStatus = ixEthAccQmgrTxWrite(portId, qBuffer, priority); - } - } - else - { - qStatus = IX_QMGR_Q_OVERFLOW; - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit:Error: wrong schedule discipline setup\n", - 0, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - if(qStatus == IX_SUCCESS ) - { - TX_STATS_INC(portId,txQOK); - return IX_ETH_ACC_SUCCESS; - } - else if(qStatus == IX_QMGR_Q_OVERFLOW) - { - TX_STATS_INC(portId,txQDelayed); - /* - * We were unable to write the buffer to the - * appropriate H/W Q, Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId]. - ixEthAccTxData.txQ[priority], - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId), - IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - */ - TX_STATS_INC(portId,txLateNotificationEnabled); - - /* pull a buffer from the sw queue */ - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) - !=IX_ETH_ACC_FAIL) - { - /*there are buffers on the s/w queues, submit from them*/ - ixEthAccTxFromSwQ(portId, highestPriority); - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - TX_INC(portId,txUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccPortTxFrameSubmit: unexpected Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - return (IX_ETH_ACC_FAIL); - } - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * - * @brief replenish: convert a chain of mbufs to the format - * expected by the NPE - * - */ - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccPortRxFreeReplenish(IxEthAccPortId portId, - IX_OSAL_MBUF *buffer) -{ - IX_STATUS qStatus = IX_SUCCESS; - UINT32 qBuffer; - - /* - * Check buffer is valid. - */ - -#ifndef NDEBUG - /* check parameter value */ - if (buffer == 0) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - /* check initialisation is done */ - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_FATAL_LOG(" ixEthAccPortRxFreeReplenish: Unavailable Eth %d: Cannot replenish Rx Free Q.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_PORT_UNINITIALIZED ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - /* check boundaries and constraints */ - if (IX_OSAL_MBUF_MLEN(buffer) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - { - return (IX_ETH_ACC_FAIL); - } -#endif - - qBuffer = ixEthAccMbufRxQPrepare(buffer); - - /* - * Add The Rx Buffer to the H/W Free buffer Q if possible - */ - qStatus = ixEthAccQmgrLockRxWrite(portId, qBuffer); - - if (qStatus == IX_SUCCESS) - { - RX_STATS_INC(portId,rxFreeRepOK); - /* - * Buffer added to h/w Q. - */ - return (IX_SUCCESS); - } - else if (qStatus == IX_QMGR_Q_OVERFLOW) - { - RX_STATS_INC(portId,rxFreeRepDelayed); - /* - * We were unable to write the buffer to the approprate H/W Q, - * Save it in a s/w Q. - */ - IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL( - ixEthAccPortData[portId].ixEthAccRxData.freeBufferList, - buffer); - - qStatus = ixQMgrNotificationEnable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId), - IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(portId)); - - if (qStatus != IX_SUCCESS) - { - if (qStatus == IX_QMGR_WARNING) - { - /* notification is enabled for a queue - * which is already empty (the condition is already met) - * and there will be no more queue event to drain the sw queue - * move an entry from the sw queue to the hw queue */ - RX_STATS_INC(portId,rxFreeLateNotificationEnabled); - ixEthAccRxFreeFromSwQ(portId); - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: %u\n", - qStatus, 0, 0, 0, 0, 0); - } - } - } - else - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthAccRxPortFreeReplenish:Error: qStatus = %u\n", - (UINT32)qStatus, 0, 0, 0, 0, 0); - return(IX_ETH_ACC_FAIL); - } - return (IX_ETH_ACC_SUCCESS); -} - - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline - sched) -{ - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - return (IX_ETH_ACC_INVALID_PORT); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("ixEthAccTxSchedulingDisciplineSet: Unavailable Eth %d: Cannot set Tx Scheduling Discipline.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccPortData[portId].ixEthAccTxData.schDiscipline = sched; - return (IX_ETH_ACC_SUCCESS); -} - -IX_ETH_ACC_PUBLIC -IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline - sched) -{ - if (sched != FIFO_PRIORITY && sched != FIFO_NO_PRIORITY) - { - return (IX_ETH_ACC_INVALID_ARG); - } - - ixEthAccDataInfo.schDiscipline = sched; - - return (IX_ETH_ACC_SUCCESS); -} - - -/** - * @fn ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) - * - * @brief process incoming frame : - * - * @param @ref IxQMgrCallback IxQMgrMultiBufferCallback - * - * @return none - * - * @internal - * - */ -IX_ETH_ACC_PRIVATE BOOL -ixEthRxFrameProcess(IxEthAccPortId portId, IX_OSAL_MBUF *mbufPtr) -{ - UINT32 flags; - IxEthDBStatus result; - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameProcess: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return false; - } -#endif - - /* convert fields from mbuf header */ - ixEthAccMbufFromRxQ(mbufPtr); - - /* check about any special processing for this frame */ - flags = IX_ETHACC_NE_FLAGS(mbufPtr); - if ((flags & (IX_ETHACC_NE_FILTERMASK | IX_ETHACC_NE_NEWSRCMASK)) == 0) - { - /* "best case" scenario : nothing special to do for this frame */ - return true; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* if a new source MAC address is detected by the NPE, - * update IxEthDB with the portId and the MAC address. - */ - if ((flags & IX_ETHACC_NE_NEWSRCMASK & ixEthAccNewSrcMask) != 0) - { - result = ixEthDBFilteringDynamicEntryProvision(portId, - (IxEthDBMacAddr *) IX_ETHACC_NE_SOURCEMAC(mbufPtr)); - - if (result != IX_ETH_DB_SUCCESS && result != IX_ETH_DB_FEATURE_UNAVAILABLE) - { - if ((ixEthAccMacState[portId].portDisableState == ACTIVE) && (result != IX_ETH_DB_BUSY)) - { - RX_STATS_INC(portId, rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to add source MAC \ - to the Learning/Filtering database\n", 0, 0, 0, 0, 0, 0); - } - else - { - /* we expect this to fail during PortDisable, as EthDB is disabled for - * that port and will refuse to learn new addresses - */ - } - } - else - { - RX_STATS_INC(portId, rxUnlearnedMacAddress); - } - } -#endif - - /* check if this frame should have been filtered - * by the NPE and take the appropriate action - */ - if (((flags & IX_ETHACC_NE_FILTERMASK) != 0) - && (ixEthAccMacState[portId].portDisableState == ACTIVE)) - { - /* If the mbuf was allocated with a small data size, or the current data pointer is not - * within the allocated data area, then the buffer is non-standard and has to be - * replenished with the minimum size only - */ - if( (IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) < IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN) - || ((UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) > IX_OSAL_MBUF_MDATA(mbufPtr)) - || ((UINT8 *)(IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr) + - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr)) - < IX_OSAL_MBUF_MDATA(mbufPtr)) ) - { - /* set to minimum length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN; - } - else - { - /* restore original length */ - IX_OSAL_MBUF_MLEN(mbufPtr) = IX_OSAL_MBUF_PKT_LEN(mbufPtr) = - ( IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(mbufPtr) - - (IX_OSAL_MBUF_MDATA(mbufPtr) - (UINT8 *)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(mbufPtr)) ); - } - - /* replenish from here */ - if (ixEthAccPortRxFreeReplenish(portId, mbufPtr) != IX_ETH_ACC_SUCCESS) - { - IX_ETH_ACC_FATAL_LOG("ixEthRxFrameProcess: Failed to replenish with filtered frame\ - on port %d\n", portId, 0, 0, 0, 0, 0); - } - - RX_STATS_INC(portId, rxFiltered); - - /* indicate that frame should not be subjected to further processing */ - return false; - } - - return true; -} - - -/** - * @fn ixEthRxFrameQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed one-at-a-time to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 destPortId; - UINT32 npeId; - UINT32 rxQReadStatus; - - /* - * Design note : entries are read in a buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameQMCallback: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* process frame, check the return code and skip the remaining of - * the loop if the frame is to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* destination portId for this packet */ - destPortId = IX_ETHACC_NE_DESTPORTID(mbufPtr); - - if (destPortId != IX_ETH_DB_UNKNOWN_PORT) - { - destPortId = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(destPortId); - } - - /* test if QoS is enabled in ethAcc - */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxFrameQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag, - mbufPtr, - destPortId); - } - } - } while (rxQReadStatus == IX_SUCCESS); -} - -/** - * @fn ixEthRxMultiBufferQMCallback - * - * @brief receive callback for Frame receive Q from NPE - * - * Frames are passed as an array to the user - * - * @param @ref IxQMgrCallback - * - * @return none - * - * @internal - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - IX_OSAL_MBUF *nextMbufPtr; - UINT32 qEntry; - UINT32 nextQEntry; - UINT32 *qEntryPtr; - UINT32 portId; - UINT32 npeId; - UINT32 rxQReadStatus; - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra zeroed entry so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 rxQEntry[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - static IX_OSAL_MBUF *rxMbufPortArray[IX_ETH_ACC_NUMBER_OF_PORTS][IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK + 1]; - IX_OSAL_MBUF **rxMbufPtr[IX_ETH_ACC_NUMBER_OF_PORTS]; - - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - - /* - * Indication of the number of times the callback is used. - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackCounter); - - do - { - /* - * Indication of the number of times the queue is drained - */ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.rxCallbackBurstRead); - - /* ensure the last entry of the array contains a zeroed value */ - qEntryPtr = rxQEntry; - qEntryPtr[IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK] = 0; - - rxQReadStatus = ixQMgrQBurstRead(qId, - IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if ((rxQReadStatus != IX_QMGR_Q_UNDERFLOW) - && (rxQReadStatus != IX_SUCCESS)) - { - ixEthAccDataStats.unexpectedError++; - /*major error*/ - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: %u\n", - (UINT32)rxQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert and preload the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *qEntryPtr; - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - while(nextQEntry != 0) - { - /* get the next entry */ - qEntry = nextQEntry; - mbufPtr = nextMbufPtr; - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFrameMultiBufferQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* convert the next entry - * (the conversion function takes care about null pointers which - * are used to mark the end of the loop) - */ - nextQEntry = *(++qEntryPtr); - nextMbufPtr = ixEthAccEntryFromQConvert(nextQEntry, - IX_ETHNPE_QM_Q_RXENET_ADDR_MASK); - - /* - * Get Port and Npe ID from message. - */ - npeId = ((IX_ETHNPE_QM_Q_RXENET_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - - /* skip the remaining of the loop if the frame is - * to be filtered out - */ - if (ixEthRxFrameProcess(portId, mbufPtr)) - { - /* store a mbuf pointer in an array */ - *rxMbufPtr[portId]++ = mbufPtr; - - /* - * increment priority stats - */ - RX_STATS_INC(portId,rxPriority[IX_ETHACC_NE_QOS(mbufPtr)]); - } - - /* test for QoS enabled in ethAcc */ - if (ixEthAccDataInfo.schDiscipline == FIFO_PRIORITY) - { - /* check if there is a higher priority queue - * which may require processing and then process it. - */ - if (ixEthAccDataInfo.higherPriorityQueue[qId] < IX_QMGR_MAX_NUM_QUEUES) - { - ixEthRxMultiBufferQMCallback(ixEthAccDataInfo.higherPriorityQueue[qId], - callbackId); - } - } - } - - /* check if any of the the arrays contains any entry */ - for (portId = 0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - if (rxMbufPtr[portId] != rxMbufPortArray[portId]) - { - /* add a last NULL pointer at the end of the - * array of mbuf pointers - */ - *rxMbufPtr[portId] = NULL; - - /* - * increment callback count stats - */ - RX_STATS_INC(portId,rxFrameClientCallback); - - /* - * Call user level callback with an array of - * buffers (NULL terminated) - */ - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackFn( - ixEthAccPortData[portId].ixEthAccRxData. - rxMultiBufferCallbackTag, - rxMbufPortArray[portId]); - - /* reset the buffer pointer to the beginning of - * the array - */ - rxMbufPtr[portId] = rxMbufPortArray[portId]; - } - } - - } while (rxQReadStatus == IX_SUCCESS); -} - - -/** - * @brief rxFree low event handler - * - */ -void ixEthRxFreeQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD; - IX_STATUS qStatus = IX_SUCCESS; - - /* - * We have reached a low threshold on one of the Rx Free Qs - */ - - /*note that due to the fact that we are working off an Empty threshold, this callback - need only write a single entry to the Rx Free queue in order to re-arm the notification - */ - - RX_STATS_INC(portId,rxFreeLowCallback); - - /* - * Get buffers from approprite S/W Rx freeBufferList Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - /* - * Turn off Q callback notification for Q in Question. - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - RX_INC(portId,rxUnexpectedError); - IX_ETH_ACC_FATAL_LOG( - "ixEthRxFreeQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - return; - } - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - /* - * Load the H/W Q with buffers from the s/w Q. - */ - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * And endianess converted if required. - */ - if (ixEthAccRxFreeFromSwQ(portId) != IX_SUCCESS) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - if (IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(ixEthAccPortData[portId]. - ixEthAccRxData.freeBufferList)) - { - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(portId)); - } - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - break; - } - } - while (--maxQWritesToPerform); - } -} -/** - * @fn Tx queue low event handler - * - */ -void -ixEthTxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IxEthAccPortId portId = (IxEthAccPortId) callbackId; - int lockVal; - UINT32 maxQWritesToPerform = IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK; - IX_STATUS qStatus = IX_SUCCESS; - IxEthAccTxPriority highestPriority; - - - /* - * We have reached a low threshold on the Tx Q, and are being asked to - * supply a buffer for transmission from our S/W TX queues - */ - TX_STATS_INC(portId,txLowThreshCallback); - - /* - * Get buffers from approprite Q. - */ - -#ifndef NDEBUG - if (!IX_ETH_ACC_IS_PORT_VALID(portId)) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: Invalid Port 0x%08X\n", - portId, 0, 0, 0, 0, 0); - return; - } -#endif - - do - { - /* - * Consume Q entries. - Note Q contains Physical addresss, - * and have already been flushed to memory, - * and endianess already sone if required. - */ - - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); - - if(ixEthAccTxSwQHighestPriorityGet(portId, &highestPriority) == - IX_ETH_ACC_FAIL) - { - /* - * No more entries in s/w Q. - * Turn off Q callback indication - */ - qStatus = ixQMgrNotificationDisable( - IX_ETH_ACC_PORT_TO_TX_Q_ID(portId)); - - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - - if (qStatus != IX_SUCCESS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameQMCallback:Error: unexpected QM status 0x%08X\n", - qStatus, 0, 0, 0, 0, 0); - } - - return; - } - else - { - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); - if (ixEthAccTxFromSwQ(portId,highestPriority)!=IX_SUCCESS) - { - /* nothing left in the sw queue or the hw queues are - * full. There is no point to continue to drain the - * sw queues - */ - return; - } - } - } - while (--maxQWritesToPerform); -} - -/** - * @brief TxDone event handler - * - * Design note : while processing the entry X, entry X+1 is preloaded - * into memory to reduce the number of stall cycles - * - */ - -void -ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId) -{ - IX_OSAL_MBUF *mbufPtr; - UINT32 qEntry; - UINT32 *qEntryPtr; - UINT32 txDoneQReadStatus; - UINT32 portId; - UINT32 npeId; - - /* - * Design note : entries are read in a static buffer, This buffer contains - * an extra entyry (which is zeroed by the compiler), so the loop will - * always terminate on a null entry, whatever the result of Burst read is. - */ - static UINT32 txDoneQEntry[IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK + 1]; - - /* - * Indication that Tx frames have been transmitted from the NPE. - */ - - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.txDoneCallbackCounter); - - do{ - qEntryPtr = txDoneQEntry; - txDoneQReadStatus = ixQMgrQBurstRead(IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, - IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK, - qEntryPtr); - -#ifndef NDEBUG - if (txDoneQReadStatus != IX_QMGR_Q_UNDERFLOW - && (txDoneQReadStatus != IX_SUCCESS)) - { - /*major error*/ - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: %u\n", - (UINT32)txDoneQReadStatus, 0, 0, 0, 0, 0); - return; - } -#endif - - qEntry = *qEntryPtr; - - while(qEntry != 0) - { - mbufPtr = ixEthAccEntryFromQConvert(qEntry, - IX_ETHNPE_QM_Q_TXENET_ADDR_MASK); - -#ifndef NDEBUG - if (mbufPtr == NULL) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback:Error: Null Mbuf Ptr\n", - 0, 0, 0, 0, 0, 0); - return; - } -#endif - - /* endianness conversions and stats updates */ - ixEthAccMbufFromTxQ(mbufPtr); - - /* - * Get NPE id from message, then convert to portId. - */ - npeId = ((IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK & - qEntry) >> - IX_ETHNPE_QM_Q_FIELD_NPEID_R); - portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - ixEthAccDataStats.unexpectedError++; - IX_ETH_ACC_FATAL_LOG( - "ixEthTxFrameDoneQMCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - TX_STATS_INC(portId,txDoneClientCallback); - - /* - * Call user level callback. - */ - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn( - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag, - mbufPtr); - - /* move to next queue entry */ - qEntry = *(++qEntryPtr); - - } - } while( txDoneQReadStatus == IX_SUCCESS ); -} - -IX_ETH_ACC_PUBLIC -void ixEthAccDataPlaneShow(void) -{ - UINT32 numTx0Entries; - UINT32 numTx1Entries; - UINT32 numTxDoneEntries; - UINT32 numRxEntries; - UINT32 numRxFree0Entries; - UINT32 numRxFree1Entries; - UINT32 portId; -#ifdef __ixp46X - UINT32 numTx2Entries; - UINT32 numRxFree2Entries; -#endif -#ifndef NDEBUG - UINT32 priority; - UINT32 numBuffersInRx=0; - UINT32 numBuffersInTx=0; - UINT32 numBuffersInSwQ=0; - UINT32 totalBuffers=0; - UINT32 rxFreeCallbackCounter = 0; - UINT32 txCallbackCounter = 0; -#endif - UINT32 key; - - /* snapshot of stats */ - IxEthAccTxDataStats tx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccRxDataStats rx[IX_ETH_ACC_NUMBER_OF_PORTS]; - IxEthAccDataPlaneStats stats; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return; - } - - /* get a reliable snapshot */ - key = ixOsalIrqLock(); - - numTx0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET0_Q, &numTx0Entries); - numTx1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET1_Q, &numTx1Entries); - numTxDoneEntries = 0; - ixQMgrQNumEntriesGet( IX_ETH_ACC_TX_FRAME_DONE_ETH_Q, &numTxDoneEntries); - numRxEntries = 0; - ixEthAccQMgrRxQEntryGet(&numRxEntries); - numRxFree0Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q, &numRxFree0Entries); - numRxFree1Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q, &numRxFree1Entries); - -#ifdef __ixp46X - numTx2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_TX_FRAME_ENET2_Q, &numTx2Entries); - numRxFree2Entries = 0; - ixQMgrQNumEntriesGet(IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q, &numRxFree2Entries); -#endif - - for(portId=IX_ETH_PORT_1; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - memcpy(&tx[portId], - &ixEthAccPortData[portId].ixEthAccTxData.stats, - sizeof(tx[portId])); - memcpy(&rx[portId], - &ixEthAccPortData[portId].ixEthAccRxData.stats, - sizeof(rx[portId])); - } - memcpy(&stats, &ixEthAccDataStats, sizeof(stats)); - - ixOsalIrqUnlock(key); - -#ifdef NDEBUG - printf("Detailed statistics collection not supported in this load\n"); -#endif - - /* print snapshot */ - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((IX_ETH_PORT_1 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_2 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - if ((IX_ETH_PORT_3 == portId) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - continue ; - } - } - - printf("PORT %u --------------------------------\n", - portId); -#ifndef NDEBUG - printf("Tx Done Frames : %u\n", - tx[portId].txDoneClientCallback + - tx[portId].txDoneSwQDuringDisable + - tx[portId].txDoneDuringDisable); - printf("Tx Frames : %u\n", - tx[portId].txQOK + tx[portId].txQDelayed); - printf("Tx H/W Q Added OK : %u\n", - tx[portId].txQOK); - printf("Tx H/W Q Delayed : %u\n", - tx[portId].txQDelayed); - printf("Tx From S/W Q Added OK : %u\n", - tx[portId].txFromSwQOK); - printf("Tx From S/W Q Delayed : %u\n", - tx[portId].txFromSwQDelayed); - printf("Tx Overflow : %u\n", - tx[portId].txOverflow); - printf("Tx Mutual Lock : %u\n", - tx[portId].txLock); - printf("Tx Late Ntf Enabled : %u\n", - tx[portId].txLateNotificationEnabled); - printf("Tx Low Thresh CB : %u\n", - tx[portId].txLowThreshCallback); - printf("Tx Done from H/W Q (Disable) : %u\n", - tx[portId].txDoneDuringDisable); - printf("Tx Done from S/W Q (Disable) : %u\n", - tx[portId].txDoneSwQDuringDisable); - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (tx[portId].txPriority[priority]) - { - printf("Tx Priority %u : %u\n", - priority, - tx[portId].txPriority[priority]); - } - } -#endif - printf("Tx unexpected errors : %u (should be 0)\n", - tx[portId].txUnexpectedError); - -#ifndef NDEBUG - printf("Rx Frames : %u\n", - rx[portId].rxFrameClientCallback + - rx[portId].rxSwQDuringDisable+ - rx[portId].rxDuringDisable); - printf("Rx Free Replenish : %u\n", - rx[portId].rxFreeRepOK + rx[portId].rxFreeRepDelayed); - printf("Rx Free H/W Q Added OK : %u\n", - rx[portId].rxFreeRepOK); - printf("Rx Free H/W Q Delayed : %u\n", - rx[portId].rxFreeRepDelayed); - printf("Rx Free From S/W Q Added OK : %u\n", - rx[portId].rxFreeRepFromSwQOK); - printf("Rx Free From S/W Q Delayed : %u\n", - rx[portId].rxFreeRepFromSwQDelayed); - printf("Rx Free Overflow : %u\n", - rx[portId].rxFreeOverflow); - printf("Rx Free Mutual Lock : %u\n", - rx[portId].rxFreeLock); - printf("Rx Free Late Ntf Enabled : %u\n", - rx[portId].rxFreeLateNotificationEnabled); - printf("Rx Free Low CB : %u\n", - rx[portId].rxFreeLowCallback); - printf("Rx From H/W Q (Disable) : %u\n", - rx[portId].rxDuringDisable); - printf("Rx From S/W Q (Disable) : %u\n", - rx[portId].rxSwQDuringDisable); - printf("Rx unlearned Mac Address : %u\n", - rx[portId].rxUnlearnedMacAddress); - printf("Rx Filtered (Rx => RxFree) : %u\n", - rx[portId].rxFiltered); - - for (priority = IX_ETH_ACC_TX_PRIORITY_0; - priority <= IX_ETH_ACC_TX_PRIORITY_7; - priority++) - { - if (rx[portId].rxPriority[priority]) - { - printf("Rx Priority %u : %u\n", - priority, - rx[portId].rxPriority[priority]); - } - } -#endif - printf("Rx unexpected errors : %u (should be 0)\n", - rx[portId].rxUnexpectedError); - -#ifndef NDEBUG - numBuffersInTx = tx[portId].txQOK + - tx[portId].txQDelayed - - tx[portId].txDoneClientCallback - - tx[portId].txDoneSwQDuringDisable - - tx[portId].txDoneDuringDisable; - - printf("# Tx Buffers currently for transmission : %u\n", - numBuffersInTx); - - numBuffersInRx = rx[portId].rxFreeRepOK + - rx[portId].rxFreeRepDelayed - - rx[portId].rxFrameClientCallback - - rx[portId].rxSwQDuringDisable - - rx[portId].rxDuringDisable; - - printf("# Rx Buffers currently for reception : %u\n", - numBuffersInRx); - - totalBuffers += numBuffersInRx + numBuffersInTx; -#endif - } - - printf("---------------------------------------\n"); - -#ifndef NDEBUG - printf("\n"); - printf("Mbufs :\n"); - printf("Tx Unchained mbufs : %u\n", - stats.unchainedTxMBufs); - printf("Tx Chained bufs : %u\n", - stats.chainedTxMBufs); - printf("TxDone Unchained mbufs : %u\n", - stats.unchainedTxDoneMBufs); - printf("TxDone Chained bufs : %u\n", - stats.chainedTxDoneMBufs); - printf("RxFree Unchained mbufs : %u\n", - stats.unchainedRxFreeMBufs); - printf("RxFree Chained bufs : %u\n", - stats.chainedRxFreeMBufs); - printf("Rx Unchained mbufs : %u\n", - stats.unchainedRxMBufs); - printf("Rx Chained bufs : %u\n", - stats.chainedRxMBufs); - - printf("\n"); - printf("Software queue usage :\n"); - printf("Buffers added to S/W Q : %u\n", - stats.addToSwQ); - printf("Buffers removed from S/W Q : %u\n", - stats.removeFromSwQ); - - printf("\n"); - printf("Hardware queues callbacks :\n"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - rxFreeCallbackCounter += rx[portId].rxFreeLowCallback; - txCallbackCounter += tx[portId].txLowThreshCallback; - } - printf("Tx Done QM Callback invoked : %u\n", - stats.txDoneCallbackCounter); - printf("Tx QM Callback invoked : %u\n", - txCallbackCounter); - printf("Rx QM Callback invoked : %u\n", - stats.rxCallbackCounter); - printf("Rx QM Callback burst read : %u\n", - stats.rxCallbackBurstRead); - printf("Rx Free QM Callback invoked : %u\n", - rxFreeCallbackCounter); -#endif - printf("Unexpected errors in CB : %u (should be 0)\n", - stats.unexpectedError); - printf("\n"); - - printf("Hardware queues levels :\n"); - printf("Transmit Port 1 Q : %u \n",numTx0Entries); - printf("Transmit Port 2 Q : %u \n",numTx1Entries); -#ifdef __ixp46X - printf("Transmit Port 3 Q : %u \n",numTx2Entries); -#endif - printf("Transmit Done Q : %u \n",numTxDoneEntries); - printf("Receive Q : %u \n",numRxEntries); - printf("Receive Free Port 1 Q : %u \n",numRxFree0Entries); - printf("Receive Free Port 2 Q : %u \n",numRxFree1Entries); -#ifdef __ixp46X - printf("Receive Free Port 3 Q : %u \n",numRxFree2Entries); -#endif - -#ifndef NDEBUG - printf("\n"); - printf("# Total Buffers accounted for : %u\n", - totalBuffers); - - numBuffersInSwQ = ixEthAccDataStats.addToSwQ - - ixEthAccDataStats.removeFromSwQ; - - printf(" Buffers in S/W Qs : %u\n", - numBuffersInSwQ); - printf(" Buffers in H/W Qs or NPEs : %u\n", - totalBuffers - numBuffersInSwQ); -#endif - - printf("Rx QoS Discipline : %s\n", - (ixEthAccDataInfo.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - - for(portId=0; portId < IX_ETH_ACC_NUMBER_OF_PORTS; portId++) - { - printf("Tx QoS Discipline port %u : %s\n", - portId, - (ixEthAccPortData[portId].ixEthAccTxData.schDiscipline == - FIFO_PRIORITY ) ? "Enabled" : "Disabled"); - } - printf("\n"); -} - - - - - diff --git a/drivers/net/npe/IxEthAccMac.c b/drivers/net/npe/IxEthAccMac.c deleted file mode 100644 index 65113448d27..00000000000 --- a/drivers/net/npe/IxEthAccMac.c +++ /dev/null @@ -1,2617 +0,0 @@ -/** - * @file IxEthAccMac.c - * - * @author Intel Corporation - * @date - * - * @brief MAC control functions - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMh.h" -#ifdef CONFIG_IXP425_COMPONENT_ETHDB -#include "IxEthDB.h" -#endif -#include "IxEthDBPortDefs.h" -#include "IxEthNpe.h" -#include "IxEthAcc.h" -#include "IxEthAccDataPlane_p.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" - -/* Maximum number of retries during ixEthAccPortDisable, which - * is approximately 10 seconds -*/ -#define IX_ETH_ACC_MAX_RETRY 500 - -/* Maximum number of retries during ixEthAccPortDisable when expecting - * timeout - */ -#define IX_ETH_ACC_MAX_RETRY_TIMEOUT 5 - -#define IX_ETH_ACC_VALIDATE_PORT_ID(portId) \ - do \ - { \ - if(!IX_ETH_ACC_IS_PORT_VALID(portId)) \ - { \ - return IX_ETH_ACC_INVALID_PORT; \ - } \ - } while(0) - -PUBLIC IxEthAccMacState ixEthAccMacState[IX_ETH_ACC_NUMBER_OF_PORTS]; - -PRIVATE UINT32 ixEthAccMacBase[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/*Forward function declarations*/ -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); - -PRIVATE void -ixEthAccPortDisableTxDone (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit (UINT32 cbTag, - IX_OSAL_MBUF *mbuf); - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId); - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -PRIVATE void -ixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg); - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId); - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2); - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m); - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId); - -IxEthAccStatus -ixEthAccMacMemInit(void) -{ - ixEthAccMacBase[IX_ETH_PORT_1] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, - IX_OSAL_IXP400_ETHA_MAP_SIZE); - ixEthAccMacBase[IX_ETH_PORT_2] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_1_BASE, - IX_OSAL_IXP400_ETHB_MAP_SIZE); -#ifdef __ixp46X - ixEthAccMacBase[IX_ETH_PORT_3] = - (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_2_BASE, - IX_OSAL_IXP400_ETH_NPEA_MAP_SIZE); - if (ixEthAccMacBase[IX_ETH_PORT_3] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } -#endif - - if (ixEthAccMacBase[IX_ETH_PORT_1] == 0 - || ixEthAccMacBase[IX_ETH_PORT_2] == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MAC I/O memory\n", - 0, 0, 0, 0, 0 ,0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMacUnload(void) -{ - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_1]); - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_2]); -#ifdef __ixp46X - IX_OSAL_MEM_UNMAP(ixEthAccMacBase[IX_ETH_PORT_3]); - ixEthAccMacBase[IX_ETH_PORT_3] = 0; -#endif - ixEthAccMacBase[IX_ETH_PORT_2] = 0; - ixEthAccMacBase[IX_ETH_PORT_1] = 0; -} - -IxEthAccStatus -ixEthAccPortEnablePriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: (Mac) cannot enable port %d, port not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if (ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn == NULL) - { - /* TxDone callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, TxDone callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if ((ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn == NULL) - && (ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn == NULL)) - { - /* Receive callback not registered */ - printf("EthAcc: (Mac) cannot enable port %d, Rx callback not registered\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - if(!ixEthAccMacState[portId].initDone) - { - printf("EthAcc: (Mac) cannot enable port %d, MAC address not set\n", portId); - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing*/ - if (ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* enable ethernet database for this port */ - if (ixEthDBPortEnable(portId) != IX_ETH_DB_SUCCESS) - { - printf("EthAcc: (Mac) cannot enable port %d, EthDB failure\n", portId); - return IX_ETH_ACC_FAIL; - } -#endif - - /* set the MAC core registers */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL2, - IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RANDOM_SEED, - IX_ETH_ACC_RANDOM_SEED_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_EMPTY, - IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_THRESH_P_FULL, - IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_DEFER, - IX_ETH_ACC_MAC_TX_DEFER_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_1, - IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_TWO_DEFER_2, - IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_SLOT_TIME, - IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_BUF_SIZE_TX, - IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - IX_ETH_ACC_TX_CNTRL1_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - IX_ETH_ACC_RX_CNTRL1_DEFAULT); - - /* set the global state */ - ixEthAccMacState[portId].portDisableState = ACTIVE; - ixEthAccMacState[portId].enabled = true; - - /* rewrite the setup (including mac filtering) depending - * on current options - */ - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* - * PortDisable local variables. They contain the intermediate steps - * while the port is being disabled and the buffers being drained out - * of the NPE. - */ -typedef void (*IxEthAccPortDisableRx)(IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback); -static IxEthAccPortRxCallback -ixEthAccPortDisableFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortMultiBufferRxCallback -ixEthAccPortDisableMultiBufferFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static IxEthAccPortDisableRx -ixEthAccPortDisableRxTable[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableMultiBufferCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static IxEthAccPortTxDoneCallback -ixEthAccPortDisableTxDoneFn[IX_ETH_ACC_NUMBER_OF_PORTS]; -static UINT32 -ixEthAccPortDisableTxDoneCbTag[IX_ETH_ACC_NUMBER_OF_PORTS]; - -static UINT32 -ixEthAccPortDisableUserBufferCount[IX_ETH_ACC_NUMBER_OF_PORTS]; - -/* - * PortDisable private callbacks functions. They handle the user - * traffic, and the special buffers (one for tx, one for rx) used - * in portDisable. - */ -PRIVATE void -ixEthAccPortDisableTxDone(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - /* check for the special mbuf used in portDisable */ - if (mbuf == ixEthAccMacState[portId].portDisableTxMbufPtr) - { - *txState = TRANSMIT_DONE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* call client TxDone function */ - ixEthAccPortDisableTxDoneFn[portId](ixEthAccPortDisableTxDoneCbTag[portId], mbuf); - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryTransmit(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - /* transmit the special buffer again if it is transmitted - * and update the txState - * This section is protected because the portDisable context - * run an identical code, so the system keeps transmitting at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*txState == TRANSMIT_DONE) - { - IX_OSAL_MBUF *mbufTxPtr = ixEthAccMacState[portId].portDisableTxMbufPtr; - *txState = TRANSMIT; - status = ixEthAccPortTxFrameSubmit(portId, - mbufTxPtr, - IX_ETH_ACC_TX_DEFAULT_PRIORITY); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableTxDoneAndSubmit(UINT32 cbTag, - IX_OSAL_MBUF *mbuf) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableTxDone(cbTag, mbuf); - - /* try to transmit the buffer used in portDisable - * if seen in TxDone - */ - ixEthAccPortDisableTryTransmit(portId); -} - -PRIVATE void -ixEthAccPortDisableRx (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - IX_OSAL_MBUF *mNextPtr; - - while (mBufPtr) - { - mNextPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(mBufPtr) = NULL; - - /* check for the special mbuf used in portDisable */ - if (mBufPtr == ixEthAccMacState[portId].portDisableRxMbufPtr) - { - *rxState = RECEIVE; - } - else - { - /* increment the count of user traffic during portDisable */ - ixEthAccPortDisableUserBufferCount[portId]++; - - /* reset the received payload length during portDisable */ - IX_OSAL_MBUF_MLEN(mBufPtr) = 0; - IX_OSAL_MBUF_PKT_LEN(mBufPtr) = 0; - - if (useMultiBufferCallback) - { - /* call the user callback with one unchained - * buffer, without payload. A small array is built - * to be used as a parameter (the user callback expects - * to receive an array ended by a NULL pointer. - */ - IX_OSAL_MBUF *mBufPtrArray[2]; - - mBufPtrArray[0] = mBufPtr; - mBufPtrArray[1] = NULL; - ixEthAccPortDisableMultiBufferFn[portId]( - ixEthAccPortDisableMultiBufferCbTag[portId], - mBufPtrArray); - } - else - { - /* call the user callback with a unchained - * buffer, without payload and the destination port is - * unknown. - */ - ixEthAccPortDisableFn[portId]( - ixEthAccPortDisableCbTag[portId], - mBufPtr, - IX_ETH_DB_UNKNOWN_PORT /* port not found */); - } - } - - mBufPtr = mNextPtr; - } -} - -PRIVATE IxEthAccStatus -ixEthAccPortDisableTryReplenish(UINT32 portId) -{ - int key; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - /* replenish with the special buffer again if it is received - * and update the rxState - * This section is protected because the portDisable context - * run an identical code, so the system keeps replenishing at the - * maximum rate. - */ - key = ixOsalIrqLock(); - if (*rxState == RECEIVE) - { - IX_OSAL_MBUF *mbufRxPtr = ixEthAccMacState[portId].portDisableRxMbufPtr; - *rxState = REPLENISH; - IX_OSAL_MBUF_MLEN(mbufRxPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - status = ixEthAccPortRxFreeReplenish(portId, mbufRxPtr); - } - ixOsalIrqUnlock(key); - - return status; -} - -PRIVATE void -ixEthAccPortDisableRxAndReplenish (IxEthAccPortId portId, - IX_OSAL_MBUF * mBufPtr, - BOOL useMultiBufferCallback) -{ - /* call the callback which forwards the traffic to the client */ - ixEthAccPortDisableRx(portId, mBufPtr, useMultiBufferCallback); - - /* try to replenish with the buffer used in portDisable - * if seen in Rx - */ - ixEthAccPortDisableTryReplenish(portId); -} - -PRIVATE void -ixEthAccPortDisableRxCallback (UINT32 cbTag, - IX_OSAL_MBUF * mBufPtr, - UINT32 learnedPortId) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - /* call the portDisable receive callback */ - (ixEthAccPortDisableRxTable[portId])(portId, mBufPtr, false); -} - -PRIVATE void -ixEthAccPortDisableMultiBufferRxCallback (UINT32 cbTag, - IX_OSAL_MBUF **mBufPtr) -{ - IxEthAccPortId portId = (IxEthAccPortId)cbTag; - - while (*mBufPtr) - { - /* call the portDisable receive callback with one buffer at a time */ - (ixEthAccPortDisableRxTable[portId])(portId, *mBufPtr++, true); - } -} - -IxEthAccStatus -ixEthAccPortDisablePriv(IxEthAccPortId portId) -{ - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - int key; - int retry, retryTimeout; - volatile IxEthAccPortDisableState *state = &ixEthAccMacState[portId].portDisableState; - volatile IxEthAccPortDisableState *rxState = &ixEthAccMacState[portId].rxState; - volatile IxEthAccPortDisableState *txState = &ixEthAccMacState[portId].txState; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable port.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* if the state is being set to what it is already at, do nothing */ - if (!ixEthAccMacState[portId].enabled) - { - return IX_ETH_ACC_SUCCESS; - } - - *state = DISABLED; - - /* disable MAC receive first */ - ixEthAccPortRxDisablePriv(portId); - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* disable ethernet database for this port - It is done now to avoid - * issuing ELT maintenance after requesting 'port disable' in an NPE - */ - if (ixEthDBPortDisable(portId) != IX_ETH_DB_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - IX_ETH_ACC_FATAL_LOG("ixEthAccPortDisable: failed to disable EthDB for this port\n", 0, 0, 0, 0, 0, 0); - } -#endif - - /* enter the critical section */ - key = ixOsalIrqLock(); - - /* swap the Rx and TxDone callbacks */ - ixEthAccPortDisableFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn; - ixEthAccPortDisableMultiBufferFn[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn; - ixEthAccPortDisableCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag; - ixEthAccPortDisableMultiBufferCbTag[portId] = ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag; - ixEthAccPortDisableTxDoneFn[portId] = ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn; - ixEthAccPortDisableTxDoneCbTag[portId] = ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag; - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - - /* register temporary callbacks */ - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferRxCallback; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = portId; - - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDone; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = portId; - - /* initialise the Rx state and Tx states */ - *txState = TRANSMIT_DONE; - *rxState = RECEIVE; - - /* exit the critical section */ - ixOsalIrqUnlock(key); - - /* enable a NPE loopback */ - if (ixEthAccNpeLoopbackEnablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - retry = 0; - - /* Step 1 : Drain Tx traffic and TxDone queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * - * (the receive callback keeps replenishing, so once we see - * the special Tx buffer, we can be sure that Tx drain is complete) - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* Step 2 : Drain Rx traffic, RxFree and Rx queues : - * - * Transmit and replenish at least once with the - * special buffers until both of them are seen - * in the callback hook - * (the transmit callback keeps transmitting, and when we see - * the special Rx buffer, we can be sure that rxFree drain - * is complete) - * - * The nested loop helps to retry if the user was keeping - * replenishing or transmitting during portDisable. - * - * The 2 nested loops ensure more retries if user traffic is - * seen during portDisable : the user should not replenish - * or transmit while portDisable is running. However, because of - * the queueing possibilities in ethAcc dataplane, it is possible - * that a lot of traffic is left in the queues (e.g. when - * transmitting over a low speed link) and therefore, more - * retries are allowed to help flushing the buffers out. - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDoneAndSubmit; - - do - { - do - { - ixEthAccPortDisableUserBufferCount[portId] = 0; - - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* keep transmitting */ - status = ixEthAccPortDisableTryTransmit(portId); - } - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((ixEthAccPortDisableUserBufferCount[portId] != 0) - || (*rxState == REPLENISH))); - - /* After the first iteration, change the receive callbacks, - * to process only 1 buffer at a time - */ - ixEthAccPortDisableRxTable[portId] - = ixEthAccPortDisableRx; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn - = ixEthAccPortDisableTxDone; - - /* repeat the whole process while user traffic is seen in TxDone - * - * The conditions to stop the loop are - * - Xscale has both Rx and Tx special buffers - * (txState = transmit, rxState = receive) - * - any error in txSubmit or rxReplenish - * - no user traffic seen - * - an excessive amount of retries - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry < IX_ETH_ACC_MAX_RETRY) - && (*txState == TRANSMIT)); - - /* check the loop exit conditions. The NPE should not hold - * the special buffers. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - - if (status == IX_ETH_ACC_SUCCESS) - { - /* Step 3 : Replenish without transmitting until a timeout - * occurs, in order to drain the internal NPE fifos - * - * we can expect a few frames srill held - * in the NPE. - * - * The 2 nested loops take care about the NPE dropping traffic - * (including loopback traffic) when the Rx queue is full. - * - * The timeout value is very conservative - * since the loopback used keeps replenishhing. - * - */ - do - { - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRxAndReplenish; - ixEthAccPortDisableUserBufferCount[portId] = 0; - retryTimeout = 0; - do - { - /* keep replenishing */ - status = ixEthAccPortDisableTryReplenish(portId); - if (status == IX_ETH_ACC_SUCCESS) - { - /* wait for some traffic being processed */ - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - - /* Step 4 : Transmit once. Stop replenish - * - * After the Rx timeout, we are sure that the NPE does not - * hold any frame in its internal NPE fifos. - * - * At this point, the NPE still holds the last rxFree buffer. - * By transmitting a single frame, this should unblock the - * last rxFree buffer. This code just transmit once and - * wait for both frames seen in TxDone and in rxFree. - * - */ - ixEthAccPortDisableRxTable[portId] = ixEthAccPortDisableRx; - status = ixEthAccPortDisableTryTransmit(portId); - - /* the NPE should immediatelyt release - * the last Rx buffer and the last transmitted buffer - * unless the last Tx frame was dropped (rx queue full) - */ - if (status == IX_ETH_ACC_SUCCESS) - { - retryTimeout = 0; - do - { - ixOsalSleep(IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS); - } - while ((*rxState == REPLENISH) - && (retryTimeout++ < IX_ETH_ACC_MAX_RETRY_TIMEOUT)); - } - - /* the NPE may have dropped the traffic because of Rx - * queue being full. This code ensures that the last - * Tx and Rx frames are both received. - */ - } - while ((status == IX_ETH_ACC_SUCCESS) - && (retry++ < IX_ETH_ACC_MAX_RETRY) - && ((*txState == TRANSMIT) - || (*rxState == REPLENISH) - || (ixEthAccPortDisableUserBufferCount[portId] != 0))); - - /* Step 5 : check the final states : the NPE has - * no buffer left, nor in Tx , nor in Rx directions. - */ - if ((*rxState == REPLENISH) || (*txState == TRANSMIT)) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* now all the buffers are drained, disable NPE loopback - * This is done regardless of the logic to drain the queues and - * the internal buffers held by the NPE. - */ - if (ixEthAccNpeLoopbackDisablePriv(portId) != IX_ETH_ACC_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - /* disable MAC Tx and Rx services */ - ixEthAccMacState[portId].enabled = false; - ixEthAccMacStateUpdate(portId); - - /* restore the Rx and TxDone callbacks (within a critical section) */ - key = ixOsalIrqLock(); - - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackFn = ixEthAccPortDisableFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxCallbackTag = ixEthAccPortDisableCbTag[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackFn = ixEthAccPortDisableMultiBufferFn[portId]; - ixEthAccPortData[portId].ixEthAccRxData.rxMultiBufferCallbackTag = ixEthAccPortDisableMultiBufferCbTag[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txBufferDoneCallbackFn = ixEthAccPortDisableTxDoneFn[portId]; - ixEthAccPortData[portId].ixEthAccTxData.txCallbackTag = ixEthAccPortDisableTxDoneCbTag[portId]; - - ixOsalIrqUnlock(key); - - /* the MAC core rx/tx disable may left the MAC hardware in an - * unpredictable state. A hw reset is executed before resetting - * all the MAC parameters to a known value. - */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return status; -} - -IxEthAccStatus -ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable port.\n",(INT32)portId,0,0,0,0,0); - - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - /* Since Eth NPE is not available, port must be disabled */ - *enabled = false ; - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - *enabled = ixEthAccMacState[portId].enabled; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMacResetPriv(IxEthAccPortId portId) -{ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot reset Ethernet coprocessor.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - /* rewrite all parameters to their current value */ - ixEthAccMacStateUpdate(portId); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackEnable(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_LOOP_EN); - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE void -ixEthAccNpeLoopbackMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG("IXETHACC:ixEthAccPortDisableMessageCallback: Illegal port: %u\n", - (UINT32) portId, 0, 0, 0, 0, 0); - - return; - } -#endif - - /* unlock message reception mutex */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].npeLoopbackMessageLock); -} - -IxEthAccStatus -ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* enable NPE loopback (lsb of the message contains the value 1) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL) - | 0x01; - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId]. npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable TX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxEnablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable RX.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortLoopbackDisable(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*disable MAC loopabck */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_LOOP_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId) -{ - IX_STATUS npeMhStatus; - IxNpeMhMessage message; - IxEthAccStatus status = IX_ETH_ACC_SUCCESS; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot enable NPE loopback.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* disable NPE loopback (lsb of the message contains the value 0) */ - message.data[0] = (IX_ETHNPE_SETLOOPBACK_MODE << IX_ETH_ACC_MAC_MSGID_SHL); - message.data[1] = 0; - - npeMhStatus = ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_SETLOOPBACK_MODE_ACK, - ixEthAccNpeLoopbackMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT); - - if (npeMhStatus != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - else - { - /* wait for NPE loopbackEnable response */ - if (ixOsalMutexLock(&ixEthAccMacState[portId].npeLoopbackMessageLock, - IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS) - != IX_SUCCESS) - { - status = IX_ETH_ACC_FAIL; - } - } - - return status; -} - -IxEthAccStatus -ixEthAccPortTxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable TX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - (regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortRxDisablePriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Eth %d: Cannot disable RX.\n", (INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* read register */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - /* update register */ - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - (regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN)); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - /* Turn off promiscuous mode */ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*set bit 5 of Rx control 1 - enable address filtering*/ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = false; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId) -{ - UINT32 regval; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set promiscuous mode.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* - * Set bit 5 of Rx control 1 - We enable address filtering even in - * promiscuous mode because we want the MAC to set the appropriate - * bits in m_flags which doesn't happen if we turn off filtering. - */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN); - - ixEthAccMacState[portId].promiscuous = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressSetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot set Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ) - { - /* This is a multicast/broadcast address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - - if ( macAddr->macAddress[0] == 0 && - macAddr->macAddress[1] == 0 && - macAddr->macAddress[2] == 0 && - macAddr->macAddress[3] == 0 && - macAddr->macAddress[4] == 0 && - macAddr->macAddress[5] == 0 ) - { - /* This is an invalid mac address cant set it ! */ - return IX_ETH_ACC_FAIL; - } - -#ifdef CONFIG_IXP425_COMPONENT_ETHDB - /* update the MAC address in the ethernet database */ - if (ixEthDBPortAddressSet(portId, (IxEthDBMacAddr *) macAddr) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } -#endif - - /*Set the Unicast MAC to the specified value*/ - for(i=0;imacAddress[i]); - } - ixEthAccMacState[portId].initDone = true; - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortUnicastMacAddressGetPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Unicast MAC from h/w - for the specified port*/ - UINT32 i; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get Unicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - /* Since Eth Npe is unavailable, return invalid MAC Address = 00:00:00:00:00:00 */ - for(i=0;imacAddress[i] = 0; - } - return IX_ETH_ACC_SUCCESS ; - } - - if(!ixEthAccMacState[portId].initDone) - { - return (IX_ETH_ACC_MAC_UNINITIALIZED); - } - - if (macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacAddressGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - - return IX_ETH_ACC_SUCCESS; -} - -PRIVATE IxEthAccStatus -ixEthAccPortMulticastMacFilterGet (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - /*Return the current value of the Multicast MAC from h/w - for the specified port*/ - UINT32 i; - - for(i=0;imacAddress[i]); - } - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinPriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr broadcastAddr = {{0xff,0xff,0xff,0xff,0xff,0xff}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join Multicast Mac Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - - /* Check that this is a multicast address */ - if (!(macAddr->macAddress[0] & IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT)) - { - return IX_ETH_ACC_FAIL; - } - - /* We don't add the Broadcast address */ - if(ixEthAccMacEqual(&broadcastAddr, macAddr)) - { - return IX_ETH_ACC_FAIL; - } - - for (i = 0; - i= IX_ETH_ACC_MAX_MULTICAST_ADDRESSES) - { - return IX_ETH_ACC_FAIL; - } - - /*First add the address to the multicast table for the - specified port*/ - i=ixEthAccMacState[portId].mcastAddrIndex; - - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[i], - &macAddr->macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - /*Increment the index into the table, this must be done here - as MulticastAddressSet below needs to know about the latest - entry. - */ - ixEthAccMacState[portId].mcastAddrIndex++; - - /*Then calculate the new value to be written to the address and - address mask registers*/ - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - - -IxEthAccStatus -ixEthAccPortMulticastAddressJoinAllPriv (IxEthAccPortId portId) -{ - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot join all Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /* remove all entries from the database and - * insert a multicast entry - */ - memcpy(&ixEthAccMacState[portId].mcastAddrsTable[0], - &mcastMacAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - - ixEthAccMacState[portId].mcastAddrIndex = 1; - ixEthAccMacState[portId].joinAll = true; - - ixEthAccMulticastAddressSet(portId); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccPortMulticastAddressLeavePriv (IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) -{ - UINT32 i; - IxEthAccMacAddr mcastMacAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - /*Check that the port parameter is valid*/ - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot leave Multicast Address.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - /*Check that the mac address is valid*/ - if(macAddr == NULL) - { - return IX_ETH_ACC_FAIL; - } - /* Remove this mac address from the mask for the specified port - * we copy down all entries above the blanked entry, and - * decrement the index - */ - i=0; - - while(i= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock); - -} - -PRIVATE void -ixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats) -{ - /* endianness conversion */ - - /* Rx stats */ - retStats->dot3StatsAlignmentErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors); - retStats->dot3StatsFCSErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors); - retStats->dot3StatsInternalMacReceiveErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors); - retStats->RxOverrunDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards); - retStats->RxLearnedEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards); - retStats->RxLargeFramesDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards); - retStats->RxSTPBlockedDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards); - retStats->RxVLANTypeFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards); - retStats->RxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards); - retStats->RxInvalidSourceDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards); - retStats->RxBlackListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards); - retStats->RxWhiteListDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards); - retStats->RxUnderflowEntryDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards); - - /* Tx stats */ - retStats->dot3StatsSingleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames); - retStats->dot3StatsMultipleCollisionFrames = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames); - retStats->dot3StatsDeferredTransmissions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions); - retStats->dot3StatsLateCollisions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions); - retStats->dot3StatsExcessiveCollsions = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions); - retStats->dot3StatsInternalMacTransmitErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors); - retStats->dot3StatsCarrierSenseErrors = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors); - retStats->TxLargeFrameDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards); - retStats->TxVLANIdFilterDiscards = - IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards); -} - -IxEthAccStatus -ixEthAccMibIIStatsGet (IxEthAccPortId portId, - IxEthEthObjStats *retStats ) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get operation - at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_GETSTATS, - ixEthAccMacNpeStatsMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - printf("EthAcc: (Mac) StatsGet failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to - this request - we need this mutex in order to ensure - that the return from this function is synchronous */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* Permit other tasks to perform MIB statistics Get operation */ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixEthAccMibIIStatsEndianConvert (retStats); - - return IX_ETH_ACC_SUCCESS; -} - - -PRIVATE void -ixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId, - IxNpeMhMessage msg) -{ - IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId); - -#ifndef NDEBUG - /* Prudent to at least check the port is within range */ - if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS) - { - IX_ETH_ACC_FATAL_LOG( - "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n", - (UINT32)portId, 0, 0, 0, 0, 0); - return; - } -#endif - - /*Unblock Stats Get & reset call*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock); - -} - - - -IxEthAccStatus -ixEthAccMibIIStatsGetClear (IxEthAccPortId portId, - IxEthEthObjStats *retStats) -{ - IxNpeMhMessage message; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n"); - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (retStats == NULL) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n"); - return (IX_ETH_ACC_FAIL); - } - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId); - - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0); - - /* Return all zero stats */ - IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats)); - - return IX_ETH_ACC_SUCCESS ; - } - - if (!IX_ETH_IS_PORT_INITIALIZED(portId)) - { - printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId); - return (IX_ETH_ACC_PORT_UNINITIALIZED); - } - - IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats)); - - message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL; - message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats); - - /* Permit only one task to request MIB statistics Get-Reset operation at a time */ - ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER); - - if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId), - message, - IX_ETHNPE_RESETSTATS, - ixEthAccMacNpeStatsResetMessageCallback, - IX_NPEMH_SEND_RETRIES_DEFAULT) - != IX_SUCCESS) - { - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n"); - - return IX_ETH_ACC_FAIL; - } - - /* Wait for callback invocation indicating response to this request */ - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS); - - /* permit other tasks to get and reset MIB stats*/ - ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixEthAccMibIIStatsEndianConvert(retStats); - - return IX_ETH_ACC_SUCCESS; -} - -IxEthAccStatus -ixEthAccMibIIStatsClear (IxEthAccPortId portId) -{ - static IxEthEthObjStats retStats; - IxEthAccStatus status; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot clear MIB II Stats.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - /* there is no reset operation without a corresponding Get */ - status = ixEthAccMibIIStatsGetClear(portId, &retStats); - - return status; -} - -/* Initialize the ethernet MAC settings */ -IxEthAccStatus -ixEthAccMacInit(IxEthAccPortId portId) -{ - IX_OSAL_MBUF_POOL* portDisablePool; - UINT8 *data; - - IX_ETH_ACC_VALIDATE_PORT_ID(portId); - - if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId)) - { - IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot initialize Mac.\n",(INT32)portId,0,0,0,0,0); - return IX_ETH_ACC_SUCCESS ; - } - - if(ixEthAccMacState[portId].macInitialised == false) - { - ixEthAccMacState[portId].fullDuplex = true; - ixEthAccMacState[portId].rxFCSAppend = true; - ixEthAccMacState[portId].txFCSAppend = true; - ixEthAccMacState[portId].txPADAppend = true; - ixEthAccMacState[portId].enabled = false; - ixEthAccMacState[portId].promiscuous = true; - ixEthAccMacState[portId].joinAll = false; - ixEthAccMacState[portId].initDone = false; - ixEthAccMacState[portId].macInitialised = true; - - /* initialize MIB stats mutexes */ - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].ackMIBStatsResetLock); - ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsResetLock, IX_OSAL_WAIT_FOREVER); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock); - - ixOsalMutexInit(&ixEthAccMacState[portId].npeLoopbackMessageLock); - - ixEthAccMacState[portId].portDisableRxMbufPtr = NULL; - ixEthAccMacState[portId].portDisableTxMbufPtr = NULL; - - portDisablePool = IX_OSAL_MBUF_POOL_INIT(2, - IX_ETHACC_RX_MBUF_MIN_SIZE, - "portDisable Pool"); - - IX_OSAL_ENSURE(portDisablePool != NULL, "Failed to initialize PortDisable pool"); - - ixEthAccMacState[portId].portDisableRxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - ixEthAccMacState[portId].portDisableTxMbufPtr = IX_OSAL_MBUF_POOL_GET(portDisablePool); - - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableRxMbufPtr != NULL, - "Pool allocation failed"); - IX_OSAL_ENSURE(ixEthAccMacState[portId].portDisableTxMbufPtr != NULL, - "Pool allocation failed"); - /* fill the payload of the Rx mbuf used in portDisable */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableRxMbufPtr) = IX_ETHACC_RX_MBUF_MIN_SIZE; - - memset(IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableRxMbufPtr), - 0xAA, - IX_ETHACC_RX_MBUF_MIN_SIZE); - - /* fill the payload of the Tx mbuf used in portDisable (64 bytes) */ - IX_OSAL_MBUF_MLEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - IX_OSAL_MBUF_PKT_LEN(ixEthAccMacState[portId].portDisableTxMbufPtr) = 64; - - data = (UINT8 *) IX_OSAL_MBUF_MDATA(ixEthAccMacState[portId].portDisableTxMbufPtr); - memset(data, 0xBB, 64); - data[0] = 0x00; /* unicast destination MAC address */ - data[6] = 0x00; /* unicast source MAC address */ - data[12] = 0x08; /* typelength : IP frame */ - data[13] = 0x00; /* typelength : IP frame */ - - IX_OSAL_CACHE_FLUSH(data, 64); - } - - IX_OSAL_ASSERT (ixEthAccMacBase[portId] != 0); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_RESET); - - ixOsalSleep(IX_ETH_ACC_MAC_RESET_DELAY); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_CORE_CNTRL, - IX_ETH_ACC_CORE_MDC_EN); - - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_INT_CLK_THRESH, - IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT); - - ixEthAccMacStateUpdate(portId); - - return IX_ETH_ACC_SUCCESS; -} - -/* PRIVATE Functions*/ - -PRIVATE void -ixEthAccMacStateUpdate(IxEthAccPortId portId) -{ - UINT32 regval; - - if ( ixEthAccMacState[portId].enabled == false ) - { - /* Just disable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN); - } - - if(ixEthAccMacState[portId].fullDuplex) - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_FULL_DUPLEX); - } - else - { - ixEthAccPortDuplexModeSetPriv (portId, IX_ETH_ACC_HALF_DUPLEX); - } - - if(ixEthAccMacState[portId].rxFCSAppend) - { - ixEthAccPortRxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortRxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txFCSAppend) - { - ixEthAccPortTxFrameAppendFCSEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendFCSDisablePriv (portId); - } - - if(ixEthAccMacState[portId].txPADAppend) - { - ixEthAccPortTxFrameAppendPaddingEnablePriv (portId); - } - else - { - ixEthAccPortTxFrameAppendPaddingDisablePriv (portId); - } - - if(ixEthAccMacState[portId].promiscuous) - { - ixEthAccPortPromiscuousModeSetPriv(portId); - } - else - { - ixEthAccPortPromiscuousModeClearPriv(portId); - } - - if ( ixEthAccMacState[portId].enabled == true ) - { - /* Enable both the transmitter and reciver in the MAC. */ - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_RX_CNTRL1, - regval | IX_ETH_ACC_RX_CNTRL1_RX_EN); - - REG_READ(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval); - REG_WRITE(ixEthAccMacBase[portId], - IX_ETH_ACC_MAC_TX_CNTRL1, - regval | IX_ETH_ACC_TX_CNTRL1_TX_EN); - } -} - - -PRIVATE BOOL -ixEthAccMacEqual(IxEthAccMacAddr *macAddr1, - IxEthAccMacAddr *macAddr2) -{ - UINT32 i; - for(i=0;imacAddress[i] != macAddr2->macAddress[i]) - { - return false; - } - } - return true; -} - -PRIVATE void -ixEthAccMacPrint(IxEthAccMacAddr *m) -{ - printf("%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x", - m->macAddress[0], m->macAddress[1], - m->macAddress[2], m->macAddress[3], - m->macAddress[4], m->macAddress[5]); -} - -/* Set the multicast address and address mask registers - * - * A bit in the address mask register must be set if - * all multicast addresses always have that bit set, or if - * all multicast addresses always have that bit cleared. - * - * A bit in the address register must be set if all multicast - * addresses have that bit set, otherwise, it should be cleared - */ - -PRIVATE void -ixEthAccMulticastAddressSet(IxEthAccPortId portId) -{ - UINT32 i; - UINT32 j; - IxEthAccMacAddr addressMask; - IxEthAccMacAddr address; - IxEthAccMacAddr alwaysClearBits; - IxEthAccMacAddr alwaysSetBits; - - /* calculate alwaysClearBits and alwaysSetBits: - * alwaysClearBits is calculated by ORing all - * multicast addresses, those bits that are always - * clear are clear in the result - * - * alwaysSetBits is calculated by ANDing all - * multicast addresses, those bits that are always set - * are set in the result - */ - - if (ixEthAccMacState[portId].promiscuous == true) - { - /* Promiscuous Mode is set, and filtering - * allow all packets, and enable the mcast and - * bcast detection. - */ - memset(&addressMask.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(&address.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - if(ixEthAccMacState[portId].joinAll == true) - { - /* Join all is set. The mask and address are - * the multicast settings. - */ - IxEthAccMacAddr macAddr = {{0x1,0x0,0x0,0x0,0x0,0x0}}; - - memcpy(addressMask.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - memcpy(address.macAddress, - macAddr.macAddress, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else if(ixEthAccMacState[portId].mcastAddrIndex == 0) - { - /* No entry in the filtering database, - * Promiscuous Mode is cleared, Broadcast filtering - * is configured. - */ - memset(addressMask.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(address.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - } - else - { - /* build a mask and an address which mix all entreis - * from the list of multicast addresses - */ - memset(alwaysClearBits.macAddress, - 0, - IX_IEEE803_MAC_ADDRESS_SIZE); - memset(alwaysSetBits.macAddress, - IX_ETH_ACC_MAC_ALL_BITS_SET, - IX_IEEE803_MAC_ADDRESS_SIZE); - - for(i=0;i> 8) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - (mdioCommand >> 16) & 0xff); - - REG_WRITE(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - (mdioCommand >> 24) & 0xff); -} - -PRIVATE void -ixEthAccMdioCmdRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_CMD_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - -PRIVATE void -ixEthAccMdioStatusRead(UINT32 *data) -{ - UINT32 regval; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_1, - regval); - - *data = regval & 0xff; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_2, - regval); - - *data |= (regval & 0xff) << 8; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_3, - regval); - - *data |= (regval & 0xff) << 16; - - REG_READ(miiBaseAddressVirt, - IX_ETH_ACC_MAC_MDIO_STS_4, - regval); - - *data |= (regval & 0xff) << 24; - -} - - -/******************************************************************** - * ixEthAccMiiInit - */ -IxEthAccStatus -ixEthAccMiiInit() -{ - if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS) - { - return IX_ETH_ACC_FAIL; - } - - miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE); - - if (miiBaseAddressVirt == 0) - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthAcc: Could not map MII I/O mapped memory\n", - 0, 0, 0, 0, 0, 0); - - return IX_ETH_ACC_FAIL; - } - - return IX_ETH_ACC_SUCCESS; -} - -void -ixEthAccMiiUnload(void) -{ - IX_OSAL_MEM_UNMAP(miiBaseAddressVirt); - - miiBaseAddressVirt = 0; -} - -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount) -{ - if (retryCount < 1) return IX_ETH_ACC_FAIL; - - ixEthAccMiiRetryCount = retryCount; - ixEthAccMiiAccessTimeout = timeout; - - return IX_ETH_ACC_SUCCESS; -} - -/********************************************************************* - * ixEthAccMiiReadRtn - read a 16 bit value from a PHY - */ -IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - if (value == NULL) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL; - mdioCommand |= IX_ETH_ACC_MII_GO; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - - - if(miiTimeout == 0) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - - ixEthAccMdioStatusRead(®val); - if(regval & IX_ETH_ACC_MII_READ_FAIL) - { - ixOsalMutexUnlock(&miiAccessLock); - *value = 0xffff; - return IX_ETH_ACC_FAIL; - } - - *value = regval & 0xffff; - ixOsalMutexUnlock(&miiAccessLock); - return IX_ETH_ACC_SUCCESS; - -} - - -/********************************************************************* - * ixEthAccMiiWriteRtn - write a 16 bit value to a PHY - */ -IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) -{ - UINT32 mdioCommand; - UINT32 regval; - UINT16 readVal; - UINT32 miiTimeout; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR) - || (phyReg >= IXP425_ETH_ACC_MII_MAX_REG)) - { - return (IX_ETH_ACC_FAIL); - } - - /* ensure that a PHY is present at this address */ - if(ixEthAccMiiReadRtn(phyAddr, - IX_ETH_ACC_MII_CTRL_REG, - &readVal) != IX_ETH_ACC_SUCCESS) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL - | phyAddr << IX_ETH_ACC_MII_ADDR_SHL ; - mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value; - - ixEthAccMdioCmdWrite(mdioCommand); - - miiTimeout = ixEthAccMiiRetryCount; - - while(miiTimeout) - { - - ixEthAccMdioCmdRead(®val); - - /*The "GO" bit is reset to 0 when the write completes*/ - if((regval & IX_ETH_ACC_MII_GO) == 0x0) - { - break; - } - /* Sleep for a while */ - ixOsalSleep(ixEthAccMiiAccessTimeout); - miiTimeout--; - } - - ixOsalMutexUnlock(&miiAccessLock); - if(miiTimeout == 0) - { - return IX_ETH_ACC_FAIL; - } - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Phy query functions - * - */ -IxEthAccStatus -ixEthAccMiiStatsShow (UINT32 phyAddr) -{ - UINT16 regval; - printf("Regisers on PHY at address 0x%x\n", phyAddr); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val); - printf(" Control Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val); - printf(" Status Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val); - printf(" PHY ID1 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val); - printf(" PHY ID2 Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val); - printf(" Auto Neg ADS Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val); - printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val); - printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val); - printf(" Auto Neg Next Register : 0x%4.4x\n", regval); - - return IX_ETH_ACC_SUCCESS; -} - - -/***************************************************************** - * - * Interface query functions - * - */ -IxEthAccStatus -ixEthAccMdioShow (void) -{ - UINT32 regval; - - if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED()) - { - return (IX_ETH_ACC_FAIL); - } - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioCmdRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO command register\n"); - printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26); - printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f); - printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f); - - ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER); - ixEthAccMdioStatusRead(®val); - ixOsalMutexUnlock(&miiAccessLock); - - printf("MDIO status register\n"); - printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31); - printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff); - - return IX_ETH_ACC_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBAPI.c b/drivers/net/npe/IxEthDBAPI.c deleted file mode 100644 index 023cf502487..00000000000 --- a/drivers/net/npe/IxEthDBAPI.c +++ /dev/null @@ -1,424 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxFeatureCtrl.h" - -extern HashTable dbHashtable; -extern IxEthDBPortMap overflowUpdatePortList; -extern BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, true); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - return ixEthDBTriggerAddPortUpdate(macAddr, portID, false); -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - ixEthDBReleaseHashNode(searchResult); - - /* build a remove event and place it on the event queue */ - return ixEthDBTriggerRemovePortUpdate(macAddr, ((MacDescriptor *) searchResult->data)->portID); -} - -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance() -{ - HashIterator iterator; - UINT32 portIndex; - BOOL agingRequired = false; - - /* ports who will have deleted records and therefore will need updating */ - IxEthDBPortMap triggerPorts; - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED != - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - return; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* check if there's at least a port that needs aging */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].agingEnabled && ixEthDBPortInfo[portIndex].enabled) - { - agingRequired = true; - } - } - - if (agingRequired) - { - /* ask each NPE port to write back the database for aging inspection */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE - && ixEthDBPortInfo[portIndex].agingEnabled - && ixEthDBPortInfo[portIndex].enabled) - { - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* unused */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - ixEthDBNPESyncScan(portIndex, ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_SUPPORT_TRACE("DB: (API) Finished scanning NPE tree on port %d\n", portIndex); - } - else - { - ixEthDBPortInfo[portIndex].agingEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portIndex].updateMethod.userControlled = true; - - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (Maintenance) warning, disabling aging and updates for port %d (assumed dead)\n", - portIndex, 0, 0, 0, 0, 0); - - ixEthDBDatabaseClear(portIndex, IX_ETH_DB_ALL_RECORD_TYPES); - } - } - } - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - UINT32 *age = NULL; - BOOL staticEntry = true; - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - age = &descriptor->recordData.filteringData.age; - staticEntry = descriptor->recordData.filteringData.staticEntry; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - age = &descriptor->recordData.filteringVlanData.age; - staticEntry = descriptor->recordData.filteringVlanData.staticEntry; - } - else - { - staticEntry = true; - } - - if (ixEthDBPortInfo[descriptor->portID].agingEnabled && (staticEntry == false)) - { - /* manually increment the age if the port has no such capability */ - if ((ixEthDBPortDefinitions[descriptor->portID].capabilities & IX_ETH_ENTRY_AGING) == 0) - { - *age += (IX_ETH_DB_MAINTENANCE_TIME / 60); - } - - /* age entry if it exceeded the maximum time to live */ - if (*age >= (IX_ETH_DB_LEARNING_ENTRY_AGE_TIME / 60)) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - } -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) -{ - IxEthDBPortMap triggerPorts; - HashIterator iterator; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS && portID != IX_ETH_DB_ALL_PORTS) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* check if the user passes some extra bits */ - if ((recordType | IX_ETH_DB_ALL_RECORD_TYPES) != IX_ETH_DB_ALL_RECORD_TYPES) - { - return IX_ETH_DB_INVALID_ARG; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - /* browse database and age entries */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (((descriptor->portID == portID) || (portID == IX_ETH_DB_ALL_PORTS)) - && ((descriptor->type & recordType) != 0)) - { - /* add to trigger if automatic updates are required */ - if (ixEthDBPortUpdateRequired[descriptor->type]) - { - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, descriptor->portID); - } - - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - /* update ports which lost records */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - IxEthDBStatus result = IX_ETH_DB_NO_SUCH_ADDR; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - if (((MacDescriptor *) (searchResult->data))->portID == portID) - { - result = IX_ETH_DB_SUCCESS; /* address and port match */ - } - - ixEthDBReleaseHashNode(searchResult); - - return result; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* return the port ID */ - *portID = ((MacDescriptor *) searchResult->data)->portID; - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = false; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_LEARNING); - - ixEthDBPortInfo[portID].agingEnabled = true; - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* return the port ID */ - *portID = descriptor->portID; - - /* reset entry age */ - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = 0; - } - else - { - descriptor->recordData.filteringVlanData.age = 0; - } - - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - /* force bit at offset 255 to 0 (reserved) */ - dependencyPortMap[31] &= 0xFE; - - COPY_DEPENDENCY_MAP(ixEthDBPortInfo[portID].dependencyPortMap, dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(dependencyPortMap); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - COPY_DEPENDENCY_MAP(dependencyPortMap, ixEthDBPortInfo[portID].dependencyPortMap); - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FILTERING); - - ixEthDBPortInfo[portID].updateMethod.updateEnabled = enableUpdate; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBAPISupport.c b/drivers/net/npe/IxEthDBAPISupport.c deleted file mode 100644 index c265d942e01..00000000000 --- a/drivers/net/npe/IxEthDBAPISupport.c +++ /dev/null @@ -1,651 +0,0 @@ -/** - * @file IxEthDBAPISupport.c - * - * @brief Public API support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include - -#include "IxEthDB_p.h" -#include "IxEthDBMessages_p.h" -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -#ifdef IX_UNIT_TEST - -int dbAccessCounter = 0; -int overflowEvent = 0; - -#endif - -/* - * External declaration - */ -extern HashTable dbHashtable; - -/* - * Internal declaration - */ -IX_ETH_DB_PUBLIC -PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -IX_ETH_DB_PRIVATE -struct -{ - BOOL saved; - IxEthDBPriorityTable priorityTable; - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - IxEthDBFirewallMode firewallMode; - BOOL stpBlocked; - BOOL srcAddressFilterEnabled; - UINT32 maxRxFrameSize; - UINT32 maxTxFrameSize; -} ixEthDBPortState[IX_ETH_DB_NUMBER_OF_PORTS]; - -#define IX_ETH_DB_DEFAULT_FRAME_SIZE (1518) - -/** - * @brief initializes a port - * - * @param portID ID of the port to be initialized - * - * Note that redundant initializations are silently - * dealt with and do not constitute an error - * - * This function is fully documented in the main - * header file, IxEthDB.h - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID) -{ - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) - { - WARNING_LOG("EthDB: Unavailable Eth %d: Cannot initialize EthDB Port.\n", (UINT32) portID); - - return; - } - - if (portInfo->initialized) - { - /* redundant */ - return; - } - - /* initialize core fields */ - portInfo->portID = portID; - SET_DEPENDENCY_MAP(portInfo->dependencyPortMap, portID); - - /* default values */ - portInfo->agingEnabled = false; - portInfo->enabled = false; - portInfo->macAddressUploaded = false; - portInfo->maxRxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - portInfo->maxTxFrameSize = IX_ETHDB_DEFAULT_FRAME_SIZE; - - /* default update control values */ - portInfo->updateMethod.searchTree = NULL; - portInfo->updateMethod.searchTreePendingWrite = false; - portInfo->updateMethod.treeInitialized = false; - portInfo->updateMethod.updateEnabled = false; - portInfo->updateMethod.userControlled = false; - - /* default WiFi parameters */ - memset(portInfo->bbsid, 0, sizeof (portInfo->bbsid)); - portInfo->frameControlDurationID = 0; - - /* Ethernet NPE-specific initializations */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* update handler */ - portInfo->updateMethod.updateHandler = ixEthDBNPEUpdateHandler; - } - - /* initialize state save */ - ixEthDBPortState[portID].saved = false; - - portInfo->initialized = true; -} - -/** - * @brief enables a port - * - * @param portID ID of the port to enable - * - * This function is fully documented in the main - * header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if enabling was - * accomplished, or a meaningful error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) -{ - IxEthDBPortMap triggerPorts; - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - SET_DEPENDENCY_MAP(triggerPorts, portID); - - /* mark as enabled */ - portInfo->enabled = true; - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE && !portInfo->macAddressUploaded) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) MAC address not set on port %d, enable failed\n", portID); - - /* must use UnicastAddressSet() before enabling an NPE port */ - return IX_ETH_DB_MAC_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Attempting to enable the NPE callback for port %d...\n", portID); - - if (!portInfo->updateMethod.userControlled - && ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0)) - { - portInfo->updateMethod.updateEnabled = true; - } - - /* if this is first time initialization then we already have - write access to the tree and can AccessRelease directly */ - if (!portInfo->updateMethod.treeInitialized) - { - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Initializing tree for port %d\n", portID); - - /* create an initial tree and release access into it */ - ixEthDBUpdatePortLearningTrees(triggerPorts); - - /* mark tree as being initialized */ - portInfo->updateMethod.treeInitialized = true; - } - } - - if (ixEthDBPortState[portID].saved) - { - /* previous configuration data stored, restore state */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet(portID, ixEthDBPortState[portID].firewallMode); - ixEthDBFirewallInvalidAddressFilterEnable(portID, ixEthDBPortState[portID].srcAddressFilterEnabled); - } - -#if 0 /* test-only */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBAcceptableFrameTypeSet(portID, ixEthDBPortState[portID].frameFilter); - ixEthDBIngressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].taggingAction); - - ixEthDBEgressVlanTaggingEnabledSet(portID, ixEthDBPortState[portID].transmitTaggingInfo); - ixEthDBPortVlanMembershipSet(portID, ixEthDBPortState[portID].vlanMembership); - - ixEthDBPriorityMappingTableSet(portID, ixEthDBPortState[portID].priorityTable); - } -#endif - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet(portID, ixEthDBPortState[portID].stpBlocked); - } - - ixEthDBFilteringPortMaximumRxFrameSizeSet(portID, ixEthDBPortState[portID].maxRxFrameSize); - ixEthDBFilteringPortMaximumTxFrameSizeSet(portID, ixEthDBPortState[portID].maxTxFrameSize); - - /* discard previous save */ - ixEthDBPortState[portID].saved = false; - } - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Enabling succeeded for port %d\n", portID); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief disables a port - * - * @param portID ID of the port to disable - * - * This function is fully documented in the - * main header file, IxEthDB.h - * - * @return IX_ETH_DB_SUCCESS if disabling was - * successful or an appropriate error message - * otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) -{ - HashIterator iterator; - IxEthDBPortMap triggerPorts; /* ports who will have deleted records and therefore will need updating */ - BOOL result; - PortInfo *portInfo; - IxEthDBFeature learningEnabled; -#if 0 /* test-only */ - IxEthDBPriorityTable classZeroTable; -#endif - - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - if (!portInfo->enabled) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - /* save filtering state */ - ixEthDBPortState[portID].firewallMode = portInfo->firewallMode; - ixEthDBPortState[portID].frameFilter = portInfo->frameFilter; - ixEthDBPortState[portID].taggingAction = portInfo->taggingAction; - ixEthDBPortState[portID].stpBlocked = portInfo->stpBlocked; - ixEthDBPortState[portID].srcAddressFilterEnabled = portInfo->srcAddressFilterEnabled; - ixEthDBPortState[portID].maxRxFrameSize = portInfo->maxRxFrameSize; - ixEthDBPortState[portID].maxTxFrameSize = portInfo->maxTxFrameSize; - - memcpy(ixEthDBPortState[portID].vlanMembership, portInfo->vlanMembership, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].transmitTaggingInfo, portInfo->transmitTaggingInfo, sizeof (IxEthDBVlanSet)); - memcpy(ixEthDBPortState[portID].priorityTable, portInfo->priorityTable, sizeof (IxEthDBPriorityTable)); - - ixEthDBPortState[portID].saved = true; - - /* now turn off all EthDB filtering features on the port */ - -#if 0 /* test-only */ - /* VLAN & QoS */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - ixEthDBPortVlanMembershipRangeAdd((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - ixEthDBEgressVlanRangeTaggingEnabledSet((IxEthDBPortId) portID, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID, false); - ixEthDBAcceptableFrameTypeSet((IxEthDBPortId) portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - ixEthDBIngressVlanTaggingEnabledSet((IxEthDBPortId) portID, IX_ETH_DB_PASS_THROUGH); - - memset(classZeroTable, 0, sizeof (classZeroTable)); - ixEthDBPriorityMappingTableSet((IxEthDBPortId) portID, classZeroTable); - } -#endif - - /* STP */ - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - ixEthDBSpanningTreeBlockingStateSet((IxEthDBPortId) portID, false); - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - ixEthDBFirewallModeSet((IxEthDBPortId) portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - ixEthDBFirewallTableDownload((IxEthDBPortId) portID); - ixEthDBFirewallInvalidAddressFilterEnable((IxEthDBPortId) portID, false); - } - - /* Frame size filter */ - ixEthDBFilteringPortMaximumFrameSizeSet((IxEthDBPortId) portID, IX_ETH_DB_DEFAULT_FRAME_SIZE); - - /* WiFi */ - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - ixEthDBWiFiConversionTableDownload((IxEthDBPortId) portID); - } - - /* save and disable the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - portInfo->featureStatus &= ~IX_ETH_DB_LEARNING; - } - else - { - /* save the learning feature bit */ - learningEnabled = portInfo->featureStatus & IX_ETH_DB_LEARNING; - } - - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - ixEthDBUpdateLock(); - - /* wipe out current entries for this port */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - /* check if the port match. If so, remove the entry */ - if (descriptor->portID == portID - && (descriptor->type == IX_ETH_DB_FILTERING_RECORD || descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - && !descriptor->recordData.filteringData.staticEntry) - { - /* delete entry */ - BUSY_RETRY(ixEthDBRemoveEntryAtHashIterator(&dbHashtable, &iterator)); - - /* add port to the set of update trigger ports */ - JOIN_PORT_TO_MAP(triggerPorts, portID); - } - else - { - /* move to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (portInfo->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(portInfo->updateMethod.searchTree); - portInfo->updateMethod.searchTree = NULL; - } - - ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FILTERING_RECORD); - } - - /* mark as disabled */ - portInfo->enabled = false; - - /* disable updates unless the user has specifically altered the default behavior */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if (!portInfo->updateMethod.userControlled) - { - portInfo->updateMethod.updateEnabled = false; - } - - /* make sure we re-initialize the NPE learning tree when the port is re-enabled */ - portInfo->updateMethod.treeInitialized = false; - } - - ixEthDBUpdateUnlock(); - - /* restore learning feature bit */ - portInfo->featureStatus |= learningEnabled; - - /* if we've removed any records or lost any events make sure to force an update */ - IS_EMPTY_DEPENDENCY_MAP(result, triggerPorts); - - if (!result) - { - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends the updated maximum Tx/Rx frame lengths to the NPE - * - * @param portID ID of the port to update - * - * @return IX_ETH_DB_SUCCESS if the update completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortFrameLengthsUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IX_STATUS result; - - FILL_SETMAXFRAMELENGTHS_MSG(message, portID, portInfo->maxRxFrameSize, portInfo->maxTxFrameSize); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the port maximum Rx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumRxFrameSize maximum Rx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumRxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumRxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumRxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx frame size - * - * @param portID ID of the port to set the frame size on - * @param maximumTxFrameSize maximum Tx frame size - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumTxFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumTxFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxTxFrameSize = maximumTxFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the port maximum Tx and Rx frame sizes - * - * @param portID ID of the port to set the frame size on - * @param maximumFrameSize maximum Tx and Rx frame sizes - * - * This function updates the internal data structures and - * calls ixEthDBPortFrameLengthsUpdate() for NPE update. - * - * Note that both the maximum Tx and Rx frame size are set - * to the same value. This function is kept for compatibility - * reasons. - * - * This function is fully documented in the main header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation was - * successfull or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - if ((maximumFrameSize < IX_ETHDB_MIN_NPE_FRAME_SIZE) || - (maximumFrameSize > IX_ETHDB_MAX_NPE_FRAME_SIZE)) - { - return IX_ETH_DB_INVALID_ARG; - } - } - else - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* update internal structure */ - ixEthDBPortInfo[portID].maxRxFrameSize = maximumFrameSize; - ixEthDBPortInfo[portID].maxTxFrameSize = maximumFrameSize; - - /* update the maximum frame size in the NPE */ - return ixEthDBPortFrameLengthsUpdate(portID); -} - -/** - * @brief sets the MAC address of an NPE port - * - * @param portID port ID to set the MAC address on - * @param macAddr pointer to the 6-byte MAC address - * - * This function is called by the EthAcc - * ixEthAccUnicastMacAddressSet() and should not be - * manually invoked unless required by special circumstances. - * - * @return IX_ETH_DB_SUCCESS if the operation succeeded - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* use this macro instead CHECK_PORT - as the port doesn't need to be enabled */ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - if (!ixEthDBPortInfo[portID].initialized) - { - return IX_ETH_DB_PORT_UNINITIALIZED; - } - - /* Operation stops here when Ethernet Learning is not enabled */ - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED == - ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING)) - { - return IX_ETH_DB_SUCCESS; - } - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - /* exit if the port is not an Ethernet NPE */ - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - return IX_ETH_DB_INVALID_PORT; - } - - /* populate message */ - FILL_SETPORTADDRESS_MSG(message, portID, macAddr->macAddress); - - IX_ETH_DB_SUPPORT_TRACE("DB: (Support) Sending SetPortAddress on port %d...\n", portID); - - /* send a SetPortAddress message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - ixEthDBPortInfo[portID].macAddressUploaded = true; - } - - return result; -} diff --git a/drivers/net/npe/IxEthDBCore.c b/drivers/net/npe/IxEthDBCore.c deleted file mode 100644 index 3d3050d5ce4..00000000000 --- a/drivers/net/npe/IxEthDBCore.c +++ /dev/null @@ -1,439 +0,0 @@ -/** - * @file IxEthDBDBCore.c - * - * @brief Database support functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* list of database hashtables */ -IX_ETH_DB_PUBLIC HashTable dbHashtable; -IX_ETH_DB_PUBLIC MatchFunction matchFunctions[IX_ETH_DB_MAX_KEY_INDEX + 1]; -IX_ETH_DB_PUBLIC BOOL ixEthDBPortUpdateRequired[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyType[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -/* private initialization flag */ -IX_ETH_DB_PRIVATE BOOL ethDBInitializationComplete = false; - -/** - * @brief initializes EthDB - * - * This function must be called to initialize the component. - * - * It does the following things: - * - checks the port definition structure - * - scans the capabilities of the NPE images and sets the - * capabilities of the ports accordingly - * - initializes the memory pools internally used in EthDB - * for storing database records and handling data - * - registers automatic update handlers for add and remove - * operations - * - registers hashing match functions, depending on key sets - * - initializes the main database hashtable - * - allocates contiguous memory zones to be used for NPE - * updates - * - registers the serialize methods used to convert data - * into NPE-readable format - * - starts the event processor - * - * Note that this function is documented in the public - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS or an appropriate error if the - * component failed to initialize correctly - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void) -{ - IxEthDBStatus result; - - if (ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* trap an invalid port definition structure */ - IX_ETH_DB_PORTS_ASSERTION; - - /* memory management */ - ixEthDBInitMemoryPools(); - - /* register hashing search methods */ - ixEthDBMatchMethodsRegister(matchFunctions); - - /* register type-based automatic port updates */ - ixEthDBUpdateTypeRegister(ixEthDBPortUpdateRequired); - - /* register record to key type mappings */ - ixEthDBKeyTypeRegister(ixEthDBKeyType); - - /* hash table */ - ixEthDBInitHash(&dbHashtable, NUM_BUCKETS, ixEthDBEntryXORHash, matchFunctions, (FreeFunction) ixEthDBFreeMacDescriptor); - - /* NPE update zones */ - ixEthDBNPEUpdateAreasInit(); - - /* register record serialization methods */ - ixEthDBRecordSerializeMethodsRegister(); - - /* start the event processor */ - result = ixEthDBEventProcessorInit(); - - /* scan NPE features */ - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBFeatureCapabilityScan(); - } - - ethDBInitializationComplete = true; - - return result; -} - -/** - * @brief prepares EthDB for unloading - * - * This function must be called before removing the - * EthDB component from memory (e.g. doing rmmod in - * Linux) if the component is to be re-initialized again - * without rebooting the platform. - * - * All the EthDB ports must be disabled before this - * function is to be called. Failure to disable all - * the ports will return the IX_ETH_DB_BUSY error. - * - * This function will destroy mutexes, deallocate - * memory and stop the event processor. - * - * Note that this function is fully documented in the - * main component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if de-initialization - * completed successfully or an appropriate error - * message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void) -{ - IxEthDBPortId portIndex; - - if (!ethDBInitializationComplete) - { - /* redundant */ - return IX_ETH_DB_SUCCESS; - } - - /* check if any ports are enabled */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortInfo[portIndex].enabled) - { - return IX_ETH_DB_BUSY; - } - } - - /* free port resources */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - ixOsalMutexDestroy(&ixEthDBPortInfo[portIndex].npeAckLock); - } - - ixEthDBPortInfo[portIndex].initialized = false; - } - - /* shutdown event processor */ - ixEthDBStopLearningFunction(); - - /* deallocate NPE update zones */ - ixEthDBNPEUpdateAreasUnload(); - - ethDBInitializationComplete = false; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a new entry to the Ethernet database - * - * @param newRecordTemplate address of the record template to use - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * Creates a new database entry, populates it with the data - * copied from the given template and adds the record to the - * database hash table. - * It also checks whether the new record type is registered to trigger - * automatic updates; if it is, the update trigger will contain the - * port on which the record insertion was performed, as well as the - * old port in case the addition was a record migration (from one port - * to the other). The caller can use the updateTrigger to trigger - * automatic updates on the ports changed as a result of this addition. - * - * @retval IX_ETH_DB_SUCCESS addition successful - * @retval IX_ETH_DB_NOMEM insertion failed, no memory left in the mac descriptor memory pool - * @retval IX_ETH_DB_BUSY database busy, cannot insert due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - MacDescriptor *newDescriptor; - IxEthDBPortId originalPortID; - HashNode *node = NULL; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, ixEthDBKeyType[newRecordTemplate->type], newRecordTemplate, &node)); - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (node == NULL) - { - /* not found, create a new one */ - newDescriptor = ixEthDBAllocMacDescriptor(); - - if (newDescriptor == NULL) - { - return IX_ETH_DB_NOMEM; /* no memory */ - } - - /* old port does not exist, avoid unnecessary updates */ - originalPortID = newRecordTemplate->portID; - } - else - { - /* a node with the same key exists, will update node */ - newDescriptor = (MacDescriptor *) node->data; - - /* save original port id */ - originalPortID = newDescriptor->portID; - } - - /* copy/update fields into new record */ - memcpy(newDescriptor->macAddress, newRecordTemplate->macAddress, sizeof (IxEthDBMacAddr)); - memcpy(&newDescriptor->recordData, &newRecordTemplate->recordData, sizeof (IxEthDBRecordData)); - - newDescriptor->type = newRecordTemplate->type; - newDescriptor->portID = newRecordTemplate->portID; - newDescriptor->user = newRecordTemplate->user; - - if (node == NULL) - { - /* new record, insert into hashtable */ - BUSY_RETRY_WITH_RESULT(ixEthDBAddHashEntry(&dbHashtable, newDescriptor), result); - - if (result != IX_ETH_DB_SUCCESS) - { - ixEthDBFreeMacDescriptor(newDescriptor); - - return result; /* insertion failed */ - } - } - - if (node != NULL) - { - /* release access */ - ixEthDBReleaseHashNode(node); - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL && - ixEthDBPortUpdateRequired[newRecordTemplate->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, newRecordTemplate->portID); - - /* check if record has moved, we'll need to update the old port as well */ - if (originalPortID != newDescriptor->portID) - { - JOIN_PORT_TO_MAP(updateTrigger, originalPortID); - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief remove a record from the Ethernet database - * - * @param templateRecord template record used to determine - * what record is to be removed - * @param updateTrigger port map containing the update triggers - * resulting from this update operation - * - * This function will examine the template record it receives - * and attempts to delete a record of the same type and containing - * the same keys as the template record. If deletion is successful - * and the record type is registered for automatic port updates the - * port will also be set in the updateTrigger port map, so that the - * client can perform an update of the port. - * - * @retval IX_ETH_DB_SUCCESS removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR the record with the given MAC address was not found - * @retval IX_ETH_DB_BUSY database busy, cannot remove due to locking - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger) -{ - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - BUSY_RETRY_WITH_RESULT(ixEthDBRemoveHashEntry(&dbHashtable, ixEthDBKeyType[templateRecord->type], templateRecord), result); - - if (result != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_NO_SUCH_ADDR; /* not found */ - } - - /* trigger add/remove update if required by type */ - if (updateTrigger != NULL - &&ixEthDBPortUpdateRequired[templateRecord->type]) - { - /* add new port to update list */ - JOIN_PORT_TO_MAP(updateTrigger, templateRecord->portID); - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief register record key types - * - * This function registers the appropriate key types, - * depending on record types. - * - * All filtering records use the MAC address as the key. - * WiFi and Firewall records use a compound key consisting - * in both the MAC address and the port ID. - * - * @return the number of registered record types - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType) -{ - /* safety */ - memset(keyType, 0, sizeof (keyType)); - - /* register all known record types */ - keyType[IX_ETH_DB_FILTERING_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_FILTERING_VLAN_RECORD] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_ALL_FILTERING_RECORDS] = IX_ETH_DB_MAC_KEY; - keyType[IX_ETH_DB_WIFI_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - keyType[IX_ETH_DB_FIREWALL_RECORD] = IX_ETH_DB_MAC_PORT_KEY; - - return 5; -} - -/** - * @brief Sets a user-defined field into a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) -{ - HashNode *result = NULL; - - if (macAddr == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - ((MacDescriptor *) result->data)->user = field; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief Retrieves a user-defined field from a database record - * - * Note that this function is fully documented in the main component - * header file. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) -{ - HashNode *result = NULL; - - if (macAddr == NULL || field == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - if (recordType == IX_ETH_DB_FILTERING_RECORD) - { - result = ixEthDBSearch(macAddr, recordType); - } - else if (recordType == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - result = ixEthDBVlanSearch(macAddr, vlanID, recordType); - } - else if (recordType == IX_ETH_DB_WIFI_RECORD || recordType == IX_ETH_DB_FIREWALL_RECORD) - { - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - result = ixEthDBPortSearch(macAddr, portID, recordType); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - if (result == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - *field = ((MacDescriptor *) result->data)->user; - - ixEthDBReleaseHashNode(result); - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBEvents.c b/drivers/net/npe/IxEthDBEvents.c deleted file mode 100644 index 5b3be0b6c1d..00000000000 --- a/drivers/net/npe/IxEthDBEvents.c +++ /dev/null @@ -1,496 +0,0 @@ -/** - * @file IxEthDBEvents.c - * - * @brief Implementation of the event processor component - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBEventProcessorLoop(void *); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PRIVATE void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); - -/* data */ -IX_ETH_DB_PRIVATE IxOsalSemaphore eventQueueSemaphore; -IX_ETH_DB_PRIVATE PortEventQueue eventQueue; -IX_ETH_DB_PRIVATE IxOsalMutex eventQueueLock; -IX_ETH_DB_PRIVATE IxOsalMutex portUpdateLock; - -IX_ETH_DB_PRIVATE BOOL ixEthDBLearningShutdown = false; -IX_ETH_DB_PRIVATE BOOL ixEthDBEventProcessorRunning = false; - -/* imported data */ -extern HashTable dbHashtable; - -/** - * @brief initializes the event processor - * - * Initializes the event processor queue and processing thread. - * Called from ixEthDBInit() DB-subcomponent master init function. - * - * @warning do not call directly - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OSAL or mutex init failure) - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEventProcessorInit(void) -{ - if (ixOsalMutexInit(&portUpdateLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (ixOsalMutexInit(&eventQueueLock) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == - ixFeatureCtrlSwConfigurationCheck (IX_FEATURECTRL_ETH_LEARNING)) - { - - /* start processor loop thread */ - if (ixEthDBStartLearningFunction() != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief initializes the event queue and the event processor - * - * This function is called by the component initialization - * function, ixEthDBInit(). - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStartLearningFunction(void) -{ - IxOsalThread eventProcessorThread; - IxOsalThreadAttr threadAttr; - - threadAttr.name = "EthDB event thread"; - threadAttr.stackSize = 32 * 1024; /* 32kbytes */ - threadAttr.priority = 128; - - /* reset event queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - RESET_QUEUE(&eventQueue); - - ixOsalMutexUnlock(&eventQueueLock); - - /* init event queue semaphore */ - if (ixOsalSemaphoreInit(&eventQueueSemaphore, 0) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - ixEthDBLearningShutdown = false; - - /* create processor loop thread */ - if (ixOsalThreadCreate(&eventProcessorThread, &threadAttr, ixEthDBEventProcessorLoop, NULL) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - /* start event processor */ - ixOsalThreadStart(&eventProcessorThread); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief stops the event processor - * - * Stops the event processor and frees the event queue semaphore - * Called by the component de-initialization function, ixEthDBUnload() - * - * @warning do not call directly - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise; - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBStopLearningFunction(void) -{ - ixEthDBLearningShutdown = true; - - /* wake up event processing loop to actually process the shutdown event */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - if (ixOsalSemaphoreDestroy(&eventQueueSemaphore) != IX_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief default NPE event processing callback - * - * @param npeID ID of the NPE that generated the event - * @param msg NPE message (encapsulated event) - * - * Creates an event object on the Ethernet event processor queue - * and signals the new event by incrementing the event queue semaphore. - * Events are processed by @ref ixEthDBEventProcessorLoop() which runs - * at user level. - * - * @see ixEthDBEventProcessorLoop() - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - PortEvent *local_event; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) new event received by processor callback from port %d, id 0x%X\n", IX_ETH_DB_NPE_TO_PORT_ID(npeID), NPE_MSG_ID(msg), 0, 0, 0, 0); - - if (CAN_ENQUEUE(&eventQueue)) - { - TEST_FIXTURE_LOCK_EVENT_QUEUE; - - local_event = QUEUE_HEAD(&eventQueue); - - /* create event structure on queue */ - local_event->eventType = NPE_MSG_ID(msg); - local_event->portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - - /* update queue */ - PUSH_UPDATE_QUEUE(&eventQueue); - - TEST_FIXTURE_UNLOCK_EVENT_QUEUE; - - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Waking up main processor loop...\n", 0, 0, 0, 0, 0, 0); - - /* increment event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - } - else - { - IX_ETH_DB_IRQ_EVENTS_TRACE("DB: (Events) Warning: could not enqueue event (overflow)\n", 0, 0, 0, 0, 0, 0); - } -} - -/** - * @brief Ethernet event processor loop - * - * Extracts at most EVENT_PROCESSING_LIMIT batches of events and - * sends them for processing to @ref ixEthDBProcessEvent(). - * Triggers port updates which normally follow learning events. - * - * @warning do not call directly, executes in separate thread - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBEventProcessorLoop(void *unused1) -{ - IxEthDBPortMap triggerPorts; - IxEthDBPortId portIndex; - - ixEthDBEventProcessorRunning = true; - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Event processor loop was started\n"); - - while (!ixEthDBLearningShutdown) - { - BOOL keepProcessing = true; - UINT32 processedEvents = 0; - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Waiting for new learning event...\n"); - - ixOsalSemaphoreWait(&eventQueueSemaphore, IX_OSAL_WAIT_FOREVER); - - IX_ETH_DB_EVENTS_VERBOSE_TRACE("DB: (Events) Received new event\n"); - - if (!ixEthDBLearningShutdown) - { - /* port update handling */ - SET_EMPTY_DEPENDENCY_MAP(triggerPorts); - - while (keepProcessing) - { - PortEvent local_event; - UINT32 intLockKey; - - /* lock queue */ - ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); - - /* lock NPE interrupts */ - intLockKey = ixOsalIrqLock(); - - /* extract event */ - local_event = *(QUEUE_TAIL(&eventQueue)); - - SHIFT_UPDATE_QUEUE(&eventQueue); - - ixOsalIrqUnlock(intLockKey); - - ixOsalMutexUnlock(&eventQueueLock); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Processing event with ID 0x%X\n", local_event.eventType); - - ixEthDBProcessEvent(&local_event, triggerPorts); - - processedEvents++; - - if (processedEvents > EVENT_PROCESSING_LIMIT /* maximum burst reached? */ - || ixOsalSemaphoreTryWait(&eventQueueSemaphore) != IX_SUCCESS) /* or empty queue? */ - { - keepProcessing = false; - } - } - - ixEthDBUpdatePortLearningTrees(triggerPorts); - } - } - - /* turn off automatic updates */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBPortInfo[portIndex].updateMethod.updateEnabled = false; - } - - ixEthDBEventProcessorRunning = false; -} - -/** - * @brief event processor routine - * - * @param event event to be processed - * @param triggerPorts port map accumulating ports to be updated - * - * Processes learning events by synchronizing the database with - * newly learnt data. Called only by @ref ixEthDBEventProcessorLoop(). - * - * @warning do not call directly - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBProcessEvent(PortEvent *local_event, IxEthDBPortMap triggerPorts) -{ - MacDescriptor recordTemplate; - - switch (local_event->eventType) - { - case IX_ETH_DB_ADD_FILTERING_RECORD: - /* add record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD; - recordTemplate.portID = local_event->portID; - recordTemplate.recordData.filteringData.staticEntry = local_event->staticEntry; - - ixEthDBAdd(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Added record on port %d\n", local_event->portID); - - break; - - case IX_ETH_DB_REMOVE_FILTERING_RECORD: - /* remove record */ - memset(&recordTemplate, 0, sizeof (recordTemplate)); - memcpy(recordTemplate.macAddress, local_event->macAddr.macAddress, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD; - - ixEthDBRemove(&recordTemplate, triggerPorts); - - IX_ETH_DB_EVENTS_TRACE("DB: (Events) Removed record on port %d\n", local_event->portID); - - break; - - default: - /* can't handle/not interested in this event type */ - ERROR_LOG("DB: (Events) Event processor received an unknown event type (0x%X)\n", local_event->eventType); - - return; - } -} - -/** - * @brief asynchronously adds a filtering record - * by posting an ADD_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the new record - * @param portID port ID of the new record - * @param staticEntry true if record is static, false if dynamic - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - /* fill search fields */ - memcpy(reference.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = IX_ETH_DB_ALL_FILTERING_RECORDS; - - if (ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference) == IX_ETH_DB_SUCCESS) - { - /* already have an identical record */ - return IX_ETH_DB_SUCCESS; - } - else - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_ADD_FILTERING_RECORD, macAddr, portID, staticEntry); - } -} - -/** - * @brief asynchronously removes a filtering record - * by posting a REMOVE_FILTERING_RECORD event to the event queue - * - * @param macAddr MAC address of the record to remove - * @param portID port ID of the record to remove - * - * @return IX_ETH_DB_SUCCESS if the event creation was - * successfull or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID) -{ - if (ixEthDBPeek(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS) != IX_ETH_DB_NO_SUCH_ADDR) - { - return ixEthDBTriggerPortUpdate(IX_ETH_DB_REMOVE_FILTERING_RECORD, macAddr, portID, false); - } - else - { - return IX_ETH_DB_NO_SUCH_ADDR; - } -} - -/** - * @brief adds an ADD or REMOVE event to the main event queue - * - * @param eventType event type - IX_ETH_DB_ADD_FILTERING_RECORD - * to add and IX_ETH_DB_REMOVE_FILTERING_RECORD to remove a - * record. - * - * @return IX_ETH_DB_SUCCESS if the event was successfully - * sent or IX_ETH_DB_BUSY if the event queue is full - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBTriggerPortUpdate(UINT32 eventType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry) -{ - UINT32 intLockKey; - - /* lock interrupts to protect queue */ - intLockKey = ixOsalIrqLock(); - - if (CAN_ENQUEUE(&eventQueue)) - { - PortEvent *queueEvent = QUEUE_HEAD(&eventQueue); - - /* update fields on the queue */ - memcpy(queueEvent->macAddr.macAddress, macAddr->macAddress, sizeof (IxEthDBMacAddr)); - - queueEvent->eventType = eventType; - queueEvent->portID = portID; - queueEvent->staticEntry = staticEntry; - - PUSH_UPDATE_QUEUE(&eventQueue); - - /* imcrement event queue semaphore */ - ixOsalSemaphorePost(&eventQueueSemaphore); - - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_SUCCESS; - } - else /* event queue full */ - { - /* unlock interrupts */ - ixOsalIrqUnlock(intLockKey); - - return IX_ETH_DB_BUSY; - } -} - -/** - * @brief Locks learning tree updates and port disable - * - * - * This function locks portUpdateLock single mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateLock(void) -{ - ixOsalMutexLock(&portUpdateLock, IX_OSAL_WAIT_FOREVER); -} - -/** - * @brief Unlocks learning tree updates and port disable - * - * - * This function unlocks a portUpdateLock mutex. It is primarily used - * to avoid executing 'port disable' during ELT maintenance. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdateUnlock(void) -{ - ixOsalMutexUnlock(&portUpdateLock); -} - diff --git a/drivers/net/npe/IxEthDBFeatures.c b/drivers/net/npe/IxEthDBFeatures.c deleted file mode 100644 index 1f7624016af..00000000000 --- a/drivers/net/npe/IxEthDBFeatures.c +++ /dev/null @@ -1,638 +0,0 @@ -/** - * @file IxEthDBFeatures.c - * - * @brief Implementation of the EthDB feature control API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxNpeDl.h" -#include "IxEthDBQoS.h" -#include "IxEthDB_p.h" - -/** - * @brief scans the capabilities of the loaded NPE images - * - * This function MUST be called by the ixEthDBInit() function. - * No EthDB features (including learning and filtering) are enabled - * before this function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFeatureCapabilityScan(void) -{ - IxNpeDlImageId imageId, npeAImageId; - IxEthDBPortId portIndex; - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IX_STATUS result; - UINT32 queueIndex; - UINT32 queueStructureIndex; - UINT32 trafficClassDefinitionIndex; - - /* read version of NPE A - required to set the AQM queues for B and C */ - npeAImageId.functionalityId = 0; - ixNpeDlLoadedImageGet(IX_NPEDL_NPEID_NPEA, &npeAImageId); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - IxNpeMhMessage msg; - - portInfo = &ixEthDBPortInfo[portIndex]; - - /* check and bypass if NPE B or C is fused out */ - if (ixEthDBSingleEthNpeCheck(portIndex) != IX_ETH_DB_SUCCESS) continue; - - /* all ports are capable of LEARNING by default */ - portInfo->featureCapability |= IX_ETH_DB_LEARNING; - portInfo->featureStatus |= IX_ETH_DB_LEARNING; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - - if (ixNpeDlLoadedImageGet(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), &imageId) != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) NpeDl did not provide the image ID for NPE port %d\n", portIndex); - } - else - { - /* initialize and empty NPE response mutex */ - ixOsalMutexInit(&portInfo->npeAckLock); - ixOsalMutexLock(&portInfo->npeAckLock, IX_OSAL_WAIT_FOREVER); - - /* check NPE response to GetStatus */ - msg.data[0] = IX_ETHNPE_NPE_GETSTATUS << 24; - msg.data[1] = 0; - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portIndex), msg, result); - if (result != IX_SUCCESS) - { - WARNING_LOG("DB: (FeatureScan) warning, could not send message to the NPE\n"); - continue; - } - - - if (imageId.functionalityId == 0x00 - || imageId.functionalityId == 0x03 - || imageId.functionalityId == 0x04 - || imageId.functionalityId == 0x80) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - } - else if (imageId.functionalityId == 0x01 - || imageId.functionalityId == 0x81) - { - portInfo->featureCapability |= IX_ETH_DB_FILTERING; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - else if (imageId.functionalityId == 0x02 - || imageId.functionalityId == 0x82) - { - portInfo->featureCapability |= IX_ETH_DB_WIFI_HEADER_CONVERSION; - portInfo->featureCapability |= IX_ETH_DB_FIREWALL; - portInfo->featureCapability |= IX_ETH_DB_SPANNING_TREE_PROTOCOL; - portInfo->featureCapability |= IX_ETH_DB_VLAN_QOS; - } - - /* reset AQM queues */ - memset(portInfo->ixEthDBTrafficClassAQMAssignments, 0, sizeof (portInfo->ixEthDBTrafficClassAQMAssignments)); - - /* ensure there's at least one traffic class record in the definition table, otherwise we have no default case, hence no queues */ - IX_ENSURE(sizeof (ixEthDBTrafficClassDefinitions) != 0, "DB: no traffic class definitions found, check IxEthDBQoS.h"); - - /* find the traffic class definition index compatible with the current NPE A functionality ID */ - for (trafficClassDefinitionIndex = 0 ; - trafficClassDefinitionIndex < ARRAY_SIZE(ixEthDBTrafficClassDefinitions); - trafficClassDefinitionIndex++) - { - if (ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX] == npeAImageId.functionalityId) - { - /* found it */ - break; - } - } - - /* select the default case if we went over the array boundary */ - if (trafficClassDefinitionIndex == ARRAY_SIZE(ixEthDBTrafficClassDefinitions)) - { - trafficClassDefinitionIndex = 0; /* the first record is the default case */ - } - - /* select queue assignment structure based on the traffic class configuration index */ - queueStructureIndex = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX]; - - /* only traffic class 0 is active at initialization time */ - portInfo->ixEthDBTrafficClassCount = 1; - - /* enable port, VLAN and Firewall feature bits to initialize QoS/VLAN/Firewall configuration */ - portInfo->featureStatus |= IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus |= IX_ETH_DB_FIREWALL; - portInfo->enabled = true; - -#define CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* set VLAN initial configuration (permissive) */ - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) /* QoS-enabled image */ - { - /* QoS capable */ - portInfo->ixEthDBTrafficClassAvailable = ixEthDBTrafficClassDefinitions[trafficClassDefinitionIndex][IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX]; - - /* set AQM queues */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = ixEthDBQueueAssignments[queueStructureIndex][queueIndex]; - } - - /* set default PVID (0) and default traffic class 0 */ - ixEthDBPortVlanTagSet(portIndex, 0); - - /* enable reception of all frames */ - ixEthDBAcceptableFrameTypeSet(portIndex, IX_ETH_DB_ACCEPT_ALL_FRAMES); - - /* clear full VLAN membership */ - ixEthDBPortVlanMembershipRangeRemove(portIndex, 0, IX_ETH_DB_802_1Q_MAX_VLAN_ID); - - /* clear TTI table - no VLAN tagged frames will be transmitted */ - ixEthDBEgressVlanRangeTaggingEnabledSet(portIndex, 0, 4094, false); - - /* set membership on 0, otherwise no Tx or Rx is working */ - ixEthDBPortVlanMembershipAdd(portIndex, 0); - } - else /* QoS not available in this image */ -#endif /* test-only */ - { - /* initialize traffic class availability (only class 0 is available) */ - portInfo->ixEthDBTrafficClassAvailable = 1; - - /* point all AQM queues to traffic class 0 */ - for (queueIndex = 0 ; queueIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; queueIndex++) - { - portInfo->ixEthDBTrafficClassAQMAssignments[queueIndex] = - ixEthDBQueueAssignments[queueStructureIndex][0]; - } - } - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* download priority mapping table and Rx queue configuration */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - ixEthDBPriorityMappingTableSet(portIndex, defaultPriorityTable); -#endif - - /* by default we turn off invalid source MAC address filtering */ - ixEthDBFirewallInvalidAddressFilterEnable(portIndex, false); - - /* disable port, VLAN, Firewall feature bits */ - portInfo->featureStatus &= ~IX_ETH_DB_VLAN_QOS; - portInfo->featureStatus &= ~IX_ETH_DB_FIREWALL; - portInfo->enabled = false; - - /* enable filtering by default if present */ - if ((portInfo->featureCapability & IX_ETH_DB_FILTERING) != 0) - { - portInfo->featureStatus |= IX_ETH_DB_FILTERING; - } - } - } - } -} - -/** - * @brief returns the capability of a port - * - * @param portID ID of the port - * @param featureSet location to store the port capability in - * - * This function will save the capability set of the given port - * into the given location. Capabilities are bit-ORed, each representing - * a bit of the feature set. - * - * Note that this function is documented in the main component - * public header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_INVALID_PORT if the given port is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) -{ - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - IX_ETH_DB_CHECK_REFERENCE(featureSet); - - *featureSet = ixEthDBPortInfo[portID].featureCapability; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables a port capability - * - * @param portID ID of the port - * @param feature feature to enable or disable - * @param enabled true to enable the selected feature or false to disable it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enable) -{ - PortInfo *portInfo; - IxEthDBPriorityTable defaultPriorityTable; - IxEthDBVlanSet vlanSet; - IxEthDBStatus status = IX_ETH_DB_SUCCESS; - BOOL portEnabled; - - IX_ETH_DB_CHECK_PORT_INITIALIZED(portID); - - portInfo = &ixEthDBPortInfo[portID]; - portEnabled = portInfo->enabled; - - /* check that only one feature is selected */ - if (!ixEthDBCheckSingleBitValue(feature)) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* port capable of this feature? */ - if ((portInfo->featureCapability & feature) == 0) - { - return IX_ETH_DB_FEATURE_UNAVAILABLE; - } - - /* mutual exclusion between learning and WiFi header conversion */ - if (enable && ((feature | portInfo->featureStatus) & (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - == (IX_ETH_DB_FILTERING | IX_ETH_DB_WIFI_HEADER_CONVERSION)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* learning must be enabled before filtering */ - if (enable && (feature == IX_ETH_DB_FILTERING) && ((portInfo->featureStatus & IX_ETH_DB_LEARNING) == 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* filtering must be disabled before learning */ - if (!enable && (feature == IX_ETH_DB_LEARNING) && ((portInfo->featureStatus & IX_ETH_DB_FILTERING) != 0)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* redundant enabling or disabling */ - if ((!enable && ((portInfo->featureStatus & feature) == 0)) - || (enable && ((portInfo->featureStatus & feature) != 0))) - { - /* do nothing */ - return IX_ETH_DB_SUCCESS; - } - - /* force port enabled */ - portInfo->enabled = true; - - if (enable) - { - /* turn on enable bit */ - portInfo->featureStatus |= feature; - -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - /* if this is VLAN/QoS set the default priority table */ - if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn on VLAN/QoS (most permissive mode): - - set default 802.1Q priority mapping table, in accordance to the - availability of traffic classes - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - set full VLAN membership list - - set full TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - enable TPID port extraction - */ - - portInfo->ixEthDBTrafficClassCount = portInfo->ixEthDBTrafficClassAvailable; - - /* set default 802.1Q priority mapping table - note that C indexing starts from 0, so we substract 1 here */ - memcpy (defaultPriorityTable, - (const void *) ixEthIEEE802_1QUserPriorityToTrafficClassMapping[portInfo->ixEthDBTrafficClassCount - 1], - sizeof (defaultPriorityTable)); - - /* update priority mapping and AQM queue assignments */ - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* set membership and TTI tables */ - memset (vlanSet, 0xFF, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* enable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, true); - } - } - else if (feature == IX_ETH_DB_FIREWALL) -#endif - { - /* firewall starts in black-list mode unless otherwise configured before * - * note that invalid source MAC address filtering is disabled by default */ - if (portInfo->firewallMode != IX_ETH_DB_FIREWALL_BLACK_LIST - && portInfo->firewallMode != IX_ETH_DB_FIREWALL_WHITE_LIST) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - } - } - - if (status != IX_ETH_DB_SUCCESS) - { - /* checks failed, disable */ - portInfo->featureStatus &= ~feature; - } - } - else - { - /* turn off features */ - if (feature == IX_ETH_DB_FIREWALL) - { - /* turning off the firewall is equivalent to: - - set to black-list mode - - clear all the entries and download the new table - - turn off the invalid source address checking - */ - - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_FIREWALL_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallModeSet(portID, IX_ETH_DB_FIREWALL_BLACK_LIST); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallInvalidAddressFilterEnable(portID, false); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBFirewallTableDownload(portID); - } - } - else if (feature == IX_ETH_DB_WIFI_HEADER_CONVERSION) - { - /* turn off header conversion */ - status = ixEthDBDatabaseClear(portID, IX_ETH_DB_WIFI_RECORD); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBWiFiConversionTableDownload(portID); - } - } -#ifdef CONFIG_WITH_VLAN /* test-only: VLAN support not included to save space!!! */ - else if (feature == IX_ETH_DB_VLAN_QOS) - { - /* turn off VLAN/QoS: - - set a priority mapping table with one traffic class - - set the acceptable frame filter to accept all - - set the Ingress tagging mode to pass-through - - clear the VLAN membership list - - clear the TTI table - - set the default 802.1Q tag to 0 (VLAN ID 0, Pri 0, CFI 0) - - disable TPID port extraction - */ - - /* initialize all => traffic class 0 priority mapping table */ - memset (defaultPriorityTable, 0, sizeof (defaultPriorityTable)); - portInfo->ixEthDBTrafficClassCount = 1; - status = ixEthDBPriorityMappingTableSet(portID, defaultPriorityTable); - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBAcceptableFrameTypeSet(portID, IX_ETH_DB_ACCEPT_ALL_FRAMES); - } - - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBIngressVlanTaggingEnabledSet(portID, IX_ETH_DB_PASS_THROUGH); - } - - /* clear membership and TTI tables */ - memset (vlanSet, 0, sizeof (vlanSet)); - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->vlanMembership, vlanSet); - } - - if (status == IX_ETH_DB_SUCCESS) - { - /* use the internal function to bypass PVID check */ - status = ixEthDBPortVlanTableSet(portID, portInfo->transmitTaggingInfo, vlanSet); - } - - /* reset the PVID */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBPortVlanTagSet(portID, 0); - } - - /* disable TPID port extraction */ - if (status == IX_ETH_DB_SUCCESS) - { - status = ixEthDBVlanPortExtractionEnable(portID, false); - } - } -#endif - - if (status == IX_ETH_DB_SUCCESS) - { - /* checks passed, disable */ - portInfo->featureStatus &= ~feature; - } - } - - /* restore port enabled state */ - portInfo->enabled = portEnabled; - - return status; -} - -/** - * @brief returns the status of a feature - * - * @param portID port ID - * @param present location to store a boolean value indicating - * if the feature is present (true) or not (false) - * @param enabled location to store a booleam value indicating - * if the feature is present (true) or not (false) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_REFERENCE(present); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - portInfo = &ixEthDBPortInfo[portID]; - - *present = (portInfo->featureCapability & feature) != 0; - *enabled = (portInfo->featureStatus & feature) != 0; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief returns the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param type location to store the property type into - * @param value location to store the property value into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - IX_ETH_DB_CHECK_REFERENCE(type); - - IX_ETH_DB_CHECK_REFERENCE(value); - - if (feature == IX_ETH_DB_VLAN_QOS) - { - if (property == IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY) - { - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - else if (property >= IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY - && property <= IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY) - { - UINT32 classDelta = property - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY; - - if (classDelta >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_FAIL; - } - - * (UINT32 *) value = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[classDelta]; - *type = IX_ETH_DB_INTEGER_PROPERTY; - - return IX_ETH_DB_SUCCESS; - } - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief sets the value of an EthDB property - * - * @param portID ID of the port - * @param feature feature owning the property - * @param property ID of the property - * @param value location containing the property value - * - * This function implements a private property intended - * only for EthAcc usage. Upon setting the IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE - * property (the value is ignored), the availability of traffic classes is - * frozen to whatever traffic class structure is currently in use. - * This means that if VLAN_QOS has been enabled before EthAcc - * initialization then all the defined traffic classes will be available; - * otherwise only one traffic class (0) will be available. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h as not accepting any parameters. The - * current implementation is only intended for the private use of EthAcc. - * - * Also note that once this function is called the effect is irreversible, - * unless EthDB is complete unloaded and re-initialized. - * - * @return IX_ETH_DB_INVALID_ARG (no read-write properties are - * supported in this release) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) -{ - IX_ETH_DB_CHECK_PORT_EXISTS(portID); - - if ((feature == IX_ETH_DB_VLAN_QOS) && (property == IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE)) - { - ixEthDBPortInfo[portID].ixEthDBTrafficClassAvailable = ixEthDBPortInfo[portID].ixEthDBTrafficClassCount; - - return IX_ETH_DB_SUCCESS; - } - - return IX_ETH_DB_INVALID_ARG; -} diff --git a/drivers/net/npe/IxEthDBFirewall.c b/drivers/net/npe/IxEthDBFirewall.c deleted file mode 100644 index c0ae5624ff5..00000000000 --- a/drivers/net/npe/IxEthDBFirewall.c +++ /dev/null @@ -1,242 +0,0 @@ -/** - * @file IxEthDBFirewall.c - * - * @brief Implementation of the firewall API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief updates the NPE firewall operating mode and - * firewall address table - * - * @param portID ID of the port - * @param epDelta initial entry point for binary searches (NPE optimization) - * @param address address of the firewall MAC address table - * - * This function will send a message to the NPE configuring the - * firewall mode (white list or black list), invalid source - * address filtering and downloading a new MAC address database - * to be used for firewall matching. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 mode = 0; - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - - mode = (portInfo->srcAddressFilterEnabled != false) << 1 | (portInfo->firewallMode == IX_ETH_DB_FIREWALL_WHITE_LIST); - - FILL_SETFIREWALLMODE_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, - mode, - IX_OSAL_MMU_VIRT_TO_PHYS(address)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief configures the firewall white list/black list - * access mode - * - * @param portID ID of the port - * @param mode firewall filtering mode (IX_ETH_DB_FIREWALL_WHITE_LIST - * or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - if (mode != IX_ETH_DB_FIREWALL_WHITE_LIST - && mode != IX_ETH_DB_FIREWALL_BLACK_LIST) - { - return IX_ETH_DB_INVALID_ARG; - } - - ixEthDBPortInfo[portID].firewallMode = mode; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief enables or disables the invalid source MAC address filter - * - * @param portID ID of the port - * @param enable true to enable invalid source MAC address filtering - * or false to disable it - * - * The invalid source MAC address filter will discard, when enabled, - * frames whose source MAC address is a multicast or the broadcast MAC - * address. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - ixEthDBPortInfo[portID].srcAddressFilterEnabled = enable; - - return ixEthDBFirewallTableDownload(portID); -} - -/** - * @brief adds a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the new record - * - * This function will add a new firewall record - * on the specified port, using the specified - * MAC address. If the record already exists this - * function will silently return IX_ETH_DB_SUCCESS, - * although no duplicate records are added. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief removes a firewall record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * This function will attempt to remove a firewall - * record from the given port, using the specified - * MAC address. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully of an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_FIREWALL_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief downloads the firewall address table to an NPE - * - * @param portID ID of the port - * - * This function will download the firewall address table to - * an NPE port. - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_FAIL otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - IxEthDBStatus result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_FIREWALL); - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - ixEthDBPortInfo[portID].updateMethod.searchTree = ixEthDBQuery(NULL, query, IX_ETH_DB_FIREWALL_RECORD, MAX_FW_SIZE); - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_FIREWALL_RECORD); - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthDBHashtable.c b/drivers/net/npe/IxEthDBHashtable.c deleted file mode 100644 index 9493a5b48bc..00000000000 --- a/drivers/net/npe/IxEthDBHashtable.c +++ /dev/null @@ -1,618 +0,0 @@ -/** - * @file ethHash.c - * - * @brief Hashtable implementation - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" -#include "IxEthDBLocks_p.h" - -/** - * @addtogroup EthDB - * - * @{ - */ - -/** - * @brief initializes a hash table object - * - * @param hashTable uninitialized hash table structure - * @param numBuckets number of buckets to use - * @param entryHashFunction hash function used - * to hash entire hash node data block (for adding) - * @param matchFunctions array of match functions, indexed on type, - * used to differentiate records with the same hash value - * @param freeFunction function used to free node data blocks - * - * Initializes the given hash table object. - * - * @internal - */ -void ixEthDBInitHash(HashTable *hashTable, - UINT32 numBuckets, - HashFunction entryHashFunction, - MatchFunction *matchFunctions, - FreeFunction freeFunction) -{ - UINT32 bucketIndex; - UINT32 hashSize = numBuckets * sizeof(HashNode *); - - /* entry hashing, matching and freeing methods */ - hashTable->entryHashFunction = entryHashFunction; - hashTable->matchFunctions = matchFunctions; - hashTable->freeFunction = freeFunction; - - /* buckets */ - hashTable->numBuckets = numBuckets; - - /* set to 0 all buckets */ - memset(hashTable->hashBuckets, 0, hashSize); - - /* init bucket locks - note that initially all mutexes are unlocked after MutexInit()*/ - for (bucketIndex = 0 ; bucketIndex < numBuckets ; bucketIndex++) - { - ixOsalFastMutexInit(&hashTable->bucketLocks[bucketIndex]); - } -} - -/** - * @brief adds an entry to the hash table - * - * @param hashTable hash table to add the entry to - * @param entry entry to add - * - * The entry will be hashed using the entry hashing function and added to the - * hash table, unless a locking blockage occurs, in which case the caller - * should retry. - * - * @retval IX_ETH_DB_SUCCESS if adding entry has succeeded - * @retval IX_ETH_DB_NOMEM if there's no memory left in the hash node pool - * @retval IX_ETH_DB_BUSY if there's a locking failure on the insertion path - * - * @internal - */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry) -{ - UINT32 hashValue = hashTable->entryHashFunction(entry); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *bucket = hashTable->hashBuckets[bucketIndex]; - HashNode *newNode; - - LockStack locks; - - INIT_STACK(&locks); - - /* lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - /* lock insertion element (first in chain), if any */ - if (bucket != NULL) - { - PUSH_LOCK(&locks, &bucket->lock); - } - - /* get new node */ - newNode = ixEthDBAllocHashNode(); - - if (newNode == NULL) - { - /* unlock everything */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_NOMEM; - } - - /* init lock - note that mutexes are unlocked after MutexInit */ - ixOsalFastMutexInit(&newNode->lock); - - /* populate new link */ - newNode->data = entry; - - /* add to bucket */ - newNode->next = bucket; - hashTable->hashBuckets[bucketIndex] = newNode; - - /* unlock bucket and insertion point */ - UNROLL_STACK(&locks); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief removes an entry from the hashtable - * - * @param hashTable hash table to remove entry from - * @param keyType type of record key used for matching - * @param reference reference key used to identify the entry - * - * The reference key will be hashed using the key hashing function, - * the entry is searched using the hashed value and then examined - * against the reference entry using the match function. A positive - * match will trigger the deletion of the entry. - * Locking failures are reported and the caller should retry. - * - * @retval IX_ETH_DB_SUCCESS if the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR if the entry was not found - * @retval IX_ETH_DB_BUSY if a locking failure occured during the process - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue = hashTable->entryHashFunction(reference); - UINT32 bucketIndex = hashValue % hashTable->numBuckets; - HashNode *node = hashTable->hashBuckets[bucketIndex]; - HashNode *previousNode = NULL; - - LockStack locks; - - INIT_STACK(&locks); - - while (node != NULL) - { - /* try to lock node */ - PUSH_LOCK(&locks, &node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - /* found entry */ - if (node->next != NULL) - { - PUSH_LOCK(&locks, &node->next->lock); - } - - if (previousNode == NULL) - { - /* node is head of chain */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[bucketIndex]); - - hashTable->hashBuckets[bucketIndex] = node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - previousNode->next = node->next; - } - - UNROLL_STACK(&locks); - - /* free node */ - hashTable->freeFunction(node->data); - ixEthDBFreeHashNode(node); - - return IX_ETH_DB_SUCCESS; - } - else - { - if (previousNode != NULL) - { - /* unlock previous node */ - SHIFT_STACK(&locks); - } - - /* advance to next element in chain */ - previousNode = node; - node = node->next; - } - } - - UNROLL_STACK(&locks); - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief retrieves an entry from the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * @param searchResult pointer where a reference to the located hash node - * is placed - * - * Searches the entry with the same key as reference and places the - * pointer to the resulting node in searchResult. - * An implicit write access lock is granted after a search, which gives the - * caller the opportunity to modify the entry. - * Access should be released as soon as possible using @ref ixEthDBReleaseHashNode(). - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @warning unless the return value is IX_ETH_DB_SUCCESS the searchResult - * location is NOT modified and therefore using a NULL comparison test when the - * value was not properly initialized would be an error - * - * @internal - */ -IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - *searchResult = node; - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief reports the existence of an entry in the hash table - * - * @param hashTable hash table to perform the search into - * @param reference search key (a MAC address) - * @param keyType type of record key used for matching - * - * Searches the entry with the same key as reference. - * No implicit write access lock is granted after a search, hence the - * caller cannot access or modify the entry. The result is only temporary. - * - * @see ixEthDBReleaseHashNode() - * - * @retval IX_ETH_DB_SUCCESS if the search was completed successfully - * @retval IX_ETH_DB_NO_SUCH_ADDRESS if no entry with the given key was found - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case - * the caller should retry - * - * @internal - */ -IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference) -{ - UINT32 hashValue; - HashNode *node; - - hashValue = hashTable->entryHashFunction(reference); - node = hashTable->hashBuckets[hashValue % hashTable->numBuckets]; - - while (node != NULL) - { - TRY_LOCK(&node->lock); - - if (hashTable->matchFunctions[keyType](reference, node->data)) - { - UNLOCK(&node->lock); - - return IX_ETH_DB_SUCCESS; - } - else - { - UNLOCK(&node->lock); - - node = node->next; - } - } - - /* not found */ - return IX_ETH_DB_NO_SUCH_ADDR; -} - -/** - * @brief releases the write access lock - * - * @pre the node should have been obtained via @ref ixEthDBSearchHashEntry() - * - * @see ixEthDBSearchHashEntry() - * - * @internal - */ -void ixEthDBReleaseHashNode(HashNode *node) -{ - UNLOCK(&node->lock); -} - -/** - * @brief initializes a hash iterator - * - * @param hashTable hash table to be iterated - * @param iterator iterator object - * - * If the initialization is successful the iterator will point to the - * first hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if initialization was successful and the iterator points - * to the first valid table node - * @retval IX_ETH_DB_FAIL if the table is empty - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - iterator->bucketIndex = 0; - iterator->node = NULL; - iterator->previousNode = NULL; - - return ixEthDBIncrementHashIterator(hashTable, iterator); -} - -/** - * @brief releases the write access locks of the iterator nodes - * - * @warning use of this function is required only when the caller terminates an iteration - * before reaching the end of the table - * - * @see ixEthDBInitHashIterator() - * @see ixEthDBIncrementHashIterator() - * - * @param iterator iterator whose node(s) should be unlocked - * - * @internal - */ -void ixEthDBReleaseHashIterator(HashIterator *iterator) -{ - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - } -} - -/** - * @brief incremenents an iterator so that it points to the next valid entry of the table - * (if any) - * - * @param hashTable hash table to iterate - * @param iterator iterator object - * - * @pre the iterator object must be initialized using @ref ixEthDBInitHashIterator() - * - * If the increment operation is successful the iterator will point to the - * next hash table record (if any). - * Testing if the iterator has not passed the end of the table should be - * done using the IS_ITERATOR_VALID(iteratorPtr) macro. - * An implicit write access lock is granted on the entry pointed by the iterator. - * The access is automatically revoked when the iterator is re-incremented. - * If the caller decides to terminate the iteration before the end of the table is - * passed then the manual access release method, @ref ixEthDBReleaseHashIterator, - * must be called. - * Is is guaranteed that no other thread can remove or change the iterated entry until - * the iterator is incremented successfully. - * - * @see ixEthDBReleaseHashIterator() - * - * @retval IX_ETH_DB_SUCCESS if the operation was successful and the iterator points - * to the next valid table node - * @retval IX_ETH_DB_FAIL if the iterator has passed the end of the table - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @warning do not use ixEthDBReleaseHashNode() on entries pointed by the iterator, as this - * might place the database in a permanent invalid lock state - * - * @internal - */ -IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - /* unless iterator is just initialized... */ - if (iterator->node != NULL) - { - /* try next in chain */ - if (iterator->node->next != NULL) - { - TRY_LOCK(&iterator->node->next->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->previousNode = iterator->node; - iterator->node = iterator->node->next; - - return IX_ETH_DB_SUCCESS; - } - else - { - /* last in chain, prepare for next bucket */ - iterator->bucketIndex++; - } - } - - /* try next used bucket */ - for (; iterator->bucketIndex < hashTable->numBuckets ; iterator->bucketIndex++) - { - HashNode **nodePtr = &(hashTable->hashBuckets[iterator->bucketIndex]); - HashNode *node = *nodePtr; -#if (CPU!=SIMSPARCSOLARIS) && !defined (__wince) - if (((iterator->bucketIndex & IX_ETHDB_BUCKET_INDEX_MASK) == 0) && - (iterator->bucketIndex < (hashTable->numBuckets - IX_ETHDB_BUCKETPTR_AHEAD))) - { - /* preload next cache line (2 cache line ahead) */ - nodePtr += IX_ETHDB_BUCKETPTR_AHEAD; - __asm__ ("pld [%0];\n": : "r" (nodePtr)); - } -#endif - if (node != NULL) - { - TRY_LOCK(&node->lock); - - /* unlock last one or two nodes in the previous chain */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* redirect iterator */ - iterator->previousNode = NULL; - iterator->node = node; - - return IX_ETH_DB_SUCCESS; - } - } - - /* could not advance iterator */ - if (iterator->node != NULL) - { - UNLOCK(&iterator->node->lock); - - if (iterator->previousNode != NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - - iterator->node = NULL; - } - - return IX_ETH_DB_END; -} - -/** - * @brief removes an entry pointed by an iterator - * - * @param hashTable iterated hash table - * @param iterator iterator object - * - * Removes the entry currently pointed by the iterator and repositions the iterator - * on the next valid entry (if any). Handles locking issues automatically and - * implicitely grants write access lock to the new pointed entry. - * Failures due to concurrent threads having write access locks in the same region - * preserve the state of the database and the iterator object, leaving the caller - * free to retry without loss of access. It is guaranteed that only the thread owning - * the iterator can remove the object pointed by the iterator. - * - * @retval IX_ETH_DB_SUCCESS if removal has succeeded - * @retval IX_ETH_DB_BUSY if a locking failure has occured, in which case the caller - * should retry - * - * @internal - */ -IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator) -{ - HashIterator nextIteratorPos; - LockStack locks; - - INIT_STACK(&locks); - - /* set initial bucket index for next position */ - nextIteratorPos.bucketIndex = iterator->bucketIndex; - - /* compute iterator position before removing anything and lock ahead */ - if (iterator->node->next != NULL) - { - PUSH_LOCK(&locks, &iterator->node->next->lock); - - /* reposition on the next node in the chain */ - nextIteratorPos.node = iterator->node->next; - nextIteratorPos.previousNode = iterator->previousNode; - } - else - { - /* try next chain - don't know yet if we'll find anything */ - nextIteratorPos.node = NULL; - - /* if we find something it's a chain head */ - nextIteratorPos.previousNode = NULL; - - /* browse up in the buckets to find a non-null chain */ - while (++nextIteratorPos.bucketIndex < hashTable->numBuckets) - { - nextIteratorPos.node = hashTable->hashBuckets[nextIteratorPos.bucketIndex]; - - if (nextIteratorPos.node != NULL) - { - /* found a non-empty chain, try to lock head */ - PUSH_LOCK(&locks, &nextIteratorPos.node->lock); - - break; - } - } - } - - /* restore links over the to-be-deleted item */ - if (iterator->previousNode == NULL) - { - /* first in chain, lock bucket */ - PUSH_LOCK(&locks, &hashTable->bucketLocks[iterator->bucketIndex]); - - hashTable->hashBuckets[iterator->bucketIndex] = iterator->node->next; - - POP_LOCK(&locks); - } - else - { - /* relink */ - iterator->previousNode->next = iterator->node->next; - - /* unlock last remaining node in current chain when moving between chains */ - if (iterator->node->next == NULL) - { - UNLOCK(&iterator->previousNode->lock); - } - } - - /* delete entry */ - hashTable->freeFunction(iterator->node->data); - ixEthDBFreeHashNode(iterator->node); - - /* reposition iterator */ - *iterator = nextIteratorPos; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @} - */ diff --git a/drivers/net/npe/IxEthDBLearning.c b/drivers/net/npe/IxEthDBLearning.c deleted file mode 100644 index 1080d112de5..00000000000 --- a/drivers/net/npe/IxEthDBLearning.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * @file IxEthDBLearning.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/** - * @brief hashes the mac address in a mac descriptor with a XOR function - * - * @param entry pointer to a mac descriptor to be hashed - * - * This function only extracts the mac address and employs ixEthDBKeyXORHash() - * to do the actual hashing. - * Used only to add a whole entry to a hash table, as opposed to searching which - * takes only a key and uses the key hashing directly. - * - * @see ixEthDBKeyXORHash() - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBEntryXORHash(void *entry) -{ - MacDescriptor *descriptor = (MacDescriptor *) entry; - - return ixEthDBKeyXORHash(descriptor->macAddress); -} - -/** - * @brief hashes a mac address - * - * @param key pointer to a 6 byte structure (typically an IxEthDBMacAddr pointer) - * to be hashed - * - * Given a 6 bytes MAC address, the hash used is: - * - * hash(MAC[0:5]) = MAC[0:1] ^ MAC[2:3] ^ MAC[4:5] - * - * Used by the hash table to search and remove entries based - * solely on their keys (mac addresses). - * - * @return the hash value - * - * @internal - */ -UINT32 ixEthDBKeyXORHash(void *key) -{ - UINT32 hashValue; - UINT8 *value = (UINT8 *) key; - - hashValue = (value[5] << 8) | value[4]; - hashValue ^= (value[3] << 8) | value[2]; - hashValue ^= (value[1] << 8) | value[0]; - - return hashValue; -} - -/** - * @brief mac descriptor match function - * - * @param reference mac address (typically an IxEthDBMacAddr pointer) structure - * @param entry pointer to a mac descriptor whose key (mac address) is to be - * matched against the reference key - * - * Used by the hash table to retrieve entries. Hashing entries can produce - * collisions, i.e. descriptors with different mac addresses and the same - * hash value, where this function is used to differentiate entries. - * - * @retval true if the entry matches the reference key (equal addresses) - * @retval false if the entry does not match the reference key - * - * @internal - */ -BOOL ixEthDBAddressMatch(void *reference, void *entry) -{ - return (ixEthDBAddressCompare(reference, ((MacDescriptor *) entry)->macAddress) == 0); -} - -/** - * @brief compares two mac addresses - * - * @param mac1 first mac address to compare - * @param mac2 second mac address to compare - * - * This comparison works in a similar way to strcmp, producing similar results. - * Used to insert values keyed on mac addresses into binary search trees. - * - * @retval -1 if mac1 < mac2 - * @retval 0 if ma1 == mac2 - * @retval 1 if mac1 > mac2 - */ -UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2) -{ - UINT32 local_index; - - for (local_index = 0 ; local_index < IX_IEEE803_MAC_ADDRESS_SIZE ; local_index++) - { - if (mac1[local_index] > mac2[local_index]) - { - return 1; - } - else if (mac1[local_index] < mac2[local_index]) - { - return -1; - } - } - - return 0; -} - diff --git a/drivers/net/npe/IxEthDBMem.c b/drivers/net/npe/IxEthDBMem.c deleted file mode 100644 index 78fce4bd924..00000000000 --- a/drivers/net/npe/IxEthDBMem.c +++ /dev/null @@ -1,625 +0,0 @@ -/** - * @file IxEthDBDBMem.c - * - * @brief Memory handling routines for the MAC address database - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -IX_ETH_DB_PRIVATE HashNode *nodePool = NULL; -IX_ETH_DB_PRIVATE MacDescriptor *macPool = NULL; -IX_ETH_DB_PRIVATE MacTreeNode *treePool = NULL; - -IX_ETH_DB_PRIVATE HashNode nodePoolArea[NODE_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacDescriptor macPoolArea[MAC_POOL_SIZE]; -IX_ETH_DB_PRIVATE MacTreeNode treePoolArea[TREE_POOL_SIZE]; - -IX_ETH_DB_PRIVATE IxOsalMutex nodePoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex macPoolLock; -IX_ETH_DB_PRIVATE IxOsalMutex treePoolLock; - -#define LOCK_NODE_POOL { ixOsalMutexLock(&nodePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_NODE_POOL { ixOsalMutexUnlock(&nodePoolLock); } - -#define LOCK_MAC_POOL { ixOsalMutexLock(&macPoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_MAC_POOL { ixOsalMutexUnlock(&macPoolLock); } - -#define LOCK_TREE_POOL { ixOsalMutexLock(&treePoolLock, IX_OSAL_WAIT_FOREVER); } -#define UNLOCK_TREE_POOL { ixOsalMutexUnlock(&treePoolLock); } - -/* private function prototypes */ -IX_ETH_DB_PRIVATE MacDescriptor* ixEthDBPoolAllocMacDescriptor(void); -IX_ETH_DB_PRIVATE void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor); - -/** - * @addtogroup EthMemoryManagement - * - * @{ - */ - -/** - * @brief initializes the memory pools used by the ethernet database component - * - * Initializes the hash table node, mac descriptor and mac tree node pools. - * Called at initialization time by @ref ixEthDBInit(). - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBInitMemoryPools(void) -{ - int local_index; - - /* HashNode pool */ - ixOsalMutexInit(&nodePoolLock); - - for (local_index = 0 ; local_index < NODE_POOL_SIZE ; local_index++) - { - HashNode *freeNode = &nodePoolArea[local_index]; - - freeNode->nextFree = nodePool; - nodePool = freeNode; - } - - /* MacDescriptor pool */ - ixOsalMutexInit(&macPoolLock); - - for (local_index = 0 ; local_index < MAC_POOL_SIZE ; local_index++) - { - MacDescriptor *freeDescriptor = &macPoolArea[local_index]; - - freeDescriptor->nextFree = macPool; - macPool = freeDescriptor; - } - - /* MacTreeNode pool */ - ixOsalMutexInit(&treePoolLock); - - for (local_index = 0 ; local_index < TREE_POOL_SIZE ; local_index++) - { - MacTreeNode *freeNode = &treePoolArea[local_index]; - - freeNode->nextFree = treePool; - treePool = freeNode; - } -} - -/** - * @brief allocates a hash node from the pool - * - * Allocates a hash node and resets its value. - * - * @return the allocated hash node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBAllocHashNode(void) -{ - HashNode *allocatedNode = NULL; - - if (nodePool != NULL) - { - LOCK_NODE_POOL; - - allocatedNode = nodePool; - nodePool = nodePool->nextFree; - - UNLOCK_NODE_POOL; - - memset(allocatedNode, 0, sizeof(HashNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a hash node into the pool - * - * @param hashNode node to be freed - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeHashNode(HashNode *hashNode) -{ - if (hashNode != NULL) - { - LOCK_NODE_POOL; - - hashNode->nextFree = nodePool; - nodePool = hashNode; - - UNLOCK_NODE_POOL; - } -} - -/** - * @brief allocates a mac descriptor from the pool - * - * Allocates a mac descriptor and resets its value. - * This function is not used directly, instead @ref ixEthDBAllocMacDescriptor() - * is used, which keeps track of the pointer reference count. - * - * @see ixEthDBAllocMacDescriptor() - * - * @warning this function is not used directly by any other function - * apart from ixEthDBAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacDescriptor* ixEthDBPoolAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = NULL; - - if (macPool != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor = macPool; - macPool = macPool->nextFree; - - UNLOCK_MAC_POOL; - - memset(allocatedDescriptor, 0, sizeof(MacDescriptor)); - } - - return allocatedDescriptor; -} - -/** - * @brief allocates and initializes a mac descriptor smart pointer - * - * Uses @ref ixEthDBPoolAllocMacDescriptor() to allocate a mac descriptor - * from the pool and initializes its reference count. - * - * @see ixEthDBPoolAllocMacDescriptor() - * - * @return the allocated mac descriptor or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBAllocMacDescriptor(void) -{ - MacDescriptor *allocatedDescriptor = ixEthDBPoolAllocMacDescriptor(); - - if (allocatedDescriptor != NULL) - { - LOCK_MAC_POOL; - - allocatedDescriptor->refCount++; - - UNLOCK_MAC_POOL; - } - - return allocatedDescriptor; -} - -/** - * @brief frees a mac descriptor back into the pool - * - * @param macDescriptor mac descriptor to be freed - * - * @warning this function is not to be called by anyone but - * ixEthDBFreeMacDescriptor() - * - * @see ixEthDBFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPoolFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - macDescriptor->nextFree = macPool; - macPool = macDescriptor; - - UNLOCK_MAC_POOL; -} - -/** - * @brief frees or reduces the usage count of a mac descriptor smart pointer - * - * If the reference count reaches 0 (structure is no longer used anywhere) - * then the descriptor is freed back into the pool using ixEthDBPoolFreeMacDescriptor(). - * - * @see ixEthDBPoolFreeMacDescriptor() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacDescriptor(MacDescriptor *macDescriptor) -{ - if (macDescriptor != NULL) - { - LOCK_MAC_POOL; - - if (macDescriptor->refCount > 0) - { - macDescriptor->refCount--; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - ixEthDBPoolFreeMacDescriptor(macDescriptor); - } - else - { - UNLOCK_MAC_POOL; - } - } - else - { - UNLOCK_MAC_POOL; - } - } -} - -/** - * @brief clones a mac descriptor smart pointer - * - * @param macDescriptor mac descriptor to clone - * - * Increments the usage count of the smart pointer - * - * @returns the cloned smart pointer - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor) -{ - LOCK_MAC_POOL; - - if (macDescriptor->refCount == 0) - { - UNLOCK_MAC_POOL; - - return NULL; - } - - macDescriptor->refCount++; - - UNLOCK_MAC_POOL; - - return macDescriptor; -} - -/** - * @brief allocates a mac tree node from the pool - * - * Allocates and initializes a mac tree node from the pool. - * - * @return the allocated mac tree node or NULL if the pool is empty - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBAllocMacTreeNode(void) -{ - MacTreeNode *allocatedNode = NULL; - - if (treePool != NULL) - { - LOCK_TREE_POOL; - - allocatedNode = treePool; - treePool = treePool->nextFree; - - UNLOCK_TREE_POOL; - - memset(allocatedNode, 0, sizeof(MacTreeNode)); - } - - return allocatedNode; -} - -/** - * @brief frees a mac tree node back into the pool - * - * @param macNode mac tree node to be freed - * - * @warning not to be used except from ixEthDBFreeMacTreeNode(). - * - * @see ixEthDBFreeMacTreeNode() - * - * @internal - */ -void ixEthDBPoolFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - LOCK_TREE_POOL; - - macNode->nextFree = treePool; - treePool = macNode; - - UNLOCK_TREE_POOL; - } -} - -/** - * @brief frees or reduces the usage count of a mac tree node smart pointer - * - * @param macNode mac tree node to free - * - * Reduces the usage count of the given mac node. If the usage count - * reaches 0 the node is freed back into the pool using ixEthDBPoolFreeMacTreeNode() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBFreeMacTreeNode(MacTreeNode *macNode) -{ - if (macNode->descriptor != NULL) - { - ixEthDBFreeMacDescriptor(macNode->descriptor); - } - - if (macNode->left != NULL) - { - ixEthDBFreeMacTreeNode(macNode->left); - } - - if (macNode->right != NULL) - { - ixEthDBFreeMacTreeNode(macNode->right); - } - - ixEthDBPoolFreeMacTreeNode(macNode); -} - -/** - * @brief clones a mac tree node - * - * @param macNode mac tree node to be cloned - * - * Increments the usage count of the node, its associated descriptor - * and recursively of all its child nodes. - * - * @warning this function is recursive and clones whole trees/subtrees, use only for - * root nodes - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *macNode) -{ - if (macNode != NULL) - { - MacTreeNode *clonedMacNode = ixEthDBAllocMacTreeNode(); - - if (clonedMacNode != NULL) - { - if (macNode->right != NULL) - { - clonedMacNode->right = ixEthDBCloneMacTreeNode(macNode->right); - } - - if (macNode->left != NULL) - { - clonedMacNode->left = ixEthDBCloneMacTreeNode(macNode->left); - } - - if (macNode->descriptor != NULL) - { - clonedMacNode->descriptor = ixEthDBCloneMacDescriptor(macNode->descriptor); - } - } - - return clonedMacNode; - } - else - { - return NULL; - } -} - -#ifndef NDEBUG -/* Debug statistical functions for memory usage */ - -extern HashTable dbHashtable; -int ixEthDBNumHashElements(void); - -int ixEthDBNumHashElements(void) -{ - UINT32 bucketIndex; - int numElements = 0; - HashTable *hashTable = &dbHashtable; - - for (bucketIndex = 0 ; bucketIndex < hashTable->numBuckets ; bucketIndex++) - { - if (hashTable->hashBuckets[bucketIndex] != NULL) - { - HashNode *node = hashTable->hashBuckets[bucketIndex]; - - while (node != NULL) - { - numElements++; - - node = node->next; - } - } - } - - return numElements; -} - -UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree) -{ - if (tree == NULL) - { - return 0; - } - else - { - return 1 /* this node */ + ixEthDBSearchTreeUsageGet(tree->left) + ixEthDBSearchTreeUsageGet(tree->right); - } -} - -int ixEthDBShowMemoryStatus(void) -{ - MacDescriptor *mac; - MacTreeNode *tree; - HashNode *node; - - int macCounter = 0; - int treeCounter = 0; - int nodeCounter = 0; - - int totalTreeUsage = 0; - int totalDescriptorUsage = 0; - int totalCloneDescriptorUsage = 0; - int totalNodeUsage = 0; - - UINT32 portIndex; - - LOCK_NODE_POOL; - LOCK_MAC_POOL; - LOCK_TREE_POOL; - - mac = macPool; - tree = treePool; - node = nodePool; - - while (mac != NULL) - { - macCounter++; - - mac = mac->nextFree; - - if (macCounter > MAC_POOL_SIZE) - { - break; - } - } - - while (tree != NULL) - { - treeCounter++; - - tree = tree->nextFree; - - if (treeCounter > TREE_POOL_SIZE) - { - break; - } - } - - while (node != NULL) - { - nodeCounter++; - - node = node->nextFree; - - if (nodeCounter > NODE_POOL_SIZE) - { - break; - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - int treeUsage = ixEthDBSearchTreeUsageGet(ixEthDBPortInfo[portIndex].updateMethod.searchTree); - - totalTreeUsage += treeUsage; - totalCloneDescriptorUsage += treeUsage; /* each tree node contains a descriptor */ - } - - totalNodeUsage = ixEthDBNumHashElements(); - totalDescriptorUsage += totalNodeUsage; /* each hash table entry contains a descriptor */ - - UNLOCK_NODE_POOL; - UNLOCK_MAC_POOL; - UNLOCK_TREE_POOL; - - printf("Ethernet database memory usage stats:\n\n"); - - if (macCounter <= MAC_POOL_SIZE) - { - printf("\tMAC descriptor pool : %d free out of %d entries (%d%%)\n", macCounter, MAC_POOL_SIZE, macCounter * 100 / MAC_POOL_SIZE); - } - else - { - printf("\tMAC descriptor pool : invalid state (ring within the pool), normally %d entries\n", MAC_POOL_SIZE); - } - - if (treeCounter <= TREE_POOL_SIZE) - { - printf("\tTree node pool : %d free out of %d entries (%d%%)\n", treeCounter, TREE_POOL_SIZE, treeCounter * 100 / TREE_POOL_SIZE); - } - else - { - printf("\tTREE descriptor pool : invalid state (ring within the pool), normally %d entries\n", TREE_POOL_SIZE); - } - - if (nodeCounter <= NODE_POOL_SIZE) - { - printf("\tHash node pool : %d free out of %d entries (%d%%)\n", nodeCounter, NODE_POOL_SIZE, nodeCounter * 100 / NODE_POOL_SIZE); - } - else - { - printf("\tNODE descriptor pool : invalid state (ring within the pool), normally %d entries\n", NODE_POOL_SIZE); - } - - printf("\n"); - printf("\tMAC descriptor usage : %d entries, %d cloned\n", totalDescriptorUsage, totalCloneDescriptorUsage); - printf("\tTree node usage : %d entries\n", totalTreeUsage); - printf("\tHash node usage : %d entries\n", totalNodeUsage); - printf("\n"); - - /* search for duplicate nodes in the mac pool */ - { - MacDescriptor *reference = macPool; - - while (reference != NULL) - { - MacDescriptor *comparison = reference->nextFree; - - while (comparison != NULL) - { - if (reference == comparison) - { - printf("Warning: reached a duplicate (%p), invalid MAC pool state\n", reference); - - return 1; - } - - comparison = comparison->nextFree; - } - - reference = reference->nextFree; - } - } - - printf("No duplicates found in the MAC pool (sanity check ok)\n"); - - return 0; -} - -#endif /* NDEBUG */ - -/** - * @} EthMemoryManagement - */ diff --git a/drivers/net/npe/IxEthDBNPEAdaptor.c b/drivers/net/npe/IxEthDBNPEAdaptor.c deleted file mode 100644 index 30e1f61ab99..00000000000 --- a/drivers/net/npe/IxEthDBNPEAdaptor.c +++ /dev/null @@ -1,695 +0,0 @@ -/** - * @file IxEthDBDBNPEAdaptor.c - * - * @brief Routines that read and write learning/search trees in NPE-specific format - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" -#include "IxEthDBLog_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PUBLIC void ixEthDBELTShow(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBShowNpeMsgHistory(void); - -/* data */ -UINT8* ixEthDBNPEUpdateArea[IX_ETH_DB_NUMBER_OF_PORTS]; -UINT32 dumpEltSize; - -/* private data */ -IX_ETH_DB_PRIVATE IxEthDBNoteWriteFn ixEthDBNPENodeWrite[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1]; - -#define IX_ETH_DB_MAX_DELTA_ZONES (6) /* at most 6 EP Delta zones, according to NPE FS */ -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDeltaOffset[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; -IX_ETH_DB_PRIVATE UINT32 ixEthDBEPDelta[IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1][IX_ETH_DB_MAX_DELTA_ZONES]; - -/** - * @brief allocates non-cached or contiguous NPE tree update areas for all the ports - * - * This function is called only once at initialization time from - * @ref ixEthDBInit(). - * - * @warning do not call manually - * - * @see ixEthDBInit() - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasInit(void) -{ - UINT32 portIndex; - PortUpdateMethod *update; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - update = &ixEthDBPortInfo[portIndex].updateMethod; - - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - update->npeUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_ELT_BYTE_SIZE); - update->npeGwUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_GW_BYTE_SIZE); - update->vlanUpdateZone = IX_OSAL_CACHE_DMA_MALLOC(FULL_VLAN_BYTE_SIZE); - - if (update->npeUpdateZone == NULL - || update->npeGwUpdateZone == NULL - || update->vlanUpdateZone == NULL) - { - ERROR_LOG("Fatal error: IX_ACC_DRV_DMA_MALLOC() returned NULL, no NPE update zones available\n"); - } - else - { - memset(update->npeUpdateZone, 0, FULL_ELT_BYTE_SIZE); - memset(update->npeGwUpdateZone, 0, FULL_GW_BYTE_SIZE); - memset(update->vlanUpdateZone, 0, FULL_VLAN_BYTE_SIZE); - } - } - else - { - /* unused */ - update->npeUpdateZone = NULL; - update->npeGwUpdateZone = NULL; - update->vlanUpdateZone = NULL; - } - } -} - -/** - * @brief deallocates the NPE update areas for all the ports - * - * This function is called at component de-initialization time - * by @ref ixEthDBUnload(). - * - * @warning do not call manually - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEUpdateAreasUnload(void) -{ - UINT32 portIndex; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (ixEthDBPortDefinitions[portIndex].type == IX_ETH_NPE) - { - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.npeGwUpdateZone); - IX_OSAL_CACHE_DMA_FREE(ixEthDBPortInfo[portIndex].updateMethod.vlanUpdateZone); - } - } -} - -/** - * @brief general-purpose NPE callback function - * - * @param npeID NPE ID - * @param msg NPE message - * - * This function will unblock the caller by unlocking - * the npeAckLock mutex defined for each NPE port - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg) -{ - IxEthDBPortId portID = IX_ETH_DB_NPE_TO_PORT_ID(npeID); - PortInfo *portInfo; - - if (portID >= IX_ETH_DB_NUMBER_OF_PORTS) - { - /* invalid port */ - return; - } - - if (ixEthDBPortDefinitions[portID].type != IX_ETH_NPE) - { - /* not an NPE */ - return; - } - - portInfo = &ixEthDBPortInfo[portID]; - - ixOsalMutexUnlock(&portInfo->npeAckLock); -} - -/** - * @brief synchronizes the database with tree - * - * @param portID port ID of the NPE whose tree is to be scanned - * @param eltBaseAddress memory base address of the NPE serialized tree - * @param eltSize size in bytes of the NPE serialized tree - * - * Scans the NPE learning tree and resets the age of active database records. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize) -{ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE(eltBaseAddress, eltSize); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - /* debug */ - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) checking node at offset %d...\n", eltEntryOffset / ELT_ENTRY_SIZE); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress) != true) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is empty\n"); - } - else if (eltEntryOffset == ELT_ROOT_OFFSET) - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... node is root\n"); - } - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* check only active entries belonging to this port */ - if (ixEthDBPortInfo[portID].agingEnabled && IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) && (portID == entryPortID) - && ((ixEthDBPortDefinitions[portID].capabilities & IX_ETH_ENTRY_AGING) == 0)) - { - /* search record */ - HashNode *node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_FILTERING_RECORDS); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) synced entry [%s] already in the database, updating fields\n", mac2string(eltNodeAddress)); - - /* reset age - set to -1 so that maintenance will restore it to 0 (or more) when incrementing */ - if (!descriptor->recordData.filteringData.staticEntry) - { - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - descriptor->recordData.filteringData.age = AGE_RESET; - } - else if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - descriptor->recordData.filteringVlanData.age = AGE_RESET; - } - } - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - } - else - { - IX_ETH_DB_NPE_VERBOSE_TRACE("\t... found portID %d, we check only port %d\n", entryPortID, portID); - } - } - } -} - -/** - * @brief writes a search tree in NPE format - * - * @param type type of records to be written into the NPE update zone - * @param totalSize maximum size of the linearized tree - * @param baseAddress memory base address where to write the NPE tree into - * @param tree search tree to write in NPE format - * @param blocks number of written 64-byte blocks - * @param startIndex optimal binary search start index - * - * Serializes the given tree in NPE linear format - * - * @return none - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *epDelta, UINT32 *blocks) -{ - MacTreeNodeStack *stack; - UINT32 maxOffset = 0; - UINT32 emptyOffset; - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (NPEAdaptor) failed to allocate the node stack for learning tree linearization, out of memory?\n"); - return; - } - - /* zero out empty root */ - memset(baseAddress, 0, ELT_ENTRY_SIZE); - - NODE_STACK_INIT(stack); - - if (tree != NULL) - { - /* push tree root at offset 1 */ - NODE_STACK_PUSH(stack, tree, 1); - - maxOffset = 1; - } - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* update maximum offset */ - if (offset > maxOffset) - { - maxOffset = offset; - } - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing MAC [%s] at offset %d\n", mac2string(node->descriptor->macAddress), offset); - - /* add node to NPE ELT at position indicated by offset */ - if (offset < MAX_ELT_SIZE) - { - ixEthDBNPENodeWrite[type]((void *) (((UINT32) baseAddress) + offset * ELT_ENTRY_SIZE), node); - } - - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + LEFT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - else - { - /* ensure this entry is zeroed */ - memset((void *) ((UINT32) baseAddress + RIGHT_CHILD_OFFSET(offset) * ELT_ENTRY_SIZE), 0, ELT_ENTRY_SIZE); - } - } - - emptyOffset = maxOffset + 1; - - /* zero out rest of the tree */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Emptying tree from offset %d, address 0x%08X, %d bytes\n", - emptyOffset, ((UINT32) baseAddress) + emptyOffset * ELT_ENTRY_SIZE, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - - if (emptyOffset < MAX_ELT_SIZE - 1) - { - memset((void *) (((UINT32) baseAddress) + (emptyOffset * ELT_ENTRY_SIZE)), 0, totalSize - (emptyOffset * ELT_ENTRY_SIZE)); - } - - /* flush cache */ - IX_OSAL_CACHE_FLUSH(baseAddress, totalSize); - - /* debug */ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Ethernet learning/filtering tree XScale wrote at address 0x%08X (max %d bytes):\n\n", - (UINT32) baseAddress, FULL_ELT_BYTE_SIZE); - - IX_ETH_DB_NPE_DUMP_ELT(baseAddress, FULL_ELT_BYTE_SIZE); - - /* compute number of 64-byte blocks */ - if (blocks != NULL) - { - *blocks = maxOffset != 0 ? 1 + maxOffset / 8 : 0; - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Wrote %d 64-byte blocks\n", *blocks); - } - - /* compute epDelta - start index for binary search */ - if (epDelta != NULL) - { - UINT32 deltaIndex = 0; - - *epDelta = 0; - - for (; deltaIndex < IX_ETH_DB_MAX_DELTA_ZONES ; deltaIndex ++) - { - if (ixEthDBEPDeltaOffset[type][deltaIndex] >= maxOffset) - { - *epDelta = ixEthDBEPDelta[type][deltaIndex]; - break; - } - } - - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Computed epDelta %d (based on maxOffset %d)\n", *epDelta, maxOffset); - } - - ixOsalCacheDmaFree(stack); -} - -/** - * @brief implements a dummy node serialization function - * - * @param address address of where the node is to be serialized (unused) - * @param node tree node to be serialized (unused) - * - * This function is registered for safety reasons and should - * never be called. It will display an error message if this - * function is called. - * - * @return none - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNullSerialize(void *address, MacTreeNode *node) -{ - IX_ETH_DB_NPE_TRACE("DB: (NPEAdaptor) Warning, the NullSerialize function was called, wrong record type?\n"); -} - -/** - * @brief writes a filtering entry in NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPELearningNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy port ID */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET) = IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(node->descriptor->portID); - - /* copy flags (valid and not active, as the NPE sets it to active) and clear reserved section (bits 2-7) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) = (UINT8) IX_EDB_FLAGS_INACTIVE_VALID; - - IX_ETH_DB_NPE_VERBOSE_TRACE("DB: (NPEAdaptor) writing ELT node 0x%08x:0x%08x\n", * (UINT32 *) address, * (((UINT32 *) (address)) + 1)); -} - -/** - * @brief writes a WiFi header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEWiFiNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* copy index */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET) = node->descriptor->recordData.wifiData.gwAddressIndex; - - /* copy flags (type and valid) */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET) = node->descriptor->recordData.wifiData.type << 1 | IX_EDB_FLAGS_VALID; -} - -/** - * @brief writes a WiFi gateway header conversion record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node) -{ - /* copy mac address */ - memcpy(address, node->descriptor->recordData.wifiData.gwMacAddress, IX_IEEE803_MAC_ADDRESS_SIZE); - - /* set reserved field, two bytes */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET + 1) = 0; -} - -/** - * @brief writes a firewall record in - * NPE linear format - * - * @param address memory address to write node to - * @param node node to be written - * - * Used by @ref ixEthDBNPETreeWrite to liniarize a search tree - * in NPE-readable format. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBNPEFirewallNodeWrite(void *address, MacTreeNode *node) -{ - /* set reserved field */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_RESERVED_OFFSET) = 0; - - /* set flags */ - NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_FW_FLAGS_OFFSET) = IX_EDB_FLAGS_VALID; - - /* copy mac address */ - memcpy((void *) ((UINT32) address + IX_EDB_NPE_NODE_FW_ADDR_OFFSET), node->descriptor->macAddress, IX_IEEE803_MAC_ADDRESS_SIZE); -} - -/** - * @brief registers the NPE serialization methods - * - * This functions registers NPE serialization methods - * for writing the following types of records in NPE - * readable linear format: - * - filtering records - * - WiFi header conversion records - * - WiFi gateway header conversion records - * - firewall records - * - * Note that this function should be called by the - * component initialization function. - * - * @return number of registered record types - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBRecordSerializeMethodsRegister() -{ - int i; - - /* safety - register a blank method for everybody first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_RECORD_TYPE_INDEX + 1 ; i++) - { - ixEthDBNPENodeWrite[i] = ixEthDBNullSerialize; - } - - /* register real methods */ - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FILTERING_VLAN_RECORD] = ixEthDBNPELearningNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_WIFI_RECORD] = ixEthDBNPEWiFiNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_FIREWALL_RECORD] = ixEthDBNPEFirewallNodeWrite; - ixEthDBNPENodeWrite[IX_ETH_DB_GATEWAY_RECORD] = ixEthDBNPEGatewayNodeWrite; - - /* EP Delta arrays */ - memset(ixEthDBEPDeltaOffset, 0, sizeof (ixEthDBEPDeltaOffset)); - memset(ixEthDBEPDelta, 0, sizeof (ixEthDBEPDelta)); - - /* filtering records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FILTERING_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_FILTERING_RECORD][2] = 14; - - /* wifi records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][0] = 1; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][1] = 3; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][1] = 7; - - ixEthDBEPDeltaOffset[IX_ETH_DB_WIFI_RECORD][2] = 511; - ixEthDBEPDelta[IX_ETH_DB_WIFI_RECORD][2] = 14; - - /* firewall records */ - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][0] = 0; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][1] = 1; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][1] = 5; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][2] = 3; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][2] = 13; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][3] = 7; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][3] = 21; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][4] = 15; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][4] = 29; - - ixEthDBEPDeltaOffset[IX_ETH_DB_FIREWALL_RECORD][5] = 31; - ixEthDBEPDelta[IX_ETH_DB_FIREWALL_RECORD][5] = 37; - - return 5; /* 5 methods registered */ -} - -#ifndef IX_NDEBUG - -IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen = 0; - -/** - * When compiled in DEBUG mode, this function can be used to display - * the history of messages sent to the NPEs (up to 100). - */ -IX_ETH_DB_PUBLIC -void ixEthDBShowNpeMsgHistory() -{ - UINT32 i = 0; - UINT32 base, len; - - if (npeMsgHistoryLen <= IX_ETH_DB_NPE_MSG_HISTORY_DEPTH) - { - base = 0; - len = npeMsgHistoryLen; - } - else - { - base = npeMsgHistoryLen % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - len = IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - } - - printf("NPE message history [last %d messages, from least to most recent]:\n", len); - - for (; i < len ; i++) - { - UINT32 pos = (base + i) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; - printf("msg[%d]: 0x%08x:0x%08x\n", i, npeMsgHistory[pos][0], npeMsgHistory[pos][1]); - } -} - -IX_ETH_DB_PUBLIC -void ixEthDBELTShow(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - /* send EDB_GetMACAddressDatabase message */ - FILL_GETMACADDRESSDATABASE(message, - 0 /* reserved */, - IX_OSAL_MMU_VIRT_TO_PHYS(ixEthDBPortInfo[portID].updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* analyze NPE copy */ - UINT32 eltEntryOffset; - UINT32 entryPortID; - - UINT32 eltBaseAddress = (UINT32) ixEthDBPortInfo[portID].updateMethod.npeUpdateZone; - UINT32 eltSize = FULL_ELT_BYTE_SIZE; - - /* invalidate cache */ - IX_OSAL_CACHE_INVALIDATE((void *) eltBaseAddress, eltSize); - - printf("Listing records in main learning tree for port %d\n", portID); - - for (eltEntryOffset = ELT_ROOT_OFFSET ; eltEntryOffset < eltSize ; eltEntryOffset += ELT_ENTRY_SIZE) - { - /* (eltBaseAddress + eltEntryOffset) points to a valid NPE tree node - * - * the format of the node is MAC[6 bytes]:PortID[1 byte]:Reserved[6 bits]:Active[1 bit]:Valid[1 bit] - * therefore we can just use the pointer for database searches as only the first 6 bytes are checked - */ - void *eltNodeAddress = (void *) ((UINT32) eltBaseAddress + eltEntryOffset); - - if (IX_EDB_NPE_NODE_VALID(eltNodeAddress)) - { - HashNode *node; - - entryPortID = IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(IX_EDB_NPE_NODE_PORT_ID(eltNodeAddress)); - - /* search record */ - node = ixEthDBSearch((IxEthDBMacAddr *) eltNodeAddress, IX_ETH_DB_ALL_RECORD_TYPES); - - printf("%s - port %d - %s ", mac2string((unsigned char *) eltNodeAddress), entryPortID, - IX_EDB_NPE_NODE_ACTIVE(eltNodeAddress) ? "active" : "inactive"); - - /* safety check, maybe user deleted record right before sync? */ - if (node != NULL) - { - /* found record */ - MacDescriptor *descriptor = (MacDescriptor *) node->data; - - printf("- %s ", - descriptor->type == IX_ETH_DB_FILTERING_RECORD ? "filtering" : - descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD ? "vlan" : - descriptor->type == IX_ETH_DB_WIFI_RECORD ? "wifi" : "other (check main DB)"); - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) printf("- age %d - %s ", - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) printf("- age %d - %s - tci %d ", - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - descriptor->recordData.filteringVlanData.ieee802_1qTag); - - /* end transaction */ - ixEthDBReleaseHashNode(node); - } - else - { - printf("- not synced"); - } - - printf("\n"); - } - } - } - else - { - ixOsalLog(IX_OSAL_LOG_LVL_FATAL, IX_OSAL_LOG_DEV_STDOUT, - "EthDB: (ShowELT) Could not complete action (communication failure)\n", - portID, 0, 0, 0, 0, 0); - } -} - -#endif diff --git a/drivers/net/npe/IxEthDBPortUpdate.c b/drivers/net/npe/IxEthDBPortUpdate.c deleted file mode 100644 index 92af331a540..00000000000 --- a/drivers/net/npe/IxEthDBPortUpdate.c +++ /dev/null @@ -1,716 +0,0 @@ -/** - * @file IxEthDBDBPortUpdate.c - * - * @brief Implementation of dependency and port update handling - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototype declarations */ -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor); -IX_ETH_DB_PRIVATE void ixEthDBCreateTrees(IxEthDBPortMap updatePorts); -IX_ETH_DB_PRIVATE MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size); -IX_ETH_DB_PRIVATE void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count); -IX_ETH_DB_PRIVATE UINT32 ixEthDBRebalanceLog2Floor(UINT32 x); - -extern HashTable dbHashtable; - -/** - * @brief register types requiring automatic updates - * - * @param typeArray array indexed on record types, each - * element indicating whether the record type requires an - * automatic update (true) or not (false) - * - * Automatic updates are done for registered record types - * upon adding, updating (that is, updating the record portID) - * and removing records. Whenever an automatic update is triggered - * the appropriate ports will be provided with new database - * information. - * - * It is assumed that the typeArray parameter is allocated large - * enough to hold all the user defined types. Also, the type - * array should be initialized to false as this function only - * caters for types which do require automatic updates. - * - * Note that this function should be called by the component - * initialization function. - * - * @return number of record types registered for automatic - * updates - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray) -{ - typeArray[IX_ETH_DB_FILTERING_RECORD] = true; - typeArray[IX_ETH_DB_FILTERING_VLAN_RECORD] = true; - - return 2; -} - -/** - * @brief computes dependencies and triggers port learning tree updates - * - * @param triggerPorts port map consisting in the ports which triggered the update - * - * This function browses through all the ports and determines how to waterfall the update - * event from the trigger ports to all other ports depending on them. - * - * Once the list of ports to be updated is determined this function - * calls @ref ixEthDBCreateTrees. - * - * @internal - */ -IX_ETH_DB_PUBLIC -void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts) -{ - IxEthDBPortMap updatePorts; - UINT32 portIndex; - - ixEthDBUpdateLock(); - - SET_EMPTY_DEPENDENCY_MAP(updatePorts); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *port = &ixEthDBPortInfo[portIndex]; - BOOL mapsCollide; - - MAPS_COLLIDE(mapsCollide, triggerPorts, port->dependencyPortMap); - - if (mapsCollide /* do triggers influence this port? */ - && !IS_PORT_INCLUDED(portIndex, updatePorts) /* and it's not already in the update list */ - && port->updateMethod.updateEnabled) /* and we're allowed to update it */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding port %d to update set\n", portIndex); - - JOIN_PORT_TO_MAP(updatePorts, portIndex); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Didn't add port %d to update set, reasons follow:\n", portIndex); - - if (!mapsCollide) - { - IX_ETH_DB_UPDATE_TRACE("\tMaps don't collide on port %d\n", portIndex); - } - - if (IS_PORT_INCLUDED(portIndex, updatePorts)) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d is already in the update set\n", portIndex); - } - - if (!port->updateMethod.updateEnabled) - { - IX_ETH_DB_UPDATE_TRACE("\tPort %d doesn't have updateEnabled set\n", portIndex); - } - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Updating port set\n"); - - ixEthDBCreateTrees(updatePorts); - - ixEthDBUpdateUnlock(); -} - -/** - * @brief creates learning trees and calls the port update handlers - * - * @param updatePorts set of ports in need of learning trees - * - * This function determines the optimal method of creating learning - * trees using a minimal number of database queries, keeping in mind - * that different ports can either use the same learning trees or they - * can partially share them. The actual tree building routine is - * @ref ixEthDBQuery. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBCreateTrees(IxEthDBPortMap updatePorts) -{ - UINT32 portIndex; - BOOL result; - BOOL portsLeft = true; - - while (portsLeft) - { - /* get port with minimal dependency map and NULL search tree */ - UINT32 minPortIndex = MAX_PORT_SIZE; - UINT32 minimalSize = MAX_PORT_SIZE; - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - UINT32 size; - PortInfo *port = &ixEthDBPortInfo[portIndex]; - - /* generate trees only for ports that need them */ - if (!port->updateMethod.searchTreePendingWrite && IS_PORT_INCLUDED(portIndex, updatePorts)) - { - GET_MAP_SIZE(port->dependencyPortMap, size); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Dependency map for port %d: size %d\n", - portIndex, size); - - if (size < minimalSize) - { - minPortIndex = portIndex; - minimalSize = size; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Skipped port %d from tree diff (%s)\n", portIndex, - port->updateMethod.searchTreePendingWrite ? "pending write access" : "ignored by query"); - } - } - - /* if a port was found than minimalSize is not MAX_PORT_SIZE */ - if (minimalSize != MAX_PORT_SIZE) - { - /* minPortIndex is the port we seek */ - PortInfo *port = &ixEthDBPortInfo[minPortIndex]; - - IxEthDBPortMap query; - MacTreeNode *baseTree; - - /* now try to find a port with minimal map difference */ - PortInfo *minimalDiffPort = NULL; - UINT32 minimalDiff = MAX_PORT_SIZE; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal size port is %d\n", minPortIndex); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *diffPort = &ixEthDBPortInfo[portIndex]; - BOOL mapIsSubset; - - IS_MAP_SUBSET(mapIsSubset, diffPort->dependencyPortMap, port->dependencyPortMap); - - - if (portIndex != minPortIndex - && diffPort->updateMethod.searchTree != NULL - && mapIsSubset) - { - /* compute size and pick only minimal size difference */ - UINT32 diffPortSize; - UINT32 sizeDifference; - - GET_MAP_SIZE(diffPort->dependencyPortMap, diffPortSize); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Checking port %d for differences...\n", portIndex); - - sizeDifference = minimalSize - diffPortSize; - - if (sizeDifference < minimalDiff) - { - minimalDiffPort = diffPort; - minimalDiff = sizeDifference; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Minimal difference 0x%x was found on port %d\n", - minimalDiff, portIndex); - } - } - } - - /* check if filtering is enabled on this port */ - if ((port->featureStatus & IX_ETH_DB_FILTERING) != 0) - { - /* if minimalDiff is not MAX_PORT_SIZE minimalDiffPort points to the most similar port */ - if (minimalDiff != MAX_PORT_SIZE) - { - baseTree = ixEthDBCloneMacTreeNode(minimalDiffPort->updateMethod.searchTree); - DIFF_MAPS(query, port->dependencyPortMap , minimalDiffPort->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Found minimal diff, extending tree %d on query\n", - minimalDiffPort->portID); - } - else /* .. otherwise no similar port was found, build tree from scratch */ - { - baseTree = NULL; - - COPY_DEPENDENCY_MAP(query, port->dependencyPortMap); - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No similar diff, creating tree from query\n"); - } - - IS_EMPTY_DEPENDENCY_MAP(result, query); - - if (!result) /* otherwise we don't need anything more on top of the cloned tree */ - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Adding query tree to port %d\n", minPortIndex); - - /* build learning tree */ - port->updateMethod.searchTree = ixEthDBQuery(baseTree, query, IX_ETH_DB_ALL_FILTERING_RECORDS, MAX_ELT_SIZE); - } - else - { - IX_ETH_DB_UPDATE_TRACE("DB: (Update) Query is empty, assuming identical nearest tree\n"); - - port->updateMethod.searchTree = baseTree; - } - } - else - { - /* filtering is not enabled, will download an empty tree */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - port->updateMethod.searchTree = NULL; - } - - /* mark tree as valid */ - port->updateMethod.searchTreePendingWrite = true; - } - else - { - portsLeft = false; - - IX_ETH_DB_UPDATE_TRACE("DB: (Update) No trees to create this round\n"); - } - } - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - PortInfo *updatePort = &ixEthDBPortInfo[portIndex]; - - if (updatePort->updateMethod.searchTreePendingWrite) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Starting procedure to upload new search tree (%snull) into NPE %d\n", - updatePort->updateMethod.searchTree != NULL ? "not " : "", - portIndex); - - updatePort->updateMethod.updateHandler(portIndex, IX_ETH_DB_FILTERING_RECORD); - } - } -} - -/** - * @brief standard NPE update handler - * - * @param portID id of the port to be updated - * @param type record type to be pushed during this update - * - * The NPE update handler manages updating the NPE databases - * given a certain record type. - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type) -{ - UINT32 epDelta, blockCount; - IxNpeMhMessage message; - UINT32 treeSize = 0; - PortInfo *port = &ixEthDBPortInfo[portID]; - - /* size selection and type check */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - treeSize = FULL_ELT_BYTE_SIZE; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - treeSize = FULL_FW_BYTE_SIZE; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - /* serialize tree into memory */ - ixEthDBNPETreeWrite(type, treeSize, port->updateMethod.npeUpdateZone, port->updateMethod.searchTree, &epDelta, &blockCount); - - /* free internal copy */ - if (port->updateMethod.searchTree != NULL) - { - ixEthDBFreeMacTreeNode(port->updateMethod.searchTree); - } - - /* forget last used search tree */ - port->updateMethod.searchTree = NULL; - port->updateMethod.searchTreePendingWrite = false; - - /* dependending on the update type we do different things */ - if (type == IX_ETH_DB_FILTERING_RECORD || type == IX_ETH_DB_WIFI_RECORD) - { - IX_STATUS result; - - FILL_SETMACADDRESSDATABASE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - epDelta, blockCount, - IX_OSAL_MMU_VIRT_TO_PHYS(port->updateMethod.npeUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) Finished downloading NPE tree on port %d\n", portID); - } - else - { - ixEthDBPortInfo[portID].agingEnabled = false; - ixEthDBPortInfo[portID].updateMethod.updateEnabled = false; - ixEthDBPortInfo[portID].updateMethod.userControlled = true; - - ERROR_LOG("EthDB: (PortUpdate) disabling aging and updates on port %d (assumed dead)\n", portID); - - ixEthDBDatabaseClear(portID, IX_ETH_DB_ALL_RECORD_TYPES); - - return IX_ETH_DB_FAIL; - } - - return IX_ETH_DB_SUCCESS; - } - else if (type == IX_ETH_DB_FIREWALL_RECORD) - { - return ixEthDBFirewallUpdate(portID, port->updateMethod.npeUpdateZone, epDelta); - } - - return IX_ETH_DB_INVALID_ARG; -} - -/** - * @brief queries the database for a set of records to be inserted into a given tree - * - * @param searchTree pointer to a tree where insertions will be performed; can be NULL - * @param query set of ports that a database record must match to be inserted into the tree - * - * The query method browses through the database, extracts all the descriptors matching - * the given query parameter and inserts them into the given learning tree. - * Note that this is an append procedure, the given tree needs not to be empty. - * A "descriptor matching the query" is a descriptor whose port id is in the query map. - * If the given tree is empty (NULL) a new tree is created and returned. - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maxEntries) -{ - HashIterator iterator; - UINT32 entryCount = 0; - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) querying [%s]:%d on port map ... ", - mac2string(descriptor->macAddress), - descriptor->portID); - - if ((descriptor->type & recordFilter) != 0 - && IS_PORT_INCLUDED(descriptor->portID, query)) - { - MacDescriptor *descriptorClone = ixEthDBCloneMacDescriptor(descriptor); - - IX_ETH_DB_UPDATE_TRACE("match\n"); - - if (descriptorClone != NULL) - { - /* add descriptor to tree */ - searchTree = ixEthDBTreeInsert(searchTree, descriptorClone); - - entryCount++; - } - } - else - { - IX_ETH_DB_UPDATE_TRACE("no match\n"); - } - - if (entryCount < maxEntries) - { - /* advance to the next record */ - BUSY_RETRY(ixEthDBIncrementHashIterator(&dbHashtable, &iterator)); - } - else - { - /* the NPE won't accept more entries so we can stop now */ - ixEthDBReleaseHashIterator(&iterator); - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) number of elements reached maximum supported by port\n"); - - break; - } - } - - IX_ETH_DB_UPDATE_TRACE("DB: (PortUpdate) query inserted %d records in the search tree\n", entryCount); - - return ixEthDBTreeRebalance(searchTree); -} - -/** - * @brief inserts a mac descriptor into an tree - * - * @param searchTree tree where the insertion is to be performed (may be NULL) - * @param descriptor descriptor to insert into tree - * - * @return the tree root - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeInsert(MacTreeNode *searchTree, MacDescriptor *descriptor) -{ - MacTreeNode *currentNode = searchTree; - MacTreeNode *insertLocation = NULL; - MacTreeNode *newNode; - INT32 insertPosition = RIGHT; - - if (descriptor == NULL) - { - return searchTree; - } - - /* create a new node */ - newNode = ixEthDBAllocMacTreeNode(); - - if (newNode == NULL) - { - /* out of memory */ - ERROR_LOG("Warning: ixEthDBAllocMacTreeNode returned NULL in file %s:%d (out of memory?)\n", __FILE__, __LINE__); - - ixEthDBFreeMacDescriptor(descriptor); - - return NULL; - } - - /* populate node */ - newNode->descriptor = descriptor; - - /* an empty initial tree is a special case */ - if (searchTree == NULL) - { - return newNode; - } - - /* get insertion location */ - while (insertLocation == NULL) - { - MacTreeNode *nextNode; - - /* compare given key with current node key */ - insertPosition = ixEthDBAddressCompare(descriptor->macAddress, currentNode->descriptor->macAddress); - - /* navigate down */ - if (insertPosition == RIGHT) - { - nextNode = currentNode->right; - } - else if (insertPosition == LEFT) - { - nextNode = currentNode->left; - } - else - { - /* error, duplicate key */ - ERROR_LOG("Warning: trapped insertion of a duplicate MAC address in an NPE search tree\n"); - - /* this will free the MAC descriptor as well */ - ixEthDBFreeMacTreeNode(newNode); - - return searchTree; - } - - /* when we can no longer dive through the tree we found the insertion place */ - if (nextNode != NULL) - { - currentNode = nextNode; - } - else - { - insertLocation = currentNode; - } - } - - /* insert node */ - if (insertPosition == RIGHT) - { - insertLocation->right = newNode; - } - else - { - insertLocation->left = newNode; - } - - return searchTree; -} - -/** - * @brief balance a tree - * - * @param searchTree tree to balance - * - * Converts a tree into a balanced tree and returns the root of - * the balanced tree. The resulting tree is route balanced - * not perfectly balanced. This makes no difference to the - * average tree search time which is the same in both cases, O(log2(n)). - * - * @return root of the balanced tree or NULL if there's no memory left - * - * @internal - */ -IX_ETH_DB_PRIVATE -MacTreeNode* ixEthDBTreeRebalance(MacTreeNode *searchTree) -{ - MacTreeNode *pseudoRoot = ixEthDBAllocMacTreeNode(); - UINT32 size; - - if (pseudoRoot == NULL) - { - /* out of memory */ - return NULL; - } - - pseudoRoot->right = searchTree; - - ixEthDBRebalanceTreeToVine(pseudoRoot, &size); - ixEthDBRebalanceVineToTree(pseudoRoot, size); - - searchTree = pseudoRoot->right; - - /* remove pseudoRoot right branch, otherwise it will free the entire tree */ - pseudoRoot->right = NULL; - - ixEthDBFreeMacTreeNode(pseudoRoot); - - return searchTree; -} - -/** - * @brief converts a tree into a vine - * - * @param root root of tree to convert - * @param size depth of vine (equal to the number of nodes in the tree) - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceTreeToVine(MacTreeNode *root, UINT32 *size) -{ - MacTreeNode *vineTail = root; - MacTreeNode *remainder = vineTail->right; - MacTreeNode *tempPtr; - - *size = 0; - - while (remainder != NULL) - { - if (remainder->left == NULL) - { - /* move tail down one */ - vineTail = remainder; - remainder = remainder->right; - (*size)++; - } - else - { - /* rotate around remainder */ - tempPtr = remainder->left; - remainder->left = tempPtr->right; - tempPtr->right = remainder; - remainder = tempPtr; - vineTail->right = tempPtr; - } - } -} - -/** - * @brief converts a vine into a balanced tree - * - * @param root vine to convert - * @param size depth of vine - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceVineToTree(MacTreeNode *root, UINT32 size) -{ - UINT32 leafCount = size + 1 - (1 << ixEthDBRebalanceLog2Floor(size + 1)); - - ixEthDBRebalanceCompression(root, leafCount); - - size = size - leafCount; - - while (size > 1) - { - ixEthDBRebalanceCompression(root, size / 2); - - size /= 2; - } -} - -/** - * @brief compresses a vine/tree stage into a more balanced vine/tree - * - * @param root root of the tree to compress - * @param count number of "spine" nodes - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRebalanceCompression(MacTreeNode *root, UINT32 count) -{ - MacTreeNode *scanner = root; - MacTreeNode *child; - UINT32 local_index; - - for (local_index = 0 ; local_index < count ; local_index++) - { - child = scanner->right; - scanner->right = child->right; - scanner = scanner->right; - child->right = scanner->left; - scanner->left = child; - } -} - -/** - * @brief computes |_log2(x)_| (a.k.a. floor(log2(x))) - * - * @param x number to compute |_log2(x)_| for - * - * @return |_log2(x)_| - * - * @internal - */ -IX_ETH_DB_PRIVATE -UINT32 ixEthDBRebalanceLog2Floor(UINT32 x) -{ - UINT32 log = 0; - UINT32 val = 1; - - while (val < x) - { - log++; - val <<= 1; - } - - return val == x ? log : log - 1; -} - diff --git a/drivers/net/npe/IxEthDBReports.c b/drivers/net/npe/IxEthDBReports.c deleted file mode 100644 index d74f1215fdc..00000000000 --- a/drivers/net/npe/IxEthDBReports.c +++ /dev/null @@ -1,628 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; -IX_ETH_DB_PRIVATE void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter); -IX_ETH_DB_PRIVATE IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map); - -/** - * @brief displays a port dependency map - * - * @param portID ID of the port - * @param map port map to display - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDependencyPortMapShow(IxEthDBPortId portID, IxEthDBPortMap map) -{ - UINT32 portIndex; - BOOL mapSelf = true, mapNone = true, firstPort = true; - - /* dependency port maps */ - printf("Dependency port map: "); - - /* browse the port map */ - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - if (IS_PORT_INCLUDED(portIndex, map)) - { - mapNone = false; - - if (portIndex != portID) - { - mapSelf = false; - } - - printf("%s%d", firstPort ? "{" : ", ", portIndex); - - firstPort = false; - } - } - - if (mapNone) - { - mapSelf = false; - } - - printf("%s (%s)\n", firstPort ? "" : "}", mapSelf ? "self" : mapNone ? "none" : "group"); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to a port - * - * @param portID ID of the port to display - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(portID, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) -{ - IxEthDBStatus local_result; - HashIterator iterator; - PortInfo *portInfo; - UINT32 recordCount = 0; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - portInfo = &ixEthDBPortInfo[portID]; - - /* display table header */ - printf("Ethernet database records for port ID [%d]\n", portID); - - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf("NPE updates are %s\n\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf("updates disabled (not an NPE)\n\n"); - } - - printf(" MAC address | Age | Type \n"); - printf("___________________________________\n"); - - /* browse database */ - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - recordCount++; - - /* display entry */ - printf(" %02X:%02X:%02X:%02X:%02X:%02X | %5d | %s\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - return IX_ETH_DB_FAIL; - } - } - - /* display number of records */ - printf("\nFound %d records\n", recordCount); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays all the filtering records belonging to all the ports - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @warning deprecated, use @ref ixEthDBFilteringDatabaseShowRecords() - * instead. Calling this function is equivalent to calling - * ixEthDBFilteringDatabaseShowRecords(IX_ETH_DB_ALL_PORTS, IX_ETH_DB_FILTERING_RECORD) - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll() -{ - IxEthDBPortId portIndex; - - printf("\nEthernet learning/filtering database: listing %d ports\n\n", (UINT32) IX_ETH_DB_NUMBER_OF_PORTS); - - for (portIndex = 0 ; portIndex < IX_ETH_DB_NUMBER_OF_PORTS ; portIndex++) - { - ixEthDBFilteringDatabaseShow(portIndex); - - if (portIndex < IX_ETH_DB_NUMBER_OF_PORTS - 1) - { - printf("\n"); - } - } -} - -/** - * @brief displays one record in a format depending on the record filter - * - * @param descriptor pointer to the record - * @param recordFilter format filter - * - * This function will display the fields in a record depending on the - * selected record filter. - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBRecordShow(MacDescriptor *descriptor, IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | %d | %d | %d\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static" : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s | - | - | -\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | %3d | %s \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static" : "dynamic"); - } - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | %02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | ----no gateway----- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address \n"); - printf("__________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header - leave this commented code in place, its purpose is to align the print format with the header - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); */ - - if (descriptor->type == IX_ETH_DB_FILTERING_VLAN_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | VLAN | %2d | %s | %4d | %1d | %1d | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringVlanData.age, - descriptor->recordData.filteringVlanData.staticEntry ? "static " : "dynamic", - IX_ETH_DB_GET_VLAN_ID(descriptor->recordData.filteringVlanData.ieee802_1qTag), - (descriptor->recordData.filteringVlanData.ieee802_1qTag & 0x1000) >> 12, - IX_ETH_DB_GET_QOS_PRIORITY(descriptor->recordData.filteringVlanData.ieee802_1qTag)); - } - else if (descriptor->type == IX_ETH_DB_FILTERING_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | Filter | %2d | %s | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.filteringData.age, - descriptor->recordData.filteringData.staticEntry ? "static " : "dynamic"); - } - else if (descriptor->type == IX_ETH_DB_WIFI_RECORD) - { - if (descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* gateway address present */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>AP | ---- | - | --- | %02X:%02X:%02X:%02X:%02X:%02X\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5], - descriptor->recordData.wifiData.gwMacAddress[0], - descriptor->recordData.wifiData.gwMacAddress[1], - descriptor->recordData.wifiData.gwMacAddress[2], - descriptor->recordData.wifiData.gwMacAddress[3], - descriptor->recordData.wifiData.gwMacAddress[4], - descriptor->recordData.wifiData.gwMacAddress[5]); - } - else - { - /* no gateway */ - printf("%02X:%02X:%02X:%02X:%02X:%02X | WiFi | -- | AP=>ST | ---- | - | --- | -- no gateway -- \n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else if (descriptor->type == IX_ETH_DB_FIREWALL_RECORD) - { - printf("%02X:%02X:%02X:%02X:%02X:%02X | FW | -- | ------- | ---- | - | --- | -----------------\n", - descriptor->macAddress[0], - descriptor->macAddress[1], - descriptor->macAddress[2], - descriptor->macAddress[3], - descriptor->macAddress[4], - descriptor->macAddress[5]); - } - } - else - { - printf("invalid record filter\n"); - } -} - -/** - * @brief displays the status, records and configuration information of a port - * - * @param portID ID of the port - * @param recordFilter record filter to display - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBPortInfoShow(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT32 recordCount = 0; - HashIterator iterator; - IxEthDBStatus local_result; - - /* display port status */ - printf("== Port ID %d ==\n", portID); - - /* display capabilities */ - printf("- Capabilities: "); - - if ((portInfo->featureCapability & IX_ETH_DB_LEARNING) != 0) - { - printf("Learning (%s) ", ((portInfo->featureStatus & IX_ETH_DB_LEARNING) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_VLAN_QOS) != 0) - { - printf("VLAN/QoS (%s) ", ((portInfo->featureStatus & IX_ETH_DB_VLAN_QOS) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - printf("Firewall (%s) ", ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - printf("WiFi (%s) ", ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) ? "on" : "off"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) - { - printf("STP (%s) ", ((portInfo->featureStatus & IX_ETH_DB_SPANNING_TREE_PROTOCOL) != 0) ? "on" : "off"); - } - - printf("\n"); - - /* dependency map */ - ixEthDBDependencyPortMapShow(portID, portInfo->dependencyPortMap); - - /* NPE dynamic updates */ - if (ixEthDBPortDefinitions[portID].type == IX_ETH_NPE) - { - printf(" - NPE dynamic update is %s\n", portInfo->updateMethod.updateEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - dynamic update disabled (not an NPE)\n"); - } - - if ((portInfo->featureCapability & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_WIFI_HEADER_CONVERSION) != 0) - { - /* WiFi header conversion */ - if ((portInfo->frameControlDurationID - + portInfo->bbsid[0] - + portInfo->bbsid[1] - + portInfo->bbsid[2] - + portInfo->bbsid[3] - + portInfo->bbsid[4] - + portInfo->bbsid[5]) == 0) - { - printf(" - WiFi header conversion not configured\n"); - } - else - { - printf(" - WiFi header conversion: BBSID [%02X:%02X:%02X:%02X:%02X:%02X], Frame Control 0x%X, Duration/ID 0x%X\n", - portInfo->bbsid[0], - portInfo->bbsid[1], - portInfo->bbsid[2], - portInfo->bbsid[3], - portInfo->bbsid[4], - portInfo->bbsid[5], - portInfo->frameControlDurationID >> 16, - portInfo->frameControlDurationID & 0xFFFF); - } - } - else - { - printf(" - WiFi header conversion not enabled\n"); - } - } - - /* Firewall */ - if ((portInfo->featureCapability & IX_ETH_DB_FIREWALL) != 0) - { - if ((portInfo->featureStatus & IX_ETH_DB_FIREWALL) != 0) - { - printf(" - Firewall is in %s-list mode\n", portInfo->firewallMode == IX_ETH_DB_FIREWALL_BLACK_LIST ? "black" : "white"); - printf(" - Invalid source MAC address filtering is %s\n", portInfo->srcAddressFilterEnabled ? "enabled" : "disabled"); - } - else - { - printf(" - Firewall not enabled\n"); - } - } - - /* browse database if asked to display records */ - if (recordFilter != IX_ETH_DB_NO_RECORD_TYPE) - { - printf("\n"); - ixEthDBHeaderShow(recordFilter); - - BUSY_RETRY(ixEthDBInitHashIterator(&dbHashtable, &iterator)); - - while (IS_ITERATOR_VALID(&iterator)) - { - MacDescriptor *descriptor = (MacDescriptor *) iterator.node->data; - - if (descriptor->portID == portID && (descriptor->type & recordFilter) != 0) - { - recordCount++; - - /* display entry */ - ixEthDBRecordShow(descriptor, recordFilter); - } - - /* move to the next record */ - BUSY_RETRY_WITH_RESULT(ixEthDBIncrementHashIterator(&dbHashtable, &iterator), local_result); - - /* debug */ - if (local_result == IX_ETH_DB_BUSY) - { - printf("EthDB (API): Error, database browser failed (no access), giving up\n"); - } - } - - printf("\nFound %d records\n\n", recordCount); - } -} - -/** - * @brief displays a record header - * - * @param recordFilter record type filter - * - * This function displays a record header, depending on - * the given record type filter. It is useful when used - * in conjunction with ixEthDBRecordShow which will display - * record fields formatted for the header, provided the same - * record filter is used. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or IX_ETH_DB_INVALID_ARG if the recordFilter - * parameter is invalid or not supported - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBHeaderShow(IxEthDBRecordType recordFilter) -{ - if (recordFilter == IX_ETH_DB_FILTERING_VLAN_RECORD - || recordFilter == (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD)) - { - /* display VLAN record header */ - printf(" MAC address | Age | Type | VLAN ID | CFI | QoS class \n"); - printf("___________________________________________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FILTERING_RECORD) - { - /* display filtering record header */ - printf(" MAC address | Age | Type \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_WIFI_RECORD) - { - /* display WiFi record header */ - printf(" MAC address | GW MAC address \n"); - printf("_______________________________________\n"); - } - else if (recordFilter == IX_ETH_DB_FIREWALL_RECORD) - { - /* display Firewall record header */ - printf(" MAC address \n"); - printf("__________________\n"); - } - else if (recordFilter == IX_ETH_DB_ALL_RECORD_TYPES) - { - /* display composite record header */ - printf(" MAC address | Record | Age| Type | VLAN |CFI| QoS | GW MAC address \n"); - printf("_______________________________________________________________________________\n"); - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief displays database information (records and port information) - * - * @param portID ID of the port to display (or IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record filter (use IX_ETH_DB_NO_RECORD_TYPE to display only - * port information) - * - * Note that this function is documented in the main component header - * file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully or - * an appropriate error code otherwise - * - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) -{ - IxEthDBPortId currentPort; - BOOL showAllPorts = (portID == IX_ETH_DB_ALL_PORTS); - - IX_ETH_DB_CHECK_PORT_ALL(portID); - - printf("\nEthernet learning/filtering database: listing %d port(s)\n\n", showAllPorts ? (UINT32) IX_ETH_DB_NUMBER_OF_PORTS : 1); - - currentPort = showAllPorts ? 0 : portID; - - while (currentPort != IX_ETH_DB_NUMBER_OF_PORTS) - { - /* display port info */ - ixEthDBPortInfoShow(currentPort, recordFilter); - - /* next port */ - currentPort = showAllPorts ? currentPort + 1 : IX_ETH_DB_NUMBER_OF_PORTS; - } - - return IX_ETH_DB_SUCCESS; -} - diff --git a/drivers/net/npe/IxEthDBSearch.c b/drivers/net/npe/IxEthDBSearch.c deleted file mode 100644 index 4fd28da080d..00000000000 --- a/drivers/net/npe/IxEthDBSearch.c +++ /dev/null @@ -1,303 +0,0 @@ -/** - * @file IxEthDBSearch.c - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -extern HashTable dbHashtable; - -/** - * @brief matches two database records based on their MAC addresses - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (ixEthDBAddressCompare((UINT8 *) entry->macAddress, (UINT8 *) reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and VLAN IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (IX_ETH_DB_GET_VLAN_ID(entry->recordData.filteringVlanData.ieee802_1qTag) == - IX_ETH_DB_GET_VLAN_ID(reference->recordData.filteringVlanData.ieee802_1qTag)) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief matches two database records based on their MAC addresses - * and port IDs - * - * @param untypedReference record to match against - * @param untypedEntry record to match - * - * @return true if the match is successful or false otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry) -{ - MacDescriptor *entry = (MacDescriptor *) untypedEntry; - MacDescriptor *reference = (MacDescriptor *) untypedReference; - - /* check accepted record types */ - if ((entry->type & reference->type) == 0) return false; - - return (entry->portID == reference->portID) && - (ixEthDBAddressCompare(entry->macAddress, reference->macAddress) == 0); -} - -/** - * @brief dummy matching function, registered for safety - * - * @param reference record to match against (unused) - * @param entry record to match (unused) - * - * This function is registered in the matching functions - * array on invalid types. Calling it will display an - * error message, indicating an error in the component logic. - * - * @return false - * - * @internal - */ -IX_ETH_DB_PUBLIC -BOOL ixEthDBNullMatch(void *reference, void *entry) -{ - /* display an error message */ - - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, "DB: (Search) The NullMatch function was called, wrong key type?\n", 0, 0, 0, 0, 0, 0); - - - return false; -} - -/** - * @brief registers hash matching methods - * - * @param matchFunctions table of match functions to be populated - * - * This function registers the available record matching functions - * by indexing them on record types into the given function array. - * - * Note that it is compulsory to call this in ixEthDBInit(), - * otherwise hashtable searching and removal will not work - * - * @return number of registered functions - * - * @internal - */ -IX_ETH_DB_PUBLIC -UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions) -{ - UINT32 i; - - /* safety first */ - for ( i = 0 ; i < IX_ETH_DB_MAX_KEY_INDEX + 1 ; i++) - { - matchFunctions[i] = ixEthDBNullMatch; - } - - /* register MAC search method */ - matchFunctions[IX_ETH_DB_MAC_KEY] = ixEthDBAddressRecordMatch; - - /* register MAC/PortID search method */ - matchFunctions[IX_ETH_DB_MAC_PORT_KEY] = ixEthDBPortRecordMatch; - - /* register MAC/VLAN ID search method */ - matchFunctions[IX_ETH_DB_MAC_VLAN_KEY] = ixEthDBVlanRecordMatch; - - return 3; /* three methods */ -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference, &searchResult)); - - return searchResult; -} - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter) -{ - MacDescriptor reference; - IxEthDBStatus result; - - TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER; - - if (macAddress == NULL) - { - return IX_ETH_DB_INVALID_ARG; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - - /* set acceptable record types */ - reference.type = typeFilter; - - result = ixEthDBPeekHashEntry(&dbHashtable, IX_ETH_DB_MAC_KEY, &reference); - - return result; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param portID port ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/port ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.portID = portID; - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_PORT_KEY, &reference, &searchResult)); - - return searchResult; -} - -/** - * @brief search a record in the Ethernet datbase - * - * @param macAddress MAC address to perform the search on - * @param vlanID VLAN ID to perform the search on - * @param typeFilter type of records to consider for matching - * - * @warning if searching is successful an implicit write lock - * to the search result is granted, therefore unlock the - * entry using @ref ixEthDBReleaseHashNode() as soon as possible. - * - * @see ixEthDBReleaseHashNode() - * - * @return the search result, or NULL if a record with the given - * MAC address/VLAN ID combination was not found - * - * @internal - */ -IX_ETH_DB_PUBLIC -HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter) -{ - HashNode *searchResult = NULL; - MacDescriptor reference; - - if (macAddress == NULL) - { - return NULL; - } - - /* fill search fields */ - memcpy(reference.macAddress, macAddress, sizeof (IxEthDBMacAddr)); - reference.recordData.filteringVlanData.ieee802_1qTag = - IX_ETH_DB_SET_VLAN_ID(reference.recordData.filteringVlanData.ieee802_1qTag, vlanID); - - /* set acceptable record types */ - reference.type = typeFilter; - - BUSY_RETRY(ixEthDBSearchHashEntry(&dbHashtable, IX_ETH_DB_MAC_VLAN_KEY, &reference, &searchResult)); - - return searchResult; -} diff --git a/drivers/net/npe/IxEthDBSpanningTree.c b/drivers/net/npe/IxEthDBSpanningTree.c deleted file mode 100644 index e12be0d884a..00000000000 --- a/drivers/net/npe/IxEthDBSpanningTree.c +++ /dev/null @@ -1,83 +0,0 @@ -/** - * @file IxEthDBSpanningTree.c - * - * @brief Implementation of the STP API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxEthDB_p.h" - -/** - * @brief sets the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked true to block the port or false to unblock it - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - ixEthDBPortInfo[portID].stpBlocked = blocked; - - FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the STP blocking state of a port - * - * @param portID ID of the port - * @param blocked address to write the blocked status into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_SPANNING_TREE_PROTOCOL); - - IX_ETH_DB_CHECK_REFERENCE(blocked); - - *blocked = ixEthDBPortInfo[portID].stpBlocked; - - return IX_ETH_DB_SUCCESS; -} diff --git a/drivers/net/npe/IxEthDBUtil.c b/drivers/net/npe/IxEthDBUtil.c deleted file mode 100644 index 40d4470befb..00000000000 --- a/drivers/net/npe/IxEthDBUtil.c +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file ethUtil.c - * - * @brief Utility functions - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -#include "IxFeatureCtrl.h" -#include "IxEthDB_p.h" - -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portID) -{ - /* If not IXP42X A0 stepping, proceed to check for existence of coprocessors */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if ((portID == 0) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 1) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - - if ((portID == 2) && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA_ETH) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; -} - -IX_ETH_DB_PUBLIC -BOOL ixEthDBCheckSingleBitValue(UINT32 value) -{ -#if (CPU != SIMSPARCSOLARIS) && !defined (__wince) - UINT32 shift; - - /* use the count-leading-zeros XScale instruction */ - __asm__ ("clz %0, %1\n" : "=r" (shift) : "r" (value)); - - return ((value << shift) == 0x80000000UL); - -#else - - while (value != 0) - { - if (value == 1) return true; - else if ((value & 1) == 1) return false; - - value >>= 1; - } - - return false; - -#endif -} - -const char *mac2string(const unsigned char *mac) -{ - static char str[19]; - - if (mac == NULL) - { - return NULL; - } - - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); - - return str; -} diff --git a/drivers/net/npe/IxEthDBVlan.c b/drivers/net/npe/IxEthDBVlan.c deleted file mode 100644 index 483e348934c..00000000000 --- a/drivers/net/npe/IxEthDBVlan.c +++ /dev/null @@ -1,1155 +0,0 @@ -/** - * @file IxEthDBVlan.c - * - * @brief Implementation of the VLAN API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB.h" -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex); -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* contants used by various functions as "action" parameter */ -#define ADD_VLAN (0x1) -#define REMOVE_VLAN (0x2) - -/** - * @brief adds or removes a VLAN from a VLAN set - * - * @param vlanID VLAN ID to add or remove - * @param table VLAN set to add into or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @internal - */ -IX_ETH_DB_PRIVATE -void ixEthDBLocalVlanMembershipChange(UINT32 vlanID, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffset; - - /* add/remove VID to membership table */ - setOffset = VLAN_SET_OFFSET(vlanID); /* we need 9 bits to index the 512 byte membership array */ - - if (action == ADD_VLAN) - { - table[setOffset] |= 1 << VLAN_SET_MASK(vlanID); - } - else if (action == REMOVE_VLAN) - { - table[setOffset] &= ~(1 << VLAN_SET_MASK(vlanID)); - } -} - -/** - * @brief updates a set of 8 VLANs in an NPE - * - * @param portID ID of the port - * @param setOffset offset of the 8 VLANs - * - * This function updates the VLAN membership table - * and Transmit Tagging Info table for 8 consecutive - * VLAN IDs indexed by setOffset. - * - * For example, a setOffset of 0 indexes VLAN IDs 0 - * through 7, 1 indexes VLAN IDs 8 through 9 etc. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableEntryUpdate(IxEthDBPortId portID, UINT32 setOffset) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETPORTVLANTABLEENTRY_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - 2 * setOffset, - portInfo->vlanMembership[setOffset], - portInfo->transmitTaggingInfo[setOffset]); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates a VLAN range in an NPE - * - * @param portID ID of the port - * - * This function is similar to @ref ixEthDBVlanTableEntryUpdate - * except that it can update more than one VLAN set (up to - * the entire VLAN membership and TTI tables if the offset is 0 - * and length is sizeof (IxEthDBVlanSet) (512 bytes). - * - * Updating the NPE via this method is slower as it requires - * a memory copy from SDRAM, hence it is recommended that the - * ixEthDBVlanTableEntryUpdate function is used where possible. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBVlanTableRangeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - UINT8 *vlanUpdateZone = (UINT8 *) portInfo->updateMethod.vlanUpdateZone; - IxNpeMhMessage message; - UINT32 setIndex; - IX_STATUS result; - - /* copy membership info and transmit tagging into into exchange area */ - for (setIndex = 0 ; setIndex < sizeof (portInfo->vlanMembership) ; setIndex++) - { - /* membership and TTI data are interleaved */ - vlanUpdateZone[setIndex * 2] = portInfo->vlanMembership[setIndex]; - vlanUpdateZone[setIndex * 2 + 1] = portInfo->transmitTaggingInfo[setIndex]; - } - - IX_OSAL_CACHE_FLUSH(vlanUpdateZone, FULL_VLAN_BYTE_SIZE); - - /* build NPE message */ - FILL_SETPORTVLANTABLERANGE_MSG(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), 0, 0, - IX_OSAL_MMU_VIRT_TO_PHYS(vlanUpdateZone)); - - /* send message */ - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief adds or removes a VLAN from a port's VLAN membership table - * or Transmit Tagging Information table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add or remove - * @param table to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipChange(IxEthDBPortId portID, IxEthDBVlanId vlanID, IxEthDBVlanSet table, UINT32 action) -{ - /* change VLAN in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanID, table, action); - - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, VLAN_SET_OFFSET(vlanID)); -} - -/** - * @brief sets the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag port VLAN tag (802.1Q tag) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* add VLAN ID to local membership table */ - ixEthDBPortVlanMembershipChange(portID, - vlanTag & IX_ETH_DB_802_1Q_VLAN_MASK, - ixEthDBPortInfo[portID].vlanMembership, - ADD_VLAN); - - /* set tag in portInfo */ - ixEthDBPortInfo[portID].vlanTag = vlanTag; - - /* build VLAN_SetDefaultRxVID message */ - FILL_SETDEFAULTRXVID_MSG(message, - IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), - IX_IEEE802_1Q_VLAN_TPID, - vlanTag); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief retrieves the default port VLAN tag (the lower 3 bytes are the PVID) - * - * @param portID ID of the port - * @param vlanTag address to write the port VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - *vlanTag = ixEthDBPortInfo[portID].vlanTag; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the VLAN tag (the lower 3 bytes are the PVID) of a - * database filtering record - * - * @param portID ID of the port - * @param vlanTag VLAN tag (802.1Q tag) - * - * Important: filtering records are automatically converted to - * IX_ETH_DB_FILTERING_VLAN record when added a VLAN tag. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_VLAN_TAG(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_ALL_FILTERING_RECORDS); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* set record type to VLAN if not already set */ - descriptor->type = IX_ETH_DB_FILTERING_VLAN_RECORD; - - /* add vlan tag */ - descriptor->recordData.filteringVlanData.ieee802_1qTag = vlanTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief retrieves the VLAN tag (the lower 3 bytes are the PVID) from a - * database VLAN filtering record - * - * @param portID ID of the port - * @param vlanTag address to write the VLAN tag (802.1Q tag) into - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) -{ - HashNode *searchResult; - MacDescriptor *descriptor; - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_REFERENCE(vlanTag); - - searchResult = ixEthDBSearch(macAddr, IX_ETH_DB_FILTERING_VLAN_RECORD); - - if (searchResult == NULL) - { - return IX_ETH_DB_NO_SUCH_ADDR; - } - - descriptor = (MacDescriptor *) searchResult->data; - - /* get vlan tag */ - *vlanTag = descriptor->recordData.filteringVlanData.ieee802_1qTag; - - /* transaction completed */ - ixEthDBReleaseHashNode(searchResult); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief adds a VLAN to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to add - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanID VLAN ID to remove - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - /* for safety isolate only the VLAN ID in the tag (the lower 12 bits) */ - vlanID = vlanID & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* check we're not asked to remove the default port VID */ - if (vlanID == IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag)) - { - return IX_ETH_DB_NO_PERMISSION; - } - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief adds or removes a VLAN range from a port's - * VLAN membership table or TTI table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * @param table VLAN set to add or remove from - * @param action ADD_VLAN or REMOVE_VLAN - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBPortVlanMembershipRangeChange(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, IxEthDBVlanSet table, UINT32 action) -{ - UINT32 setOffsetMin, setOffsetMax; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMin); - - IX_ETH_DB_CHECK_VLAN_ID(vlanIDMax); - - /* for safety isolate only the VLAN ID in the tags (the lower 12 bits) */ - vlanIDMin = vlanIDMin & IX_ETH_DB_802_1Q_VLAN_MASK; - vlanIDMax = vlanIDMax & IX_ETH_DB_802_1Q_VLAN_MASK; - - /* is this a range? */ - if (vlanIDMax < vlanIDMin) - { - return IX_ETH_DB_INVALID_VLAN; - } - - /* check that we're not specifically asked to remove the default port VID */ - if (action == REMOVE_VLAN && vlanIDMax == vlanIDMin && IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag) == vlanIDMin) - { - return IX_ETH_DB_NO_PERMISSION; - } - - /* compute set offsets */ - setOffsetMin = VLAN_SET_OFFSET(vlanIDMin); - setOffsetMax = VLAN_SET_OFFSET(vlanIDMax); - - /* change VLAN range */ - for (; vlanIDMin <= vlanIDMax ; vlanIDMin++) - { - /* change vlan in local membership table */ - ixEthDBLocalVlanMembershipChange(vlanIDMin, table, action); - } - - /* if the range is within one set (max 8 VLANs in one table byte) we can just update that entry in the NPE */ - if (setOffsetMin == setOffsetMax) - { - /* send updated entry to NPE */ - return ixEthDBVlanTableEntryUpdate(portID, setOffsetMin); - } - else - { - /* update a zone of the membership/transmit tag info table */ - return ixEthDBVlanTableRangeUpdate(portID); - } -} - -/** - * @brief adds a VLAN range to a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, ADD_VLAN); -} - -/** - * @brief removes a VLAN range from a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanIDMin start of the VLAN range - * @param vlanIDMax end of the VLAN range - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].vlanMembership, REMOVE_VLAN); -} - -/** - * @brief sets a port's VLAN membership table or TTI table and - * updates the NPE VLAN configuration - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to set - * @param vlanSet new set contents - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(portVlanTable, vlanSet, sizeof (IxEthDBVlanSet)); - - return ixEthDBVlanTableRangeUpdate(portID); -} - -/** - * @brief retireves a port's VLAN membership table or TTI table - * - * @param portID ID of the port - * @param portVlanTable port VLAN table to retrieve - * @param vlanSet address to - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTableGet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - memcpy(vlanSet, portVlanTable, sizeof (IxEthDBVlanSet)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet new VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the bit corresponding to the PVID just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief retrieves a port's VLAN membership table - * - * @param portID ID of the port - * @param vlanSet location to store the port's VLAN membership table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].vlanMembership, vlanSet); -} - -/** - * @brief enables or disables Egress tagging for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to enable or disable Egress tagging on - * @param enabled true to enable and false to disable tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - return ixEthDBPortVlanMembershipChange(portID, vlanID, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief retrieves the Egress tagging status for one VLAN ID - * - * @param portID ID of the port - * @param vlanID VLAN ID to retrieve the tagging status for - * @param enabled location to store the tagging status - * (true - tagging enabled, false - tagging disabled) - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(enabled); - - IX_ETH_DB_CHECK_VLAN_ID(vlanID); - - *enabled = ((ixEthDBPortInfo[portID].transmitTaggingInfo[VLAN_SET_OFFSET(vlanID)] & (1 << VLAN_SET_MASK(vlanID))) != 0); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables Egress VLAN tagging for a VLAN range - * - * @param portID ID of the port - * @param vlanIDMin start of VLAN range - * @param vlanIDMax end of VLAN range - * @param enabled true to enable or false to disable VLAN tagging - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBPortVlanMembershipRangeChange(portID, vlanIDMin, vlanIDMax, ixEthDBPortInfo[portID].transmitTaggingInfo, enabled? ADD_VLAN : REMOVE_VLAN); -} - -/** - * @brief sets the Egress VLAN tagging table (the Transmit Tagging - * Information table) - * - * @param portID ID of the port - * @param vlanSet new TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IxEthDBVlanId vlanID; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(vlanSet); - - /* set the PVID bit just in case */ - vlanID = IX_ETH_DB_GET_VLAN_ID(ixEthDBPortInfo[portID].vlanTag); - vlanSet[VLAN_SET_OFFSET(vlanID)] |= 1 << VLAN_SET_MASK(vlanID); - - return ixEthDBPortVlanTableSet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief retrieves the Egress VLAN tagging table (the Transmit - * Tagging Information table) - * - * @param portID ID of the port - * @param vlanSet location to store the port's TTI table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - return ixEthDBVlanTableGet(portID, ixEthDBPortInfo[portID].transmitTaggingInfo, vlanSet); -} - -/** - * @brief sends the NPE the updated frame filter and default - * Ingress tagging - * - * @param portID ID of the port - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBIngressVlanModeUpdate(IxEthDBPortId portID) -{ - PortInfo *portInfo = &ixEthDBPortInfo[portID]; - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETRXTAGMODE_MSG(message, portID, portInfo->npeFrameFilter, portInfo->npeTaggingAction); - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the default Ingress tagging behavior - * - * @param portID ID of the port - * @param taggingAction default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) -{ - PortInfo *portInfo; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - portInfo = &ixEthDBPortInfo[portID]; - - if (taggingAction == IX_ETH_DB_PASS_THROUGH) - { - portInfo->npeTaggingAction = 0x00; - } - else if (taggingAction == IX_ETH_DB_ADD_TAG) - { - portInfo->npeTaggingAction = 0x02; - } - else if (taggingAction == IX_ETH_DB_REMOVE_TAG) - { - portInfo->npeTaggingAction = 0x01; - } - else - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo->taggingAction = taggingAction; - - return ixEthDBIngressVlanModeUpdate(portID); -} - -/** - * @brief retrieves the default Ingress tagging behavior of a port - * - * @param portID ID of the port - * @param taggingAction location to save the default tagging behavior - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(taggingAction); - - *taggingAction = ixEthDBPortInfo[portID].taggingAction; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets the Ingress acceptable frame type filter - * - * @param portID ID of the port - * @param frameFilter acceptable frame type filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) -{ - PortInfo *portInfo; - IxEthDBStatus result = IX_ETH_DB_SUCCESS; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check parameter range - the ORed value of the valid values is 0x7 - a value having extra bits is invalid */ - if ((frameFilter | 0x7) != 0x7 || frameFilter == 0) - { - return IX_ETH_DB_INVALID_ARG; - } - - portInfo = &ixEthDBPortInfo[portID]; - - portInfo->frameFilter = frameFilter; - portInfo->npeFrameFilter = 0; /* allow all by default */ - - /* if accepting priority tagged but not all VLAN tagged - set the membership table to contain only VLAN ID 0 - hence remove vlans 1-4094 and add VLAN ID 0 */ - if (((frameFilter & IX_ETH_DB_PRIORITY_TAGGED_FRAMES) != 0) - && ((frameFilter & IX_ETH_DB_VLAN_TAGGED_FRAMES) == 0)) - { - result = ixEthDBPortVlanMembershipRangeChange(portID, - 1, IX_ETH_DB_802_1Q_MAX_VLAN_ID, portInfo->vlanMembership, REMOVE_VLAN); - - if (result == IX_ETH_DB_SUCCESS) - { - ixEthDBLocalVlanMembershipChange(0, portInfo->vlanMembership, ADD_VLAN); - result = ixEthDBVlanTableRangeUpdate(portID); - } - } - - /* untagged only? */ - if (frameFilter == IX_ETH_DB_UNTAGGED_FRAMES) - { - portInfo->npeFrameFilter = 0x01; - } - - /* tagged only? */ - if ((frameFilter & IX_ETH_DB_UNTAGGED_FRAMES) == 0) - { - portInfo->npeFrameFilter = 0x02; - } - - if (result == IX_ETH_DB_SUCCESS) - { - result = ixEthDBIngressVlanModeUpdate(portID); - } - - return result; -} - -/** - * @brief retrieves the acceptable frame type filter for a port - * - * @param portID ID of the port - * @param frameFilter location to store the frame filter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(frameFilter); - - *frameFilter = ixEthDBPortInfo[portID].frameFilter; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sends an NPE the updated configuration related - * to one QoS priority (associated traffic class and AQM mapping) - * - * @param portID ID of the port - * @param classIndex QoS priority (traffic class index) - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUpdateTrafficClass(IxEthDBPortId portID, UINT32 classIndex) -{ - IxNpeMhMessage message; - IX_STATUS result; - - UINT32 trafficClass = ixEthDBPortInfo[portID].priorityTable[classIndex]; - UINT32 aqmQueue = ixEthDBPortInfo[portID].ixEthDBTrafficClassAQMAssignments[trafficClass]; - - FILL_SETRXQOSENTRY(message, IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(portID), classIndex, trafficClass, aqmQueue); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the priority mapping table - * - * @param portID ID of the port - * @param priorityTable new priority mapping table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - UINT32 classIndex; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - /* check range */ - if (priorityTable[classIndex] >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - } - - /* set new traffic classes */ - for (classIndex = 0 ; classIndex < IX_IEEE802_1Q_QOS_PRIORITY_COUNT ; classIndex++) - { - ixEthDBPortInfo[portID].priorityTable[classIndex] = priorityTable[classIndex]; - - if (ixEthDBUpdateTrafficClass(portID, classIndex) != IX_ETH_DB_SUCCESS) - { - return IX_ETH_DB_FAIL; - } - } - - return IX_ETH_DB_SUCCESS; - } - -/** - * @brief retrieves a port's priority mapping table - * - * @param portID ID of the port - * @param priorityTable location to store the priority table - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(priorityTable); - - memcpy(priorityTable, ixEthDBPortInfo[portID].priorityTable, sizeof (IxEthDBPriorityTable)); - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief sets one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - /* check ranges for userPriority and trafficClass */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT || trafficClass >= ixEthDBPortInfo[portID].ixEthDBTrafficClassCount) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - ixEthDBPortInfo[portID].priorityTable[userPriority] = trafficClass; - - return ixEthDBUpdateTrafficClass(portID, userPriority); -} - -/** - * @brief retrieves one QoS priority => traffic class mapping - * - * @param portID ID of the port - * @param userPriority QoS (user) priority - * @param trafficClass location to store the associated traffic class - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - IX_ETH_DB_CHECK_REFERENCE(trafficClass); - - /* check userPriority range */ - if (userPriority >= IX_IEEE802_1Q_QOS_PRIORITY_COUNT) - { - return IX_ETH_DB_INVALID_PRIORITY; - } - - *trafficClass = ixEthDBPortInfo[portID].priorityTable[userPriority]; - - return IX_ETH_DB_SUCCESS; -} - -/** - * @brief enables or disables the source port extraction - * from the VLAN TPID field - * - * @param portID ID of the port - * @param enable true to enable or false to disable - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_VLAN_QOS); - - FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} diff --git a/drivers/net/npe/IxEthDBWiFi.c b/drivers/net/npe/IxEthDBWiFi.c deleted file mode 100644 index 44edd47f2f5..00000000000 --- a/drivers/net/npe/IxEthDBWiFi.c +++ /dev/null @@ -1,456 +0,0 @@ -/** - * @file IxEthDBAPI.c - * - * @brief Implementation of the public API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxEthDB_p.h" - -/* forward prototypes */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations); - -/** - * @brief sets the BBSID value for the WiFi header conversion feature - * - * @param portID ID of the port - * @param bbsid pointer to the 6-byte BBSID value - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) -{ - IxNpeMhMessage message; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - IX_ETH_DB_CHECK_REFERENCE(bbsid); - - memcpy(ixEthDBPortInfo[portID].bbsid, bbsid, sizeof (IxEthDBMacAddr)); - - FILL_SETBBSID_MSG(message, portID, bbsid); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief updates the Frame Control and Duration/ID WiFi header - * conversion parameters in an NPE - * - * @param portID ID of the port - * - * This function will send a message to the NPE updating the - * frame conversion parameters for 802.3 => 802.11 header conversion. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or IX_ETH_DB_FAIL otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiFrameControlDurationIDUpdate(IxEthDBPortId portID) -{ - IxNpeMhMessage message; - IX_STATUS result; - - FILL_SETFRAMECONTROLDURATIONID(message, portID, ixEthDBPortInfo[portID].frameControlDurationID); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - return result; -} - -/** - * @brief sets the Duration/ID WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Duration/ID parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF0000) | durationID; - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief sets the Frame Control WiFi frame header conversion parameter - * - * @param portID ID of the port - * @param durationID 16-bit value containing the new Frame Control parameter - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) -{ - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - ixEthDBPortInfo[portID].frameControlDurationID = (ixEthDBPortInfo[portID].frameControlDurationID & 0xFFFF) | (frameControl << 16); - - return ixEthDBWiFiFrameControlDurationIDUpdate(portID); -} - -/** - * @brief removes a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to remove - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - return ixEthDBRemove(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway (or - * NULL if this is a station record) - * - * This function adds a record of type AP_TO_AP (gateway is not NULL) - * or AP_TO_STA (gateway is NULL) in the main database as a - * WiFi header conversion record. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - * - * @internal - */ -IX_ETH_DB_PRIVATE -IxEthDBStatus ixEthDBWiFiEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - MacDescriptor recordTemplate; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_REFERENCE(macAddr); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - memcpy(recordTemplate.macAddress, macAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.type = IX_ETH_DB_WIFI_RECORD; - recordTemplate.portID = portID; - - if (gatewayMacAddr != NULL) - { - memcpy(recordTemplate.recordData.wifiData.gwMacAddress, gatewayMacAddr, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_AP; - } - else - { - memset(recordTemplate.recordData.wifiData.gwMacAddress, 0, sizeof (IxEthDBMacAddr)); - - recordTemplate.recordData.wifiData.type = IX_ETH_DB_WIFI_AP_TO_STA; - } - - return ixEthDBAdd(&recordTemplate, NULL); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * @param gatewayMacAddr address of the gateway - * - * This function adds a record of type AP_TO_AP - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) -{ - IX_ETH_DB_CHECK_REFERENCE(gatewayMacAddr); - - return ixEthDBWiFiEntryAdd(portID, macAddr, gatewayMacAddr); -} - -/** - * @brief adds a WiFi header conversion record - * - * @param portID ID of the port - * @param macAddr MAC address of the record to add - * - * This function adds a record of type AP_TO_STA - * in the main database as a WiFi header conversion record. - * - * This is simply a wrapper over @ref ixEthDBWiFiEntryAdd(). - * - * Note that this function is documented in the main - * component header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed - * successfully or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) -{ - return ixEthDBWiFiEntryAdd(portID, macAddr, NULL); -} - -/** - * @brief selects a set of gateways from a tree of - * WiFi header conversion records - * - * @param stations binary tree containing pointers to WiFi header - * conversion records - * - * This function browses through the input binary tree, identifies - * records of type AP_TO_AP, clones these records and appends them - * to a vine (a single right-branch binary tree) which is returned - * as result. A maximum of MAX_GW_SIZE entries containing gateways - * will be cloned from the original tree. - * - * @return vine (linear binary tree) containing record - * clones of AP_TO_AP type, which have a gateway field - * - * @internal - */ -IX_ETH_DB_PUBLIC -MacTreeNode *ixEthDBGatewaySelect(MacTreeNode *stations) -{ - MacTreeNodeStack *stack; - MacTreeNode *gateways, *insertionPlace; - UINT32 gwIndex = 1; /* skip the empty root */ - - if (stations == NULL) - { - return NULL; - } - - stack = ixOsalCacheDmaMalloc(sizeof (MacTreeNodeStack)); - - if (stack == NULL) - { - ERROR_LOG("DB: (WiFi) failed to allocate the node stack for gateway tree linearization, out of memory?\n"); - return NULL; - } - - /* initialize root node */ - gateways = insertionPlace = NULL; - - /* start browsing the station tree */ - NODE_STACK_INIT(stack); - - /* initialize stack by pushing the tree root at offset 0 */ - NODE_STACK_PUSH(stack, stations, 0); - - while (NODE_STACK_NONEMPTY(stack)) - { - MacTreeNode *node; - UINT32 offset; - - NODE_STACK_POP(stack, node, offset); - - /* we can store maximum 31 (32 total, 1 empty root) entries in the gateway tree */ - if (offset > (MAX_GW_SIZE - 1)) break; - - /* check if this record has a gateway address */ - if (node->descriptor != NULL && node->descriptor->recordData.wifiData.type == IX_ETH_DB_WIFI_AP_TO_AP) - { - /* found a record, create an insertion place */ - if (insertionPlace != NULL) - { - insertionPlace->right = ixEthDBAllocMacTreeNode(); - insertionPlace = insertionPlace->right; - } - else - { - gateways = ixEthDBAllocMacTreeNode(); - insertionPlace = gateways; - } - - if (insertionPlace == NULL) - { - /* no nodes left, bail out with what we have */ - ixOsalCacheDmaFree(stack); - return gateways; - } - - /* clone the original record for the gateway tree */ - insertionPlace->descriptor = ixEthDBCloneMacDescriptor(node->descriptor); - - /* insert and update the offset in the original record */ - node->descriptor->recordData.wifiData.gwAddressIndex = gwIndex++; - } - - /* browse the tree */ - if (node->left != NULL) - { - NODE_STACK_PUSH(stack, node->left, LEFT_CHILD_OFFSET(offset)); - } - - if (node->right != NULL) - { - NODE_STACK_PUSH(stack, node->right, RIGHT_CHILD_OFFSET(offset)); - } - } - - ixOsalCacheDmaFree(stack); - return gateways; -} - -/** - * @brief downloads the WiFi header conversion table to an NPE - * - * @param portID ID of the port - * - * This function prepares the WiFi header conversion tables and - * downloads them to the specified NPE port. - * - * The header conversion tables consist in the main table of - * addresses and the secondary table of gateways. AP_TO_AP records - * from the first table contain index fields into the second table - * for gateway selection. - * - * Note that this function is documented in the main component - * header file, IxEthDB.h. - * - * @return IX_ETH_DB_SUCCESS if the operation completed successfully - * or an appropriate error message otherwise - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) -{ - IxEthDBPortMap query; - MacTreeNode *stations = NULL, *gateways = NULL, *gateway = NULL; - IxNpeMhMessage message; - PortInfo *portInfo; - IX_STATUS result; - - IX_ETH_DB_CHECK_PORT(portID); - - IX_ETH_DB_CHECK_SINGLE_NPE(portID); - - IX_ETH_DB_CHECK_FEATURE(portID, IX_ETH_DB_WIFI_HEADER_CONVERSION); - - portInfo = &ixEthDBPortInfo[portID]; - - SET_DEPENDENCY_MAP(query, portID); - - ixEthDBUpdateLock(); - - stations = ixEthDBQuery(NULL, query, IX_ETH_DB_WIFI_RECORD, MAX_ELT_SIZE); - gateways = ixEthDBGatewaySelect(stations); - - /* clean up gw area */ - memset((void *) portInfo->updateMethod.npeGwUpdateZone, FULL_GW_BYTE_SIZE, 0); - - /* write all gateways */ - gateway = gateways; - - while (gateway != NULL) - { - ixEthDBNPEGatewayNodeWrite((void *) (((UINT32) portInfo->updateMethod.npeGwUpdateZone) - + gateway->descriptor->recordData.wifiData.gwAddressIndex * ELT_ENTRY_SIZE), - gateway); - - gateway = gateway->right; - } - - /* free the gateway tree */ - if (gateways != NULL) - { - ixEthDBFreeMacTreeNode(gateways); - } - - FILL_SETAPMACTABLE_MSG(message, - IX_OSAL_MMU_VIRT_TO_PHYS(portInfo->updateMethod.npeGwUpdateZone)); - - IX_ETHDB_SEND_NPE_MSG(IX_ETH_DB_PORT_ID_TO_NPE(portID), message, result); - - if (result == IX_SUCCESS) - { - /* update the main tree (the stations tree) */ - portInfo->updateMethod.searchTree = stations; - - result = ixEthDBNPEUpdateHandler(portID, IX_ETH_DB_WIFI_RECORD); - } - - ixEthDBUpdateUnlock(); - - return result; -} diff --git a/drivers/net/npe/IxEthMii.c b/drivers/net/npe/IxEthMii.c deleted file mode 100644 index 27f3548ce0b..00000000000 --- a/drivers/net/npe/IxEthMii.c +++ /dev/null @@ -1,473 +0,0 @@ -/** - * @file IxEthMii.c - * - * @author Intel Corporation - * @date - * - * @brief MII control functions - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include "IxEthAcc.h" -#include "IxEthMii_p.h" - -#ifdef __wince -#include "IxOsPrintf.h" -#endif - -/* Array to store the phy IDs of the discovered phys */ -PRIVATE UINT32 ixEthMiiPhyId[IXP425_ETH_ACC_MII_MAX_ADDR]; - -/********************************************************* - * - * Scan for PHYs on the MII bus. This function returns - * an array of booleans, one for each PHY address. - * If a PHY is found at a particular address, the - * corresponding entry in the array is set to true. - * - */ - -PUBLIC IX_STATUS -ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) -{ - UINT32 i; - UINT16 regval, regvalId1, regvalId2; - - /*Search for PHYs on the MII*/ - /*Search for existant phys on the MDIO bus*/ - - if ((phyPresent == NULL) || - (maxPhyCount > IXP425_ETH_ACC_MII_MAX_ADDR)) - { - return IX_FAIL; - } - - /* fill the array */ - for(i=0; - i 0 && i= IX_ETH_MII_RESET_DELAY_MS) - { - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_FAIL; - } - - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else if (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_KS8995_PHY_ID) - { - /* reset bit is reserved, just reset the control register */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } - else - { - /* unknown PHY, set the control register reset bit, - * wait 2 s. and clear the control register. - */ - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_RESET); - - ixOsalSleep (IX_ETH_MII_RESET_DELAY_MS); - - ixEthAccMiiWriteRtn(phyAddr, IX_ETH_MII_CTRL_REG, - IX_ETH_MII_CR_NORM_EN); - return IX_SUCCESS; - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - return IX_FAIL; -} - -/***************************************************************** - * - * Link state query functions - */ - -PUBLIC IX_STATUS -ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) -{ - UINT16 ctrlRegval, statRegval, regval, regval4, regval5; - - /* check the parameters */ - if ((linkUp == NULL) || - (speed100 == NULL) || - (fullDuplex == NULL) || - (autoneg == NULL)) - { - return IX_FAIL; - } - - *linkUp = false; - *speed100 = false; - *fullDuplex = false; - *autoneg = false; - - if ((phyAddr < IXP425_ETH_ACC_MII_MAX_ADDR) && - (ixEthMiiPhyId[phyAddr] != IX_ETH_MII_INVALID_PHY_ID)) - { - if ((ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT971_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT972_PHY_ID) || - (ixEthMiiPhyId[phyAddr] == IX_ETH_MII_LXT9785_PHY_ID) - ) - { - /* --------------------------------------------------*/ - /* Retrieve information from PHY specific register */ - /* --------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_STAT2_REG, - ®val) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - *linkUp = ((regval & IX_ETH_MII_SR2_LINK) != 0); - *speed100 = ((regval & IX_ETH_MII_SR2_100) != 0); - *fullDuplex = ((regval & IX_ETH_MII_SR2_FD) != 0); - *autoneg = ((regval & IX_ETH_MII_SR2_AUTO) != 0); - return IX_SUCCESS; - } /* end of if(ixEthMiiPhyId) */ - else - { - /* ----------------------------------------------------*/ - /* Retrieve information from status and ctrl registers */ - /* ----------------------------------------------------*/ - if (ixEthAccMiiReadRtn(phyAddr, - IX_ETH_MII_CTRL_REG, - &ctrlRegval) != IX_ETH_ACC_SUCCESS) - { - return IX_FAIL; - } - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &statRegval); - - *linkUp = ((statRegval & IX_ETH_MII_SR_LINK_STATUS) != 0); - if (*linkUp) - { - *autoneg = ((ctrlRegval & IX_ETH_MII_CR_AUTO_EN) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_SEL) != 0) && - ((statRegval & IX_ETH_MII_SR_AUTO_NEG) != 0); - - if (*autoneg) - { - /* mask the current stat values with the capabilities */ - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_ADS_REG, ®val4); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_AN_PRTN_REG, ®val5); - /* merge the flags from the 3 registers */ - regval = (statRegval & ((regval4 & regval5) << 6)); - /* initialise from status register values */ - if ((regval & IX_ETH_MII_SR_TX_FULL_DPX) != 0) - { - /* 100 Base X full dplx */ - *speed100 = true; - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_TX_HALF_DPX) != 0) - { - /* 100 Base X half dplx */ - *speed100 = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_FULL_DPX) != 0) - { - /* 10 mb full dplx */ - *fullDuplex = true; - return IX_SUCCESS; - } - if ((regval & IX_ETH_MII_SR_10T_HALF_DPX) != 0) - { - /* 10 mb half dplx */ - return IX_SUCCESS; - } - } /* end of if(autoneg) */ - else - { - /* autonegotiate not complete, return setup parameters */ - *speed100 = ((ctrlRegval & IX_ETH_MII_CR_100) != 0); - *fullDuplex = ((ctrlRegval & IX_ETH_MII_CR_FDX) != 0); - } - } /* end of if(linkUp) */ - } /* end of if-else(ixEthMiiPhyId) */ - } /* end of if(phyAddr) */ - else - { - return IX_FAIL; - } /* end of if-else(phyAddr) */ - return IX_SUCCESS; -} - -/***************************************************************** - * - * Link state display functions - */ - -PUBLIC IX_STATUS -ixEthMiiPhyShow (UINT32 phyAddr) -{ - BOOL linkUp, speed100, fullDuplex, autoneg; - UINT16 cregval; - UINT16 sregval; - - - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_STAT_REG, &sregval); - ixEthAccMiiReadRtn(phyAddr, IX_ETH_MII_CTRL_REG, &cregval); - - /* get link information */ - if (ixEthMiiLinkStatus(phyAddr, - &linkUp, - &speed100, - &fullDuplex, - &autoneg) != IX_ETH_ACC_SUCCESS) - { - printf("PHY Status unknown\n"); - return IX_FAIL; - } - - printf("PHY ID [phyAddr]: %8.8x\n",ixEthMiiPhyId[phyAddr]); - printf( " Status reg: %4.4x\n",sregval); - printf( " control reg: %4.4x\n",cregval); - /* display link information */ - printf("PHY Status:\n"); - printf(" Link is %s\n", - (linkUp ? "Up" : "Down")); - if((sregval & IX_ETH_MII_SR_REMOTE_FAULT) != 0) - { - printf(" Remote fault detected\n"); - } - printf(" Auto Negotiation %s\n", - (autoneg ? "Completed" : "Not Completed")); - - printf("PHY Configuration:\n"); - printf(" Speed %sMb/s\n", - (speed100 ? "100" : "10")); - printf(" %s Duplex\n", - (fullDuplex ? "Full" : "Half")); - printf(" Auto Negotiation %s\n", - (autoneg ? "Enabled" : "Disabled")); - return IX_SUCCESS; -} - diff --git a/drivers/net/npe/IxFeatureCtrl.c b/drivers/net/npe/IxFeatureCtrl.c deleted file mode 100644 index 0b6807d9d7d..00000000000 --- a/drivers/net/npe/IxFeatureCtrl.c +++ /dev/null @@ -1,398 +0,0 @@ -/** - * @file IxFeatureCtrl.c - * - * @author Intel Corporation - * @date 29-Jan-2003 - * - * @brief Feature Control Public API Implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -#include "IxOsal.h" -#include "IxVersionId.h" -#include "IxFeatureCtrl.h" - -/* Macro to read from the Feature Control Register */ -#define IX_FEATURE_CTRL_READ(result) \ -do { \ -ixFeatureCtrlExpMap(); \ -(result) = IX_OSAL_READ_LONG(ixFeatureCtrlRegister); \ -} while (0) - -/* Macro to write to the Feature Control Register */ -#define IX_FEATURE_CTRL_WRITE(value) \ -do { \ -ixFeatureCtrlExpMap(); \ -IX_OSAL_WRITE_LONG(ixFeatureCtrlRegister, (value)); \ -} while (0) - -/* - * This is the offset of the feature register relative to the base of the - * Expansion Bus Controller MMR. - */ -#define IX_FEATURE_CTRL_REG_OFFSET (0x00000028) - - -/* Boolean to mark the fact that the EXP_CONFIG address space was mapped */ -PRIVATE BOOL ixFeatureCtrlExpCfgRegionMapped = false; - -/* Pointer holding the virtual address of the Feature Control Register */ -PRIVATE VUINT32 *ixFeatureCtrlRegister = NULL; - -/* Place holder to store the software configuration */ -PRIVATE BOOL swConfiguration[IX_FEATURECTRL_SWCONFIG_MAX]; - -/* Flag to control swConfiguration[] is initialized once */ -PRIVATE BOOL swConfigurationFlag = false ; - -/* Array containing component mask values */ -#ifdef __ixp42X -UINT32 componentMask[IX_FEATURECTRL_MAX_COMPONENTS] = { - (0x1<> IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET) - & IX_FEATURE_CTRL_DEVICE_TYPE_MASK); -} /* End function ixFeatureCtrlDeviceRead */ - - -/** - * Function definition: ixFeatureCtrlSwConfigurationCheck - */ -IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return IX_FEATURE_CTRL_SWCONFIG_DISABLED; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Check and return software configuration */ - return ((swConfiguration[(UINT32)swConfigType] == true) ? IX_FEATURE_CTRL_SWCONFIG_ENABLED: IX_FEATURE_CTRL_SWCONFIG_DISABLED); -} - -/** - * Function definition: ixFeatureCtrlSwConfigurationWrite - */ -void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) -{ - if (swConfigType >= IX_FEATURECTRL_SWCONFIG_MAX) - { - ixOsalLog(IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDOUT, - "FeatureCtrl: Invalid software configuraiton input.\n", - 0, 0, 0, 0, 0, 0); - - return; - } - - /* The function will only initialize once. */ - ixFeatureCtrlSwConfigurationInit(); - - /* Write software configuration */ - swConfiguration[(UINT32)swConfigType]=enabled ; -} - -/** - * Function definition: ixFeatureCtrlIxp400SwVersionShow - */ -void -ixFeatureCtrlIxp400SwVersionShow (void) -{ - printf ("\nIXP400 Software Release %s %s\n\n", IX_VERSION_ID, IX_VERSION_INTERNAL_ID); - -} - -/** - * Function definition: ixFeatureCtrlSoftwareBuildGet - */ -IxFeatureCtrlBuildDevice -ixFeatureCtrlSoftwareBuildGet (void) -{ - #ifdef __ixp42X - return IX_FEATURE_CTRL_SW_BUILD_IXP42X; - #else - return IX_FEATURE_CTRL_SW_BUILD_IXP46X; - #endif -} diff --git a/drivers/net/npe/IxNpeDl.c b/drivers/net/npe/IxNpeDl.c deleted file mode 100644 index 0e5c428323a..00000000000 --- a/drivers/net/npe/IxNpeDl.c +++ /dev/null @@ -1,916 +0,0 @@ -/** - * @file IxNpeDl.c - * - * @author Intel Corporation - * @date 08 January 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Downloader component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required - */ - -/* - * Put the user defined include files required - */ -#include "IxNpeDl.h" -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" -/* - * #defines used in this file - */ - #define IMAGEID_MAJOR_NUMBER_DEFAULT 0 - #define IMAGEID_MINOR_NUMBER_DEFAULT 0 - -/* - * Typedefs whose scope is limited to this file. - */ -typedef struct -{ - BOOL validImage; - IxNpeDlImageId imageId; -} IxNpeDlNpeState; - -/* module statistics counters */ -typedef struct -{ - UINT32 attemptedDownloads; - UINT32 successfulDownloads; - UINT32 criticalFailDownloads; -} IxNpeDlStats; - -/* - * Variable declarations global to this file only. Externs are followed - * by static variables. - */ -static IxNpeDlNpeState ixNpeDlNpeState[IX_NPEDL_NPEID_MAX] = -{ - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}}, - {false, {IX_NPEDL_NPEID_MAX, 0, 0, 0}} -}; - -static IxNpeDlStats ixNpeDlStats; - -/* - * Software guard to prevent NPE from being started multiple times. - */ -static BOOL ixNpeDlNpeStarted[IX_NPEDL_NPEID_MAX] ={false, false, false} ; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, UINT32 imageId); - -/* - * Function definition: ixNpeDlImageDownload - */ -PUBLIC IX_STATUS -ixNpeDlImageDownload (IxNpeDlImageId *imageIdPtr, - BOOL verify) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = imageIdPtr->npeId; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageDownload\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageDownload - invalid parameter\n"); - } - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if(IX_FEATURE_CTRL_SILICON_TYPE_B0) */ /*End of Silicon Type Check*/ - - /* stop and reset the NPE */ - if (IX_SUCCESS != ixNpeDlNpeStopAndReset (npeId)) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return IX_FAIL; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageLocate (imageIdPtr, &imageCodePtr, - &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, - verify); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].imageId = *imageIdPtr; - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageDownload : status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesCountGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesCountGet (UINT32 *numImagesPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesCountGet\n"); - - /* Check input parameters */ - if (numImagesPtr == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesCountGet - " - "invalid parameter\n"); - } - else - { - /* - * Use ImageMgr module to get no. of images listed in Image Library Header. - * If NULL is passed as imageListPtr parameter to following function, - * it will only fill number of images into numImagesPtr - */ - status = ixNpeDlImageMgrImageListExtract (NULL, numImagesPtr); - } /* end of if-else(numImagesPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesCountGet : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlAvailableImagesListGet - */ -PUBLIC IX_STATUS -ixNpeDlAvailableImagesListGet (IxNpeDlImageId *imageIdListPtr, - UINT32 *listSizePtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlAvailableImagesListGet\n"); - - /* Check input parameters */ - if ((imageIdListPtr == NULL) || (listSizePtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlAvailableImagesListGet - " - "invalid parameter\n"); - } - else - { - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrImageListExtract (imageIdListPtr, - listSizePtr); - } /* end of if-else(imageIdListPtr) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlAvailableImagesListGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLoadedImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageGet (IxNpeDlNpeId npeId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLoadedImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0) || (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageGet - invalid parameter\n"); - } - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - if (ixNpeDlNpeState[npeId].validImage) - { - /* use npeId to get imageId from list of currently loaded - images */ - *imageIdPtr = ixNpeDlNpeState[npeId].imageId; - } - else - { - status = IX_FAIL; - } /* end of if-else(ixNpeDlNpeState) */ - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLoadedImageGet : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlLatestImageGet - */ -PUBLIC IX_STATUS -ixNpeDlLatestImageGet ( - IxNpeDlNpeId npeId, - IxNpeDlFunctionalityId functionalityId, - IxNpeDlImageId *imageIdPtr) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlLatestImageGet\n"); - - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || - (npeId < 0) || - (imageIdPtr == NULL)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlLatestImageGet - " - "invalid parameter\n"); - } /* end of if(npeId) */ - else - { - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEB && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - - if (npeId == IX_NPEDL_NPEID_NPEC && - (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC) == - IX_FEATURE_CTRL_COMPONENT_DISABLED)) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified does" - " not exist\n"); - return IX_SUCCESS; - } /* end of if(npeId) */ - } /* end of if not IXP42x-A0 silicon */ - - imageIdPtr->npeId = npeId; - imageIdPtr->functionalityId = functionalityId; - imageIdPtr->major = IMAGEID_MAJOR_NUMBER_DEFAULT; - imageIdPtr->minor = IMAGEID_MINOR_NUMBER_DEFAULT; - /* Call ImageMgr to get list of images listed in Image Library Header */ - status = ixNpeDlImageMgrLatestImageExtract(imageIdPtr); - } /* end of if-else(npeId) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlLatestImageGet : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeStopAndReset - */ -PUBLIC IX_STATUS -ixNpeDlNpeStopAndReset (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeStopAndReset\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeStopAndReset - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeStopAndReset - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - if (status == IX_SUCCESS) - { - /* call NpeMgr function to reset the NPE */ - status = ixNpeDlNpeMgrNpeReset (npeId); - } - } /* end of if(status) */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeStopAndReset : status = %d\n", status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStart (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStart\n"); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStart - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStart - invalid Npe ID\n"); - return IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42x-A0 Silicon */ - - if (true == ixNpeDlNpeStarted[npeId]) - { - /* NPE has been started. */ - return IX_SUCCESS ; - } - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* call NpeMgr function to start the NPE */ - status = ixNpeDlNpeMgrNpeStart (npeId); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has started */ - ixNpeDlNpeStarted[npeId] = true ; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStart : status = %d\n", - status); - - return status; -} - -/* - * Function definition: ixNpeDlNpeExecutionStop - */ -PUBLIC IX_STATUS -ixNpeDlNpeExecutionStop (IxNpeDlNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeExecutionStop\n"); - - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - /* - * Check whether NPE is present - */ - if (IX_NPEDL_NPEID_NPEA == npeId) - { - /* Check whether NPE A is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE A does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEA does not present.\n"); - return IX_SUCCESS; - } - } /* end of if(IX_NPEDL_NPEID_NPEA) */ - else if (IX_NPEDL_NPEID_NPEB == npeId) - { - /* Check whether NPE B is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE B does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEB does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEB) */ - else if (IX_NPEDL_NPEID_NPEC == npeId) - { - /* Check whether NPE C is present */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - /* NPE C does not present */ - IX_NPEDL_WARNING_REPORT ("ixNpeDlNpeExecutionStop - Warning:NPEC does not present.\n"); - return IX_SUCCESS; - } - } /* end of elseif(IX_NPEDL_NPEID_NPEC) */ - else - { - /* Invalid NPE ID */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeExecutionStop - invalid Npe ID\n"); - status = IX_NPEDL_PARAM_ERR; - } /* end of if-else(IX_NPEDL_NPEID_NPEC) */ - } /* end of if not IXP42X-AO Silicon */ - - if (status == IX_SUCCESS) - { - /* call NpeMgr function to stop the NPE */ - status = ixNpeDlNpeMgrNpeStop (npeId); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeExecutionStop : status = %d\n", - status); - - if (IX_SUCCESS == status) - { - /* Indicate NPE has been stopped */ - ixNpeDlNpeStarted[npeId] = false ; - } - - return status; -} - -/* - * Function definition: ixNpeDlUnload - */ -PUBLIC IX_STATUS -ixNpeDlUnload (void) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlUnload\n"); - - status = ixNpeDlNpeMgrUninit(); - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlUnload : status = %d\n", - status); - return status; -} - -/* - * Function definition: ixNpeDlStatsShow - */ -PUBLIC void -ixNpeDlStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlStatsShow:\n" - "\tDownloads Attempted by user: %u\n" - "\tSuccessful Downloads: %u\n" - "\tFailed Downloads (due to Critical Error): %u\n\n", - ixNpeDlStats.attemptedDownloads, - ixNpeDlStats.successfulDownloads, - ixNpeDlStats.criticalFailDownloads, - 0,0,0); - - ixNpeDlImageMgrStatsShow (); - ixNpeDlNpeMgrStatsShow (); -} - -/* - * Function definition: ixNpeDlStatsReset - */ -PUBLIC void -ixNpeDlStatsReset (void) -{ - ixNpeDlStats.attemptedDownloads = 0; - ixNpeDlStats.successfulDownloads = 0; - ixNpeDlStats.criticalFailDownloads = 0; - - ixNpeDlImageMgrStatsReset (); - ixNpeDlNpeMgrStatsReset (); -} - -/* - * Function definition: ixNpeDlNpeInitAndStartInternal - */ -PRIVATE IX_STATUS -ixNpeDlNpeInitAndStartInternal (UINT32 *imageLibrary, - UINT32 imageId) -{ - UINT32 imageSize; - UINT32 *imageCodePtr = NULL; - IX_STATUS status; - IxNpeDlNpeId npeId = IX_NPEDL_NPEID_FROM_IMAGEID_GET(imageId); - IxFeatureCtrlDeviceId deviceId = IX_NPEDL_DEVICEID_FROM_IMAGEID_GET(imageId); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeInitAndStartInternal\n"); - - ixNpeDlStats.attemptedDownloads++; - - /* Check input parameter device correctness */ - if ((deviceId >= IX_FEATURE_CTRL_DEVICE_TYPE_MAX) || - (deviceId < IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } /* End valid device id checking */ - - /* Check input parameters */ - else if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "invalid parameter\n"); - } - - else - { - /* Ensure initialisation has been completed */ - ixNpeDlNpeMgrInit(); - - /* Checking if image being loaded is meant for device that is running. - * Image is forward compatible. i.e Image built for IXP42X should run - * on IXP46X but not vice versa.*/ - if (deviceId > (ixFeatureCtrlDeviceRead() & IX_FEATURE_CTRL_DEVICE_TYPE_MASK)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeInitAndStartInternal - " - "Device type mismatch. NPE Image not " - "meant for device in use \n"); - return IX_NPEDL_DEVICE_ERR; - }/* if statement - matching image device and current device */ - - /* If not IXP42X A0 stepping, proceed to check for existence of npe's */ - if ((IX_FEATURE_CTRL_SILICON_TYPE_A0 != - (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK)) - || (IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X != ixFeatureCtrlDeviceRead ())) - { - if (npeId == IX_NPEDL_NPEID_NPEA) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEA) == - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE A component you specified does" - " not exist\n"); - return IX_SUCCESS; - } - } /* end of if(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEB) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEB)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE B component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - else if (npeId == IX_NPEDL_NPEID_NPEC) - { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_NPEC)== - IX_FEATURE_CTRL_COMPONENT_DISABLED) - { - IX_NPEDL_WARNING_REPORT("Warning: the NPE C component you specified" - " does not exist\n"); - return IX_SUCCESS; - } - } /* end of elseif(npeId) */ - } /* end of if not IXP42X-A0 Silicon */ - - /* stop and reset the NPE */ - status = ixNpeDlNpeStopAndReset (npeId); - if (IX_SUCCESS != status) - { - IX_NPEDL_ERROR_REPORT ("Failed to stop and reset NPE\n"); - return status; - } - - /* Locate image */ - status = ixNpeDlImageMgrImageFind (imageLibrary, imageId, - &imageCodePtr, &imageSize); - if (IX_SUCCESS == status) - { - /* - * If download was successful, store image Id in list of - * currently loaded images. If a critical error occured - * during download, record that the NPE has an invalid image - */ - status = ixNpeDlNpeMgrImageLoad (npeId, imageCodePtr, true); - if (IX_SUCCESS == status) - { - ixNpeDlNpeState[npeId].validImage = true; - ixNpeDlStats.successfulDownloads++; - - status = ixNpeDlNpeExecutionStart (npeId); - } - else if ((status == IX_NPEDL_CRITICAL_NPE_ERR) || - (status == IX_NPEDL_CRITICAL_MICROCODE_ERR)) - { - ixNpeDlNpeState[npeId].validImage = false; - ixNpeDlStats.criticalFailDownloads++; - } - - /* NOTE - The following section of code is here to support - * a deprecated function ixNpeDlLoadedImageGet(). When that - * function is removed from the API, this code should be revised. - */ - ixNpeDlNpeState[npeId].imageId.npeId = npeId; - ixNpeDlNpeState[npeId].imageId.functionalityId = - IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.major = - IX_NPEDL_MAJOR_FROM_IMAGEID_GET(imageId); - ixNpeDlNpeState[npeId].imageId.minor = - IX_NPEDL_MINOR_FROM_IMAGEID_GET(imageId); - } /* end of if(IX_SUCCESS) */ /* condition: image located successfully in microcode image */ - } /* end of if-else(npeId-deviceId) */ /* condition: parameter checks ok */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeInitAndStartInternal : " - "status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlCustomImageNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlCustomImageNpeInitAndStart (UINT32 *imageLibrary, - UINT32 imageId) -{ - IX_STATUS status; - - if (imageLibrary == NULL) - { - status = IX_NPEDL_PARAM_ERR; - IX_NPEDL_ERROR_REPORT ("ixNpeDlCustomImageNpeInitAndStart " - "- invalid parameter\n"); - } - else - { - status = ixNpeDlNpeInitAndStartInternal (imageLibrary, imageId); - } /* end of if-else(imageLibrary) */ - - return status; -} - -/* - * Function definition: ixNpeDlNpeInitAndStart - */ -PUBLIC IX_STATUS -ixNpeDlNpeInitAndStart (UINT32 imageId) -{ - return ixNpeDlNpeInitAndStartInternal (NULL, imageId); -} - -/* - * Function definition: ixNpeDlLoadedImageFunctionalityGet - */ -PUBLIC IX_STATUS -ixNpeDlLoadedImageFunctionalityGet (IxNpeDlNpeId npeId, - UINT8 *functionalityId) -{ - /* Check input parameters */ - if ((npeId >= IX_NPEDL_NPEID_MAX) || (npeId < 0)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - if (functionalityId == NULL) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlLoadedImageFunctionalityGet " - "- invalid parameter\n"); - return IX_NPEDL_PARAM_ERR; - } - - if (ixNpeDlNpeState[npeId].validImage) - { - *functionalityId = ixNpeDlNpeState[npeId].imageId.functionalityId; - return IX_SUCCESS; - } - else - { - return IX_FAIL; - } -} diff --git a/drivers/net/npe/IxNpeDlImageMgr.c b/drivers/net/npe/IxNpeDlImageMgr.c deleted file mode 100644 index 52f73d7ad8b..00000000000 --- a/drivers/net/npe/IxNpeDlImageMgr.c +++ /dev/null @@ -1,663 +0,0 @@ -/** - * @file IxNpeDlImageMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader ImageMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#include "IxOsal.h" - -/* - * Put the user defined include files required. - */ -#include "IxNpeDlImageMgr_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * define the flag which toggles the firmare inclusion - */ -#define IX_NPE_MICROCODE_FIRMWARE_INCLUDED 1 -#include "IxNpeMicrocode.h" - -/* - * Indicates the start of an NPE Image, in new NPE Image Library format. - * 2 consecutive occurances indicates the end of the NPE Image Library - */ -#define NPE_IMAGE_MARKER 0xfeedf00d - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 size; - UINT32 offset; - UINT32 id; -} IxNpeDlImageMgrImageEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef union -{ - IxNpeDlImageMgrImageEntry image; - UINT32 eohMarker; -} IxNpeDlImageMgrHeaderEntry; - -/* - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * TO BE DEPRECATED IN A FUTURE RELEASE - */ -typedef struct -{ - UINT32 signature; - /* 1st entry in the header (there may be more than one) */ - IxNpeDlImageMgrHeaderEntry entry[1]; -} IxNpeDlImageMgrImageLibraryHeader; - - -/* - * NPE Image Header definition, used in new NPE Image Library format - */ -typedef struct -{ - UINT32 marker; - UINT32 id; - UINT32 size; -} IxNpeDlImageMgrImageHeader; - -/* module statistics counters */ -typedef struct -{ - UINT32 invalidSignature; - UINT32 imageIdListOverflow; - UINT32 imageIdNotFound; -} IxNpeDlImageMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlImageMgrStats ixNpeDlImageMgrStats; - -static UINT32* getIxNpeMicroCodeImageLibrary(void) -{ - char *s; - - if ((s = getenv("npe_ucode")) != NULL) - return (UINT32*) simple_strtoul(s, NULL, 16); - else - return NULL; -} - -/* - * static function prototypes. - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary); - -PRIVATE void -ixNpeDlImageMgrImageIdFormat (UINT32 rawImageId, IxNpeDlImageId *imageId); - -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB); - -#if 0 -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy (UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize); - -/* - * Function definition: ixNpeDlImageMgrMicrocodeImageLibraryOverride - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrMicrocodeImageLibraryOverride ( - UINT32 *clientImageLibrary) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrMicrocodeImageLibraryOverride\n"); - - if (ixNpeDlImageMgrSignatureCheck (clientImageLibrary)) - { - IxNpeMicroCodeImageLibrary = clientImageLibrary; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrMicrocodeImageLibraryOverride: " - "Client-supplied image has invalid signature\n"); - status = IX_FAIL; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrMicrocodeImageLibraryOverride: status = %d\n", - status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageListExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageListExtract ( - IxNpeDlImageId *imageListPtr, - UINT32 *numImages) -{ - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_SUCCESS; - UINT32 imageCount = 0; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageListExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - /* - * if the image list container from calling function has capacity, - * add the image id to the list - */ - if ((imageListPtr != NULL) && (imageCount < *numImages)) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - imageListPtr[imageCount] = formattedImageId; - } - /* imageCount reflects no. of image entries in image library header */ - imageCount++; - } - - /* - * if image list container from calling function was too small to - * contain all image ids in the header, set return status to FAIL - */ - if ((imageListPtr != NULL) && (imageCount > *numImages)) - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "number of Ids found exceeds list capacity\n"); - ixNpeDlImageMgrStats.imageIdListOverflow++; - } - /* return number of image ids found in image library header */ - *numImages = imageCount; - } - else - { - status = IX_FAIL; - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageListExtract: " - "invalid signature in image\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageListExtract: status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlImageMgrImageLocate - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrImageLocate ( - IxNpeDlImageId *imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageLocate\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* if a match for imageId is found in the image library header... */ - if (ixNpeDlImageMgrImageIdCompare (imageId, &formattedImageId)) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - UINT32 *tmp=getIxNpeMicroCodeImageLibrary(); - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &tmp[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - break; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageLocate: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageLocate: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrLatestImageExtract - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -IX_STATUS -ixNpeDlImageMgrLatestImageExtract (IxNpeDlImageId *imageId) -{ - UINT32 imageCount = 0; - UINT32 rawImageId; - IxNpeDlImageId formattedImageId; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrLatestImageExtract\n"); - - header = (IxNpeDlImageMgrImageLibraryHeader *) getIxNpeMicroCodeImageLibrary(); - - if (ixNpeDlImageMgrSignatureCheck (getIxNpeMicroCodeImageLibrary())) - { - /* for each image entry in the image library header ... */ - while (header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) - { - rawImageId = header->entry[imageCount].image.id; - ixNpeDlImageMgrImageIdFormat (rawImageId, &formattedImageId); - /* - * if a match for the npe Id and functionality Id of the imageId is - * found in the image library header... - */ - if(ixNpeDlImageMgrNpeFunctionIdCompare(imageId, &formattedImageId)) - { - if(imageId->major <= formattedImageId.major) - { - if(imageId->minor < formattedImageId.minor) - { - imageId->minor = formattedImageId.minor; - } - imageId->major = formattedImageId.major; - } - status = IX_SUCCESS; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageExtract: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrLatestImageGet: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrLatestImageGet: status = %d\n", status); - return status; -} - -/* - * Function definition: ixNpeDlImageMgrSignatureCheck - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrSignatureCheck (UINT32 *microCodeImageLibrary) -{ - IxNpeDlImageMgrImageLibraryHeader *header = - (IxNpeDlImageMgrImageLibraryHeader *) microCodeImageLibrary; - BOOL result = true; - - if (!header || header->signature != IX_NPEDL_IMAGEMGR_SIGNATURE) - { - result = false; - ixNpeDlImageMgrStats.invalidSignature++; - } - - return result; -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdFormat - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE void -ixNpeDlImageMgrImageIdFormat ( - UINT32 rawImageId, - IxNpeDlImageId *imageId) -{ - imageId->npeId = (rawImageId >> - IX_NPEDL_IMAGEID_NPEID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->functionalityId = (rawImageId >> - IX_NPEDL_IMAGEID_FUNCTIONID_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->major = (rawImageId >> - IX_NPEDL_IMAGEID_MAJOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - imageId->minor = (rawImageId >> - IX_NPEDL_IMAGEID_MINOR_OFFSET) & - IX_NPEDL_NPEIMAGE_FIELD_MASK; - -} - - -/* - * Function definition: ixNpeDlImageMgrImageIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrImageIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId) && - (imageIdA->major == imageIdB->major) && - (imageIdA->minor == imageIdB->minor)) - { - return true; - } - else - { - return false; - } -} - -/* - * Function definition: ixNpeDlImageMgrNpeFunctionIdCompare - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE BOOL -ixNpeDlImageMgrNpeFunctionIdCompare ( - IxNpeDlImageId *imageIdA, - IxNpeDlImageId *imageIdB) -{ - if ((imageIdA->npeId == imageIdB->npeId) && - (imageIdA->functionalityId == imageIdB->functionalityId)) - { - return true; - } - else - { - return false; - } -} - - -/* - * Function definition: ixNpeDlImageMgrStatsShow - */ -void -ixNpeDlImageMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlImageMgrStatsShow:\n" - "\tInvalid Image Signatures: %u\n" - "\tImage Id List capacity too small: %u\n" - "\tImage Id not found: %u\n\n", - ixNpeDlImageMgrStats.invalidSignature, - ixNpeDlImageMgrStats.imageIdListOverflow, - ixNpeDlImageMgrStats.imageIdNotFound, - 0,0,0); -} - - -/* - * Function definition: ixNpeDlImageMgrStatsReset - */ -void -ixNpeDlImageMgrStatsReset (void) -{ - ixNpeDlImageMgrStats.invalidSignature = 0; - ixNpeDlImageMgrStats.imageIdListOverflow = 0; - ixNpeDlImageMgrStats.imageIdNotFound = 0; -} - - -#if 0 -/* - * Function definition: ixNpeDlImageMgrImageFind_legacy - * - * FOR BACKWARD-COMPATIBILITY WITH OLD NPE IMAGE LIBRARY FORMAT - * AND/OR LEGACY API FUNCTIONS. TO BE DEPRECATED IN A FUTURE RELEASE - */ -PRIVATE IX_STATUS -ixNpeDlImageMgrImageFind_legacy ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - UINT32 imageOffset; - /* used to index image entries in image library header */ - UINT32 imageCount = 0; - IX_STATUS status = IX_FAIL; - IxNpeDlImageMgrImageLibraryHeader *header; - BOOL imageFound = false; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlImageMgrImageFind\n"); - - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { - imageLibrary = IxNpeMicroCodeImageLibrary; - } - - if (ixNpeDlImageMgrSignatureCheck (imageLibrary)) - { - header = (IxNpeDlImageMgrImageLibraryHeader *) imageLibrary; - - /* for each image entry in the image library header ... */ - while ((header->entry[imageCount].eohMarker != - IX_NPEDL_IMAGEMGR_END_OF_HEADER) && !(imageFound)) - { - /* if a match for imageId is found in the image library header... */ - if (imageId == header->entry[imageCount].image.id) - { - /* - * get pointer to the image in the image library using offset from - * 1st word in image library - */ - imageOffset = header->entry[imageCount].image.offset; - *imagePtr = &imageLibrary[imageOffset]; - /* get the image size */ - *imageSize = header->entry[imageCount].image.size; - status = IX_SUCCESS; - imageFound = true; - } - imageCount++; - } - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - } - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "invalid signature in image library\n"); - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlImageMgrImageFind: status = %d\n", status); - return status; -} -#endif - -/* - * Function definition: ixNpeDlImageMgrImageFind - */ -IX_STATUS -ixNpeDlImageMgrImageFind ( - UINT32 *imageLibrary, - UINT32 imageId, - UINT32 **imagePtr, - UINT32 *imageSize) -{ - IxNpeDlImageMgrImageHeader *image; - UINT32 offset = 0; - - /* If user didn't specify a library to use, use the default - * one from IxNpeMicrocode.h - */ - if (imageLibrary == NULL) - { -#ifdef IX_NPEDL_READ_MICROCODE_FROM_FILE - if (ixNpeMicrocode_binaryArray == NULL) - { - printk (KERN_ERR "ixp400.o: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } - else - { - imageLibrary = ixNpeMicrocode_binaryArray; - } -#else - imageLibrary = getIxNpeMicroCodeImageLibrary(); - if (imageLibrary == NULL) - { - printf ("npe: ERROR, no Microcode found in memory\n"); - return IX_FAIL; - } -#endif /* IX_NPEDL_READ_MICROCODE_FROM_FILE */ - } - -#if 0 - /* For backward's compatibility with previous image format */ - if (ixNpeDlImageMgrSignatureCheck(imageLibrary)) - { - return ixNpeDlImageMgrImageFind_legacy(imageLibrary, - imageId, - imagePtr, - imageSize); - } -#endif - - while (*(imageLibrary+offset) == NPE_IMAGE_MARKER) - { - image = (IxNpeDlImageMgrImageHeader *)(imageLibrary+offset); - offset += sizeof(IxNpeDlImageMgrImageHeader)/sizeof(UINT32); - - if (image->id == imageId) - { - *imagePtr = imageLibrary + offset; - *imageSize = image->size; - return IX_SUCCESS; - } - /* 2 consecutive NPE_IMAGE_MARKER's indicates end of library */ - else if (image->id == NPE_IMAGE_MARKER) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "imageId not found in image library header\n"); - ixNpeDlImageMgrStats.imageIdNotFound++; - /* reached end of library, image not found */ - return IX_FAIL; - } - offset += image->size; - } - - /* If we get here, our image library may be corrupted */ - IX_NPEDL_ERROR_REPORT ("ixNpeDlImageMgrImageFind: " - "image library format may be invalid or corrupted\n"); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxNpeDlNpeMgr.c b/drivers/net/npe/IxNpeDlNpeMgr.c deleted file mode 100644 index 8d94dfac3d3..00000000000 --- a/drivers/net/npe/IxNpeDlNpeMgr.c +++ /dev/null @@ -1,907 +0,0 @@ -/** - * @file IxNpeDlNpeMgr.c - * - * @author Intel Corporation - * @date 09 January 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgr_p.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" -#include "IxFeatureCtrl.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPEDL_BYTES_PER_WORD 4 - -/* used to read download map from version in microcode image */ -#define IX_NPEDL_BLOCK_TYPE_INSTRUCTION 0x00000000 -#define IX_NPEDL_BLOCK_TYPE_DATA 0x00000001 -#define IX_NPEDL_BLOCK_TYPE_STATE 0x00000002 -#define IX_NPEDL_END_OF_DOWNLOAD_MAP 0x0000000F - -/* - * masks used to extract address info from State information context - * register addresses as read from microcode image - */ -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F -#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0 - -/* LSB offset of Context Number field in State-Info Context Address */ -#define IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM 4 - -/* size (in words) of single State Information entry (ctxt reg address|data) */ -#define IX_NPEDL_STATE_INFO_ENTRY_SIZE 2 - - - #define IX_NPEDL_RESET_NPE_PARITY 0x0800 - #define IX_NPEDL_PARITY_BIT_MASK 0x3F00FFFF - #define IX_NPEDL_CONFIG_CTRL_REG_MASK 0x3F3FFFFF - - -/* - * Typedefs whose scope is limited to this file. - */ - -typedef struct -{ - UINT32 type; - UINT32 offset; -} IxNpeDlNpeMgrDownloadMapBlockEntry; - -typedef union -{ - IxNpeDlNpeMgrDownloadMapBlockEntry block; - UINT32 eodmMarker; -} IxNpeDlNpeMgrDownloadMapEntry; - -typedef struct -{ - /* 1st entry in the download map (there may be more than one) */ - IxNpeDlNpeMgrDownloadMapEntry entry[1]; -} IxNpeDlNpeMgrDownloadMap; - - -/* used to access an instruction or data block in a microcode image */ -typedef struct -{ - UINT32 npeMemAddress; - UINT32 size; - UINT32 data[1]; -} IxNpeDlNpeMgrCodeBlock; - -/* used to access each Context Reg entry state-information block */ -typedef struct -{ - UINT32 addressInfo; - UINT32 value; -} IxNpeDlNpeMgrStateInfoCtxtRegEntry; - -/* used to access a state-information block in a microcode image */ -typedef struct -{ - UINT32 size; - IxNpeDlNpeMgrStateInfoCtxtRegEntry ctxtRegEntry[1]; -} IxNpeDlNpeMgrStateInfoBlock; - -/* used to store some useful NPE information for easy access */ -typedef struct -{ - UINT32 baseAddress; - UINT32 insMemSize; - UINT32 dataMemSize; -} IxNpeDlNpeInfo; - -/* used to distinguish instruction and data memory operations */ -typedef enum -{ - IX_NPEDL_MEM_TYPE_INSTRUCTION = 0, - IX_NPEDL_MEM_TYPE_DATA -} IxNpeDlNpeMemType; - -/* used to hold a reset value for a particular ECS register */ -typedef struct -{ - UINT32 regAddr; - UINT32 regResetVal; -} IxNpeDlEcsRegResetValue; - -/* prototype of function to write either Instruction or Data memory */ -typedef IX_STATUS (*IxNpeDlNpeMgrMemWrite) (UINT32 npeBaseAddress, - UINT32 npeMemAddress, - UINT32 npeMemData, - BOOL verify); - -/* module statistics counters */ -typedef struct -{ - UINT32 instructionBlocksLoaded; - UINT32 dataBlocksLoaded; - UINT32 stateInfoBlocksLoaded; - UINT32 criticalNpeErrors; - UINT32 criticalMicrocodeErrors; - UINT32 npeStarts; - UINT32 npeStops; - UINT32 npeResets; -} IxNpeDlNpeMgrStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ -static IxNpeDlNpeInfo ixNpeDlNpeInfo[] = -{ - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEA, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEB, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB - }, - { - 0, - IX_NPEDL_INS_MEMSIZE_WORDS_NPEC, - IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC - } -}; - -/* contains Reset values for Context Store Registers */ -static UINT32 ixNpeDlCtxtRegResetValues[] = -{ - IX_NPEDL_CTXT_REG_RESET_STEVT, - IX_NPEDL_CTXT_REG_RESET_STARTPC, - IX_NPEDL_CTXT_REG_RESET_REGMAP, - IX_NPEDL_CTXT_REG_RESET_CINDEX, -}; - -/* contains Reset values for Context Store Registers */ -static IxNpeDlEcsRegResetValue ixNpeDlEcsRegResetValues[] = -{ - {IX_NPEDL_ECS_BG_CTXT_REG_0, IX_NPEDL_ECS_BG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_1, IX_NPEDL_ECS_BG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_BG_CTXT_REG_2, IX_NPEDL_ECS_BG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_0, IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_1, IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_1_CTXT_REG_2, IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_0, IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_1, IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_PRI_2_CTXT_REG_2, IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_0, IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_1, IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET}, - {IX_NPEDL_ECS_DBG_CTXT_REG_2, IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET}, - {IX_NPEDL_ECS_INSTRUCT_REG, IX_NPEDL_ECS_INSTRUCT_REG_RESET} -}; - -static IxNpeDlNpeMgrStats ixNpeDlNpeMgrStats; - -/* Set when NPE register memory has been mapped */ -static BOOL ixNpeDlMemInitialised = false; - - -/* - * static function prototypes. - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad (IxNpeDlNpeId npeId, UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *codeBlockPtr, - BOOL verify, IxNpeDlNpeMemType npeMemType); -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad (UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *codeBlockPtr, - BOOL verify); -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck (UINT32 npeBaseAddress, UINT32 regOffset, - UINT32 expectedBitsSet); - -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId); - -/* - * Function definition: ixNpeDlNpeMgrBaseAddressGet - */ -PRIVATE UINT32 -ixNpeDlNpeMgrBaseAddressGet (IxNpeDlNpeId npeId) -{ - IX_OSAL_ASSERT (ixNpeDlMemInitialised); - return ixNpeDlNpeInfo[npeId].baseAddress; -} - - -/* - * Function definition: ixNpeDlNpeMgrInit - */ -void -ixNpeDlNpeMgrInit (void) -{ - /* Only map the memory once */ - if (!ixNpeDlMemInitialised) - { - UINT32 virtAddr; - - /* map the register memory for NPE-A */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEA, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = virtAddr; - - /* map the register memory for NPE-B */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEB, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = virtAddr; - - /* map the register memory for NPE-C */ - virtAddr = (UINT32) IX_OSAL_MEM_MAP (IX_NPEDL_NPEBASEADDRESS_NPEC, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT(virtAddr); - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = virtAddr; - - ixNpeDlMemInitialised = true; - } -} - - -/* - * Function definition: ixNpeDlNpeMgrUninit - */ -IX_STATUS -ixNpeDlNpeMgrUninit (void) -{ - if (!ixNpeDlMemInitialised) - { - return IX_FAIL; - } - - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress); - IX_OSAL_MEM_UNMAP (ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress); - - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEA].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEB].baseAddress = 0; - ixNpeDlNpeInfo[IX_NPEDL_NPEID_NPEC].baseAddress = 0; - - ixNpeDlMemInitialised = false; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeDlNpeMgrImageLoad - */ -IX_STATUS -ixNpeDlNpeMgrImageLoad ( - IxNpeDlNpeId npeId, - UINT32 *imageCodePtr, - BOOL verify) -{ - UINT32 npeBaseAddress; - IxNpeDlNpeMgrDownloadMap *downloadMap; - UINT32 *blockPtr; - UINT32 mapIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrImageLoad\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* check execution status of NPE to verify NPE Stop was successful */ - if (!ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageDownload - " - "NPE was not stopped before download\n"); - status = IX_FAIL; - } - else - { - /* - * Read Download Map, checking each block type and calling - * appropriate function to perform download - */ - downloadMap = (IxNpeDlNpeMgrDownloadMap *) imageCodePtr; - while ((downloadMap->entry[mapIndex].eodmMarker != - IX_NPEDL_END_OF_DOWNLOAD_MAP) - && (status == IX_SUCCESS)) - { - /* calculate pointer to block to be downloaded */ - blockPtr = imageCodePtr + - downloadMap->entry[mapIndex].block.offset; - - switch (downloadMap->entry[mapIndex].block.type) - { - case IX_NPEDL_BLOCK_TYPE_INSTRUCTION: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, - IX_NPEDL_MEM_TYPE_INSTRUCTION); - break; - case IX_NPEDL_BLOCK_TYPE_DATA: - status = ixNpeDlNpeMgrMemLoad (npeId, npeBaseAddress, - (IxNpeDlNpeMgrCodeBlock *)blockPtr, - verify, IX_NPEDL_MEM_TYPE_DATA); - break; - case IX_NPEDL_BLOCK_TYPE_STATE: - status = ixNpeDlNpeMgrStateInfoLoad (npeBaseAddress, - (IxNpeDlNpeMgrStateInfoBlock *) blockPtr, - verify); - break; - default: - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrImageLoad: " - "unknown block type in download map\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; - } - mapIndex++; - }/* loop: for each entry in download map, while status == SUCCESS */ - }/* condition: NPE stopped before attempting download */ - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrImageLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrMemLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrMemLoad ( - IxNpeDlNpeId npeId, - UINT32 npeBaseAddress, - IxNpeDlNpeMgrCodeBlock *blockPtr, - BOOL verify, - IxNpeDlNpeMemType npeMemType) -{ - UINT32 npeMemAddress; - UINT32 blockSize; - UINT32 memSize = 0; - IxNpeDlNpeMgrMemWrite memWriteFunc = NULL; - UINT32 localIndex = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrMemLoad\n"); - - /* - * select NPE EXCTL reg read/write commands depending on memory - * type (instruction/data) to be accessed - */ - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - memSize = ixNpeDlNpeInfo[npeId].insMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrInsMemWrite; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - memSize = ixNpeDlNpeInfo[npeId].dataMemSize; - memWriteFunc = (IxNpeDlNpeMgrMemWrite) ixNpeDlNpeMgrDataMemWrite; - } - - /* - * NPE memory is loaded contiguously from each block, so only address - * of 1st word in block is needed - */ - npeMemAddress = blockPtr->npeMemAddress; - /* number of words of instruction/data microcode in block to download */ - blockSize = blockPtr->size; - if ((npeMemAddress + blockSize) > memSize) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "Block size too big for NPE memory\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - } - else - { - for (localIndex = 0; localIndex < blockSize; localIndex++) - { - status = memWriteFunc (npeBaseAddress, npeMemAddress, - blockPtr->data[localIndex], verify); - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrMemLoad: " - "write to NPE memory failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - /* increment target (word)address in NPE memory */ - npeMemAddress++; - } - }/* condition: block size will fit in NPE memory */ - - if (status == IX_SUCCESS) - { - if (npeMemType == IX_NPEDL_MEM_TYPE_INSTRUCTION) - { - ixNpeDlNpeMgrStats.instructionBlocksLoaded++; - } - else if (npeMemType == IX_NPEDL_MEM_TYPE_DATA) - { - ixNpeDlNpeMgrStats.dataBlocksLoaded++; - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrMemLoad : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrStateInfoLoad - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrStateInfoLoad ( - UINT32 npeBaseAddress, - IxNpeDlNpeMgrStateInfoBlock *blockPtr, - BOOL verify) -{ - UINT32 blockSize; - UINT32 ctxtRegAddrInfo; - UINT32 ctxtRegVal; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 i; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrStateInfoLoad\n"); - - /* block size contains number of words of state-info in block */ - blockSize = blockPtr->size; - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* for each state-info context register entry in block */ - for (i = 0; i < (blockSize/IX_NPEDL_STATE_INFO_ENTRY_SIZE); i++) - { - /* each state-info entry is 2 words (address, value) in length */ - ctxtRegAddrInfo = (blockPtr->ctxtRegEntry[i]).addressInfo; - ctxtRegVal = (blockPtr->ctxtRegEntry[i]).value; - - ctxtReg = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG); - ctxtNum = (ctxtRegAddrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >> - IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM; - - /* error-check Context Register No. and Context Number values */ - /* NOTE that there is no STEVT register for Context 0 */ - if ((ctxtReg < 0) || - (ctxtReg >= IX_NPEDL_CTXT_REG_MAX) || - (ctxtNum > IX_NPEDL_CTXT_NUM_MAX) || - ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "invalid Context Register Address\n"); - status = IX_NPEDL_CRITICAL_MICROCODE_ERR; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors++; - break; /* abort download */ - } - - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, ctxtReg, - ctxtRegVal, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrStateInfoLoad: " - "write of state-info to NPE failed\n"); - status = IX_NPEDL_CRITICAL_NPE_ERR; - ixNpeDlNpeMgrStats.criticalNpeErrors++; - break; /* abort download */ - } - }/* loop: for each context reg entry in State Info block */ - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - if (status == IX_SUCCESS) - { - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrStateInfoLoad : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeReset - */ -IX_STATUS -ixNpeDlNpeMgrNpeReset ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IxNpeDlCtxtRegNum ctxtReg; /* identifies Context Store reg (0-3) */ - UINT32 ctxtNum; /* identifies Context number (0-16) */ - UINT32 regAddr; - UINT32 regVal; - UINT32 localIndex; - UINT32 indexMax; - IX_STATUS status = IX_SUCCESS; - IxFeatureCtrlReg unitFuseReg; - UINT32 ixNpeConfigCtrlRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeReset\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* pre-store the NPE Config Control Register Value */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, &ixNpeConfigCtrlRegVal); - - ixNpeConfigCtrlRegVal |= 0x3F000000; - - /* disable the parity interrupt */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, (ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK)); - - ixNpeDlNpeMgrDebugInstructionPreExec (npeBaseAddress); - - /* - * clear the FIFOs - */ - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_WFIFO, - IX_NPEDL_MASK_WFIFO_VALID)) - { - /* read from the Watch-point FIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WFIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_OFNE)) - { - /* read from the outFIFO until empty */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_FIFO, - ®Val); - } - - while (ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_STAT, - IX_NPEDL_MASK_STAT_IFNE)) - { - /* - * step execution of the NPE intruction to read inFIFO using - * the Debug Executing Context stack - */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RD_FIFO, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - } - - /* - * Reset the mailbox reg - */ - /* ...from XScale side */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_MBST, - IX_NPEDL_REG_RESET_MBST); - /* ...from NPE side */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, - IX_NPEDL_INSTR_RESET_MBOX, 0, 0); - - if (IX_SUCCESS != status) - { - return status; - } - - /* - * Reset the physical registers in the NPE register file: - * Note: no need to save/restore REGMAP for Context 0 here - * since all Context Store regs are reset in subsequent code - */ - for (regAddr = 0; - (regAddr < IX_NPEDL_TOTAL_NUM_PHYS_REG) && (status != IX_FAIL); - regAddr++) - { - /* for each physical register in the NPE reg file, write 0 : */ - status = ixNpeDlNpeMgrPhysicalRegWrite (npeBaseAddress, regAddr, - 0, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - - - /* - * Reset the context store: - */ - for (ctxtNum = IX_NPEDL_CTXT_NUM_MIN; - ctxtNum <= IX_NPEDL_CTXT_NUM_MAX; ctxtNum++) - { - /* set each context's Context Store registers to reset values: */ - for (ctxtReg = 0; ctxtReg < IX_NPEDL_CTXT_REG_MAX; ctxtReg++) - { - /* NOTE that there is no STEVT register for Context 0 */ - if (!((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STEVT))) - { - regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; - status = ixNpeDlNpeMgrCtxtRegWrite (npeBaseAddress, ctxtNum, - ctxtReg, regVal, true); - if (status != IX_SUCCESS) - { - return status; /* abort reset */ - } - } - } - } - - ixNpeDlNpeMgrDebugInstructionPostExec (npeBaseAddress); - - /* write Reset values to Execution Context Stack registers */ - indexMax = sizeof (ixNpeDlEcsRegResetValues) / - sizeof (IxNpeDlEcsRegResetValue); - for (localIndex = 0; localIndex < indexMax; localIndex++) - { - regAddr = ixNpeDlEcsRegResetValues[localIndex].regAddr; - regVal = ixNpeDlEcsRegResetValues[localIndex].regResetVal; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, regAddr, regVal); - } - - /* clear the profile counter */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT); - - /* clear registers EXCT, AP0, AP1, AP2 and AP3 */ - for (regAddr = IX_NPEDL_REG_OFFSET_EXCT; - regAddr <= IX_NPEDL_REG_OFFSET_AP3; - regAddr += IX_NPEDL_BYTES_PER_WORD) - { - IX_NPEDL_REG_WRITE (npeBaseAddress, regAddr, 0); - } - - /* Reset the Watch-count register */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, 0); - - /* - * WR IXA00055043 - Remove IMEM Parity Introduced by NPE Reset Operation - */ - - /* - * Call the feature control API to fused out and reset the NPE and its - * coprocessor - to reset internal states and remove parity error - */ - unitFuseReg = ixFeatureCtrlRead (); - unitFuseReg |= (IX_NPEDL_RESET_NPE_PARITY << npeId); - ixFeatureCtrlWrite (unitFuseReg); - - /* call the feature control API to un-fused and un-reset the NPE & COP */ - unitFuseReg &= (~(IX_NPEDL_RESET_NPE_PARITY << npeId)); - ixFeatureCtrlWrite (unitFuseReg); - - /* - * Call NpeMgr function to stop the NPE again after the Feature Control - * has unfused and Un-Reset the NPE and its associated Coprocessors - */ - status = ixNpeDlNpeMgrNpeStop (npeId); - - /* restore NPE configuration bus Control Register - Parity Settings */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_CTL, - (ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK)); - - ixNpeDlNpeMgrStats.npeResets++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeReset : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStart - */ -IX_STATUS -ixNpeDlNpeMgrNpeStart ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - UINT32 ecsRegVal; - BOOL npeRunning; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStart\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* - * ensure only Background Context Stack Level is Active by turning off - * the Active bit in each of the other Executing Context Stack levels - */ - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_1_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_PRI_2_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, - ecsRegVal); - - ecsRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_0); - ecsRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_ACTIVE; - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* start NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_START); - - /* - * check execution status of NPE to verify NPE Start operation was - * successful - */ - npeRunning = ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, - IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_RUN); - if (npeRunning) - { - ixNpeDlNpeMgrStats.npeStarts++; - } - else - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStart: " - "failed to start NPE execution\n"); - status = IX_FAIL; - } - - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStart : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrNpeStop - */ -IX_STATUS -ixNpeDlNpeMgrNpeStop ( - IxNpeDlNpeId npeId) -{ - UINT32 npeBaseAddress; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrNpeStop\n"); - - /* get base memory address of NPE from npeId */ - npeBaseAddress = ixNpeDlNpeMgrBaseAddressGet (npeId); - - /* stop NPE execution by issuing command through EXCTL register on NPE */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STOP); - - /* verify that NPE Stop was successful */ - if (! ixNpeDlNpeMgrBitsSetCheck (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, - IX_NPEDL_EXCTL_STATUS_STOP)) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrNpeStop: " - "failed to stop NPE execution\n"); - status = IX_FAIL; - } - - ixNpeDlNpeMgrStats.npeStops++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrNpeStop : status = %d\n", status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrBitsSetCheck - */ -PRIVATE BOOL -ixNpeDlNpeMgrBitsSetCheck ( - UINT32 npeBaseAddress, - UINT32 regOffset, - UINT32 expectedBitsSet) -{ - UINT32 regVal; - IX_NPEDL_REG_READ (npeBaseAddress, regOffset, ®Val); - - return expectedBitsSet == (expectedBitsSet & regVal); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsShow - */ -void -ixNpeDlNpeMgrStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrStatsShow:\n" - "\tInstruction Blocks loaded: %u\n" - "\tData Blocks loaded: %u\n" - "\tState Information Blocks loaded: %u\n" - "\tCritical NPE errors: %u\n" - "\tCritical Microcode errors: %u\n", - ixNpeDlNpeMgrStats.instructionBlocksLoaded, - ixNpeDlNpeMgrStats.dataBlocksLoaded, - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded, - ixNpeDlNpeMgrStats.criticalNpeErrors, - ixNpeDlNpeMgrStats.criticalMicrocodeErrors, - 0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tSuccessful NPE Starts: %u\n" - "\tSuccessful NPE Stops: %u\n" - "\tSuccessful NPE Resets: %u\n\n", - ixNpeDlNpeMgrStats.npeStarts, - ixNpeDlNpeMgrStats.npeStops, - ixNpeDlNpeMgrStats.npeResets, - 0,0,0); - - ixNpeDlNpeMgrUtilsStatsShow (); -} - - -/* - * Function definition: ixNpeDlNpeMgrStatsReset - */ -void -ixNpeDlNpeMgrStatsReset (void) -{ - ixNpeDlNpeMgrStats.instructionBlocksLoaded = 0; - ixNpeDlNpeMgrStats.dataBlocksLoaded = 0; - ixNpeDlNpeMgrStats.stateInfoBlocksLoaded = 0; - ixNpeDlNpeMgrStats.criticalNpeErrors = 0; - ixNpeDlNpeMgrStats.criticalMicrocodeErrors = 0; - ixNpeDlNpeMgrStats.npeStarts = 0; - ixNpeDlNpeMgrStats.npeStops = 0; - ixNpeDlNpeMgrStats.npeResets = 0; - - ixNpeDlNpeMgrUtilsStatsReset (); -} diff --git a/drivers/net/npe/IxNpeDlNpeMgrUtils.c b/drivers/net/npe/IxNpeDlNpeMgrUtils.c deleted file mode 100644 index db50d22d1be..00000000000 --- a/drivers/net/npe/IxNpeDlNpeMgrUtils.c +++ /dev/null @@ -1,782 +0,0 @@ -/** - * @file IxNpeDlNpeMgrUtils.c - * - * @author Intel Corporation - * @date 18 February 2002 - * - * @brief This file contains the implementation of the private API for the - * IXP425 NPE Downloader NpeMgr Utils module - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -/* - * Put the system defined include files required. - */ -#define IX_NPE_DL_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeDl.h" -#include "IxNpeDlNpeMgrUtils_p.h" -#include "IxNpeDlNpeMgrEcRegisters_p.h" -#include "IxNpeDlMacros_p.h" - -/* - * #defines and macros used in this file. - */ - -/* used to bit-mask a number of bytes */ -#define IX_NPEDL_MASK_LOWER_BYTE_OF_WORD 0x000000FF -#define IX_NPEDL_MASK_LOWER_SHORT_OF_WORD 0x0000FFFF -#define IX_NPEDL_MASK_FULL_WORD 0xFFFFFFFF - -#define IX_NPEDL_BYTES_PER_WORD 4 -#define IX_NPEDL_BYTES_PER_SHORT 2 - -#define IX_NPEDL_REG_SIZE_BYTE 8 -#define IX_NPEDL_REG_SIZE_SHORT 16 -#define IX_NPEDL_REG_SIZE_WORD 32 - -/* - * Introduce extra read cycles after issuing read command to NPE - * so that we read the register after the NPE has updated it - * This is to overcome race condition between XScale and NPE - */ -#define IX_NPEDL_DELAY_READ_CYCLES 2 -/* - * To mask top three MSBs of 32bit word to download into NPE IMEM - */ -#define IX_NPEDL_MASK_UNUSED_IMEM_BITS 0x1FFFFFFF; - - -/* - * typedefs - */ -typedef struct -{ - UINT32 regAddress; - UINT32 regSize; -} IxNpeDlCtxtRegAccessInfo; - -/* module statistics counters */ -typedef struct -{ - UINT32 insMemWrites; - UINT32 insMemWriteFails; - UINT32 dataMemWrites; - UINT32 dataMemWriteFails; - UINT32 ecsRegWrites; - UINT32 ecsRegReads; - UINT32 dbgInstructionExecs; - UINT32 contextRegWrites; - UINT32 physicalRegWrites; - UINT32 nextPcWrites; -} IxNpeDlNpeMgrUtilsStats; - - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * contains useful address and function pointers to read/write Context Regs, - * eliminating some switch or if-else statements in places - */ -static IxNpeDlCtxtRegAccessInfo ixNpeDlCtxtRegAccInfo[IX_NPEDL_CTXT_REG_MAX] = -{ - { - IX_NPEDL_CTXT_REG_ADDR_STEVT, - IX_NPEDL_REG_SIZE_BYTE - }, - { - IX_NPEDL_CTXT_REG_ADDR_STARTPC, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - IX_NPEDL_REG_SIZE_SHORT - }, - { - IX_NPEDL_CTXT_REG_ADDR_CINDEX, - IX_NPEDL_REG_SIZE_BYTE - } -}; - -static UINT32 ixNpeDlSavedExecCount = 0; -static UINT32 ixNpeDlSavedEcsDbgCtxtReg2 = 0; - -static IxNpeDlNpeMgrUtilsStats ixNpeDlNpeMgrUtilsStats; - - -/* - * static function prototypes. - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, - UINT32 addr, UINT32 data); - -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue (UINT32 npeBaseAddress, UINT32 cmd, UINT32 addr); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regSize, UINT32 ctxtNum, UINT32 *regVal); - -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite (UINT32 npeBaseAddress, UINT32 regAddr, - UINT32 regVal, UINT32 regSize, - UINT32 ctxtNum, BOOL verify); - -/* - * Function definition: ixNpeDlNpeMgrWriteCommandIssue - */ -PRIVATE __inline__ void -ixNpeDlNpeMgrWriteCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr, - UINT32 data) -{ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, data); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); -} - - -/* - * Function definition: ixNpeDlNpeMgrReadCommandIssue - */ -PRIVATE __inline__ UINT32 -ixNpeDlNpeMgrReadCommandIssue ( - UINT32 npeBaseAddress, - UINT32 cmd, - UINT32 addr) -{ - UINT32 data = 0; - int i; - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXAD, addr); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, cmd); - for (i = 0; i <= IX_NPEDL_DELAY_READ_CYCLES; i++) - { - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, &data); - } - - return data; -} - -/* - * Function definition: ixNpeDlNpeMgrInsMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrInsMemWrite ( - UINT32 npeBaseAddress, - UINT32 insMemAddress, - UINT32 insMemData, - BOOL verify) -{ - UINT32 insMemDataRtn; - - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_INS_MEM, - insMemAddress, insMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, - ~insMemData); - - /*Disabled since top 3 MSB are not used for Azusa hardware Refer WR:IXA00053900*/ - insMemData&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - insMemDataRtn=ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_INS_MEM, - insMemAddress); - - insMemDataRtn&=IX_NPEDL_MASK_UNUSED_IMEM_BITS; - - if (insMemData != insMemDataRtn) - { - ixNpeDlNpeMgrUtilsStats.insMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.insMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrDataMemWrite - */ -IX_STATUS -ixNpeDlNpeMgrDataMemWrite ( - UINT32 npeBaseAddress, - UINT32 dataMemAddress, - UINT32 dataMemData, - BOOL verify) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, - dataMemAddress, dataMemData); - if (verify) - { - /* write invalid data to this reg, so we can see if we're reading - the EXDATA register too early */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, ~dataMemData); - - if (dataMemData != - ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, - dataMemAddress)) - { - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails++; - return IX_FAIL; - } - } - - ixNpeDlNpeMgrUtilsStats.dataMemWrites++; - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegWrite - */ -void -ixNpeDlNpeMgrExecAccRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddress, - UINT32 regData) -{ - ixNpeDlNpeMgrWriteCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_WR_ECS_REG, - regAddress, regData); - ixNpeDlNpeMgrUtilsStats.ecsRegWrites++; -} - - -/* - * Function definition: ixNpeDlNpeMgrExecAccRegRead - */ -UINT32 -ixNpeDlNpeMgrExecAccRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddress) -{ - ixNpeDlNpeMgrUtilsStats.ecsRegReads++; - return ixNpeDlNpeMgrReadCommandIssue (npeBaseAddress, - IX_NPEDL_EXCTL_CMD_RD_ECS_REG, - regAddress); -} - - -/* - * Function definition: ixNpeDlNpeMgrCommandIssue - */ -void -ixNpeDlNpeMgrCommandIssue ( - UINT32 npeBaseAddress, - UINT32 command) -{ - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCommandIssue\n"); - - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCTL, command); - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCommandIssue\n"); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPreExec - */ -void -ixNpeDlNpeMgrDebugInstructionPreExec( - UINT32 npeBaseAddress) -{ - /* turn off the halt bit by clearing Execution Count register. */ - /* save reg contents 1st and restore later */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - &ixNpeDlSavedExecCount); - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, 0); - - /* ensure that IF and IE are on (temporarily), so that we don't end up - * stepping forever */ - ixNpeDlSavedEcsDbgCtxtReg2 = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_DBG_CTXT_REG_2); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - (ixNpeDlSavedEcsDbgCtxtReg2 | - IX_NPEDL_MASK_ECS_DBG_REG_2_IF | - IX_NPEDL_MASK_ECS_DBG_REG_2_IE)); -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionExec - */ -IX_STATUS -ixNpeDlNpeMgrDebugInstructionExec( - UINT32 npeBaseAddress, - UINT32 npeInstruction, - UINT32 ctxtNum, - UINT32 ldur) -{ - UINT32 ecsDbgRegVal; - UINT32 oldWatchcount, newWatchcount; - UINT32 retriesCount = 0; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrDebugInstructionExec\n"); - - /* set the Active bit, and the LDUR, in the debug level */ - ecsDbgRegVal = IX_NPEDL_MASK_ECS_REG_0_ACTIVE | - (ldur << IX_NPEDL_OFFSET_ECS_REG_0_LDUR); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - ecsDbgRegVal); - - /* - * set CCTXT at ECS DEBUG L3 to specify in which context to execute the - * instruction, and set SELCTXT at ECS DEBUG Level to specify which context - * store to access. - * Debug ECS Level Reg 1 has form 0x000n000n, where n = context number - */ - ecsDbgRegVal = (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_CCTXT) | - (ctxtNum << IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT); - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_1, - ecsDbgRegVal); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* load NPE instruction into the instruction register */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_INSTRUCT_REG, - npeInstruction); - - /* we need this value later to wait for completion of NPE execution step */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, &oldWatchcount); - - /* issue a Step One command via the Execution Control register */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_STEP); - - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - /* - * force the XScale to wait until the NPE has finished execution step - * NOTE that this delay will be very small, just long enough to allow a - * single NPE instruction to complete execution; if instruction execution - * is not completed before timeout retries, exit the while loop - */ - while ((IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - && (newWatchcount == oldWatchcount)) - { - /* Watch Count register increments when NPE completes an instruction */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_WC, - &newWatchcount); - - retriesCount++; - } - - if (IX_NPE_DL_MAX_NUM_OF_RETRIES > retriesCount) - { - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs++; - } - else - { - /* Return timeout status as the instruction has not been executed - * after maximum retries */ - status = IX_NPEDL_CRITICAL_NPE_ERR; - } - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrDebugInstructionExec\n"); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrDebugInstructionPostExec - */ -void -ixNpeDlNpeMgrDebugInstructionPostExec( - UINT32 npeBaseAddress) -{ - /* clear active bit in debug level */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_0, - 0); - - /* clear the pipeline */ - ixNpeDlNpeMgrCommandIssue (npeBaseAddress, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE); - - /* restore Execution Count register contents. */ - IX_NPEDL_REG_WRITE (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXCT, - ixNpeDlSavedExecCount); - - /* restore IF and IE bits to original values */ - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, IX_NPEDL_ECS_DBG_CTXT_REG_2, - ixNpeDlSavedEcsDbgCtxtReg2); -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegRead - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegRead ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regSize, - UINT32 ctxtNum, - UINT32 *regVal) -{ - IX_STATUS status = IX_SUCCESS; - UINT32 npeInstruction = 0; - UINT32 mask = 0; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegRead\n"); - - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_RD_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_RD_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - case IX_NPEDL_REG_SIZE_WORD: - npeInstruction = IX_NPEDL_INSTR_RD_REG_WORD; - mask = IX_NPEDL_MASK_FULL_WORD; break; - } - - /* make regAddr be the SRC and DEST operands (e.g. movX d0, d0) */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_SRC) | - (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* step execution of NPE intruction using Debug Executing Context stack */ - status = ixNpeDlNpeMgrDebugInstructionExec (npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_RD_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - - /* read value of register from Execution Data register */ - IX_NPEDL_REG_READ (npeBaseAddress, IX_NPEDL_REG_OFFSET_EXDATA, regVal); - - /* align value from left to right */ - *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegRead\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeDlNpeMgrLogicalRegWrite - */ -PRIVATE IX_STATUS -ixNpeDlNpeMgrLogicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regVal, - UINT32 regSize, - UINT32 ctxtNum, - BOOL verify) -{ - UINT32 npeInstruction = 0; - UINT32 mask = 0; - IX_STATUS status = IX_SUCCESS; - UINT32 retRegVal; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrLogicalRegWrite\n"); - - if (regSize == IX_NPEDL_REG_SIZE_WORD) - { - /* NPE register addressing is left-to-right: e.g. |d0|d1|d2|d3| */ - /* Write upper half-word (short) to |d0|d1| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, - regVal >> IX_NPEDL_REG_SIZE_SHORT, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - - /* Write lower half-word (short) to |d2|d3| */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - regAddr + IX_NPEDL_BYTES_PER_SHORT, - regVal & IX_NPEDL_MASK_LOWER_SHORT_OF_WORD, - IX_NPEDL_REG_SIZE_SHORT, - ctxtNum, verify); - - if (IX_SUCCESS != status) - { - return status; - } - } - else - { - switch (regSize) - { - case IX_NPEDL_REG_SIZE_BYTE: - npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE; - mask = IX_NPEDL_MASK_LOWER_BYTE_OF_WORD; break; - case IX_NPEDL_REG_SIZE_SHORT: - npeInstruction = IX_NPEDL_INSTR_WR_REG_SHORT; - mask = IX_NPEDL_MASK_LOWER_SHORT_OF_WORD; break; - } - /* mask out any redundant bits, so verify will work later */ - regVal &= mask; - - /* fill dest operand field of instruction with destination reg addr */ - npeInstruction |= (regAddr << IX_NPEDL_OFFSET_INSTR_DEST); - - /* fill src operand field of instruction with least-sig 5 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA) << - IX_NPEDL_OFFSET_INSTR_SRC); - - /* fill coprocessor field of instruction with most-sig 11 bits of val*/ - npeInstruction |= ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) << - IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA); - - /* step execution of NPE intruction using Debug ECS */ - status = ixNpeDlNpeMgrDebugInstructionExec(npeBaseAddress, npeInstruction, - ctxtNum, IX_NPEDL_WR_INSTR_LDUR); - - if (IX_SUCCESS != status) - { - return status; - } - }/* condition: if reg to be written is 8-bit or 16-bit (not 32-bit) */ - - if (verify) - { - status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr, - regSize, ctxtNum, &retRegVal); - - if (IX_SUCCESS == status) - { - if (regVal != retRegVal) - { - status = IX_FAIL; - } - } - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrLogicalRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrPhysicalRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrPhysicalRegWrite ( - UINT32 npeBaseAddress, - UINT32 regAddr, - UINT32 regValue, - BOOL verify) -{ - IX_STATUS status; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrPhysicalRegWrite\n"); - -/* - * There are 32 physical registers used in an NPE. These are - * treated as 16 pairs of 32-bit registers. To write one of the pair, - * write the pair number (0-16) to the REGMAP for Context 0. Then write - * the value to register 0 or 4 in the regfile, depending on which - * register of the pair is to be written - */ - - /* - * set REGMAP for context 0 to (regAddr >> 1) to choose which pair (0-16) - * of physical registers to write - */ - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, - IX_NPEDL_CTXT_REG_ADDR_REGMAP, - (regAddr >> - IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP), - IX_NPEDL_REG_SIZE_SHORT, 0, verify); - if (status == IX_SUCCESS) - { - /* regAddr = 0 or 4 */ - regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) * - IX_NPEDL_BYTES_PER_WORD; - - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, regAddr, regValue, - IX_NPEDL_REG_SIZE_WORD, 0, verify); - } - - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrPhysicalRegWrite: " - "error writing to physical register\n"); - } - - ixNpeDlNpeMgrUtilsStats.physicalRegWrites++; - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrPhysicalRegWrite : status = %d\n", - status); - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrCtxtRegWrite - */ -IX_STATUS -ixNpeDlNpeMgrCtxtRegWrite ( - UINT32 npeBaseAddress, - UINT32 ctxtNum, - IxNpeDlCtxtRegNum ctxtReg, - UINT32 ctxtRegVal, - BOOL verify) -{ - UINT32 tempRegVal; - UINT32 ctxtRegAddr; - UINT32 ctxtRegSize; - IX_STATUS status = IX_SUCCESS; - - IX_NPEDL_TRACE0 (IX_NPEDL_FN_ENTRY_EXIT, - "Entering ixNpeDlNpeMgrCtxtRegWrite\n"); - - /* - * Context 0 has no STARTPC. Instead, this value is used to set - * NextPC for Background ECS, to set where NPE starts executing code - */ - if ((ctxtNum == 0) && (ctxtReg == IX_NPEDL_CTXT_REG_STARTPC)) - { - /* read BG_CTXT_REG_0, update NEXTPC bits, and write back to reg */ - tempRegVal = ixNpeDlNpeMgrExecAccRegRead (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0); - tempRegVal &= ~IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - tempRegVal |= (ctxtRegVal << IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC) & - IX_NPEDL_MASK_ECS_REG_0_NEXTPC; - - ixNpeDlNpeMgrExecAccRegWrite (npeBaseAddress, - IX_NPEDL_ECS_BG_CTXT_REG_0, tempRegVal); - - ixNpeDlNpeMgrUtilsStats.nextPcWrites++; - } - else - { - ctxtRegAddr = ixNpeDlCtxtRegAccInfo[ctxtReg].regAddress; - ctxtRegSize = ixNpeDlCtxtRegAccInfo[ctxtReg].regSize; - status = ixNpeDlNpeMgrLogicalRegWrite (npeBaseAddress, ctxtRegAddr, - ctxtRegVal, ctxtRegSize, - ctxtNum, verify); - if (status != IX_SUCCESS) - { - IX_NPEDL_ERROR_REPORT ("ixNpeDlNpeMgrCtxtRegWrite: " - "error writing to context store register\n"); - } - - ixNpeDlNpeMgrUtilsStats.contextRegWrites++; - } - - IX_NPEDL_TRACE1 (IX_NPEDL_FN_ENTRY_EXIT, - "Exiting ixNpeDlNpeMgrCtxtRegWrite : status = %d\n", - status); - - return status; -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsShow - */ -void -ixNpeDlNpeMgrUtilsStatsShow (void) -{ - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\nixNpeDlNpeMgrUtilsStatsShow:\n" - "\tInstruction Memory writes: %u\n" - "\tInstruction Memory writes failed: %u\n" - "\tData Memory writes: %u\n" - "\tData Memory writes failed: %u\n", - ixNpeDlNpeMgrUtilsStats.insMemWrites, - ixNpeDlNpeMgrUtilsStats.insMemWriteFails, - ixNpeDlNpeMgrUtilsStats.dataMemWrites, - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails, - 0,0); - - ixOsalLog (IX_OSAL_LOG_LVL_USER, - IX_OSAL_LOG_DEV_STDOUT, - "\tExecuting Context Stack Register writes: %u\n" - "\tExecuting Context Stack Register reads: %u\n" - "\tPhysical Register writes: %u\n" - "\tContext Store Register writes: %u\n" - "\tExecution Backgound Context NextPC writes: %u\n" - "\tDebug Instructions Executed: %u\n\n", - ixNpeDlNpeMgrUtilsStats.ecsRegWrites, - ixNpeDlNpeMgrUtilsStats.ecsRegReads, - ixNpeDlNpeMgrUtilsStats.physicalRegWrites, - ixNpeDlNpeMgrUtilsStats.contextRegWrites, - ixNpeDlNpeMgrUtilsStats.nextPcWrites, - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs); -} - - -/* - * Function definition: ixNpeDlNpeMgrUtilsStatsReset - */ -void -ixNpeDlNpeMgrUtilsStatsReset (void) -{ - ixNpeDlNpeMgrUtilsStats.insMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.insMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWrites = 0; - ixNpeDlNpeMgrUtilsStats.dataMemWriteFails = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.ecsRegReads = 0; - ixNpeDlNpeMgrUtilsStats.physicalRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.contextRegWrites = 0; - ixNpeDlNpeMgrUtilsStats.nextPcWrites = 0; - ixNpeDlNpeMgrUtilsStats.dbgInstructionExecs = 0; -} diff --git a/drivers/net/npe/IxNpeMh.c b/drivers/net/npe/IxNpeMh.c deleted file mode 100644 index 5adabd82fc4..00000000000 --- a/drivers/net/npe/IxNpeMh.c +++ /dev/null @@ -1,558 +0,0 @@ -/** - * @file IxNpeMh.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the public API for the - * IXP425 NPE Message Handler component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMh.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE BOOL ixNpeMhInitialized = false; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhInitialize - */ - -PUBLIC IX_STATUS ixNpeMhInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhInitialize\n"); - - /* check the npeInterrupts parameter */ - if ((npeInterrupts != IX_NPEMH_NPEINTERRUPTS_NO) && - (npeInterrupts != IX_NPEMH_NPEINTERRUPTS_YES)) - { - IX_NPEMH_ERROR_REPORT ("Illegal npeInterrupts parameter value\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* initialize the Receive module */ - ixNpeMhReceiveInitialize (); - - /* initialize the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrInitialize (); - - /* initialize the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrInitialize (); - - /* initialize the Configuration module - * - * NOTE: This module was originally configured before the - * others, but the sequence was changed so that interrupts - * would only be enabled after the handler functions were - * set up. The above modules need to be initialised to - * handle the NPE interrupts. See SCR #2231. - */ - ixNpeMhConfigInitialize (npeInterrupts); - - ixNpeMhInitialized = true; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhInitialize\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnload - */ - -PUBLIC IX_STATUS ixNpeMhUnload (void) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnload\n"); - - if (!ixNpeMhInitialized) - { - return IX_FAIL; - } - - /* Uninitialize the Configuration module */ - ixNpeMhConfigUninit (); - - ixNpeMhInitialized = false; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnload\n"); - - return IX_SUCCESS; -} - - -/* - * Function definition: ixNpeMhUnsolicitedCallbackRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId messageId, - IxNpeMhCallback unsolicitedCallback) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the messageId parameter */ - if ((messageId < IX_NPEMH_MIN_MESSAGE_ID) - || (messageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Message ID is out of range\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhUnsolicitedCallbackForRangeRegister - */ - -PUBLIC IX_STATUS ixNpeMhUnsolicitedCallbackForRangeRegister ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId minMessageId, - IxNpeMhMessageId maxMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhMessageId messageId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the minMessageId parameter */ - if ((minMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (minMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Min message ID is out of range\n"); - return IX_FAIL; - } - - /* check the maxMessageId parameter */ - if ((maxMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (maxMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Max message ID is out of range\n"); - return IX_FAIL; - } - - /* check the semantics of the message range parameters */ - if (minMessageId > maxMessageId) - { - IX_NPEMH_ERROR_REPORT ("Min message ID greater than max message " - "ID\n"); - return IX_FAIL; - } - - /* the unsolicitedCallback parameter is allowed to be NULL */ - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* for each message ID in the range ... */ - for (messageId = minMessageId; messageId <= maxMessageId; messageId++) - { - /* save the unsolicited callback for the message ID */ - ixNpeMhUnsolicitedCbMgrCallbackSave ( - npeId, messageId, unsolicitedCallback); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCallbackForRangeRegister\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhMessageSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageSend (npeId, message, maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessageWithResponseSend - */ - -PUBLIC IX_STATUS ixNpeMhMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - IxNpeMhCallback unsolicitedCallback = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessageWithResponseSend\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* the solicitecCallback parameter is allowed to be NULL. this */ - /* signifies the client is not interested in the response message */ - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter */ - if ((solicitedMessageId < IX_NPEMH_MIN_MESSAGE_ID) - || (solicitedMessageId > IX_NPEMH_MAX_MESSAGE_ID)) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID is out of range\n"); - return IX_FAIL; - } - - /* check the solicitedMessageId parameter. if an unsolicited */ - /* callback has been registered for the specified message ID then */ - /* report an error and return failure */ - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, solicitedMessageId, &unsolicitedCallback); - if (unsolicitedCallback != NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited message ID conflicts with " - "unsolicited message ID\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* send the message */ - status = ixNpeMhSendMessageWithResponseSend ( - npeId, message, solicitedMessageId, solicitedCallback, - maxSendRetries); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to send message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessageWithResponseSend" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhMessagesReceive - */ - -PUBLIC IX_STATUS ixNpeMhMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhMessagesReceive\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* get the lock to prevent other clients from entering */ - ixNpeMhConfigLockGet (npeId); - - /* receive messages from the NPE */ - status = ixNpeMhReceiveMessagesReceive (npeId); - - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to receive message\n"); - } - - /* release the lock to allow other clients back in */ - ixNpeMhConfigLockRelease (npeId); - - IX_NPEMH_TRACE1 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhMessagesReceive" - " : status = %d\n", status); - - return status; -} - -/* - * Function definition: ixNpeMhShow - */ - -PUBLIC IX_STATUS ixNpeMhShow ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShow\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as printing the statistics */ - /* to a console may take some time and we don't want to impact */ - /* system performance. this means that the statistics displayed */ - /* may be in a state of flux and make not represent a consistent */ - /* snapshot. */ - - /* display a header */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "Current state of NPE ID %d:\n\n", npeId, 0, 0, 0, 0, 0); - - /* show the current state of each module */ - - /* show the current state of the Configuration module */ - ixNpeMhConfigShow (npeId); - - /* show the current state of the Receive module */ - ixNpeMhReceiveShow (npeId); - - /* show the current state of the Send module */ - ixNpeMhSendShow (npeId); - - /* show the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShow (npeId); - - /* show the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShow (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShow\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhShowReset - */ - -PUBLIC IX_STATUS ixNpeMhShowReset ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhShowReset\n"); - - /* check that we are initialized */ - if (!ixNpeMhInitialized) - { - IX_NPEMH_ERROR_REPORT ("IxNpeMh component is not initialized\n"); - return IX_FAIL; - } - - /* check the npeId parameter */ - if (!ixNpeMhConfigNpeIdIsValid (npeId)) - { - IX_NPEMH_ERROR_REPORT ("NPE ID invalid\n"); - return IX_FAIL; - } - - /* parameters are ok ... */ - - /* note we don't get the lock here as resetting the statistics */ - /* shouldn't impact system performance. */ - - /* reset the current state of each module */ - - /* reset the current state of the Configuration module */ - ixNpeMhConfigShowReset (npeId); - - /* reset the current state of the Receive module */ - ixNpeMhReceiveShowReset (npeId); - - /* reset the current state of the Send module */ - ixNpeMhSendShowReset (npeId); - - /* reset the current state of the Solicited Callback Manager module */ - ixNpeMhSolicitedCbMgrShowReset (npeId); - - /* reset the current state of the Unsolicited Callback Manager module */ - ixNpeMhUnsolicitedCbMgrShowReset (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhShowReset\n"); - - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxNpeMhConfig.c b/drivers/net/npe/IxNpeMhConfig.c deleted file mode 100644 index eaa9a21ad73..00000000000 --- a/drivers/net/npe/IxNpeMhConfig.c +++ /dev/null @@ -1,584 +0,0 @@ -/** - * @file IxNpeMhConfig.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Configuration module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" - -/* - * #defines and macros used in this file. - */ -#define IX_NPE_MH_MAX_NUM_OF_RETRIES 1000000 /**< Maximum number of - * retries before - * timeout - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhConfigStats - * - * @brief This structure is used to maintain statistics for the - * Configuration module. - */ - -typedef struct -{ - UINT32 outFifoReads; /**< outFifo reads */ - UINT32 inFifoWrites; /**< inFifo writes */ - UINT32 maxInFifoFullRetries; /**< max retries if inFIFO full */ - UINT32 maxOutFifoEmptyRetries; /**< max retries if outFIFO empty */ -} IxNpeMhConfigStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -IxNpeMhConfigNpeInfo ixNpeMhConfigNpeInfo[IX_NPEMH_NUM_NPES] = -{ - { - 0, - IX_NPEMH_NPEA_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEB_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - }, - { - 0, - IX_NPEMH_NPEC_INT, - 0, - 0, - 0, - 0, - 0, - NULL, - false - } -}; - -PRIVATE IxNpeMhConfigStats ixNpeMhConfigStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhConfigIsr (void *parameter); - -/* - * Function definition: ixNpeMhConfigIsr - */ - -PRIVATE -void ixNpeMhConfigIsr (void *parameter) -{ - IxNpeMhNpeId npeId = (IxNpeMhNpeId)parameter; - UINT32 ofint; - volatile UINT32 *statusReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].statusRegister; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsr\n"); - - /* get the OFINT (OutFifo interrupt) bit of the status register */ - IX_NPEMH_REGISTER_READ_BITS (statusReg, &ofint, IX_NPEMH_NPE_STAT_OFINT); - - /* if the OFINT status bit is set */ - if (ofint) - { - /* if there is an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - /* invoke the ISR routine */ - ixNpeMhConfigNpeInfo[npeId].isr (npeId); - } - else - { - /* if we don't service the interrupt the NPE will continue */ - /* to trigger the interrupt indefinitely */ - IX_NPEMH_ERROR_REPORT ("No ISR registered to service " - "interrupt\n"); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsr\n"); -} - -/* - * Function definition: ixNpeMhConfigInitialize - */ - -void ixNpeMhConfigInitialize ( - IxNpeMhNpeInterrupts npeInterrupts) -{ - IxNpeMhNpeId npeId; - UINT32 virtualAddr[IX_NPEMH_NUM_NPES]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigInitialize\n"); - - /* Request a mapping for the NPE-A config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEA] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEA_BASE, - IX_OSAL_IXP400_NPEA_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEA]); - - /* Request a mapping for the NPE-B config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEB] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEB_BASE, - IX_OSAL_IXP400_NPEB_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEB]); - - /* Request a mapping for the NPE-C config register address space */ - virtualAddr[IX_NPEMH_NPEID_NPEC] = - (UINT32) IX_OSAL_MEM_MAP (IX_NPEMH_NPEC_BASE, - IX_OSAL_IXP400_NPEC_MAP_SIZE); - IX_OSAL_ASSERT (virtualAddr[IX_NPEMH_NPEID_NPEC]); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* store the virtual addresses of the NPE registers for later use */ - npeInfo->virtualRegisterBase = virtualAddr[npeId]; - npeInfo->statusRegister = virtualAddr[npeId] + IX_NPEMH_NPESTAT_OFFSET; - npeInfo->controlRegister = virtualAddr[npeId] + IX_NPEMH_NPECTL_OFFSET; - npeInfo->inFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - npeInfo->outFifoRegister = virtualAddr[npeId] + IX_NPEMH_NPEFIFO_OFFSET; - - /* for test purposes - to verify the register addresses */ - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d status register = " - "0x%08X\n", npeId, npeInfo->statusRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d control register = " - "0x%08X\n", npeId, npeInfo->controlRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d inFifo register = " - "0x%08X\n", npeId, npeInfo->inFifoRegister); - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NPE %d outFifo register = " - "0x%08X\n", npeId, npeInfo->outFifoRegister); - - /* connect our ISR to the NPE interrupt */ - (void) ixOsalIrqBind ( - npeInfo->interruptId, ixNpeMhConfigIsr, (void *)npeId); - - /* initialise a mutex for this NPE */ - (void) ixOsalMutexInit (&npeInfo->mutex); - - /* if we should service the NPE's "outFIFO not empty" interrupt */ - if (npeInterrupts == IX_NPEMH_NPEINTERRUPTS_YES) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptEnable (npeId); - } - else - { - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInterruptDisable (npeId); - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigInitialize\n"); -} - -/* - * Function definition: ixNpeMhConfigUninit - */ - -void ixNpeMhConfigUninit (void) -{ - IxNpeMhNpeId npeId; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigUninit\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* declare a convenience pointer */ - IxNpeMhConfigNpeInfo *npeInfo = &ixNpeMhConfigNpeInfo[npeId]; - - /* disconnect ISR */ - ixOsalIrqUnbind(npeInfo->interruptId); - - /* destroy mutex associated with this NPE */ - ixOsalMutexDestroy(&npeInfo->mutex); - - IX_OSAL_MEM_UNMAP (npeInfo->virtualRegisterBase); - - npeInfo->virtualRegisterBase = 0; - npeInfo->statusRegister = 0; - npeInfo->controlRegister = 0; - npeInfo->inFifoRegister = 0; - npeInfo->outFifoRegister = 0; - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigUninit\n"); -} - -/* - * Function definition: ixNpeMhConfigIsrRegister - */ - -void ixNpeMhConfigIsrRegister ( - IxNpeMhNpeId npeId, - IxNpeMhConfigIsr isr) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigIsrRegister\n"); - - /* check if there is already an ISR registered for this NPE */ - if (ixNpeMhConfigNpeInfo[npeId].isr != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, "Over-writing registered NPE ISR\n"); - } - - /* save the ISR routine with the NPE info */ - ixNpeMhConfigNpeInfo[npeId].isr = isr; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigIsrRegister\n"); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptEnable - */ - -BOOL ixNpeMhConfigNpeInterruptEnable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is disabled then we must enable it */ - if (!ofe) - { - /* set the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigNpeInterruptDisable - */ - -BOOL ixNpeMhConfigNpeInterruptDisable ( - IxNpeMhNpeId npeId) -{ - UINT32 ofe; - volatile UINT32 *controlReg = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].controlRegister; - - /* get the OFE (OutFifoEnable) bit of the control register */ - IX_NPEMH_REGISTER_READ_BITS (controlReg, &ofe, IX_NPEMH_NPE_CTL_OFE); - - /* if the interrupt is enabled then we must disable it */ - if (ofe) - { - /* unset the OFE (OutFifoEnable) bit of the control register */ - /* we must set the OFEWE (OutFifoEnableWriteEnable) at the same */ - /* time for the write to have effect */ - IX_NPEMH_REGISTER_WRITE_BITS (controlReg, - (0 | - IX_NPEMH_NPE_CTL_OFEWE), - (IX_NPEMH_NPE_CTL_OFE | - IX_NPEMH_NPE_CTL_OFEWE)); - } - - /* return the previous state of the interrupt */ - return (ofe != 0); -} - -/* - * Function definition: ixNpeMhConfigMessageIdGet - */ - -IxNpeMhMessageId ixNpeMhConfigMessageIdGet ( - IxNpeMhMessage message) -{ - /* return the most-significant byte of the first word of the */ - /* message */ - return ((IxNpeMhMessageId) ((message.data[0] >> 24) & 0xFF)); -} - -/* - * Function definition: ixNpeMhConfigNpeIdIsValid - */ - -BOOL ixNpeMhConfigNpeIdIsValid ( - IxNpeMhNpeId npeId) -{ - /* check that the npeId parameter is within the range of valid IDs */ - return (npeId >= 0 && npeId < IX_NPEMH_NUM_NPES); -} - -/* - * Function definition: ixNpeMhConfigLockGet - */ - -void ixNpeMhConfigLockGet ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockGet\n"); - - /* lock the mutex for this NPE */ - (void) ixOsalMutexLock (&ixNpeMhConfigNpeInfo[npeId].mutex, - IX_OSAL_WAIT_FOREVER); - - /* disable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptDisable (npeId); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockGet\n"); -} - -/* - * Function definition: ixNpeMhConfigLockRelease - */ - -void ixNpeMhConfigLockRelease ( - IxNpeMhNpeId npeId) -{ - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhConfigLockRelease\n"); - - /* if the interrupt was previously enabled */ - if (ixNpeMhConfigNpeInfo[npeId].oldInterruptState) - { - /* enable the NPE's "outFIFO not empty" interrupt */ - ixNpeMhConfigNpeInfo[npeId].oldInterruptState = - ixNpeMhConfigNpeInterruptEnable (npeId); - } - - /* unlock the mutex for this NPE */ - (void) ixOsalMutexUnlock (&ixNpeMhConfigNpeInfo[npeId].mutex); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhConfigLockRelease\n"); -} - -/* - * Function definition: ixNpeMhConfigInFifoWrite - */ - -IX_STATUS ixNpeMhConfigInFifoWrite ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message) -{ - volatile UINT32 *npeInFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].inFifoRegister; - UINT32 retriesCount = 0; - - /* write the first word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[0]); - - /* need to wait for room to write second word - see SCR #493, - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigInFifoIsFull (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* write the second word of the message to the NPE's inFIFO */ - IX_NPEMH_REGISTER_WRITE (npeInFifo, message.data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxInFifoFullRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].inFifoWrites++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigOutFifoRead - */ - -IX_STATUS ixNpeMhConfigOutFifoRead ( - IxNpeMhNpeId npeId, - IxNpeMhMessage *message) -{ - volatile UINT32 *npeOutFifo = - (UINT32 *)ixNpeMhConfigNpeInfo[npeId].outFifoRegister; - UINT32 retriesCount = 0; - - /* read the first word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[0]); - - /* need to wait for NPE to write second word - see SCR #493 - poll for maximum number of retries, if exceed maximum - retries, exit from while loop */ - while ((IX_NPE_MH_MAX_NUM_OF_RETRIES > retriesCount) - && ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - retriesCount++; - } - - /* Return TIMEOUT status to caller, indicate that NPE Hang / Halt */ - if (IX_NPE_MH_MAX_NUM_OF_RETRIES == retriesCount) - { - return IX_NPEMH_CRITICAL_NPE_ERR; - } - - /* read the second word of the message from the NPE's outFIFO */ - IX_NPEMH_REGISTER_READ (npeOutFifo, &message->data[1]); - - /* record in the stats the maximum number of retries needed */ - if (ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries < retriesCount) - { - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = retriesCount; - } - - /* update statistical info */ - ixNpeMhConfigStats[npeId].outFifoReads++; - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhConfigShow - */ - -void ixNpeMhConfigShow ( - IxNpeMhNpeId npeId) -{ - /* show the message fifo read counter */ - IX_NPEMH_SHOW ("Message FIFO reads", - ixNpeMhConfigStats[npeId].outFifoReads); - - /* show the message fifo write counter */ - IX_NPEMH_SHOW ("Message FIFO writes", - ixNpeMhConfigStats[npeId].inFifoWrites); - - /* show the max retries performed when inFIFO full */ - IX_NPEMH_SHOW ("Max inFIFO Full retries", - ixNpeMhConfigStats[npeId].maxInFifoFullRetries); - - /* show the max retries performed when outFIFO empty */ - IX_NPEMH_SHOW ("Max outFIFO Empty retries", - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries); - - /* show the current status of the inFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "InFifo is %s and %s\n", - (ixNpeMhConfigInFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigInFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); - - /* show the current status of the outFifo */ - ixOsalLog (IX_OSAL_LOG_LVL_USER, IX_OSAL_LOG_DEV_STDOUT, - "OutFifo is %s and %s\n", - (ixNpeMhConfigOutFifoIsEmpty (npeId) ? - (int) "EMPTY" : (int) "NOT EMPTY"), - (ixNpeMhConfigOutFifoIsFull (npeId) ? - (int) "FULL" : (int) "NOT FULL"), - 0, 0, 0, 0); -} - -/* - * Function definition: ixNpeMhConfigShowReset - */ - -void ixNpeMhConfigShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message fifo read counter */ - ixNpeMhConfigStats[npeId].outFifoReads = 0; - - /* reset the message fifo write counter */ - ixNpeMhConfigStats[npeId].inFifoWrites = 0; - - /* reset the max inFIFO Full retries counter */ - ixNpeMhConfigStats[npeId].maxInFifoFullRetries = 0; - - /* reset the max outFIFO empty retries counter */ - ixNpeMhConfigStats[npeId].maxOutFifoEmptyRetries = 0; -} - - diff --git a/drivers/net/npe/IxNpeMhReceive.c b/drivers/net/npe/IxNpeMhReceive.c deleted file mode 100644 index 273c3733f37..00000000000 --- a/drivers/net/npe/IxNpeMhReceive.c +++ /dev/null @@ -1,296 +0,0 @@ -/** - * @file IxNpeMhReceive.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Receive module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhReceive_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhUnsolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhReceiveStats - * - * @brief This structure is used to maintain statistics for the Receive - * module. - */ - -typedef struct -{ - UINT32 isrs; /**< receive ISR invocations */ - UINT32 receives; /**< receive messages invocations */ - UINT32 messages; /**< messages received */ - UINT32 solicited; /**< solicited messages received */ - UINT32 unsolicited; /**< unsolicited messages received */ - UINT32 callbacks; /**< callbacks invoked */ -} IxNpeMhReceiveStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhReceiveStats ixNpeMhReceiveStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -void ixNpeMhReceiveIsr (int npeId); - -PRIVATE -void ixNpeMhReceiveIsr (int npeId) -{ - int lockKey; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveIsr\n"); - - lockKey = ixOsalIrqLock (); - - /* invoke the message receive routine to get messages from the NPE */ - ixNpeMhReceiveMessagesReceive (npeId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].isrs++; - - ixOsalIrqUnlock (lockKey); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveIsr\n"); -} - -/* - * Function definition: ixNpeMhReceiveInitialize - */ - -void ixNpeMhReceiveInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* register our internal ISR for the NPE to handle "outFIFO not */ - /* empty" interrupts */ - ixNpeMhConfigIsrRegister (npeId, ixNpeMhReceiveIsr); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveInitialize\n"); -} - -/* - * Function definition: ixNpeMhReceiveMessagesReceive - */ - -IX_STATUS ixNpeMhReceiveMessagesReceive ( - IxNpeMhNpeId npeId) -{ - IxNpeMhMessage message = { { 0, 0 } }; - IxNpeMhMessageId messageId = 0; - IxNpeMhCallback callback = NULL; - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhReceiveMessagesReceive\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].receives++; - - /* while the NPE has messages in its outFIFO */ - while (!ixNpeMhConfigOutFifoIsEmpty (npeId)) - { - /* read a message from the NPE's outFIFO */ - status = ixNpeMhConfigOutFifoRead (npeId, &message); - - if (IX_SUCCESS != status) - { - return status; - } - - /* get the ID of the message */ - messageId = ixNpeMhConfigMessageIdGet (message); - - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, - "Received message from NPE %d with ID 0x%02X\n", - npeId, messageId); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].messages++; - - /* try to find a matching unsolicited callback for this message. */ - - /* we assume the message is unsolicited. only if there is no */ - /* unsolicited callback for this message type do we assume the */ - /* message is solicited. it is much faster to check for an */ - /* unsolicited callback, so doing this check first should result */ - /* in better performance. */ - - ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching unsolicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].unsolicited++; - } - - /* if no unsolicited callback was found try to find a matching */ - /* solicited callback for this message */ - if (callback == NULL) - { - ixNpeMhSolicitedCbMgrCallbackRetrieve ( - npeId, messageId, &callback); - - if (callback != NULL) - { - IX_NPEMH_TRACE0 (IX_NPEMH_DEBUG, - "Found matching solicited callback\n"); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].solicited++; - } - } - - /* if a callback (either unsolicited or solicited) was found */ - if (callback != NULL) - { - /* invoke the callback to pass the message back to the client */ - callback (npeId, message); - - /* update statistical info */ - ixNpeMhReceiveStats[npeId].callbacks++; - } - else /* no callback (neither unsolicited nor solicited) was found */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_WARNING, - "No matching callback for NPE %d" - " and ID 0x%02X, discarding message\n", - npeId, messageId); - - /* the message will be discarded. this is normal behaviour */ - /* if the client passes a NULL solicited callback when */ - /* sending a message. this indicates that the client is not */ - /* interested in receiving the response. alternatively a */ - /* NULL callback here may signify an unsolicited message */ - /* with no appropriate registered callback. */ - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhReceiveMessagesReceive\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhReceiveShow - */ - -void ixNpeMhReceiveShow ( - IxNpeMhNpeId npeId) -{ - /* show the ISR invocation counter */ - IX_NPEMH_SHOW ("Receive ISR invocations", - ixNpeMhReceiveStats[npeId].isrs); - - /* show the receive message invocation counter */ - IX_NPEMH_SHOW ("Receive messages invocations", - ixNpeMhReceiveStats[npeId].receives); - - /* show the message received counter */ - IX_NPEMH_SHOW ("Messages received", - ixNpeMhReceiveStats[npeId].messages); - - /* show the solicited message counter */ - IX_NPEMH_SHOW ("Solicited messages received", - ixNpeMhReceiveStats[npeId].solicited); - - /* show the unsolicited message counter */ - IX_NPEMH_SHOW ("Unsolicited messages received", - ixNpeMhReceiveStats[npeId].unsolicited); - - /* show the callback invoked counter */ - IX_NPEMH_SHOW ("Callbacks invoked", - ixNpeMhReceiveStats[npeId].callbacks); - - /* show the message discarded counter */ - IX_NPEMH_SHOW ("Received messages discarded", - (ixNpeMhReceiveStats[npeId].messages - - ixNpeMhReceiveStats[npeId].callbacks)); -} - -/* - * Function definition: ixNpeMhReceiveShowReset - */ - -void ixNpeMhReceiveShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the ISR invocation counter */ - ixNpeMhReceiveStats[npeId].isrs = 0; - - /* reset the receive message invocation counter */ - ixNpeMhReceiveStats[npeId].receives = 0; - - /* reset the message received counter */ - ixNpeMhReceiveStats[npeId].messages = 0; - - /* reset the solicited message counter */ - ixNpeMhReceiveStats[npeId].solicited = 0; - - /* reset the unsolicited message counter */ - ixNpeMhReceiveStats[npeId].unsolicited = 0; - - /* reset the callback invoked counter */ - ixNpeMhReceiveStats[npeId].callbacks = 0; -} diff --git a/drivers/net/npe/IxNpeMhSend.c b/drivers/net/npe/IxNpeMhSend.c deleted file mode 100644 index 8b7038870a5..00000000000 --- a/drivers/net/npe/IxNpeMhSend.c +++ /dev/null @@ -1,283 +0,0 @@ -/** - * @file IxNpeMhSend.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Send module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhConfig_p.h" -#include "IxNpeMhSend_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_NPEMH_INFIFO_RETRY_DELAY_US - * - * @brief Amount of time (uSecs) to delay between retries - * while inFIFO is Full when attempting to send a message - */ -#define IX_NPEMH_INFIFO_RETRY_DELAY_US (1) - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSendStats - * - * @brief This structure is used to maintain statistics for the Send - * module. - */ - -typedef struct -{ - UINT32 sends; /**< send invocations */ - UINT32 sendWithResponses; /**< send with response invocations */ - UINT32 queueFulls; /**< fifo queue full occurrences */ - UINT32 queueFullRetries; /**< fifo queue full retry occurrences */ - UINT32 maxQueueFullRetries; /**< max fifo queue full retries */ - UINT32 callbackFulls; /**< callback list full occurrences */ -} IxNpeMhSendStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSendStats ixNpeMhSendStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries); - -/* - * Function definition: ixNpeMhSendInFifoIsFull - */ - -PRIVATE -BOOL ixNpeMhSendInFifoIsFull( - IxNpeMhNpeId npeId, - UINT32 maxSendRetries) -{ - BOOL isFull = false; - UINT32 numRetries = 0; - - /* check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* we retry a few times, just to give the NPE a chance to read from */ - /* the FIFO if the FIFO is currently full */ - while (isFull && (numRetries++ < maxSendRetries)) - { - if (numRetries >= IX_NPEMH_SEND_RETRIES_DEFAULT) - { - /* Delay here for as short a time as possible (1 us). */ - /* Adding a delay here should ensure we are not hogging */ - /* the AHB bus while we are retrying */ - ixOsalBusySleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - } - - /* re-check the NPE's inFIFO */ - isFull = ixNpeMhConfigInFifoIsFull (npeId); - - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFullRetries++; - } - - /* record the highest number of retries that occurred */ - if (ixNpeMhSendStats[npeId].maxQueueFullRetries < numRetries) - { - ixNpeMhSendStats[npeId].maxQueueFullRetries = numRetries; - } - - if (isFull) - { - /* update statistical info */ - ixNpeMhSendStats[npeId].queueFulls++; - } - - return isFull; -} - -/* - * Function definition: ixNpeMhSendMessageSend - */ - -IX_STATUS ixNpeMhSendMessageSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - UINT32 maxSendRetries) -{ - IX_STATUS status; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sends++; - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendMessageWithResponseSend - */ - -IX_STATUS ixNpeMhSendMessageWithResponseSend ( - IxNpeMhNpeId npeId, - IxNpeMhMessage message, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback, - UINT32 maxSendRetries) -{ - IX_STATUS status = IX_SUCCESS; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSendMessageWithResponseSend\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].sendWithResponses++; - - /* sr: this sleep will call the receive routine (no interrupts used!!!) */ - ixOsalSleep (IX_NPEMH_INFIFO_RETRY_DELAY_US); - - /* check if the NPE's inFIFO is full - if so return an error */ - if (ixNpeMhSendInFifoIsFull (npeId, maxSendRetries)) - { - IX_NPEMH_TRACE0 (IX_NPEMH_WARNING, "NPE's inFIFO is full\n"); - return IX_FAIL; - } - - /* save the solicited callback */ - status = ixNpeMhSolicitedCbMgrCallbackSave ( - npeId, solicitedMessageId, solicitedCallback); - if (status != IX_SUCCESS) - { - IX_NPEMH_ERROR_REPORT ("Failed to save solicited callback\n"); - - /* update statistical info */ - ixNpeMhSendStats[npeId].callbackFulls++; - - return status; - } - - /* write the message to the NPE's inFIFO */ - status = ixNpeMhConfigInFifoWrite (npeId, message); - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSendMessageWithResponseSend\n"); - - return status; -} - -/* - * Function definition: ixNpeMhSendShow - */ - -void ixNpeMhSendShow ( - IxNpeMhNpeId npeId) -{ - /* show the message send invocation counter */ - IX_NPEMH_SHOW ("Send invocations", - ixNpeMhSendStats[npeId].sends); - - /* show the message send with response invocation counter */ - IX_NPEMH_SHOW ("Send with response invocations", - ixNpeMhSendStats[npeId].sendWithResponses); - - /* show the fifo queue full occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full occurrences", - ixNpeMhSendStats[npeId].queueFulls); - - /* show the fifo queue full retry occurrence counter */ - IX_NPEMH_SHOW ("Fifo queue full retry occurrences", - ixNpeMhSendStats[npeId].queueFullRetries); - - /* show the fifo queue full maximum retries counter */ - IX_NPEMH_SHOW ("Maximum fifo queue full retries", - ixNpeMhSendStats[npeId].maxQueueFullRetries); - - /* show the callback list full occurrence counter */ - IX_NPEMH_SHOW ("Solicited callback list full occurrences", - ixNpeMhSendStats[npeId].callbackFulls); -} - -/* - * Function definition: ixNpeMhSendShowReset - */ - -void ixNpeMhSendShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the message send invocation counter */ - ixNpeMhSendStats[npeId].sends = 0; - - /* reset the message send with response invocation counter */ - ixNpeMhSendStats[npeId].sendWithResponses = 0; - - /* reset the fifo queue full occurrence counter */ - ixNpeMhSendStats[npeId].queueFulls = 0; - - /* reset the fifo queue full retry occurrence counter */ - ixNpeMhSendStats[npeId].queueFullRetries = 0; - - /* reset the max fifo queue full retries counter */ - ixNpeMhSendStats[npeId].maxQueueFullRetries = 0; - - /* reset the callback list full occurrence counter */ - ixNpeMhSendStats[npeId].callbackFulls = 0; -} diff --git a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c b/drivers/net/npe/IxNpeMhSolicitedCbMgr.c deleted file mode 100644 index c539d090715..00000000000 --- a/drivers/net/npe/IxNpeMhSolicitedCbMgr.c +++ /dev/null @@ -1,334 +0,0 @@ -/** - * @file IxNpeMhSolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for the - * Solicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ -#ifndef IXNPEMHCONFIG_P_H -# define IXNPEMHSOLICITEDCBMGR_C -#else -# error "Error, IxNpeMhConfig_p.h should not be included before this definition." -#endif - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ - -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" -#include "IxNpeMhSolicitedCbMgr_p.h" -#include "IxNpeMhConfig_p.h" -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhSolicitedCallbackListEntry - * - * @brief This structure is used to store the information associated with - * an entry in the callback list. This consists of the ID of the send - * message (which indicates the ID of the corresponding response message) - * and the callback function pointer itself. - * - */ - -typedef struct IxNpeMhSolicitedCallbackListEntry -{ - /** message ID */ - IxNpeMhMessageId messageId; - - /** callback function pointer */ - IxNpeMhCallback callback; - - /** pointer to next entry in the list */ - struct IxNpeMhSolicitedCallbackListEntry *next; -} IxNpeMhSolicitedCallbackListEntry; - -/** - * @struct IxNpeMhSolicitedCallbackList - * - * @brief This structure is used to maintain the list of response - * callbacks. The number of entries in this list will be variable, and - * they will be stored in a linked list fashion for ease of addition and - * removal. The entries themselves are statically allocated, and are - * organised into a "free" list and a "callback" list. Adding an entry - * means taking an entry from the "free" list and adding it to the - * "callback" list. Removing an entry means removing it from the - * "callback" list and returning it to the "free" list. - */ - -typedef struct -{ - /** pointer to the head of the free list */ - IxNpeMhSolicitedCallbackListEntry *freeHead; - - /** pointer to the head of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackHead; - - /** pointer to the tail of the callback list */ - IxNpeMhSolicitedCallbackListEntry *callbackTail; - - /** array of entries - the first entry is used as a dummy entry to */ - /* avoid the scenario of having an empty list, hence '+ 1' */ - IxNpeMhSolicitedCallbackListEntry entries[IX_NPEMH_MAX_CALLBACKS + 1]; -} IxNpeMhSolicitedCallbackList; - -/** - * @struct IxNpeMhSolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Solicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback list saves */ - UINT32 retrieves; /**< callback list retrieves */ -} IxNpeMhSolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhSolicitedCallbackList -ixNpeMhSolicitedCbMgrCallbackLists[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhSolicitedCbMgrStats -ixNpeMhSolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhSolicitedCbMgrInitialize - */ - -void ixNpeMhSolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId; - UINT32 localIndex; - IxNpeMhSolicitedCallbackList *list = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* for each entry in the list, after the dummy entry ... */ - for (localIndex = 1; localIndex <= IX_NPEMH_MAX_CALLBACKS; localIndex++) - { - /* initialise the entry */ - list->entries[localIndex].messageId = 0x00; - list->entries[localIndex].callback = NULL; - - /* if this entry is before the last entry */ - if (localIndex < IX_NPEMH_MAX_CALLBACKS) - { - /* chain this entry to the following entry */ - list->entries[localIndex].next = &(list->entries[localIndex + 1]); - } - else /* this entry is the last entry */ - { - /* the last entry isn't chained to anything */ - list->entries[localIndex].next = NULL; - } - } - - /* set the free list pointer to point to the first real entry */ - /* (all real entries begin chained together on the free list) */ - list->freeHead = &(list->entries[1]); - - /* set the callback list pointers to point to the dummy entry */ - /* (the callback list is initially empty) */ - list->callbackHead = &(list->entries[0]); - list->callbackTail = &(list->entries[0]); - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackSave - */ - -IX_STATUS ixNpeMhSolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* check to see if there are any entries in the free list */ - if (list->freeHead == NULL) - { - IX_NPEMH_ERROR_REPORT ("Solicited callback list is full\n"); - return IX_FAIL; - } - - /* there is an entry in the free list we can use */ - - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].saves++; - - /* remove a callback entry from the start of the free list */ - callbackEntry = list->freeHead; - list->freeHead = callbackEntry->next; - - /* fill in the callback entry with the new data */ - callbackEntry->messageId = solicitedMessageId; - callbackEntry->callback = solicitedCallback; - - /* the new callback entry will be added to the tail of the callback */ - /* list, so it isn't chained to anything */ - callbackEntry->next = NULL; - - /* chain new callback entry to the last entry of the callback list */ - list->callbackTail->next = callbackEntry; - list->callbackTail = callbackEntry; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhSolicitedCbMgrCallbackSave\n"); - - return IX_SUCCESS; -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhSolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId solicitedMessageId, - IxNpeMhCallback *solicitedCallback) -{ - IxNpeMhSolicitedCallbackList *list = NULL; - IxNpeMhSolicitedCallbackListEntry *callbackEntry = NULL; - IxNpeMhSolicitedCallbackListEntry *previousEntry = NULL; - - /* initialise a pointer to the list for convenience */ - list = &ixNpeMhSolicitedCbMgrCallbackLists[npeId]; - - /* initialise the callback entry to the first entry of the callback */ - /* list - we must skip over the dummy entry, which is the previous */ - callbackEntry = list->callbackHead->next; - previousEntry = list->callbackHead; - - /* traverse the callback list looking for an entry with a matching */ - /* message ID. note we also save the previous entry's pointer to */ - /* allow us to unchain the matching entry from the callback list */ - while ((callbackEntry != NULL) && - (callbackEntry->messageId != solicitedMessageId)) - { - previousEntry = callbackEntry; - callbackEntry = callbackEntry->next; - } - - /* if we didn't find a matching callback entry */ - if (callbackEntry == NULL) - { - /* return a NULL callback in the outgoing parameter */ - *solicitedCallback = NULL; - } - else /* we found a matching callback entry */ - { - /* update statistical info */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves++; - - /* return the callback in the outgoing parameter */ - *solicitedCallback = callbackEntry->callback; - - /* unchain callback entry by chaining previous entry to next */ - previousEntry->next = callbackEntry->next; - - /* if the callback entry is at the tail of the list */ - if (list->callbackTail == callbackEntry) - { - /* update the tail of the callback list */ - list->callbackTail = previousEntry; - } - - /* re-initialise the callback entry */ - callbackEntry->messageId = 0x00; - callbackEntry->callback = NULL; - - /* add the callback entry to the start of the free list */ - callbackEntry->next = list->freeHead; - list->freeHead = callbackEntry; - } -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShow - */ - -void ixNpeMhSolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the solicited callback list save counter */ - IX_NPEMH_SHOW ("Solicited callback list saves", - ixNpeMhSolicitedCbMgrStats[npeId].saves); - - /* show the solicited callback list retrieve counter */ - IX_NPEMH_SHOW ("Solicited callback list retrieves", - ixNpeMhSolicitedCbMgrStats[npeId].retrieves); -} - -/* - * Function definition: ixNpeMhSolicitedCbMgrShowReset - */ - -void ixNpeMhSolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the solicited callback list save counter */ - ixNpeMhSolicitedCbMgrStats[npeId].saves = 0; - - /* reset the solicited callback list retrieve counter */ - ixNpeMhSolicitedCbMgrStats[npeId].retrieves = 0; -} diff --git a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c b/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c deleted file mode 100644 index 082f677e62e..00000000000 --- a/drivers/net/npe/IxNpeMhUnsolicitedCbMgr.c +++ /dev/null @@ -1,222 +0,0 @@ -/** - * @file IxNpeMhUnsolicitedCbMgr.c - * - * @author Intel Corporation - * @date 18 Jan 2002 - * - * @brief This file contains the implementation of the private API for - * the Unsolicited Callback Manager module. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Put the system defined include files required. - */ - - -/* - * Put the user defined include files required. - */ -#include "IxOsal.h" - -#include "IxNpeMhMacros_p.h" - -#include "IxNpeMhUnsolicitedCbMgr_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @struct IxNpeMhUnsolicitedCallbackTable - * - * @brief This structure is used to maintain the list of registered - * callbacks. One entry exists for each message ID, and a NULL entry will - * signify that no callback has been registered for that ID. - */ - -typedef struct -{ - /** array of entries */ - IxNpeMhCallback entries[IX_NPEMH_MAX_MESSAGE_ID + 1]; -} IxNpeMhUnsolicitedCallbackTable; - -/** - * @struct IxNpeMhUnsolicitedCbMgrStats - * - * @brief This structure is used to maintain statistics for the Unsolicited - * Callback Manager module. - */ - -typedef struct -{ - UINT32 saves; /**< callback table saves */ - UINT32 overwrites; /**< callback table overwrites */ -} IxNpeMhUnsolicitedCbMgrStats; - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -PRIVATE IxNpeMhUnsolicitedCallbackTable -ixNpeMhUnsolicitedCallbackTables[IX_NPEMH_NUM_NPES]; - -PRIVATE IxNpeMhUnsolicitedCbMgrStats -ixNpeMhUnsolicitedCbMgrStats[IX_NPEMH_NUM_NPES]; - -/* - * Extern function prototypes. - */ - -/* - * Static function prototypes. - */ - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrInitialize - */ - -void ixNpeMhUnsolicitedCbMgrInitialize (void) -{ - IxNpeMhNpeId npeId = 0; - IxNpeMhUnsolicitedCallbackTable *table = NULL; - IxNpeMhMessageId messageId = 0; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); - - /* for each NPE ... */ - for (npeId = 0; npeId < IX_NPEMH_NUM_NPES; npeId++) - { - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* for each message ID ... */ - for (messageId = IX_NPEMH_MIN_MESSAGE_ID; - messageId <= IX_NPEMH_MAX_MESSAGE_ID; messageId++) - { - /* initialise the callback for this message ID to NULL */ - table->entries[messageId] = NULL; - } - } - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrInitialize\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackSave - */ - -void ixNpeMhUnsolicitedCbMgrCallbackSave ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Entering " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves++; - - /* check if there is a callback already registered for this NPE and */ - /* message ID */ - if (table->entries[unsolicitedMessageId] != NULL) - { - /* if we are overwriting an existing callback */ - if (unsolicitedCallback != NULL) - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "Unsolicited callback " - "overwriting existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - else /* if we are clearing an existing callback */ - { - IX_NPEMH_TRACE2 (IX_NPEMH_DEBUG, "NULL unsolicited callback " - "clearing existing callback for NPE ID %d " - "message ID 0x%02X\n", npeId, unsolicitedMessageId); - } - - /* update statistical info */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites++; - } - - /* save the callback into the table */ - table->entries[unsolicitedMessageId] = unsolicitedCallback; - - IX_NPEMH_TRACE0 (IX_NPEMH_FN_ENTRY_EXIT, "Exiting " - "ixNpeMhUnsolicitedCbMgrCallbackSave\n"); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrCallbackRetrieve - */ - -void ixNpeMhUnsolicitedCbMgrCallbackRetrieve ( - IxNpeMhNpeId npeId, - IxNpeMhMessageId unsolicitedMessageId, - IxNpeMhCallback *unsolicitedCallback) -{ - IxNpeMhUnsolicitedCallbackTable *table = NULL; - - /* initialise a pointer to the table for convenience */ - table = &ixNpeMhUnsolicitedCallbackTables[npeId]; - - /* retrieve the callback from the table */ - *unsolicitedCallback = table->entries[unsolicitedMessageId]; -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShow - */ - -void ixNpeMhUnsolicitedCbMgrShow ( - IxNpeMhNpeId npeId) -{ - /* show the unsolicited callback table save counter */ - IX_NPEMH_SHOW ("Unsolicited callback table saves", - ixNpeMhUnsolicitedCbMgrStats[npeId].saves); - - /* show the unsolicited callback table overwrite counter */ - IX_NPEMH_SHOW ("Unsolicited callback table overwrites", - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites); -} - -/* - * Function definition: ixNpeMhUnsolicitedCbMgrShowReset - */ - -void ixNpeMhUnsolicitedCbMgrShowReset ( - IxNpeMhNpeId npeId) -{ - /* reset the unsolicited callback table save counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].saves = 0; - - /* reset the unsolicited callback table overwrite counter */ - ixNpeMhUnsolicitedCbMgrStats[npeId].overwrites = 0; -} diff --git a/drivers/net/npe/IxOsalBufferMgt.c b/drivers/net/npe/IxOsalBufferMgt.c deleted file mode 100644 index f70ba05d9e1..00000000000 --- a/drivers/net/npe/IxOsalBufferMgt.c +++ /dev/null @@ -1,776 +0,0 @@ -/** - * @file IxOsalBufferMgt.c - * - * @brief Default buffer pool management and buffer management - * Implementation. - * - * Design Notes: - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* - * OS may choose to use default bufferMgt by defining - * IX_OSAL_USE_DEFAULT_BUFFER_MGT in IxOsalOsBufferMgt.h - */ - -#include "IxOsal.h" - -#define IX_OSAL_BUFFER_FREE_PROTECTION /* Define this to enable Illegal MBuf Freed Protection*/ - -/* - * The implementation is only used when the following - * is defined. - */ -#ifdef IX_OSAL_USE_DEFAULT_BUFFER_MGT - - -#define IX_OSAL_MBUF_SYS_SIGNATURE (0x8BADF00D) -#define IX_OSAL_MBUF_SYS_SIGNATURE_MASK (0xEFFFFFFF) -#define IX_OSAL_MBUF_USED_FLAG (0x10000000) -#define IX_OSAL_MBUF_SYS_SIGNATURE_INIT(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = (UINT32)IX_OSAL_MBUF_SYS_SIGNATURE - -/* -* This implementation is protect, the buffer pool management's ixOsalMBufFree -* against an invalid MBUF pointer argument that already has been freed earlier -* or in other words resides in the free pool of MBUFs. This added feature, -* checks the MBUF "USED" FLAG. The Flag tells if the MBUF is still not freed -* back to the Buffer Pool. -* Disable this feature for performance reasons by undef -* IX_OSAL_BUFFER_FREE_PROTECTION macro. -*/ -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&(IX_OSAL_MBUF_SYS_SIGNATURE_MASK) ) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) do { \ - IX_OSAL_MBUF_SIGNATURE (bufPtr)&(~IX_OSAL_MBUF_SYS_SIGNATURE_MASK);\ - IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_SYS_SIGNATURE; \ - }while(0) - -#define IX_OSAL_MBUF_SET_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)|=IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr)&=~IX_OSAL_MBUF_USED_FLAG -#define IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr) (IX_OSAL_MBUF_SIGNATURE (bufPtr)&IX_OSAL_MBUF_USED_FLAG) - -#else - -#define IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) -#define IX_OSAL_MBUF_SET_SYS_SIGNATURE(bufPtr) IX_OSAL_MBUF_SIGNATURE (bufPtr) = IX_OSAL_MBUF_SYS_SIGNATURE - -#endif /*IX_OSAL_BUFFER_FREE_PROTECTION With Buffer Free protection*/ -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * A unit of 32, used to provide bit-shift for pool - * management. Needs some work if users want more than 32 pools. - */ -#define IX_OSAL_BUFF_FREE_BITS 32 - -PRIVATE UINT32 ixOsalBuffFreePools[IX_OSAL_MBUF_MAX_POOLS / - IX_OSAL_BUFF_FREE_BITS]; - -PUBLIC IX_OSAL_MBUF_POOL ixOsalBuffPools[IX_OSAL_MBUF_MAX_POOLS]; - -static int ixOsalBuffPoolsInUse = 0; - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr); -#endif - -PRIVATE IX_OSAL_MBUF_POOL * ixOsalPoolAlloc (void); - -/* - * Function definition: ixOsalPoolAlloc - */ - -/****************************/ - -PRIVATE IX_OSAL_MBUF_POOL * -ixOsalPoolAlloc (void) -{ - register unsigned int i = 0; - - /* - * Scan for the first free buffer. Free buffers are indicated by 0 - * on the corrsponding bit in ixOsalBuffFreePools. - */ - if (ixOsalBuffPoolsInUse >= IX_OSAL_MBUF_MAX_POOLS) - { - /* - * Fail to grab a ptr this time - */ - return NULL; - } - - while (ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] & - (1 << (i % IX_OSAL_BUFF_FREE_BITS))) - i++; - /* - * Free buffer found. Mark it as busy and initialize. - */ - ixOsalBuffFreePools[i / IX_OSAL_BUFF_FREE_BITS] |= - (1 << (i % IX_OSAL_BUFF_FREE_BITS)); - - memset (&ixOsalBuffPools[i], 0, sizeof (IX_OSAL_MBUF_POOL)); - - ixOsalBuffPools[i].poolIdx = i; - ixOsalBuffPoolsInUse++; - - return &ixOsalBuffPools[i]; -} - - -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY -PRIVATE IX_OSAL_MBUF * -ixOsalBuffPoolMbufInit (UINT32 mbufSizeAligned, - UINT32 dataSizeAligned, - IX_OSAL_MBUF_POOL *poolPtr) -{ - UINT8 *dataPtr; - IX_OSAL_MBUF *realMbufPtr; - /* Allocate cache-aligned memory for mbuf header */ - realMbufPtr = (IX_OSAL_MBUF *) IX_OSAL_CACHE_DMA_MALLOC (mbufSizeAligned); - IX_OSAL_ASSERT (realMbufPtr != NULL); - memset (realMbufPtr, 0, mbufSizeAligned); - - /* Allocate cache-aligned memory for mbuf data */ - dataPtr = (UINT8 *) IX_OSAL_CACHE_DMA_MALLOC (dataSizeAligned); - IX_OSAL_ASSERT (dataPtr != NULL); - memset (dataPtr, 0, dataSizeAligned); - - /* Fill in mbuf header fields */ - IX_OSAL_MBUF_MDATA (realMbufPtr) = dataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (realMbufPtr) = (UINT32)dataPtr; - - IX_OSAL_MBUF_MLEN (realMbufPtr) = dataSizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN (realMbufPtr) = dataSizeAligned; - - IX_OSAL_MBUF_NET_POOL (realMbufPtr) = (IX_OSAL_MBUF_POOL *) poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(realMbufPtr); - - /* update some statistical information */ - poolPtr->mbufMemSize += mbufSizeAligned; - poolPtr->dataMemSize += dataSizeAligned; - - return realMbufPtr; -} -#endif /* #ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - -/* - * Function definition: ixOsalBuffPoolInit - */ - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalPoolInit (UINT32 count, UINT32 size, const char *name) -{ - - /* These variables are only used if UX_OSAL_BUFFER_ALLOC_SEPERATELY - * is defined . - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i, mbufSizeAligned, dataSizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; -#else - void *poolBufPtr; - void *poolDataPtr; - int mbufMemSize; - int dataMemSize; -#endif - - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "count = 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "NULL name \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - -/* OS can choose whether to allocate all buffers all together (if it - * can handle a huge single alloc request), or to allocate buffers - * separately by the defining IX_OSAL_BUFFER_ALLOC_SEPARATELY. - */ -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - /* Get a pool Ptr */ - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to Get PoolPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - mbufSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - dataSizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN(size); - - poolPtr->nextFreeBuf = NULL; - poolPtr->mbufMemPtr = NULL; - poolPtr->dataMemPtr = NULL; - poolPtr->bufDataSize = dataSizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - strcpy (poolPtr->name, name); - - - for (i = 0; i < count; i++) - { - /* create an mbuf */ - currentMbufPtr = ixOsalBuffPoolMbufInit (mbufSizeAligned, - dataSizeAligned, - poolPtr); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION -/* Set the Buffer USED Flag. If not, ixOsalMBufFree will fail. - ixOsalMbufFree used here is in a special case whereby, it's - used to add MBUF to the Pool. By specification, ixOsalMbufFree - deallocates an allocated MBUF from Pool. -*/ - IX_OSAL_MBUF_SET_USED_FLAG(currentMbufPtr); -#endif - /* Add it to the pool */ - ixOsalMbufFree (currentMbufPtr); - - /* flush the pool information to RAM */ - IX_OSAL_CACHE_FLUSH (currentMbufPtr, mbufSizeAligned); - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - -#else -/* Otherwise allocate buffers in a continuous block fashion */ - poolBufPtr = IX_OSAL_MBUF_POOL_MBUF_AREA_ALLOC (count, mbufMemSize); - IX_OSAL_ASSERT (poolBufPtr != NULL); - poolDataPtr = - IX_OSAL_MBUF_POOL_DATA_AREA_ALLOC (count, size, dataMemSize); - IX_OSAL_ASSERT (poolDataPtr != NULL); - - poolPtr = ixOsalNoAllocPoolInit (poolBufPtr, poolDataPtr, - count, size, name); - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalPoolInit(): " "Fail to get pool ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC; - -#endif /* IX_OSAL_BUFFER_ALLOC_SEPARATELY */ - return poolPtr; -} - -PUBLIC IX_OSAL_MBUF_POOL * -ixOsalNoAllocPoolInit (void *poolBufPtr, - void *poolDataPtr, UINT32 count, UINT32 size, const char *name) -{ - UINT32 i, mbufSizeAligned, sizeAligned; - IX_OSAL_MBUF *currentMbufPtr = NULL; - IX_OSAL_MBUF *nextMbufPtr = NULL; - IX_OSAL_MBUF_POOL *poolPtr = NULL; - - /* - * check parameters - */ - if (poolBufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL poolBufPtr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (count <= 0) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - count must > 0 \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (name == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - NULL name ptr \n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - if (strlen (name) > IX_OSAL_MBUF_POOL_NAME_LEN) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalNoAllocPoolInit(): " - "ERROR - name length should be no greater than %d \n", - IX_OSAL_MBUF_POOL_NAME_LEN, 0, 0, 0, 0, 0); - return NULL; - } - - poolPtr = ixOsalPoolAlloc (); - - if (poolPtr == NULL) - { - return NULL; - } - - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - mbufSizeAligned = - IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - /* - * clear the mbuf memory area - */ - memset (poolBufPtr, 0, mbufSizeAligned * count); - - if (poolDataPtr != NULL) - { - /* - * Adjust sizes to ensure alignment on cache line boundaries - */ - sizeAligned = IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - /* - * clear the data memory area - */ - memset (poolDataPtr, 0, sizeAligned * count); - } - else - { - sizeAligned = 0; - } - - /* - * initialise pool fields - */ - strcpy ((poolPtr)->name, name); - - poolPtr->dataMemPtr = poolDataPtr; - poolPtr->mbufMemPtr = poolBufPtr; - poolPtr->bufDataSize = sizeAligned; - poolPtr->totalBufsInPool = count; - poolPtr->mbufMemSize = mbufSizeAligned * count; - poolPtr->dataMemSize = sizeAligned * count; - - currentMbufPtr = (IX_OSAL_MBUF *) poolBufPtr; - - poolPtr->nextFreeBuf = currentMbufPtr; - - for (i = 0; i < count; i++) - { - if (i < (count - 1)) - { - nextMbufPtr = - (IX_OSAL_MBUF *) ((unsigned) currentMbufPtr + - mbufSizeAligned); - } - else - { /* last mbuf in chain */ - nextMbufPtr = NULL; - } - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (currentMbufPtr) = nextMbufPtr; - IX_OSAL_MBUF_NET_POOL (currentMbufPtr) = poolPtr; - - IX_OSAL_MBUF_SYS_SIGNATURE_INIT(currentMbufPtr); - - if (poolDataPtr != NULL) - { - IX_OSAL_MBUF_MDATA (currentMbufPtr) = poolDataPtr; - IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(currentMbufPtr) = (UINT32) poolDataPtr; - - IX_OSAL_MBUF_MLEN (currentMbufPtr) = sizeAligned; - IX_OSAL_MBUF_ALLOCATED_BUFF_LEN(currentMbufPtr) = sizeAligned; - - poolDataPtr = (void *) ((unsigned) poolDataPtr + sizeAligned); - } - - currentMbufPtr = nextMbufPtr; - } - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool = count; - - poolPtr->poolAllocType = IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC; - - return poolPtr; -} - -/* - * Get a mbuf ptr from the pool - */ -PUBLIC IX_OSAL_MBUF * -ixOsalMbufAlloc (IX_OSAL_MBUF_POOL * poolPtr) -{ - int lock; - IX_OSAL_MBUF *newBufPtr = NULL; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufAlloc(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - lock = ixOsalIrqLock (); - - newBufPtr = poolPtr->nextFreeBuf; - if (newBufPtr) - { - poolPtr->nextFreeBuf = - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr); - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (newBufPtr) = NULL; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool--; - } - else - { - /* Return NULL to indicate to caller that request is denied. */ - ixOsalIrqUnlock (lock); - - return NULL; - } - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - /* Set Buffer Used Flag to indicate state.*/ - IX_OSAL_MBUF_SET_USED_FLAG(newBufPtr); -#endif - - ixOsalIrqUnlock (lock); - - return newBufPtr; -} - -PUBLIC IX_OSAL_MBUF * -ixOsalMbufFree (IX_OSAL_MBUF * bufPtr) -{ - int lock; - IX_OSAL_MBUF_POOL *poolPtr; - - IX_OSAL_MBUF *nextBufPtr = NULL; - - /* - * check parameters - */ - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalMbufFree(): " - "ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return NULL; - } - - - - lock = ixOsalIrqLock (); - -#ifdef IX_OSAL_BUFFER_FREE_PROTECTION - - /* Prevention for Buffer freed more than once*/ - if(!IX_OSAL_MBUF_ISSET_USED_FLAG(bufPtr)) - { - return NULL; - } - IX_OSAL_MBUF_CLEAR_USED_FLAG(bufPtr); -#endif - - poolPtr = IX_OSAL_MBUF_NET_POOL (bufPtr); - - /* - * check the mbuf wrapper signature (if mbuf wrapper was used) - */ - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - IX_OSAL_ENSURE ( (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) == IX_OSAL_MBUF_SYS_SIGNATURE), - "ixOsalBuffPoolBufFree: ERROR - Invalid mbuf signature."); - } - - nextBufPtr = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr); - - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR (bufPtr) = poolPtr->nextFreeBuf; - poolPtr->nextFreeBuf = bufPtr; - - /* - * update the number of free buffers in the pool - */ - poolPtr->freeBufsInPool++; - - ixOsalIrqUnlock (lock); - - return nextBufPtr; -} - -PUBLIC void -ixOsalMbufChainFree (IX_OSAL_MBUF * bufPtr) -{ - while ((bufPtr = ixOsalMbufFree (bufPtr))); -} - -/* - * Function definition: ixOsalBuffPoolShow - */ -PUBLIC void -ixOsalMbufPoolShow (IX_OSAL_MBUF_POOL * poolPtr) -{ - IX_OSAL_MBUF *nextBufPtr; - int count = 0; - int lock; - - /* - * check parameters - */ - if (poolPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolShow(): " - "ERROR - Invalid Parameter", 0, 0, 0, 0, 0, 0); - /* - * return IX_FAIL; - */ - return; - } - - lock = ixOsalIrqLock (); - count = poolPtr->freeBufsInPool; - nextBufPtr = poolPtr->nextFreeBuf; - ixOsalIrqUnlock (lock); - - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, "=== POOL INFORMATION ===\n", 0, 0, 0, - 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Name: %s\n", - (unsigned int) poolPtr->name, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Allocation Type: %d\n", - (unsigned int) poolPtr->poolAllocType, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Mbuf Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->mbufMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Pool Data Mem Usage (bytes): %d\n", - (unsigned int) poolPtr->dataMemSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Data Capacity (bytes): %d\n", - (unsigned int) poolPtr->bufDataSize, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Total Mbufs in Pool: %d\n", - (unsigned int) poolPtr->totalBufsInPool, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Available Mbufs: %d\n", (unsigned int) count, 0, - 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Next Available Mbuf: %p\n", (unsigned int) nextBufPtr, - 0, 0, 0, 0, 0); - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_USER_ALLOC) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "Mbuf Mem Area Start address: %p\n", - (unsigned int) poolPtr->mbufMemPtr, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, - "Data Mem Area Start address: %p\n", - (unsigned int) poolPtr->dataMemPtr, 0, 0, 0, 0, 0); - } -} - -PUBLIC void -ixOsalMbufDataPtrReset (IX_OSAL_MBUF * bufPtr) -{ - IX_OSAL_MBUF_POOL *poolPtr; - UINT8 *poolDataPtr; - - if (bufPtr == NULL) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": ERROR - Invalid Parameter\n", 0, 0, 0, 0, 0, 0); - return; - } - - poolPtr = (IX_OSAL_MBUF_POOL *) IX_OSAL_MBUF_NET_POOL (bufPtr); - poolDataPtr = poolPtr->dataMemPtr; - - if (poolPtr->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { - if (IX_OSAL_MBUF_GET_SYS_SIGNATURE(bufPtr) != IX_OSAL_MBUF_SYS_SIGNATURE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": invalid mbuf, cannot reset mData pointer\n", 0, 0, - 0, 0, 0, 0); - return; - } - IX_OSAL_MBUF_MDATA (bufPtr) = (UINT8*)IX_OSAL_MBUF_ALLOCATED_BUFF_DATA (bufPtr); - } - else - { - if (poolDataPtr) - { - unsigned int bufSize = poolPtr->bufDataSize; - unsigned int bufDataAddr = - (unsigned int) IX_OSAL_MBUF_MDATA (bufPtr); - unsigned int poolDataAddr = (unsigned int) poolDataPtr; - - /* - * the pointer is still pointing somewhere in the mbuf payload. - * This operation moves the pointer to the beginning of the - * mbuf payload - */ - bufDataAddr = ((bufDataAddr - poolDataAddr) / bufSize) * bufSize; - IX_OSAL_MBUF_MDATA (bufPtr) = &poolDataPtr[bufDataAddr]; - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolBufDataPtrReset" - ": cannot be used if user supplied NULL pointer for pool data area " - "when pool was created\n", 0, 0, 0, 0, 0, 0); - return; - } - } - -} - -/* - * Function definition: ixOsalBuffPoolUninit - */ -PUBLIC IX_STATUS -ixOsalBuffPoolUninit (IX_OSAL_MBUF_POOL * pool) -{ - if (!pool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: NULL ptr \n", 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->freeBufsInPool != pool->totalBufsInPool) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, - "ixOsalBuffPoolUninit: need to return all ptrs to the pool first! \n", - 0, 0, 0, 0, 0, 0); - return IX_FAIL; - } - - if (pool->poolAllocType == IX_OSAL_MBUF_POOL_TYPE_SYS_ALLOC) - { -#ifdef IX_OSAL_BUFFER_ALLOC_SEPARATELY - UINT32 i; - IX_OSAL_MBUF* pBuf; - - pBuf = pool->nextFreeBuf; - /* Freed the Buffer one by one till all the Memory is freed*/ - for (i= pool->freeBufsInPool; i >0 && pBuf!=NULL ;i--){ - IX_OSAL_MBUF* pBufTemp; - pBufTemp = IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(pBuf); - /* Freed MBUF Data Memory area*/ - IX_OSAL_CACHE_DMA_FREE( (void *) (IX_OSAL_MBUF_ALLOCATED_BUFF_DATA(pBuf)) ); - /* Freed MBUF Struct Memory area*/ - IX_OSAL_CACHE_DMA_FREE(pBuf); - pBuf = pBufTemp; - } - -#else - IX_OSAL_CACHE_DMA_FREE (pool->mbufMemPtr); - IX_OSAL_CACHE_DMA_FREE (pool->dataMemPtr); -#endif - } - - ixOsalBuffFreePools[pool->poolIdx / IX_OSAL_BUFF_FREE_BITS] &= - ~(1 << (pool->poolIdx % IX_OSAL_BUFF_FREE_BITS)); - ixOsalBuffPoolsInUse--; - return IX_SUCCESS; -} - -/* - * Function definition: ixOsalBuffPoolDataAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolDataAreaSizeGet (int count, int size) -{ - UINT32 memorySize; - memorySize = count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (size); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolMbufAreaSizeGet - */ -PUBLIC UINT32 -ixOsalBuffPoolMbufAreaSizeGet (int count) -{ - UINT32 memorySize; - memorySize = - count * IX_OSAL_MBUF_POOL_SIZE_ALIGN (sizeof (IX_OSAL_MBUF)); - return memorySize; -} - -/* - * Function definition: ixOsalBuffPoolFreeCountGet - */ -PUBLIC UINT32 ixOsalBuffPoolFreeCountGet(IX_OSAL_MBUF_POOL * poolPtr) - -{ - - return poolPtr->freeBufsInPool; - -} - -#endif /* IX_OSAL_USE_DEFAULT_BUFFER_MGT */ diff --git a/drivers/net/npe/IxOsalIoMem.c b/drivers/net/npe/IxOsalIoMem.c deleted file mode 100644 index bf3acdc10c2..00000000000 --- a/drivers/net/npe/IxOsalIoMem.c +++ /dev/null @@ -1,307 +0,0 @@ -/** - * @file IxOsalIoMem.c - * - * @brief OS-independent IO/Mem implementation - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* Access to the global mem map is only allowed in this file */ -#define IxOsalIoMem_C - -#include "IxOsal.h" - -#define SEARCH_PHYSICAL_ADDRESS (1) -#define SEARCH_VIRTUAL_ADDRESS (2) - -/* - * Searches for map using one of the following criteria: - * - * - enough room to include a zone starting with the physical "requestedAddress" of size "size" (for mapping) - * - includes the virtual "requestedAddress" in its virtual address space (already mapped, for unmapping) - * - correct coherency - * - * Returns a pointer to the map or NULL if a suitable map is not found. - */ -PRIVATE IxOsalMemoryMap * -ixOsalMemMapFind (UINT32 requestedAddress, - UINT32 size, UINT32 searchCriteria, UINT32 requestedEndianType) -{ - UINT32 mapIndex; - - UINT32 numMapElements = ARRAY_SIZE(ixOsalGlobalMemoryMap); - - for (mapIndex = 0; mapIndex < numMapElements; mapIndex++) - { - IxOsalMemoryMap *map = &ixOsalGlobalMemoryMap[mapIndex]; - - if (searchCriteria == SEARCH_PHYSICAL_ADDRESS - && requestedAddress >= map->physicalAddress - && (requestedAddress + size) <= (map->physicalAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_VIRTUAL_ADDRESS - && requestedAddress >= map->virtualAddress - && requestedAddress <= (map->virtualAddress + map->size) - && (map->mapEndianType & requestedEndianType) != 0) - { - return map; - } - else if (searchCriteria == SEARCH_PHYSICAL_ADDRESS) - { - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "Osal: Checking [phys addr 0x%x:size 0x%x:endianType %d]\n", - map->physicalAddress, map->size, map->mapEndianType, 0, 0, 0); - } - } - - /* - * not found - */ - return NULL; -} - -/* - * This function maps an I/O mapped physical memory zone of the given size - * into a virtual memory zone accessible by the caller and returns a cookie - - * the start address of the virtual memory zone. - * IX_OSAL_MMAP_PHYS_TO_VIRT should NOT therefore be used on the returned - * virtual address. - * The memory zone is to be unmapped using ixOsalMemUnmap once the caller has - * finished using this zone (e.g. on driver unload) using the cookie as - * parameter. - * The IX_OSAL_READ/WRITE_LONG/SHORT macros should be used to read and write - * the mapped memory, adding the necessary offsets to the address cookie. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_MAP - * instead. - */ -PUBLIC void * -ixOsalIoMemMap (UINT32 requestedAddress, - UINT32 size, IxOsalMapEndianessType requestedEndianType) -{ - IxOsalMemoryMap *map; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - "OSAL: Mapping [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - if (requestedEndianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemMap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return (NULL); - } - map = ixOsalMemMapFind (requestedAddress, - size, SEARCH_PHYSICAL_ADDRESS, requestedEndianType); - if (map != NULL) - { - UINT32 offset = requestedAddress - map->physicalAddress; - - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, "OSAL: Found map [", 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, map->name, 0, 0, 0, 0, 0, 0); - ixOsalLog (IX_OSAL_LOG_LVL_DEBUG3, - IX_OSAL_LOG_DEV_STDOUT, - ":addr 0x%x: virt 0x%x:size 0x%x:ref %d:endianType %d]\n", - map->physicalAddress, map->virtualAddress, - map->size, map->refCount, map->mapEndianType, 0); - - if (map->type == IX_OSAL_DYNAMIC_MAP && map->virtualAddress == 0) - { - if (map->mapFunction != NULL) - { - map->mapFunction (map); - - if (map->virtualAddress == 0) - { - /* - * failed - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: Remap failed - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; - } - } - else - { - /* - * error, no map function for a dynamic map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No map function for a dynamic map - " - "[addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - - return NULL; - } - } - - /* - * increment reference count - */ - map->refCount++; - - return (void *) (map->virtualAddress + offset); - } - - /* - * requested address is not described in the global memory map - */ - ixOsalLog (IX_OSAL_LOG_LVL_FATAL, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: No mapping found - [addr 0x%x:size 0x%x:endianType %d]\n", - requestedAddress, size, requestedEndianType, 0, 0, 0); - return NULL; -} - -/* - * This function unmaps a previously mapped I/O memory zone using - * the cookie obtained in the mapping operation. The memory zone in question - * becomes unavailable to the caller once unmapped and the cookie should be - * discarded. - * - * This function cannot fail if the given parameter is correct and does not - * return a value. - * - * Note: this function is not to be used directly. Use IX_OSAL_MEM_UNMAP - * instead. - */ -PUBLIC void -ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType) -{ - IxOsalMemoryMap *map; - - if (endianType == IX_OSAL_LE) - { - ixOsalLog (IX_OSAL_LOG_LVL_ERROR, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalIoMemUnmap: Please specify component coherency mode to use MEM functions \n", - 0, 0, 0, 0, 0, 0); - return; - } - - if (requestedAddress == 0) - { - /* - * invalid virtual address - */ - return; - } - - map = - ixOsalMemMapFind (requestedAddress, 0, SEARCH_VIRTUAL_ADDRESS, - endianType); - - if (map != NULL) - { - if (map->refCount > 0) - { - /* - * decrement reference count - */ - map->refCount--; - - if (map->refCount == 0) - { - /* - * no longer used, deallocate - */ - if (map->type == IX_OSAL_DYNAMIC_MAP - && map->unmapFunction != NULL) - { - map->unmapFunction (map); - } - } - } - } - else - { - ixOsalLog (IX_OSAL_LOG_LVL_WARNING, - IX_OSAL_LOG_DEV_STDERR, - "OSAL: ixOsServMemUnmap didn't find the requested map " - "[virt addr 0x%x: endianType %d], ignoring call\n", - requestedAddress, endianType, 0, 0, 0, 0); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (virtualAddress, 0, SEARCH_VIRTUAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->physicalAddress + virtualAddress - map->virtualAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS (virtualAddress); - } -} - -/* - * This function Converts a virtual address into a physical - * address, including the dynamically mapped memory. - * - * Parameters virtAddr - virtual address to convert - * Return value: corresponding physical address, or NULL - * if there is no physical address addressable - * by the given virtual address - * OS: VxWorks, Linux, WinCE, QNX, eCos - * Reentrant: Yes - * IRQ safe: Yes - */ -PUBLIC UINT32 -ixOsalIoMemPhysToVirt (UINT32 physicalAddress, UINT32 requestedCoherency) -{ - IxOsalMemoryMap *map = - ixOsalMemMapFind (physicalAddress, 0, SEARCH_PHYSICAL_ADDRESS, - requestedCoherency); - - if (map != NULL) - { - return map->virtualAddress + physicalAddress - map->physicalAddress; - } - else - { - return (UINT32) IX_OSAL_MMU_PHYS_TO_VIRT (physicalAddress); - } -} diff --git a/drivers/net/npe/IxOsalOsCacheMMU.c b/drivers/net/npe/IxOsalOsCacheMMU.c deleted file mode 100644 index 72d22e5882c..00000000000 --- a/drivers/net/npe/IxOsalOsCacheMMU.c +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file IxOsalOsCacheMMU.c (linux) - * - * @brief Cache MemAlloc and MemFree. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -#include - -/* - * Allocate on a cache line boundary (null pointers are - * not affected by this operation). This operation is NOT cache safe. - */ -void * -ixOsalCacheDmaMalloc (UINT32 n) -{ - return malloc(n); -} - -/* - * - */ -void -ixOsalCacheDmaFree (void *ptr) -{ - free(ptr); -} diff --git a/drivers/net/npe/IxOsalOsMsgQ.c b/drivers/net/npe/IxOsalOsMsgQ.c deleted file mode 100644 index 5fe368bdafd..00000000000 --- a/drivers/net/npe/IxOsalOsMsgQ.c +++ /dev/null @@ -1,55 +0,0 @@ -/** - * @file IxOsalOsMsgQ.c (eCos) - * - * @brief OS-specific Message Queue implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/******************************* - * Public functions - *******************************/ -PUBLIC IX_STATUS -ixOsalMessageQueueCreate (IxOsalMessageQueue * queue, - UINT32 msgCount, UINT32 msgLen) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueDelete (IxOsalMessageQueue * queue) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueSend (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMessageQueueReceive (IxOsalMessageQueue * queue, UINT8 * message) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - diff --git a/drivers/net/npe/IxOsalOsSemaphore.c b/drivers/net/npe/IxOsalOsSemaphore.c deleted file mode 100644 index 33de7f6e420..00000000000 --- a/drivers/net/npe/IxOsalOsSemaphore.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - * @file IxOsalOsSemaphore.c (eCos) - * - * @brief Implementation for semaphore and mutex. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" -#include "IxNpeMhReceive_p.h" - -/* Define a large number */ -#define IX_OSAL_MAX_LONG (0x7FFFFFFF) - -/* Max timeout in MS, used to guard against possible overflow */ -#define IX_OSAL_MAX_TIMEOUT_MS (IX_OSAL_MAX_LONG/HZ) - - -PUBLIC IX_STATUS -ixOsalSemaphoreInit (IxOsalSemaphore * sid, UINT32 start_value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/** - * DESCRIPTION: If the semaphore is 'empty', the calling thread is blocked. - * If the semaphore is 'full', it is taken and control is returned - * to the caller. If the time indicated in 'timeout' is reached, - * the thread will unblock and return an error indication. If the - * timeout is set to 'IX_OSAL_WAIT_NONE', the thread will never block; - * if it is set to 'IX_OSAL_WAIT_FOREVER', the thread will block until - * the semaphore is available. - * - * - */ - - -PUBLIC IX_STATUS -ixOsalSemaphoreWait (IxOsalOsSemaphore * sid, INT32 timeout) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -/* - * Attempt to get semaphore, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalSemaphoreTryWait (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/** - * - * DESCRIPTION: This function causes the next available thread in the pend queue - * to be unblocked. If no thread is pending on this semaphore, the - * semaphore becomes 'full'. - */ -PUBLIC IX_STATUS -ixOsalSemaphorePost (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreGetValue (IxOsalSemaphore * sid, UINT32 * value) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalSemaphoreDestroy (IxOsalSemaphore * sid) -{ - diag_printf("%s called\n", __FUNCTION__); - return IX_FAIL; -} - -/**************************** - * Mutex - ****************************/ - -static void drv_mutex_init(IxOsalMutex *mutex) -{ - *mutex = 0; -} - -static void drv_mutex_destroy(IxOsalMutex *mutex) -{ - *mutex = -1; -} - -static int drv_mutex_trylock(IxOsalMutex *mutex) -{ - int result = true; - - if (*mutex == 1) - result = false; - - return result; -} - -static void drv_mutex_unlock(IxOsalMutex *mutex) -{ - if (*mutex == 1) - printf("Trying to unlock unlocked mutex!"); - - *mutex = 0; -} - -PUBLIC IX_STATUS -ixOsalMutexInit (IxOsalMutex * mutex) -{ - drv_mutex_init(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalMutexLock (IxOsalMutex * mutex, INT32 timeout) -{ - int tries; - - if (timeout == IX_OSAL_WAIT_NONE) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - else - return IX_FAIL; - } - - tries = (timeout * 1000) / 50; - while (1) { - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - if (timeout != IX_OSAL_WAIT_FOREVER && tries-- <= 0) - break; - udelay(50); - } - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexUnlock (IxOsalMutex * mutex) -{ - drv_mutex_unlock(mutex); - return IX_SUCCESS; -} - -/* - * Attempt to get mutex, return immediately, - * no error info because users expect some failures - * when using this API. - */ -PUBLIC IX_STATUS -ixOsalMutexTryLock (IxOsalMutex * mutex) -{ - if (drv_mutex_trylock(mutex)) - return IX_SUCCESS; - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalMutexDestroy (IxOsalMutex * mutex) -{ - drv_mutex_destroy(mutex); - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalFastMutexInit (IxOsalFastMutex * mutex) -{ - return ixOsalMutexInit(mutex); -} - -PUBLIC IX_STATUS ixOsalFastMutexTryLock(IxOsalFastMutex *mutex) -{ - return ixOsalMutexTryLock(mutex); -} - - -PUBLIC IX_STATUS -ixOsalFastMutexUnlock (IxOsalFastMutex * mutex) -{ - return ixOsalMutexUnlock(mutex); -} - -PUBLIC IX_STATUS -ixOsalFastMutexDestroy (IxOsalFastMutex * mutex) -{ - return ixOsalMutexDestroy(mutex); -} diff --git a/drivers/net/npe/IxOsalOsServices.c b/drivers/net/npe/IxOsalOsServices.c deleted file mode 100644 index a9aa36804b4..00000000000 --- a/drivers/net/npe/IxOsalOsServices.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file IxOsalOsServices.c (linux) - * - * @brief Implementation for Irq, Mem, sleep. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include -#include -#include "IxOsal.h" -#include -#include -#include -#include -#include - -static char *traceHeaders[] = { - "", - "[fatal] ", - "[error] ", - "[warning] ", - "[message] ", - "[debug1] ", - "[debug2] ", - "[debug3] ", - "[all]" -}; - -/* by default trace all but debug message */ -PRIVATE int ixOsalCurrLogLevel = IX_OSAL_LOG_LVL_MESSAGE; - -/************************************** - * Irq services - *************************************/ - -PUBLIC IX_STATUS -ixOsalIrqBind (UINT32 vector, IxOsalVoidFnVoidPtr routine, void *parameter) -{ - return IX_FAIL; -} - -PUBLIC IX_STATUS -ixOsalIrqUnbind (UINT32 vector) -{ - return IX_FAIL; -} - -PUBLIC UINT32 -ixOsalIrqLock () -{ - return 0; -} - -/* Enable interrupts and task scheduling, - * input parameter: irqEnable status returned - * by ixOsalIrqLock(). - */ -PUBLIC void -ixOsalIrqUnlock (UINT32 lockKey) -{ -} - -PUBLIC UINT32 -ixOsalIrqLevelSet (UINT32 level) -{ - return IX_FAIL; -} - -PUBLIC void -ixOsalIrqEnable (UINT32 irqLevel) -{ -} - -PUBLIC void -ixOsalIrqDisable (UINT32 irqLevel) -{ -} - -/********************* - * Log function - *********************/ - -INT32 -ixOsalLog (IxOsalLogLevel level, - IxOsalLogDevice device, - char *format, int arg1, int arg2, int arg3, int arg4, int arg5, int arg6) -{ - /* - * Return -1 for custom display devices - */ - if ((device != IX_OSAL_LOG_DEV_STDOUT) - && (device != IX_OSAL_LOG_DEV_STDERR)) - { - debug("ixOsalLog: only IX_OSAL_LOG_DEV_STDOUT and IX_OSAL_LOG_DEV_STDERR are supported \n"); - return (IX_OSAL_LOG_ERROR); - } - - if (level <= ixOsalCurrLogLevel && level != IX_OSAL_LOG_LVL_NONE) - { -#if 0 /* sr: U-Boots printf or debug doesn't return a length */ - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : diag_printf(traceHeaders[level - 1]); - - return headerByteCount + diag_printf (format, arg1, arg2, arg3, arg4, arg5, arg6); -#else - int headerByteCount = (level == IX_OSAL_LOG_LVL_USER) ? 0 : strlen(traceHeaders[level - 1]); - - return headerByteCount + strlen(format); -#endif - } - else - { - /* - * Return error - */ - return (IX_OSAL_LOG_ERROR); - } -} - -PUBLIC UINT32 -ixOsalLogLevelSet (UINT32 level) -{ - UINT32 oldLevel; - - /* - * Check value first - */ - if ((level < IX_OSAL_LOG_LVL_NONE) || (level > IX_OSAL_LOG_LVL_ALL)) - { - ixOsalLog (IX_OSAL_LOG_LVL_MESSAGE, - IX_OSAL_LOG_DEV_STDOUT, - "ixOsalLogLevelSet: Log Level is between %d and%d \n", - IX_OSAL_LOG_LVL_NONE, IX_OSAL_LOG_LVL_ALL, 0, 0, 0, 0); - return IX_OSAL_LOG_LVL_NONE; - } - oldLevel = ixOsalCurrLogLevel; - - ixOsalCurrLogLevel = level; - - return oldLevel; -} - -/************************************** - * Task services - *************************************/ - -PUBLIC void -ixOsalBusySleep (UINT32 microseconds) -{ - udelay(microseconds); -} - -PUBLIC void -ixOsalSleep (UINT32 milliseconds) -{ - if (milliseconds != 0) { -#if 1 - /* - * sr: We poll while we wait because interrupts are off in U-Boot - * and CSR expects messages, etc to be dispatched while sleeping. - */ - int i; - IxQMgrDispatcherFuncPtr qDispatcherFunc; - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - while (milliseconds--) { - for (i = 1; i <= 2; i++) - ixNpeMhMessagesReceive(i); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - - udelay(1000); - } -#endif - } -} - -/************************************** - * Memory functions - *************************************/ - -void * -ixOsalMemAlloc (UINT32 size) -{ - return (void *)0; -} - -void -ixOsalMemFree (void *ptr) -{ -} - -/* - * Copy count bytes from src to dest , - * returns pointer to the dest mem zone. - */ -void * -ixOsalMemCopy (void *dest, void *src, UINT32 count) -{ - IX_OSAL_ASSERT (dest != NULL); - IX_OSAL_ASSERT (src != NULL); - return (memcpy (dest, src, count)); -} - -/* - * Fills a memory zone with a given constant byte, - * returns pointer to the memory zone. - */ -void * -ixOsalMemSet (void *ptr, UINT8 filler, UINT32 count) -{ - IX_OSAL_ASSERT (ptr != NULL); - return (memset (ptr, filler, count)); -} diff --git a/drivers/net/npe/IxOsalOsThread.c b/drivers/net/npe/IxOsalOsThread.c deleted file mode 100644 index b3caae19b10..00000000000 --- a/drivers/net/npe/IxOsalOsThread.c +++ /dev/null @@ -1,74 +0,0 @@ -/** - * @file IxOsalOsThread.c (eCos) - * - * @brief OS-specific thread implementation. - * - * - * @par - * IXP400 SW Release version 1.5 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include "IxOsal.h" - -/* Thread attribute is ignored */ -PUBLIC IX_STATUS -ixOsalThreadCreate (IxOsalThread * ptrTid, - IxOsalThreadAttr * threadAttr, IxOsalVoidFnVoidPtr entryPoint, void *arg) -{ - return IX_SUCCESS; -} - -/* - * Start thread after given its thread handle - */ -PUBLIC IX_STATUS -ixOsalThreadStart (IxOsalThread * tId) -{ - /* Thread already started upon creation */ - return IX_SUCCESS; -} - -/* - * In Linux threadKill does not actually destroy the thread, - * it will stop the signal handling. - */ -PUBLIC IX_STATUS -ixOsalThreadKill (IxOsalThread * tid) -{ - return IX_SUCCESS; -} - -PUBLIC void -ixOsalThreadExit (void) -{ -} - -PUBLIC IX_STATUS -ixOsalThreadPrioritySet (IxOsalOsThread * tid, UINT32 priority) -{ - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixOsalThreadSuspend (IxOsalThread * tId) -{ - return IX_SUCCESS; - -} - -PUBLIC IX_STATUS -ixOsalThreadResume (IxOsalThread * tId) -{ - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrAqmIf.c b/drivers/net/npe/IxQMgrAqmIf.c deleted file mode 100644 index 69138ccded9..00000000000 --- a/drivers/net/npe/IxQMgrAqmIf.c +++ /dev/null @@ -1,939 +0,0 @@ -/* - * @file: IxQMgrAqmIf.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This component provides a set of functions for - * perfoming I/O on the AQM hardware. - * - * Design Notes: - * These functions are intended to be as fast as possible - * and as a result perform NO PARAMETER CHECKING. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgrAqmIf_p.h - */ -#ifndef IXQMGRAQMIF_P_H -# define IXQMGRAQMIF_C -#else -# error -#endif - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrLog_p.h" - - -/* - * #defines and macros used in this file. - */ - -/* These defines are the bit offsets of the various fields of - * the queue configuration register - */ -#define IX_QMGR_Q_CONFIG_WRPTR_OFFSET 0x00 -#define IX_QMGR_Q_CONFIG_RDPTR_OFFSET 0x07 -#define IX_QMGR_Q_CONFIG_BADDR_OFFSET 0x0E -#define IX_QMGR_Q_CONFIG_ESIZE_OFFSET 0x16 -#define IX_QMGR_Q_CONFIG_BSIZE_OFFSET 0x18 -#define IX_QMGR_Q_CONFIG_NE_OFFSET 0x1A -#define IX_QMGR_Q_CONFIG_NF_OFFSET 0x1D - -#define IX_QMGR_BASE_ADDR_16_WORD_ALIGN 0x40 -#define IX_QMGR_BASE_ADDR_16_WORD_SHIFT 0x6 - -#define IX_QMGR_NE_NF_CLEAR_MASK 0x03FFFFFF -#define IX_QMGR_NE_MASK 0x7 -#define IX_QMGR_NF_MASK 0x7 -#define IX_QMGR_SIZE_MASK 0x3 -#define IX_QMGR_ENTRY_SIZE_MASK 0x3 -#define IX_QMGR_BADDR_MASK 0x003FC000 -#define IX_QMGR_RDPTR_MASK 0x7F -#define IX_QMGR_WRPTR_MASK 0x7F -#define IX_QMGR_RDWRPTR_MASK 0x00003FFF - -#define IX_QMGR_AQM_ADDRESS_SPACE_SIZE_IN_WORDS 0x1000 - -/* Base address of AQM SRAM */ -#define IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET \ -((IX_QMGR_QUECONFIG_BASE_OFFSET) + (IX_QMGR_QUECONFIG_SIZE)) - -/* Min buffer size used for generating buffer size in QUECONFIG */ -#define IX_QMGR_MIN_BUFFER_SIZE 16 - -/* Reset values of QMgr hardware registers */ -#define IX_QMGR_QUELOWSTAT_RESET_VALUE 0x33333333 -#define IX_QMGR_QUEUOSTAT_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEUPPSTAT0_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUEUPPSTAT1_RESET_VALUE 0x00000000 -#define IX_QMGR_INT0SRCSELREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QUEIEREG_RESET_VALUE 0x00000000 -#define IX_QMGR_QINTREG_RESET_VALUE 0xFFFFFFFF -#define IX_QMGR_QUECONFIG_RESET_VALUE 0x00000000 - -#define IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS IX_OSAL_IXP400_QMGR_PHYS_BASE - -#define IX_QMGR_QUELOWSTAT_BITS_PER_Q (BITS_PER_WORD/IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) - -#define IX_QMGR_QUELOWSTAT_QID_MASK 0x7 -#define IX_QMGR_Q_CONFIG_ADDR_GET(qId)\ - (((qId) * IX_QMGR_NUM_BYTES_PER_WORD) +\ - IX_QMGR_QUECONFIG_BASE_OFFSET) - -#define IX_QMGR_ENTRY1_OFFSET 0 -#define IX_QMGR_ENTRY2_OFFSET 1 -#define IX_QMGR_ENTRY4_OFFSET 3 - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ -UINT32 aqmBaseAddress = 0; -/* Store addresses and bit-masks for certain queue access and status registers. - * This is to facilitate inlining of QRead, QWrite and QStatusGet functions - * in IxQMgr,h - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; -UINT32 * ixQMgrAqmIfQueAccRegAddr[IX_QMGR_MAX_NUM_QUEUES]; -UINT32 ixQMgrAqmIfQueLowStatRegAddr[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsOffset[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueLowStatBitsMask; -UINT32 ixQMgrAqmIfQueUppStat0RegAddr; -UINT32 ixQMgrAqmIfQueUppStat1RegAddr; -UINT32 ixQMgrAqmIfQueUppStat0BitMask[IX_QMGR_MIN_QUEUPP_QID]; -UINT32 ixQMgrAqmIfQueUppStat1BitMask[IX_QMGR_MIN_QUEUPP_QID]; - -/* - * Fast mutexes, one for each queue, used to protect peek & poke functions - */ -IxOsalFastMutex ixQMgrAqmIfPeekPokeFastMutex[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * Function prototypes - */ -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ); - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize); - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords); - -PRIVATE void -ixQMgrAqmIfRegistersReset (void); - -PRIVATE void -ixQMgrAqmIfEntryAddressGet (unsigned int entryIndex, - UINT32 configRegWord, - unsigned int qEntrySizeInwords, - unsigned int qSizeInWords, - UINT32 **address); -/* - * Function definitions - */ -void -ixQMgrAqmIfInit (void) -{ - UINT32 aqmVirtualAddr; - int i; - - /* The value of aqmBaseAddress depends on the logical address - * assigned by the MMU. - */ - aqmVirtualAddr = - (UINT32) IX_OSAL_MEM_MAP(IX_QMGR_PHYSICAL_AQM_BASE_ADDRESS, - IX_OSAL_IXP400_QMGR_MAP_SIZE); - IX_OSAL_ASSERT (aqmVirtualAddr); - - ixQMgrAqmIfBaseAddressSet (aqmVirtualAddr); - - ixQMgrAqmIfRegistersReset (); - - for (i = 0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - ixOsalFastMutexInit(&ixQMgrAqmIfPeekPokeFastMutex[i]); - - /******************************************************************** - * Register addresses and bit masks are calculated and stored here to - * facilitate inlining of QRead, QWrite and QStatusGet functions in - * IxQMgr.h. - * These calculations are normally performed dynamically in inlined - * functions in IxQMgrAqmIf_p.h, and their semantics are reused here. - */ - - /* AQM Queue access reg addresses, per queue */ - ixQMgrAqmIfQueAccRegAddr[i] = - (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i)); - - - ixQMgrQInlinedReadWriteInfo[i].qConfigRegAddr = - (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(i)); - - /* AQM Queue lower-group (0-31), only */ - if (i < IX_QMGR_MIN_QUEUPP_QID) - { - /* AQM Q underflow/overflow status register addresses, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUOStatRegAddr = - (volatile UINT32 *)(aqmBaseAddress + - IX_QMGR_QUEUOSTAT0_OFFSET + - ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* AQM Q underflow status bit masks for status register per queue */ - ixQMgrQInlinedReadWriteInfo[i].qUflowStatBitMask = - (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q overflow status bit masks for status register, per queue */ - ixQMgrQInlinedReadWriteInfo[i].qOflowStatBitMask = - (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) << - ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD)); - - /* AQM Q lower-group (0-31) status register addresses, per queue */ - ixQMgrAqmIfQueLowStatRegAddr[i] = aqmBaseAddress + - IX_QMGR_QUELOWSTAT0_OFFSET + - ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_NUM_BYTES_PER_WORD); - - /* AQM Q lower-group (0-31) status register bit offset */ - ixQMgrAqmIfQueLowStatBitsOffset[i] = - (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) * - (BITS_PER_WORD / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD); - } - else /* AQM Q upper-group (32-63), only */ - { - /* AQM Q upper-group (32-63) Nearly Empty status reg bit masks */ - ixQMgrAqmIfQueUppStat0BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - - /* AQM Q upper-group (32-63) Full status register bit masks */ - ixQMgrAqmIfQueUppStat1BitMask[i - IX_QMGR_MIN_QUEUPP_QID] = - (1 << (i - IX_QMGR_MIN_QUEUPP_QID)); - } - } - - /* AQM Q lower-group (0-31) status register bit mask */ - ixQMgrAqmIfQueLowStatBitsMask = (1 << - (BITS_PER_WORD / - IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD)) - 1; - - /* AQM Q upper-group (32-63) Nearly Empty status register address */ - ixQMgrAqmIfQueUppStat0RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET; - - /* AQM Q upper-group (32-63) Full status register address */ - ixQMgrAqmIfQueUppStat1RegAddr = aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET; -} - -/* - * Uninitialise the AqmIf module by unmapping memory, etc - */ -void -ixQMgrAqmIfUninit (void) -{ - UINT32 virtAddr; - - ixQMgrAqmIfBaseAddressGet (&virtAddr); - IX_OSAL_MEM_UNMAP (virtAddr); - ixQMgrAqmIfBaseAddressSet (0); -} - -/* - * Set the the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressSet (UINT32 address) -{ - aqmBaseAddress = address; -} - -/* - * Get the logical base address of AQM - */ -void -ixQMgrAqmIfBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress; -} - -/* - * Get the logical base address of AQM SRAM - */ -void -ixQMgrAqmIfSramBaseAddressGet (UINT32 *address) -{ - *address = aqmBaseAddress + - IX_QMGR_AQM_SRAM_BASE_ADDRESS_OFFSET; -} - -/* - * This function will write the status bits of a queue - * specified by qId. - */ -void -ixQMgrAqmIfQRegisterBitsWrite (IxQMgrQId qId, - UINT32 registerBaseAddrOffset, - unsigned queuesPerRegWord, - UINT32 value) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 statusBitsMask; - UINT32 bitsPerQueue; - - bitsPerQueue = BITS_PER_WORD / queuesPerRegWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - registerBaseAddrOffset + - ((qId / queuesPerRegWord) * - IX_QMGR_NUM_BYTES_PER_WORD)); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - - if( (registerBaseAddrOffset == IX_QMGR_INT0SRCSELREG0_OFFSET) && - (qId == IX_QMGR_QUEUE_0) ) - { - statusBitsMask = 0x7 ; - - /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */ - value &= 0x7 ; - } - else - { - /* Calculate the mask for the status bits for this queue. */ - statusBitsMask = ((1 << bitsPerQueue) - 1); - statusBitsMask <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - - /* Mask out bits in value that would overwrite other q data */ - value <<= ((qId & (queuesPerRegWord - 1)) * bitsPerQueue); - value &= statusBitsMask; - } - - /* Mask out bits to write to */ - registerWord &= ~statusBitsMask; - - - /* Set the write bits */ - registerWord |= value; - - /* - * Write the data - */ - ixQMgrAqmIfWordWrite (registerAddress, registerWord); -} - -/* - * This function generates the parameters that can be used to - * check if a Qs status matches the specified source select. - * It calculates which status word to check (statusWordOffset), - * the value to check the status against (checkValue) and the - * mask (mask) to mask out all but the bits to check in the status word. - */ -void -ixQMgrAqmIfQStatusCheckValsCalc (IxQMgrQId qId, - IxQMgrSourceId srcSel, - unsigned int *statusWordOffset, - UINT32 *checkValue, - UINT32 *mask) -{ - UINT32 shiftVal; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - switch (srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - *checkValue = IX_QMGR_Q_STATUS_E_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - *checkValue = IX_QMGR_Q_STATUS_NE_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - *checkValue = IX_QMGR_Q_STATUS_NF_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_F: - *checkValue = IX_QMGR_Q_STATUS_F_BIT_MASK; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_E_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NE_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_NF_BIT_MASK; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - *checkValue = 0; - *mask = IX_QMGR_Q_STATUS_F_BIT_MASK; - break; - default: - /* Should never hit */ - IX_OSAL_ASSERT(0); - break; - } - - /* One nibble of status per queue so need to shift the - * check value and mask out to the correct position. - */ - shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) * - IX_QMGR_QUELOWSTAT_BITS_PER_Q; - - /* Calculate the which status word to check from the qId, - * 8 Qs status per word - */ - *statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD; - - *checkValue <<= shiftVal; - *mask <<= shiftVal; - } - else - { - /* One status word */ - *statusWordOffset = 0; - /* Single bits per queue and int source bit hardwired NE, - * Qs start at 32. - */ - *mask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID); - *checkValue = *mask; - } -} - -void -ixQMgrAqmIfQInterruptEnable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, (registerWord | actualBitOffset)); -} - -void -ixQMgrAqmIfQInterruptDisable (IxQMgrQId qId) -{ - volatile UINT32 *registerAddress; - UINT32 registerWord; - UINT32 actualBitOffset; - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET); - } - else - { - registerAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET); - } - - actualBitOffset = 1 << (qId % IX_QMGR_MIN_QUEUPP_QID); - - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - ixQMgrAqmIfWordWrite (registerAddress, registerWord & (~actualBitOffset)); -} - -void -ixQMgrAqmIfQueCfgWrite (IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords entrySizeInWords, - UINT32 freeSRAMAddress) -{ - volatile UINT32 *cfgAddress = NULL; - UINT32 qCfg = 0; - UINT32 baseAddress = 0; - unsigned aqmEntrySize = 0; - unsigned aqmBufferSize = 0; - - /* Build config register */ - aqmEntrySize = entrySizeToAqmEntrySize (entrySizeInWords); - qCfg |= (aqmEntrySize&IX_QMGR_ENTRY_SIZE_MASK) << - IX_QMGR_Q_CONFIG_ESIZE_OFFSET; - - aqmBufferSize = bufferSizeToAqmBufferSize (qSizeInWords); - qCfg |= (aqmBufferSize&IX_QMGR_SIZE_MASK) << IX_QMGR_Q_CONFIG_BSIZE_OFFSET; - - /* baseAddress, calculated relative to aqmBaseAddress and start address */ - baseAddress = freeSRAMAddress - - (aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Verify base address aligned to a 16 word boundary */ - if ((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) != 0) - { - IX_QMGR_LOG_ERROR0("ixQMgrAqmIfQueCfgWrite () address is not on 16 word boundary\n"); - } - /* Now convert it to a 16 word pointer as required by QUECONFIG register */ - baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - - - qCfg |= (baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET); - - - cfgAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - - - /* NOTE: High and Low watermarks are set to zero */ - ixQMgrAqmIfWordWrite (cfgAddress, qCfg); -} - -void -ixQMgrAqmIfQueCfgRead (IxQMgrQId qId, - unsigned int numEntries, - UINT32 *baseAddress, - unsigned int *ne, - unsigned int *nf, - UINT32 *readPtr, - UINT32 *writePtr) -{ - UINT32 qcfg; - UINT32 *cfgAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - UINT32 *readPtr_ = NULL; - - /* Read the queue configuration register */ - ixQMgrAqmIfWordRead (cfgAddress, &qcfg); - - /* Extract the base address */ - *baseAddress = (UINT32)((qcfg & IX_QMGR_BADDR_MASK) >> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - *baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - *baseAddress += (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET; - - /* - * Extract the watermarks. 0->0 entries, 1->1 entries, 2->2 entries, 3->4 entries...... - * If ne > 0 ==> neInEntries = 2^(ne - 1) - * If ne == 0 ==> neInEntries = 0 - * The same applies. - */ - *ne = ((qcfg) >> (IX_QMGR_Q_CONFIG_NE_OFFSET)) & IX_QMGR_NE_MASK; - *nf = ((qcfg) >> (IX_QMGR_Q_CONFIG_NF_OFFSET)) & IX_QMGR_NF_MASK; - - if (0 != *ne) - { - *ne = 1 << (*ne - 1); - } - if (0 != *nf) - { - *nf = 1 << (*nf - 1); - } - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - ixQMgrAqmIfEntryAddressGet (0/* Entry 0. i.e the readPtr*/, - qcfg, - qEntrySizeInwords, - qSizeInWords, - &readPtr_); - *readPtr = (UINT32)readPtr_; - *readPtr -= (UINT32)aqmBaseAddress;/* Offset, not absolute address */ - - *writePtr = (qcfg >> IX_QMGR_Q_CONFIG_WRPTR_OFFSET) & IX_QMGR_WRPTR_MASK; - *writePtr = *baseAddress + (*writePtr * (IX_QMGR_NUM_BYTES_PER_WORD)); - return; -} - -unsigned -ixQMgrAqmIfLog2 (unsigned number) -{ - unsigned count = 0; - - /* - * N.B. this function will return 0 - * for ixQMgrAqmIfLog2 (0) - */ - while (number/2) - { - number /=2; - count++; - } - - return count; -} - -void ixQMgrAqmIfIntSrcSelReg0Bit3Set (void) -{ - - volatile UINT32 *registerAddress; - UINT32 registerWord; - - /* - * Calculate the registerAddress - * multiple queues split accross registers - */ - registerAddress = (UINT32*)(aqmBaseAddress + - IX_QMGR_INT0SRCSELREG0_OFFSET); - - /* Read the current data */ - ixQMgrAqmIfWordRead (registerAddress, ®isterWord); - - /* Set the write bits */ - registerWord |= (1<> - (IX_QMGR_Q_CONFIG_BADDR_OFFSET)); - - /* Base address is a 16 word pointer from the start of AQM SRAM. - * Convert to absolute word address. - */ - baseAddress <<= IX_QMGR_BASE_ADDR_16_WORD_SHIFT; - baseAddress += ((UINT32)aqmBaseAddress + (UINT32)IX_QMGR_QUECONFIG_BASE_OFFSET); - - /* Extract the read pointer. Read pointer is a word pointer */ - readPtr = (UINT32)((configRegWord >> - IX_QMGR_Q_CONFIG_RDPTR_OFFSET)&IX_QMGR_RDPTR_MASK); - - /* Read/Write pointers(word pointers) are offsets from the queue buffer space base address. - * Calculate the absolute read pointer address. NOTE: Queues are circular buffers. - */ - readPtr = (readPtr + (entryIndex * qEntrySizeInwords)) & (qSizeInWords - 1); /* Mask by queue size */ - *address = (UINT32 *)(baseAddress + (readPtr * (IX_QMGR_NUM_BYTES_PER_WORD))); - - switch (qEntrySizeInwords) - { - case IX_QMGR_Q_ENTRY_SIZE1: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY1_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE2: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY2_OFFSET) < topOfAqmSram); - break; - case IX_QMGR_Q_ENTRY_SIZE4: - IX_OSAL_ASSERT((*address + IX_QMGR_ENTRY4_OFFSET) < topOfAqmSram); - break; - default: - IX_QMGR_LOG_ERROR0("Invalid Q Entry size passed to ixQMgrAqmIfEntryAddressGet"); - break; - } - -} - -IX_STATUS -ixQMgrAqmIfQPeek (IxQMgrQId qId, - unsigned int entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordRead (entryAddress++, entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAqmIfQPoke (IxQMgrQId qId, - unsigned entryIndex, - unsigned int *entry) -{ - UINT32 *cfgRegAddress = (UINT32*)(aqmBaseAddress + IX_QMGR_Q_CONFIG_ADDR_GET(qId)); - UINT32 *entryAddress = NULL; - UINT32 configRegWordOnEntry; - UINT32 configRegWordOnExit; - unsigned int qEntrySizeInwords; - unsigned int qSizeInWords; - - /* Get the queue entry size in words */ - qEntrySizeInwords = ixQMgrQEntrySizeInWordsGet (qId); - - /* Get the queue size in words */ - qSizeInWords = ixQMgrQSizeInWordsGet (qId); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnEntry); - - /* Get the entry address */ - ixQMgrAqmIfEntryAddressGet (entryIndex, - configRegWordOnEntry, - qEntrySizeInwords, - qSizeInWords, - &entryAddress); - - /* Get the lock or return busy */ - if (IX_SUCCESS != ixOsalFastMutexTryLock(&ixQMgrAqmIfPeekPokeFastMutex[qId])) - { - return IX_FAIL; - } - - /* Else read the entry directly from SRAM. This will not move the read pointer */ - while(qEntrySizeInwords--) - { - ixQMgrAqmIfWordWrite (entryAddress++, *entry++); - } - - /* Release the lock */ - ixOsalFastMutexUnlock(&ixQMgrAqmIfPeekPokeFastMutex[qId]); - - /* Read the config register */ - ixQMgrAqmIfWordRead (cfgRegAddress, &configRegWordOnExit); - - /* Check that the read and write pointers have not changed */ - if (configRegWordOnEntry != configRegWordOnExit) - { - return IX_FAIL; - } - - return IX_SUCCESS; -} - -PRIVATE unsigned -watermarkToAqmWatermark (IxQMgrWMLevel watermark ) -{ - unsigned aqmWatermark = 0; - - /* - * Watermarks 0("000"),1("001"),2("010"),4("011"), - * 8("100"),16("101"),32("110"),64("111") - */ - aqmWatermark = ixQMgrAqmIfLog2 (watermark * 2); - - return aqmWatermark; -} - -PRIVATE unsigned -entrySizeToAqmEntrySize (IxQMgrQEntrySizeInWords entrySize) -{ - /* entrySize 1("00"),2("01"),4("10") */ - return (ixQMgrAqmIfLog2 (entrySize)); -} - -PRIVATE unsigned -bufferSizeToAqmBufferSize (unsigned bufferSizeInWords) -{ - /* bufferSize 16("00"),32("01),64("10"),128("11") */ - return (ixQMgrAqmIfLog2 (bufferSizeInWords / IX_QMGR_MIN_BUFFER_SIZE)); -} - -/* - * Reset AQM registers to default values. - */ -PRIVATE void -ixQMgrAqmIfRegistersReset (void) -{ - volatile UINT32 *qConfigWordAddress = NULL; - unsigned int i; - - /* - * Need to initialize AQM hardware registers to an initial - * value as init may have been called as a result of a soft - * reset. i.e. soft reset does not reset hardware registers. - */ - - /* Reset queues 0..31 status registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT0_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT1_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT2_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUELOWSTAT3_OFFSET), - IX_QMGR_QUELOWSTAT_RESET_VALUE); - - /* Reset underflow/overflow status registers 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT0_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUOSTAT1_OFFSET), - IX_QMGR_QUEUOSTAT_RESET_VALUE); - - /* Reset queues 32..63 nearly empty status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT0_OFFSET), - IX_QMGR_QUEUPPSTAT0_RESET_VALUE); - - /* Reset queues 32..63 full status registers */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEUPPSTAT1_OFFSET), - IX_QMGR_QUEUPPSTAT1_RESET_VALUE); - - /* Reset int0 status flag source select registers 0..3 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG0_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG1_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG2_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_INT0SRCSELREG3_OFFSET), - IX_QMGR_INT0SRCSELREG_RESET_VALUE); - - /* Reset queue interrupt enable register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG0_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QUEIEREG1_OFFSET), - IX_QMGR_QUEIEREG_RESET_VALUE); - - /* Reset queue interrupt register 0..1 */ - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG0_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - ixQMgrAqmIfWordWrite((UINT32 *)(aqmBaseAddress + IX_QMGR_QINTREG1_OFFSET), - IX_QMGR_QINTREG_RESET_VALUE); - - /* Reset queue configuration words 0..63 */ - qConfigWordAddress = (UINT32 *)(aqmBaseAddress + IX_QMGR_QUECONFIG_BASE_OFFSET); - for (i = 0; i < (IX_QMGR_QUECONFIG_SIZE / sizeof(UINT32)); i++) - { - ixQMgrAqmIfWordWrite(qConfigWordAddress, - IX_QMGR_QUECONFIG_RESET_VALUE); - /* Next word */ - qConfigWordAddress++; - } -} - diff --git a/drivers/net/npe/IxQMgrDispatcher.c b/drivers/net/npe/IxQMgrDispatcher.c deleted file mode 100644 index 2baeaafeb1d..00000000000 --- a/drivers/net/npe/IxQMgrDispatcher.c +++ /dev/null @@ -1,1320 +0,0 @@ -/** - * @file IxQMgrDispatcher.c - * - * @author Intel Corporation - * @date 20-Dec-2001 - * - * @brief This file contains the implementation of the Dispatcher sub component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrDefines_p.h" -#include "IxFeatureCtrl.h" -#include "IxOsal.h" - - - -/* - * #defines and macros used in this file. - */ - - -/* - * This constant is used to indicate the number of priority levels supported - */ -#define IX_QMGR_NUM_PRIORITY_LEVELS 3 - -/* - * This constant is used to set the size of the array of status words - */ -#define MAX_Q_STATUS_WORDS 4 - -/* - * This macro is used to check if a given priority is valid - */ -#define IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority) \ -(((priority) >= IX_QMGR_Q_PRIORITY_0) && ((priority) <= IX_QMGR_Q_PRIORITY_2)) - -/* - * This macto is used to check that a given interrupt source is valid - */ -#define IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel) \ -(((srcSel) >= IX_QMGR_Q_SOURCE_ID_E) && ((srcSel) <= IX_QMGR_Q_SOURCE_ID_NOT_F)) - -/* - * Number of times a dummy callback is called before logging a trace - * message - */ -#define LOG_THROTTLE_COUNT 1000000 - -/* Priority tables limits */ -#define IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX (0) -#define IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX (16) -#define IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX (31) -#define IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX (32) -#define IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX (48) -#define IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX (63) - -/* - * This macro is used to check if a given callback type is valid - */ -#define IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type) \ - (((type) >= IX_QMGR_TYPE_REALTIME_OTHER) && \ - ((type) <= IX_QMGR_TYPE_REALTIME_SPORADIC)) - -/* - * define max index in lower queue to use in loops - */ -#define IX_QMGR_MAX_LOW_QUE_TABLE_INDEX (31) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * Information on a queue needed by the Dispatcher - */ -typedef struct -{ - IxQMgrCallback callback; /* Notification callback */ - IxQMgrCallbackId callbackId; /* Notification callback identifier */ - unsigned dummyCallbackCount; /* Number of times runs of dummy callback */ - IxQMgrPriority priority; /* Dispatch priority */ - unsigned int statusWordOffset; /* Offset to the status word to check */ - UINT32 statusMask; /* Status mask */ - UINT32 statusCheckValue; /* Status check value */ - UINT32 intRegCheckMask; /* Interrupt register check mask */ -} IxQMgrQInfo; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -/* - * Flag to keep record of what dispatcher set in featureCtrl when ixQMgrInit() - * is called. This is needed because it is possible that a client might - * change whether the live lock prevention dispatcher is used between - * calls to ixQMgrInit() and ixQMgrDispatcherLoopGet(). - */ -PRIVATE IX_STATUS ixQMgrOrigB0Dispatcher = IX_FEATURE_CTRL_COMPONENT_ENABLED; - -/* - * keep record of Q types - not in IxQMgrQInfo for performance as - * it is only used with ixQMgrDispatcherLoopRunB0LLP() - */ -PRIVATE IxQMgrType ixQMgrQTypes[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This array contains a list of queue identifiers ordered by priority. The table - * is split logically between queue identifiers 0-31 and 32-63. - */ -static IxQMgrQId priorityTable[IX_QMGR_MAX_NUM_QUEUES]; - -/* - * This flag indicates to the dispatcher that the priority table needs to be rebuilt. - */ -static BOOL rebuildTable = false; - -/* Dispatcher statistics */ -static IxQMgrDispatcherStats dispatcherStats; - -/* Table of queue information */ -static IxQMgrQInfo dispatchQInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* Masks use to identify the first queues in the priority tables -* when comparing with the interrupt register -*/ -static unsigned int lowPriorityTableFirstHalfMask; -static unsigned int uppPriorityTableFirstHalfMask; - -/* - * Static function prototypes - */ - -/* - * This function is the default callback for all queues - */ -PRIVATE void -dummyCallback (IxQMgrQId qId, - IxQMgrCallbackId cbId); - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void); - -/* - * Function definitions. - */ -void -ixQMgrDispatcherInit (void) -{ - int i; - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - BOOL stickyIntSilicon = true; - - /* Set default priorities */ - for (i=0; i< IX_QMGR_MAX_NUM_QUEUES; i++) - { - dispatchQInfo[i].callback = dummyCallback; - dispatchQInfo[i].callbackId = 0; - dispatchQInfo[i].dummyCallbackCount = 0; - dispatchQInfo[i].priority = IX_QMGR_Q_PRIORITY_2; - dispatchQInfo[i].statusWordOffset = 0; - dispatchQInfo[i].statusCheckValue = 0; - dispatchQInfo[i].statusMask = 0; - /* - * There are two interrupt registers, 32 bits each. One for the lower - * queues(0-31) and one for the upper queues(32-63). Therefore need to - * mod by 32 i.e the min upper queue identifier. - */ - dispatchQInfo[i].intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID))); - - /* - * Set the Q types - will only be used with livelock - */ - ixQMgrQTypes[i] = IX_QMGR_TYPE_REALTIME_OTHER; - - /* Reset queue statistics */ - dispatcherStats.queueStats[i].callbackCnt = 0; - dispatcherStats.queueStats[i].priorityChangeCnt = 0; - dispatcherStats.queueStats[i].intNoCallbackCnt = 0; - dispatcherStats.queueStats[i].intLostCallbackCnt = 0; - dispatcherStats.queueStats[i].notificationEnabled = false; - dispatcherStats.queueStats[i].srcSel = 0; - - } - - /* Priority table. Order the table from queue 0 to 63 */ - ixQMgrDispatcherReBuildPriorityTable(); - - /* Reset statistics */ - dispatcherStats.loopRunCnt = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead(); - - /* - * Check featureCtrl to see if Livelock prevention is required - */ - ixQMgrOrigB0Dispatcher = ixFeatureCtrlSwConfigurationCheck( - IX_FEATURECTRL_ORIGB0_DISPATCHER); - - /* - * Check if the silicon supports the sticky interrupt feature. - * IF (IXP42X AND A0) -> No sticky interrupt feature supported - */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - stickyIntSilicon = false; - } - - /* - * IF user wants livelock prev option AND silicon supports sticky interrupt - * feature -> enable the sticky interrupt bit - */ - if ((IX_FEATURE_CTRL_SWCONFIG_DISABLED == ixQMgrOrigB0Dispatcher) && - stickyIntSilicon) - { - ixQMgrStickyInterruptRegEnable(); - } -} - -IX_STATUS -ixQMgrDispatcherPrioritySet (IxQMgrQId qId, - IxQMgrPriority priority) -{ - int ixQMgrLockKey; - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!IX_QMGR_DISPATCHER_PRIORITY_CHECK(priority)) - { - return IX_QMGR_Q_INVALID_PRIORITY; - } - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Change priority */ - dispatchQInfo[qId].priority = priority; - /* Set flag */ - rebuildTable = true; - - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qId].priorityChangeCnt++; -#endif - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationCallbackSet (IxQMgrQId qId, - IxQMgrCallback callback, - IxQMgrCallbackId callbackId) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (NULL == callback) - { - /* Reset to dummy callback */ - dispatchQInfo[qId].callback = dummyCallback; - dispatchQInfo[qId].dummyCallbackCount = 0; - dispatchQInfo[qId].callbackId = 0; - } - else - { - dispatchQInfo[qId].callback = callback; - dispatchQInfo[qId].callbackId = callbackId; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrNotificationEnable (IxQMgrQId qId, - IxQMgrSourceId srcSel) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - int ixQMgrLockKey; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if ((qId < IX_QMGR_MIN_QUEUPP_QID) && - !IX_QMGR_DISPATCHER_SOURCE_ID_CHECK(srcSel)) - { - /* QId 0-31 source id invalid */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } - - if ((IX_QMGR_Q_SOURCE_ID_NE != srcSel) && - (qId >= IX_QMGR_MIN_QUEUPP_QID)) - { - /* - * For queues 32-63 the interrupt source is fixed to the Nearly - * Empty status flag and therefore should have a srcSel of NE. - */ - return IX_QMGR_INVALID_INT_SOURCE_ID; - } -#endif - -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = true; - dispatcherStats.queueStats[qId].srcSel = srcSel; -#endif - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ - - ixQMgrLockKey = ixOsalIrqLock(); - - /* Calculate the checkMask and checkValue for this q */ - ixQMgrAqmIfQStatusCheckValsCalc (qId, - srcSel, - &dispatchQInfo[qId].statusWordOffset, - &dispatchQInfo[qId].statusCheckValue, - &dispatchQInfo[qId].statusMask); - - - /* Set the interrupt source is this queue is in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - ixQMgrAqmIfIntSrcSelWrite (qId, srcSel); - } - - /* Enable the interrupt */ - ixQMgrAqmIfQInterruptEnable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - - -IX_STATUS -ixQMgrNotificationDisable (IxQMgrQId qId) -{ - int ixQMgrLockKey; - -#ifndef NDEBUG - /* Validate parameters */ - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* - * Enabling interrupts results in Read-Modify-Write - * so need critical section - */ -#ifndef NDEBUG - dispatcherStats.queueStats[qId].notificationEnabled = false; -#endif - - ixQMgrLockKey = ixOsalIrqLock(); - - ixQMgrAqmIfQInterruptDisable (qId); - - ixOsalIrqUnlock(ixQMgrLockKey); - - return IX_SUCCESS; -} - -void -ixQMgrStickyInterruptRegEnable(void) -{ - /* Use Aqm If function to set Interrupt Register0 Bit-3 */ - ixQMgrAqmIfIntSrcSelReg0Bit3Set (); -} - -#if !defined __XSCALE__ || defined __linux - -/* Count the number of leading zero bits in a word, - * and return the same value than the CLZ instruction. - * - * word (in) return value (out) - * 0x80000000 0 - * 0x40000000 1 - * ,,, ,,, - * 0x00000002 30 - * 0x00000001 31 - * 0x00000000 32 - * - * The C version of this function is used as a replacement - * for system not providing the equivalent of the CLZ - * assembly language instruction. - * - * Note that this version is big-endian - */ -unsigned int -ixQMgrCountLeadingZeros(UINT32 word) -{ - unsigned int leadingZerosCount = 0; - - if (word == 0) - { - return 32; - } - /* search the first bit set by testing the MSB and shifting the input word */ - while ((word & 0x80000000) == 0) - { - word <<= 1; - leadingZerosCount++; - } - return leadingZerosCount; -} -#endif /* not __XSCALE__ or __linux */ - -void -ixQMgrDispatcherLoopGet (IxQMgrDispatcherFuncPtr *qDispatcherFuncPtr) -{ - IxFeatureCtrlProductId productId = 0; - IxFeatureCtrlDeviceId deviceId = 0; - - /* Get the device ID for the underlying silicon */ - deviceId = ixFeatureCtrlDeviceRead(); - - /* Get the product ID for the underlying silicon */ - productId = ixFeatureCtrlProductIdRead (); - - /* IF (IXP42X AND A0 silicon) -> use ixQMgrDispatcherLoopRunA0 */ - if ((IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X == - (IX_FEATURE_CTRL_DEVICE_TYPE_MASK & deviceId)) && - (IX_FEATURE_CTRL_SILICON_TYPE_A0 == - (IX_FEATURE_CTRL_SILICON_STEPPING_MASK & productId))) - { - /*For IXP42X A0 silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunA0 ; - } - else /*For IXP42X B0 or IXP46X silicon*/ - { - if (IX_FEATURE_CTRL_SWCONFIG_ENABLED == ixQMgrOrigB0Dispatcher) - { - /* Default for IXP42X B0 and IXP46X silicon */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0; - } - else - { - /* FeatureCtrl indicated that livelock dispatcher be used */ - *qDispatcherFuncPtr = &ixQMgrDispatcherLoopRunB0LLP; - } - } -} - -void -ixQMgrDispatcherLoopRunA0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegValAfterWrite; /* Interrupt reg val after writing back */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - UINT32 qStatusWordsB4Write[MAX_Q_STATUS_WORDS]; /* Status b4 interrupt write */ - UINT32 qStatusWordsAfterWrite[MAX_Q_STATUS_WORDS]; /* Status after interrupt write */ - IxQMgrQInfo *currDispatchQInfo; - BOOL statusChangeFlag; - - int priorityTableIndex;/* Priority table index */ - int qIndex; /* Current queue being processed */ - int endIndex; /* Index of last queue to process */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read Q status registers before interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsB4Write); - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* No bit set : nothing to process (the reaminder of the algorithm is - * based on the fact that the interrupt register value contains at - * least one bit set - */ - if (intRegVal == 0) - { -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - - return; - } - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* Read Q status registers after interrupt status read/write */ - ixQMgrAqmIfQStatusRegsRead (group, qStatusWordsAfterWrite); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - /* check if any change occured during hw register modifications */ - if (IX_QMGR_QUELOW_GROUP == group) - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]) || - (qStatusWordsB4Write[1] != qStatusWordsAfterWrite[1]) || - (qStatusWordsB4Write[2] != qStatusWordsAfterWrite[2]) || - (qStatusWordsB4Write[3] != qStatusWordsAfterWrite[3]); - } - else - { - statusChangeFlag = - (qStatusWordsB4Write[0] != qStatusWordsAfterWrite[0]); - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - if (statusChangeFlag == false) - { - /* check if the interrupt register contains - * only 1 bit set (happy day scenario) - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } - } - else - { - /* A change in queue status occured during the hw interrupt - * register update. To maintain the interrupt consistency, it - * is necessary to iterate through all queues of the queue group. - */ - - /* Read interrupt status again */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegValAfterWrite); - - if (IX_QMGR_QUELOW_GROUP == group) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - endIndex = IX_QMGR_MAX_UPP_QUE_PRIORITY_TABLE_INDEX; - } - - for ( ; priorityTableIndex<=endIndex; priorityTableIndex++) - { - qIndex = priorityTable[priorityTableIndex]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - } /* if (intRegVal .. */ - - /* - * If interrupt bit is set in intRegValAfterWrite don't - * proceed as this will be caught in next interrupt - */ - else if ((intRegValAfterWrite & intRegCheckMask) == 0) - { - /* Check if an interrupt was lost for this Q */ - if (ixQMgrAqmIfQStatusCheck(qStatusWordsB4Write, - qStatusWordsAfterWrite, - currDispatchQInfo->statusWordOffset, - currDispatchQInfo->statusCheckValue, - currDispatchQInfo->statusMask)) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - dispatchQInfo[qIndex].callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; - dispatcherStats.queueStats[qIndex].intLostCallbackCnt++; -#endif - } /* if ixQMgrAqmIfQStatusCheck(.. */ - } /* else if ((intRegValAfterWrite ... */ - } /* for (priorityTableIndex=0 ... */ - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif -} - - - -void -ixQMgrDispatcherLoopRunB0 (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - - /* Write it back to clear the interrupt */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - /* only 1 queue event triggered a notification * - * Call the callback function for this queue - */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* Call the callback function for this queue */ - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -void -ixQMgrDispatcherLoopRunB0LLP (IxQMgrDispatchGroup group) -{ - UINT32 intRegVal =0; /* Interrupt reg val */ - UINT32 intRegCheckMask; /* Mask for checking interrupt bits */ - IxQMgrQInfo *currDispatchQInfo; - - int priorityTableIndex; /* Priority table index */ - int qIndex; /* Current queue being processed */ - - UINT32 intRegValCopy = 0; - UINT32 intEnableRegVal = 0; - UINT8 i = 0; - -#ifndef NDEBUG - IX_OSAL_ASSERT((group == IX_QMGR_QUEUPP_GROUP) || - (group == IX_QMGR_QUELOW_GROUP)); -#endif - - /* Read the interrupt register */ - ixQMgrAqmIfQInterruptRegRead (group, &intRegVal); - - /* - * mask any interrupts that are not enabled - */ - ixQMgrAqmIfQInterruptEnableRegRead (group, &intEnableRegVal); - intRegVal &= intEnableRegVal; - - /* No queue has interrupt register set */ - if (intRegVal != 0) - { - if (IX_QMGR_QUELOW_GROUP == group) - { - /* - * As the sticky bit is set, the interrupt register will - * not clear if write back at this point because the condition - * has not been cleared. Take a copy and write back later after - * the condition has been cleared - */ - intRegValCopy = intRegVal; - } - else - { - /* no sticky for upper Q's, so write back now */ - ixQMgrAqmIfQInterruptRegWrite (group, intRegVal); - } - - /* get the first queue Id from the interrupt register value */ - qIndex = (BITS_PER_WORD - 1) - ixQMgrCountLeadingZeros(intRegVal); - - if (IX_QMGR_QUEUPP_GROUP == group) - { - /* Set the queue range based on the queue group to proccess */ - qIndex += IX_QMGR_MIN_QUEUPP_QID; - } - - /* check if the interrupt register contains - * only 1 bit set - * For example: - * intRegVal = 0x0010 - * currDispatchQInfo->intRegCheckMask = 0x0010 - * intRegVal == currDispatchQInfo->intRegCheckMask is true. - */ - currDispatchQInfo = &dispatchQInfo[qIndex]; - if (intRegVal == currDispatchQInfo->intRegCheckMask) - { - - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - } - else - { - /* the event is triggered by more than 1 queue, - * the queue search will be starting from the beginning - * or the middle of the priority table - * - * the serach will end when all the bits of the interrupt - * register are cleared. There is no need to maintain - * a seperate value and test it at each iteration. - */ - if (IX_QMGR_QUELOW_GROUP == group) - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & lowPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_LOW_QUE_PRIORITY_TABLE_INDEX; - } - } - else - { - /* check if any bit related to queues in the first - * half of the priority table is set - */ - if (intRegVal & uppPriorityTableFirstHalfMask) - { - priorityTableIndex = - IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - } - else - { - priorityTableIndex = - IX_QMGR_MID_UPP_QUE_PRIORITY_TABLE_INDEX; - } - } - - /* iterate following the priority table until all the bits - * of the interrupt register are cleared. - */ - do - { - qIndex = priorityTable[priorityTableIndex++]; - currDispatchQInfo = &dispatchQInfo[qIndex]; - intRegCheckMask = currDispatchQInfo->intRegCheckMask; - - /* If this queue caused this interrupt to be raised */ - if (intRegVal & intRegCheckMask) - { - /* - * check if Q type periodic - only lower queues can - * have there type set to periodic. There can only be one - * periodic queue, so the sporadics are only disabled once. - */ - if (IX_QMGR_TYPE_REALTIME_PERIODIC == ixQMgrQTypes[qIndex]) - { - /* - * Disable the notifications on any sporadics - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (IX_QMGR_TYPE_REALTIME_SPORADIC == - ixQMgrQTypes[i]) - { - ixQMgrNotificationDisable(i); - /* - * remove from intRegVal as we don't want - * to service any sporadics now - */ - intRegVal &= ~dispatchQInfo[i].intRegCheckMask; -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[i].disableCount++; -#endif - } - } - } - - currDispatchQInfo->callback (qIndex, - currDispatchQInfo->callbackId); -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.queueStats[qIndex].callbackCnt++; -#endif - /* Clear the interrupt register bit */ - intRegVal &= ~intRegCheckMask; - } - } - while(intRegVal); - } /*End of intRegVal == currDispatchQInfo->intRegCheckMask */ - } /* End of intRegVal != 0 */ - -#ifndef NDEBUG - /* Update statistics */ - dispatcherStats.loopRunCnt++; -#endif - - if ((intRegValCopy != 0) && (IX_QMGR_QUELOW_GROUP == group)) - { - /* - * lower groups (therefore sticky) AND at least one enabled interrupt - * Write back to clear the interrupt - */ - ixQMgrAqmIfQInterruptRegWrite (IX_QMGR_QUELOW_GROUP, intRegValCopy); - } - - /* Rebuild the priority table if needed */ - if (rebuildTable) - { - ixQMgrDispatcherReBuildPriorityTable (); - } -} - -PRIVATE void -ixQMgrDispatcherReBuildPriorityTable (void) -{ - UINT32 qIndex; - UINT32 priority; - int lowQuePriorityTableIndex = IX_QMGR_MIN_LOW_QUE_PRIORITY_TABLE_INDEX; - int uppQuePriorityTableIndex = IX_QMGR_MIN_UPP_QUE_PRIORITY_TABLE_INDEX; - - /* Reset the rebuild flag */ - rebuildTable = false; - - /* initialize the mak used to identify the queues in the first half - * of the priority table - */ - lowPriorityTableFirstHalfMask = 0; - uppPriorityTableFirstHalfMask = 0; - - /* For each priority level */ - for(priority=0; priority dummyCallback: qId (%d), callbackId (%d)\n",qId,cbId); - } - dispatchQInfo[qId].dummyCallbackCount++; - -#ifndef NDEBUG - /* Update statistcs */ - dispatcherStats.queueStats[qId].intNoCallbackCnt++; -#endif -} -void -ixQMgrLLPShow (int resetStats) -{ -#ifndef NDEBUG - UINT8 i = 0; - UINT32 intEnableRegVal = 0; - - printf ("Livelock statistics are printed on the fly.\n"); - printf ("qId Type EnableCnt DisableCnt IntEnableState Callbacks\n"); - printf ("=== ======== ========= ========== ============== =========\n"); - - for (i=0; i<= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - if (ixQMgrQTypes[i] != IX_QMGR_TYPE_REALTIME_OTHER) - { - printf (" %2d ", i); - - if (ixQMgrQTypes[i] == IX_QMGR_TYPE_REALTIME_SPORADIC) - { - printf ("Sporadic"); - } - else - { - printf ("Periodic"); - } - - - ixQMgrAqmIfQInterruptEnableRegRead (IX_QMGR_QUELOW_GROUP, - &intEnableRegVal); - - - intEnableRegVal &= dispatchQInfo[i].intRegCheckMask; - intEnableRegVal = intEnableRegVal >> i; - - printf (" %10d %10d %10d %10d\n", - dispatcherStats.queueStats[i].enableCount, - dispatcherStats.queueStats[i].disableCount, - intEnableRegVal, - dispatcherStats.queueStats[i].callbackCnt); - - if (resetStats) - { - dispatcherStats.queueStats[i].enableCount = - dispatcherStats.queueStats[i].disableCount = - dispatcherStats.queueStats[i].callbackCnt = 0; - } - } - } -#else - IX_QMGR_LOG0("Livelock Prevention statistics are only collected in debug mode\n"); -#endif -} - -void -ixQMgrPeriodicDone (void) -{ - UINT32 i = 0; - UINT32 ixQMgrLockKey = 0; - - /* - * for the lower queues - */ - for (i=0; i <= IX_QMGR_MAX_LOW_QUE_TABLE_INDEX; i++) - { - /* - * check for sporadics - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrQTypes[i]) - { - /* - * enable any sporadics - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(i); - ixOsalIrqUnlock(ixQMgrLockKey); -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[i].enableCount++; - dispatcherStats.queueStats[i].notificationEnabled = true; -#endif - } - } -} -IX_STATUS -ixQMgrCallbackTypeSet (IxQMgrQId qId, - IxQMgrType type) -{ - UINT32 ixQMgrLockKey = 0; - IxQMgrType ixQMgrOldType =0; - -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(!IX_QMGR_DISPATCHER_CALLBACK_TYPE_CHECK(type)) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - ixQMgrOldType = ixQMgrQTypes[qId]; - ixQMgrQTypes[qId] = type; - - /* - * check if Q has been changed from type SPORADIC - */ - if (IX_QMGR_TYPE_REALTIME_SPORADIC == ixQMgrOldType) - { - /* - * previously Q was a SPORADIC, this means that LLP - * might have had it disabled. enable it now. - */ - ixQMgrLockKey = ixOsalIrqLock(); - ixQMgrAqmIfQInterruptEnable(qId); - ixOsalIrqUnlock(ixQMgrLockKey); - -#ifndef NDEBUG - /* - * Update statistics - */ - dispatcherStats.queueStats[qId].enableCount++; -#endif - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrCallbackTypeGet (IxQMgrQId qId, - IxQMgrType *type) -{ -#ifndef NDEBUG - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - if (qId >= IX_QMGR_MIN_QUEUPP_QID) - { - return IX_QMGR_PARAMETER_ERROR; - } - if(type == NULL) - { - return IX_QMGR_PARAMETER_ERROR; - } -#endif - - *type = ixQMgrQTypes[qId]; - return IX_SUCCESS; -} diff --git a/drivers/net/npe/IxQMgrInit.c b/drivers/net/npe/IxQMgrInit.c deleted file mode 100644 index 14687e61afb..00000000000 --- a/drivers/net/npe/IxQMgrInit.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - * @file IxQMgrInit.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief: Provided initialization of the QMgr component and its subcomponents. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDispatcher_p.h" -#include "IxQMgrLog_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrDefines_p.h" -#include "IxQMgrAqmIf_p.h" - -/* - * Set to true if initialized - * N.B. global so integration/unit tests can reinitialize - */ -BOOL qMgrIsInitialized = false; - -/* - * Function definitions. - */ -IX_STATUS -ixQMgrInit (void) -{ - if (qMgrIsInitialized) - { - IX_QMGR_LOG0("ixQMgrInit: IxQMgr already initialised\n"); - return IX_FAIL; - } - - /* Initialise the QCfg component */ - ixQMgrQCfgInit (); - - /* Initialise the Dispatcher component */ - ixQMgrDispatcherInit (); - - /* Initialise the Access component */ - ixQMgrQAccessInit (); - - /* Initialization complete */ - qMgrIsInitialized = true; - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrUnload (void) -{ - if (!qMgrIsInitialized) - { - return IX_FAIL; - } - - /* Uninitialise the QCfg component */ - ixQMgrQCfgUninit (); - - /* Uninitialization complete */ - qMgrIsInitialized = false; - - return IX_SUCCESS; -} - -void -ixQMgrShow (void) -{ - IxQMgrQCfgStats *qCfgStats = NULL; - IxQMgrDispatcherStats *dispatcherStats = NULL; - int i; - UINT32 lowIntRegRead, upIntRegRead; - - qCfgStats = ixQMgrQCfgStatsGet (); - dispatcherStats = ixQMgrDispatcherStatsGet (); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUELOW_GROUP, &lowIntRegRead); - ixQMgrAqmIfQInterruptRegRead (IX_QMGR_QUEUPP_GROUP, &upIntRegRead); - printf("Generic Stats........\n"); - printf("=====================\n"); - printf("Loop Run Count..........%u\n",dispatcherStats->loopRunCnt); - printf("Watermark set count.....%d\n", qCfgStats->wmSetCnt); - printf("===========================================\n"); - printf("On the fly Interrupt Register Stats........\n"); - printf("===========================================\n"); - printf("Lower Interrupt Register............0x%08x\n",lowIntRegRead); - printf("Upper Interrupt Register............0x%08x\n",upIntRegRead); - printf("==============================================\n"); - printf("Queue Specific Stats........\n"); - printf("============================\n"); - - for (i=0; iqStats[qId].qName); - printf(" Size in words............ %u\n", qCfgStats->qStats[qId].qSizeInWords); - printf(" Entry size in words...... %u\n", qCfgStats->qStats[qId].qEntrySizeInWords); - printf(" Nearly empty watermark... %u\n", qCfgStats->qStats[qId].ne); - printf(" Nearly full watermark.... %u\n", qCfgStats->qStats[qId].nf); - printf(" Number of full entries... %u\n", qCfgStats->qStats[qId].numEntries); - printf(" Sram base address........ 0x%X\n", qCfgStats->qStats[qId].baseAddress); - printf(" Read pointer............. 0x%X\n", qCfgStats->qStats[qId].readPtr); - printf(" Write pointer............ 0x%X\n", qCfgStats->qStats[qId].writePtr); - -#ifndef NDEBUG - if (dispatcherStats->queueStats[qId].notificationEnabled) - { - char *localEvent = "none ????"; - switch (dispatcherStats->queueStats[qId].srcSel) - { - case IX_QMGR_Q_SOURCE_ID_E: - localEvent = "Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NE: - localEvent = "Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NF: - localEvent = "Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_F: - localEvent = "Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_E: - localEvent = "Not Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NE: - localEvent = "Not Nearly Empty"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_NF: - localEvent = "Not Nearly Full"; - break; - case IX_QMGR_Q_SOURCE_ID_NOT_F: - localEvent = "Not Full"; - break; - default : - break; - } - printf(" Notifications localEvent...... %s\n", localEvent); - } - else - { - printf(" Notifications............ not enabled\n"); - } - printf(" IxQMgrDispatcher Stats\n"); - printf(" Callback count................%d\n", - dispatcherStats->queueStats[qId].callbackCnt); - printf(" Priority change count.........%d\n", - dispatcherStats->queueStats[qId].priorityChangeCnt); - printf(" Interrupt no callback count...%d\n", - dispatcherStats->queueStats[qId].intNoCallbackCnt); - printf(" Interrupt lost callback count...%d\n", - dispatcherStats->queueStats[qId].intLostCallbackCnt); -#endif - - return IX_SUCCESS; -} - - - - diff --git a/drivers/net/npe/IxQMgrQAccess.c b/drivers/net/npe/IxQMgrQAccess.c deleted file mode 100644 index 13ee0f4f118..00000000000 --- a/drivers/net/npe/IxQMgrQAccess.c +++ /dev/null @@ -1,772 +0,0 @@ -/** - * @file IxQMgrQAccess.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This file contains functions for putting entries on a queue and - * removing entries from a queue. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * Inlines are compiled as function when this is defined. - * N.B. Must be placed before #include of "IxQMgr.h" - */ -#ifndef IXQMGR_H -# define IXQMGRQACCESS_C -#else -# error -#endif - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQAccess_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * Global variables and extern definitions - */ -extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - -/* - * Function definitions. - */ -void -ixQMgrQAccessInit (void) -{ -} - -IX_STATUS -ixQMgrQReadWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPop (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qReadCount-- > infoPtr->qSizeInEntries) - { - infoPtr->qReadCount = 0; - } - - /* Check if underflow occurred on the read */ - if (ixQMgrAqmIfUnderflowCheck (qId)) - { - return IX_QMGR_Q_UNDERFLOW; - } - - return IX_SUCCESS; -} - -/* this function reads the remaining of the q entry - * for queues configured with many words. - * (the first word of the entry is already read - * in the inlined function and the entry pointer already - * incremented - */ -IX_STATUS -ixQMgrQReadMWordsMinus1 (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize = infoPtr->qEntrySizeInWords; - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - while (--entrySize) - { - /* read the entry and accumulate the result */ - *(++entry) = IX_OSAL_READ_LONG(++qAccRegAddr); - } - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQWriteWithChecks (IxQMgrQId qId, - UINT32 *entry) -{ - IxQMgrQEntrySizeInWords entrySizeInWords; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - if (NULL == entry) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - /* Get the q entry size in words */ - entrySizeInWords = ixQMgrQEntrySizeInWordsGet (qId); - - ixQMgrAqmIfQPush (qId, entrySizeInWords, entry); - - /* reset the current read count if the counter wrapped around - * (unsigned arithmetic) - */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - if (infoPtr->qWriteCount++ >= infoPtr->qSizeInEntries) - { - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write*/ - if (ixQMgrAqmIfOverflowCheck (qId)) - { - return IX_QMGR_Q_OVERFLOW; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQPeek (IxQMgrQId qId, - unsigned int entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex >= IX_QMGR_Q_SIZE_INVALID)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (entryIndex >= numEntries) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPeek (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQPoke (IxQMgrQId qId, - unsigned entryIndex, - UINT32 *entry) -{ - unsigned int numEntries; - -#ifndef NDEBUG - if ((NULL == entry) || (entryIndex > 128)) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &numEntries)) - { - return IX_FAIL; - } - - if (numEntries < (entryIndex + 1)) /* entryIndex starts at 0 */ - { - return IX_QMGR_ENTRY_INDEX_OUT_OF_BOUNDS; - } - - return ixQMgrAqmIfQPoke (qId, entryIndex, entry); -} - -IX_STATUS -ixQMgrQStatusGetWithChecks (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - if (NULL == qStatus) - { - return IX_QMGR_PARAMETER_ERROR; - } - - if (!ixQMgrQIsConfigured (qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - ixQMgrAqmIfQueStatRead (qId, qStatus); - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrQNumEntriesGet (IxQMgrQId qId, - unsigned *numEntriesPtr) -{ - UINT32 qPtrs; - UINT32 qStatus; - unsigned numEntries; - IxQMgrQInlinedReadWriteInfo *infoPtr; - - -#ifndef NDEBUG - if (NULL == numEntriesPtr) - { - return IX_QMGR_PARAMETER_ERROR; - } - - /* Check QId */ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } -#endif - - /* get fast access data */ - infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - - /* get snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - numEntries = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (numEntries == 0) - { - /* - * Could mean either full or empty queue - * so look at status - */ - ixQMgrAqmIfQueStatRead (qId, &qStatus); - - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - if (qStatus & IX_QMGR_Q_STATUS_E_BIT_MASK) - { - /* Empty */ - *numEntriesPtr = 0; - } - else if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* Full */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* - * Queue status and read/write pointers are volatile. - * The queue state has changed since we took the - * snapshot of the read and write pointers. - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - else /* It is an upper queue which does not have an empty status bit maintained */ - { - if (qStatus & IX_QMGR_Q_STATUS_F_BIT_MASK) - { - /* The queue is Full at the time of snapshot. */ - *numEntriesPtr = infoPtr->qSizeInEntries; - } - else - { - /* The queue is either empty, either moving, - * Client can retry if they wish - */ - *numEntriesPtr = 0; - return IX_QMGR_WARNING; - } - } - } - else - { - *numEntriesPtr = (numEntries / infoPtr->qEntrySizeInWords) & (infoPtr->qSizeInEntries - 1); - } - - return IX_SUCCESS; -} - -#if defined(__wince) && defined(NO_INLINE_APIS) - -PUBLIC IX_STATUS -ixQMgrQRead (IxQMgrQId qId, - UINT32 *entryPtr) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entry, entrySize; - - /* get a new entry */ - entrySize = infoPtr->qEntrySizeInWords; - entry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - *entryPtr = entry; - /* process the remaining part of the entry */ - return ixQMgrQReadMWordsMinus1(qId, entryPtr); - } - - /* underflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* the counter of queue entries is decremented. In happy - * day scenario there are many entries in the queue - * and the counter does not reach zero. - */ - if (infoPtr->qReadCount-- == 0) - { - /* There is maybe no entry in the queue - * qReadCount is now negative, but will be corrected before - * the function returns. - */ - UINT32 qPtrs; /* queue internal pointers */ - - /* when a queue is empty, the hw guarantees to return - * a null value. If the value is not null, the queue is - * not empty. - */ - if (entry == 0) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* check the underflow status */ - if (status & infoPtr->qUflowStatBitMask) - { - /* the queue is empty - * clear the underflow status bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - *entryPtr = 0; - infoPtr->qReadCount = 0; - return IX_QMGR_Q_UNDERFLOW; - } - } - /* store the result */ - *entryPtr = entry; - - /* No underflow occured : someone is filling the queue - * or the queue contains null entries. - * The current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get snapshot of queue pointers */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* no entry in the queue */ - infoPtr->qReadCount = 0; - } - else - { - /* convert the number of words inside the queue - * to a number of entries - */ - infoPtr->qReadCount = qPtrs & (infoPtr->qSizeInEntries - 1); - } - return IX_SUCCESS; - } - } - *entryPtr = entry; - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstRead (IxQMgrQId qId, - UINT32 numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 nullCheckEntry; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - - /* the code is optimized to take care of data dependencies: - * Durig a read, there are a few cycles needed to get the - * read complete. During these cycles, it is poossible to - * do some CPU, e.g. increment pointers and decrement - * counters. - */ - - /* fetch a queue entry */ - nullCheckEntry = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr); - - /* iterate the specified number of queue entries */ - while (--numEntries) - { - /* check the result of the previous read */ - if (nullCheckEntry == 0) - { - /* if we read a NULL entry, stop. We have underflowed */ - break; - } - else - { - /* write the entry */ - *entries = nullCheckEntry; - /* fetch next entry */ - nullCheckEntry = IX_OSAL_READ_LONG(qAccRegAddr); - /* increment the write address */ - entries++; - } - } - /* write the pre-fetched entry */ - *entries = nullCheckEntry; - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - /* read the specified number of queue entries */ - nullCheckEntry = 0; - while (numEntries--) - { - int i; - - for (i = 0; i < entrySizeInWords; i++) - { - *entries = IX_OSAL_READ_LONG(infoPtr->qAccRegAddr + i); - nullCheckEntry |= *entries++; - } - - /* if we read a NULL entry, stop. We have underflowed */ - if (nullCheckEntry == 0) - { - break; - } - nullCheckEntry = 0; - } - } - - /* reset the current read count : next access to the read function - * will force a underflow status check - */ - infoPtr->qWriteCount = 0; - - /* Check if underflow occurred on the read */ - if (nullCheckEntry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - if (status & infoPtr->qUflowStatBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qUflowStatBitMask); - return IX_QMGR_Q_UNDERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQWrite (IxQMgrQId qId, - UINT32 *entry) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 entrySize; - - /* write the entry */ - IX_OSAL_WRITE_LONG(infoPtr->qAccRegAddr, *entry); - entrySize = infoPtr->qEntrySizeInWords; - - if (entrySize != IX_QMGR_Q_ENTRY_SIZE1) - { - /* process the remaining part of the entry */ - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (--entrySize) - { - ++entry; - IX_OSAL_WRITE_LONG(++qAccRegAddr, *entry); - } - entrySize = infoPtr->qEntrySizeInWords; - } - - /* overflow is available for lower queues only */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - UINT32 qSize = infoPtr->qSizeInEntries; - /* increment the current number of entries in the queue - * and check for overflow - */ - if (infoPtr->qWriteCount++ == qSize) - { - /* the queue may have overflow */ - UINT32 qPtrs; /* queue internal pointers */ - - /* get the queue status */ - UINT32 status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be immediately ready after the write operation - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* the queue is full, clear the overflow status - * bit if it was set - */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - return IX_QMGR_Q_OVERFLOW; - } - /* No overflow occured : someone is draining the queue - * and the current counter needs to be - * updated from the current number of entries in the queue - */ - - /* get q pointer snapshot */ - qPtrs = IX_OSAL_READ_LONG(infoPtr->qConfigRegAddr); - - /* Mod subtraction of pointers to get number of words in Q. */ - qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f; - - if (qPtrs == 0) - { - /* the queue may be full at the time of the - * snapshot. Next access will check - * the overflow status again. - */ - infoPtr->qWriteCount = qSize; - } - else - { - /* convert the number of words to a number of entries */ - if (entrySize == IX_QMGR_Q_ENTRY_SIZE1) - { - infoPtr->qWriteCount = qPtrs & (qSize - 1); - } - else - { - infoPtr->qWriteCount = (qPtrs / entrySize) & (qSize - 1); - } - } - } - } - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQBurstWrite (IxQMgrQId qId, - unsigned numEntries, - UINT32 *entries) -{ - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - UINT32 status; - - /* update the current write count */ - infoPtr->qWriteCount += numEntries; - - if (infoPtr->qEntrySizeInWords == IX_QMGR_Q_ENTRY_SIZE1) - { - volatile UINT32 *qAccRegAddr = infoPtr->qAccRegAddr; - while (numEntries--) - { - IX_OSAL_WRITE_LONG(qAccRegAddr, *entries); - entries++; - } - } - else - { - IxQMgrQEntrySizeInWords entrySizeInWords = infoPtr->qEntrySizeInWords; - int i; - - /* write each queue entry */ - while (numEntries--) - { - /* write the queueEntrySize number of words for each entry */ - for (i = 0; i < entrySizeInWords; i++) - { - IX_OSAL_WRITE_LONG((infoPtr->qAccRegAddr + i), *entries); - entries++; - } - } - } - - /* check if the write count overflows */ - if (infoPtr->qWriteCount > infoPtr->qSizeInEntries) - { - /* reset the current write count */ - infoPtr->qWriteCount = infoPtr->qSizeInEntries; - } - - /* Check if overflow occurred on the write operation */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - /* get the queue status */ - status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr); - - /* read the status twice because the status may - * not be ready at the time of the write - */ - if ((status & infoPtr->qOflowStatBitMask) || - ((status = IX_OSAL_READ_LONG(infoPtr->qUOStatRegAddr)) - & infoPtr->qOflowStatBitMask)) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(infoPtr->qUOStatRegAddr, - status & ~infoPtr->qOflowStatBitMask); - return IX_QMGR_Q_OVERFLOW; - } - } - - return IX_SUCCESS; -} - -PUBLIC IX_STATUS -ixQMgrQStatusGet (IxQMgrQId qId, - IxQMgrQStatus *qStatus) -{ - /* read the status of a queue in the range 0-31 */ - if (qId < IX_QMGR_MIN_QUEUPP_QID) - { - extern UINT32 ixQMgrAqmIfQueLowStatRegAddr[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsOffset[]; - extern UINT32 ixQMgrAqmIfQueLowStatBitsMask; - extern IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[]; - IxQMgrQInlinedReadWriteInfo *infoPtr = &ixQMgrQInlinedReadWriteInfo[qId]; - volatile UINT32 *lowStatRegAddr = (UINT32*)ixQMgrAqmIfQueLowStatRegAddr[qId]; - volatile UINT32 *qUOStatRegAddr = infoPtr->qUOStatRegAddr; - - UINT32 lowStatBitsOffset = ixQMgrAqmIfQueLowStatBitsOffset[qId]; - UINT32 lowStatBitsMask = ixQMgrAqmIfQueLowStatBitsMask; - UINT32 underflowBitMask = infoPtr->qUflowStatBitMask; - UINT32 overflowBitMask = infoPtr->qOflowStatBitMask; - - /* read the status register for this queue */ - *qStatus = IX_OSAL_READ_LONG(lowStatRegAddr); - /* mask out the status bits relevant only to this queue */ - *qStatus = (*qStatus >> lowStatBitsOffset) & lowStatBitsMask; - - /* Check if the queue has overflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & overflowBitMask) - { - /* clear the overflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~overflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_OF_BIT_MASK; - } - - /* Check if the queue has underflowed */ - if (IX_OSAL_READ_LONG(qUOStatRegAddr) & underflowBitMask) - { - /* clear the underflow status bit if it was set */ - IX_OSAL_WRITE_LONG(qUOStatRegAddr, - (IX_OSAL_READ_LONG(qUOStatRegAddr) & - ~underflowBitMask)); - *qStatus |= IX_QMGR_Q_STATUS_UF_BIT_MASK; - } - } - else /* read status of a queue in the range 32-63 */ - { - extern UINT32 ixQMgrAqmIfQueUppStat0RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat1RegAddr; - extern UINT32 ixQMgrAqmIfQueUppStat0BitMask[]; - extern UINT32 ixQMgrAqmIfQueUppStat1BitMask[]; - - volatile UINT32 *qNearEmptyStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat0RegAddr; - volatile UINT32 *qFullStatRegAddr = (UINT32*)ixQMgrAqmIfQueUppStat1RegAddr; - int maskIndex = qId - IX_QMGR_MIN_QUEUPP_QID; - UINT32 qNearEmptyStatBitMask = ixQMgrAqmIfQueUppStat0BitMask[maskIndex]; - UINT32 qFullStatBitMask = ixQMgrAqmIfQueUppStat1BitMask[maskIndex]; - - /* Reset the status bits */ - *qStatus = 0; - - /* Check if the queue is nearly empty */ - if (IX_OSAL_READ_LONG(qNearEmptyStatRegAddr) & qNearEmptyStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_NE_BIT_MASK; - } - - /* Check if the queue is full */ - if (IX_OSAL_READ_LONG(qFullStatRegAddr) & qFullStatBitMask) - { - *qStatus |= IX_QMGR_Q_STATUS_F_BIT_MASK; - } - } - return IX_SUCCESS; -} -#endif /* def NO_INLINE_APIS */ diff --git a/drivers/net/npe/IxQMgrQCfg.c b/drivers/net/npe/IxQMgrQCfg.c deleted file mode 100644 index b64bb2dd909..00000000000 --- a/drivers/net/npe/IxQMgrQCfg.c +++ /dev/null @@ -1,519 +0,0 @@ -/** - * @file QMgrQCfg.c - * - * @author Intel Corporation - * @date 30-Oct-2001 - * - * @brief This modules provides an interface for setting up the static - * configuration of AQM queues.This file contains the following - * functions: - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* - * System defined include files. - */ - -/* - * User defined include files. - */ -#include "IxOsal.h" -#include "IxQMgr.h" -#include "IxQMgrAqmIf_p.h" -#include "IxQMgrQCfg_p.h" -#include "IxQMgrDefines_p.h" - -/* - * #defines and macros used in this file. - */ - -#define IX_QMGR_MIN_ENTRY_SIZE_IN_WORDS 16 - -/* Total size of SRAM */ -#define IX_QMGR_AQM_SRAM_SIZE_IN_BYTES 0x4000 - -/* - * Check that qId is a valid queue identifier. This is provided to - * make the code easier to read. - */ -#define IX_QMGR_QID_IS_VALID(qId) \ -(((qId) >= (IX_QMGR_MIN_QID)) && ((qId) <= (IX_QMGR_MAX_QID))) - -/* - * Typedefs whose scope is limited to this file. - */ - -/* - * This struct describes an AQM queue. - * N.b. bufferSizeInWords and qEntrySizeInWords are stored in the queue - * as these are requested by Access in the data path. sizeInEntries is - * not required by the data path so it can be calculated dynamically. - * - */ -typedef struct -{ - char qName[IX_QMGR_MAX_QNAME_LEN+1]; /* Textual description of a queue*/ - IxQMgrQSizeInWords qSizeInWords; /* The number of words in the queue */ - IxQMgrQEntrySizeInWords qEntrySizeInWords; /* Number of words per queue entry*/ - BOOL isConfigured; /* This flag is true if the queue has - * been configured - */ -} IxQMgrCfgQ; - -/* - * Variable declarations global to this file. Externs are followed by - * statics. - */ - -extern UINT32 * ixQMgrAqmIfQueAccRegAddr[]; - -/* Store data required to inline read and write access - */ -IxQMgrQInlinedReadWriteInfo ixQMgrQInlinedReadWriteInfo[IX_QMGR_MAX_NUM_QUEUES]; - -static IxQMgrCfgQ cfgQueueInfo[IX_QMGR_MAX_NUM_QUEUES]; - -/* This pointer holds the starting address of AQM SRAM not used by - * the AQM queues. - */ -static UINT32 freeSramAddress=0; - -/* 4 words of zeroed memory for inline access */ -static UINT32 zeroedPlaceHolder[4] = { 0, 0, 0, 0 }; - -static BOOL cfgInitialized = false; - -static IxOsalMutex ixQMgrQCfgMutex; - -/* - * Statistics - */ -static IxQMgrQCfgStats stats; - -/* - * Function declarations - */ -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level); - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize); - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize); - -/* - * Function definitions. - */ -void -ixQMgrQCfgInit (void) -{ - int loopIndex; - - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - /* info for code inlining */ - ixQMgrAqmIfQueAccRegAddr[loopIndex] = zeroedPlaceHolder; - - /* info for code inlining */ - ixQMgrQInlinedReadWriteInfo[loopIndex].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qAccRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUOStatRegAddr = zeroedPlaceHolder; - ixQMgrQInlinedReadWriteInfo[loopIndex].qUflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qOflowStatBitMask = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qEntrySizeInWords = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qSizeInEntries = 0; - ixQMgrQInlinedReadWriteInfo[loopIndex].qConfigRegAddr = zeroedPlaceHolder; - } - - /* Initialise the AqmIf component */ - ixQMgrAqmIfInit (); - - /* Reset all queues to have queue name = NULL, entry size = 0 and - * isConfigured = false - */ - for (loopIndex=0; loopIndex < IX_QMGR_MAX_NUM_QUEUES;loopIndex++) - { - strcpy (cfgQueueInfo[loopIndex].qName, ""); - cfgQueueInfo[loopIndex].qSizeInWords = 0; - cfgQueueInfo[loopIndex].qEntrySizeInWords = 0; - cfgQueueInfo[loopIndex].isConfigured = false; - - /* Statistics */ - stats.qStats[loopIndex].isConfigured = false; - stats.qStats[loopIndex].qName = cfgQueueInfo[loopIndex].qName; - } - - /* Statistics */ - stats.wmSetCnt = 0; - - ixQMgrAqmIfSramBaseAddressGet (&freeSramAddress); - - ixOsalMutexInit(&ixQMgrQCfgMutex); - - cfgInitialized = true; -} - -void -ixQMgrQCfgUninit (void) -{ - cfgInitialized = false; - - /* Uninitialise the AqmIf component */ - ixQMgrAqmIfUninit (); -} - -IX_STATUS -ixQMgrQConfig (char *qName, - IxQMgrQId qId, - IxQMgrQSizeInWords qSizeInWords, - IxQMgrQEntrySizeInWords qEntrySizeInWords) -{ - UINT32 aqmLocalBaseAddress; - - if (!cfgInitialized) - { - return IX_FAIL; - } - - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return IX_QMGR_INVALID_Q_ID; - } - - else if (NULL == qName) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (strlen (qName) > IX_QMGR_MAX_QNAME_LEN) - { - return IX_QMGR_PARAMETER_ERROR; - } - - else if (!qSizeInWordsIsOk (qSizeInWords)) - { - return IX_QMGR_INVALID_QSIZE; - } - - else if (!qEntrySizeInWordsIsOk (qEntrySizeInWords)) - { - return IX_QMGR_INVALID_Q_ENTRY_SIZE; - } - - else if (cfgQueueInfo[qId].isConfigured) - { - return IX_QMGR_Q_ALREADY_CONFIGURED; - } - - ixOsalMutexLock(&ixQMgrQCfgMutex, IX_OSAL_WAIT_FOREVER); - - /* Write the config register */ - ixQMgrAqmIfQueCfgWrite (qId, - qSizeInWords, - qEntrySizeInWords, - freeSramAddress); - - - strcpy (cfgQueueInfo[qId].qName, qName); - cfgQueueInfo[qId].qSizeInWords = qSizeInWords; - cfgQueueInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - - /* store pre-computed information in the same cache line - * to facilitate inlining of QRead and QWrite functions - * in IxQMgr.h - */ - ixQMgrQInlinedReadWriteInfo[qId].qReadCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qWriteCount = 0; - ixQMgrQInlinedReadWriteInfo[qId].qEntrySizeInWords = qEntrySizeInWords; - ixQMgrQInlinedReadWriteInfo[qId].qSizeInEntries = - (UINT32)qSizeInWords / (UINT32)qEntrySizeInWords; - - /* Calculate the new freeSramAddress from the size of the queue - * currently being configured. - */ - freeSramAddress += (qSizeInWords * IX_QMGR_NUM_BYTES_PER_WORD); - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - IX_OSAL_ASSERT((freeSramAddress - (aqmLocalBaseAddress + (IX_QMGR_QUEBUFFER_SPACE_OFFSET))) <= - IX_QMGR_QUE_BUFFER_SPACE_SIZE); - - /* The queue is now configured */ - cfgQueueInfo[qId].isConfigured = true; - - ixOsalMutexUnlock(&ixQMgrQCfgMutex); - -#ifndef NDEBUG - /* Update statistics */ - stats.qStats[qId].isConfigured = true; - stats.qStats[qId].qName = cfgQueueInfo[qId].qName; -#endif - return IX_SUCCESS; -} - -IxQMgrQSizeInWords -ixQMgrQSizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qSizeInWords); -} - -IX_STATUS -ixQMgrQSizeInEntriesGet (IxQMgrQId qId, - unsigned *qSizeInEntries) -{ - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if(NULL == qSizeInEntries) - { - return IX_QMGR_PARAMETER_ERROR; - } - - *qSizeInEntries = (UINT32)(cfgQueueInfo[qId].qSizeInWords) / - (UINT32)cfgQueueInfo[qId].qEntrySizeInWords; - - return IX_SUCCESS; -} - -IxQMgrQEntrySizeInWords -ixQMgrQEntrySizeInWordsGet (IxQMgrQId qId) -{ - /* No parameter checking as this is used on the data path */ - return (cfgQueueInfo[qId].qEntrySizeInWords); -} - -IX_STATUS -ixQMgrWatermarkSet (IxQMgrQId qId, - IxQMgrWMLevel ne, - IxQMgrWMLevel nf) -{ - IxQMgrQStatus qStatusOnEntry;/* The queue status on entry/exit */ - IxQMgrQStatus qStatusOnExit; /* to this function */ - - if (!ixQMgrQIsConfigured(qId)) - { - return IX_QMGR_Q_NOT_CONFIGURED; - } - - if (!watermarkLevelIsOk (qId, ne)) - { - return IX_QMGR_INVALID_Q_WM; - } - - if (!watermarkLevelIsOk (qId, nf)) - { - return IX_QMGR_INVALID_Q_WM; - } - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnEntry); - -#ifndef NDEBUG - /* Update statistics */ - stats.wmSetCnt++; -#endif - - ixQMgrAqmIfWatermarkSet (qId, - ne, - nf); - - /* Get the current queue status */ - ixQMgrAqmIfQueStatRead (qId, &qStatusOnExit); - - /* If the status has changed return a warning */ - if (qStatusOnEntry != qStatusOnExit) - { - return IX_QMGR_WARNING; - } - - return IX_SUCCESS; -} - -IX_STATUS -ixQMgrAvailableSramAddressGet (UINT32 *address, - unsigned *sizeOfFreeRam) -{ - UINT32 aqmLocalBaseAddress; - - if ((NULL == address)||(NULL == sizeOfFreeRam)) - { - return IX_QMGR_PARAMETER_ERROR; - } - if (!cfgInitialized) - { - return IX_FAIL; - } - - *address = freeSramAddress; - - /* Get the virtual SRAM address */ - ixQMgrAqmIfBaseAddressGet (&aqmLocalBaseAddress); - - /* - * Calculate the size in bytes of free sram - * i.e. current free SRAM virtual pointer from - * (base + total size) - */ - *sizeOfFreeRam = - (aqmLocalBaseAddress + - IX_QMGR_AQM_SRAM_SIZE_IN_BYTES) - - freeSramAddress; - - if (0 == *sizeOfFreeRam) - { - return IX_QMGR_NO_AVAILABLE_SRAM; - } - - return IX_SUCCESS; -} - -BOOL -ixQMgrQIsConfigured (IxQMgrQId qId) -{ - if (!IX_QMGR_QID_IS_VALID(qId)) - { - return false; - } - - return cfgQueueInfo[qId].isConfigured; -} - -IxQMgrQCfgStats* -ixQMgrQCfgStatsGet (void) -{ - return &stats; -} - -IxQMgrQCfgStats* -ixQMgrQCfgQStatsGet (IxQMgrQId qId) -{ - unsigned int ne; - unsigned int nf; - UINT32 baseAddress; - UINT32 readPtr; - UINT32 writePtr; - - stats.qStats[qId].qSizeInWords = cfgQueueInfo[qId].qSizeInWords; - stats.qStats[qId].qEntrySizeInWords = cfgQueueInfo[qId].qEntrySizeInWords; - - if (IX_SUCCESS != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - if (IX_QMGR_WARNING != ixQMgrQNumEntriesGet (qId, &stats.qStats[qId].numEntries)) - { - IX_QMGR_LOG_WARNING1("Failed to get the number of entries in queue.... %d\n", qId); - } - } - - ixQMgrAqmIfQueCfgRead (qId, - stats.qStats[qId].numEntries, - &baseAddress, - &ne, - &nf, - &readPtr, - &writePtr); - - stats.qStats[qId].baseAddress = baseAddress; - stats.qStats[qId].ne = ne; - stats.qStats[qId].nf = nf; - stats.qStats[qId].readPtr = readPtr; - stats.qStats[qId].writePtr = writePtr; - - return &stats; -} - -/* - * Static function definitions - */ - -PRIVATE BOOL -watermarkLevelIsOk (IxQMgrQId qId, IxQMgrWMLevel level) -{ - unsigned qSizeInEntries; - - switch (level) - { - case IX_QMGR_Q_WM_LEVEL0: - case IX_QMGR_Q_WM_LEVEL1: - case IX_QMGR_Q_WM_LEVEL2: - case IX_QMGR_Q_WM_LEVEL4: - case IX_QMGR_Q_WM_LEVEL8: - case IX_QMGR_Q_WM_LEVEL16: - case IX_QMGR_Q_WM_LEVEL32: - case IX_QMGR_Q_WM_LEVEL64: - break; - default: - return false; - } - - /* Check watermark is not bigger than the qSizeInEntries */ - ixQMgrQSizeInEntriesGet(qId, &qSizeInEntries); - - if ((unsigned)level > qSizeInEntries) - { - return false; - } - - return true; -} - -PRIVATE BOOL -qSizeInWordsIsOk (IxQMgrQSizeInWords qSize) -{ - BOOL status; - - switch (qSize) - { - case IX_QMGR_Q_SIZE16: - case IX_QMGR_Q_SIZE32: - case IX_QMGR_Q_SIZE64: - case IX_QMGR_Q_SIZE128: - status = true; - break; - default: - status = false; - break; - } - - return status; -} - -PRIVATE BOOL -qEntrySizeInWordsIsOk (IxQMgrQEntrySizeInWords entrySize) -{ - BOOL status; - - switch (entrySize) - { - case IX_QMGR_Q_ENTRY_SIZE1: - case IX_QMGR_Q_ENTRY_SIZE2: - case IX_QMGR_Q_ENTRY_SIZE4: - status = true; - break; - default: - status = false; - break; - } - - return status; -} diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile deleted file mode 100644 index 07792552167..00000000000 --- a/drivers/net/npe/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux -CFLAGS += $(LOCAL_CFLAGS) -CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend - -obj-y := npe.o \ - miiphy.o \ - IxOsalBufferMgt.o \ - IxOsalIoMem.o \ - IxOsalOsCacheMMU.o \ - IxOsalOsMsgQ.o \ - IxOsalOsSemaphore.o \ - IxOsalOsServices.o \ - IxOsalOsThread.o \ - IxEthAcc.o \ - IxEthAccCommon.o \ - IxEthAccControlInterface.o \ - IxEthAccDataPlane.o \ - IxEthAccMac.o \ - IxEthAccMii.o \ - IxEthDBAPI.o \ - IxEthDBAPISupport.o \ - IxEthDBCore.o \ - IxEthDBEvents.o \ - IxEthDBFeatures.o \ - IxEthDBFirewall.o \ - IxEthDBHashtable.o \ - IxEthDBLearning.o \ - IxEthDBMem.o \ - IxEthDBNPEAdaptor.o \ - IxEthDBPortUpdate.o \ - IxEthDBReports.o \ - IxEthDBSearch.o \ - IxEthDBSpanningTree.o \ - IxEthDBUtil.o \ - IxEthDBVlan.o \ - IxEthDBWiFi.o \ - IxEthMii.o \ - IxQMgrAqmIf.o \ - IxQMgrDispatcher.o \ - IxQMgrInit.o \ - IxQMgrQAccess.o \ - IxQMgrQCfg.o \ - IxFeatureCtrl.o \ - IxNpeDl.o \ - IxNpeDlImageMgr.o \ - IxNpeDlNpeMgr.o \ - IxNpeDlNpeMgrUtils.o \ - IxNpeMh.o \ - IxNpeMhConfig.o \ - IxNpeMhReceive.o \ - IxNpeMhSend.o \ - IxNpeMhSolicitedCbMgr.o \ - IxNpeMhUnsolicitedCbMgr.o diff --git a/drivers/net/npe/include/IxAssert.h b/drivers/net/npe/include/IxAssert.h deleted file mode 100644 index 8be0cafc44f..00000000000 --- a/drivers/net/npe/include/IxAssert.h +++ /dev/null @@ -1,47 +0,0 @@ -/** - * @file IxAssert.h - * - * @date 21-MAR-2002 (replaced by OSAL) - * - * @brief This file contains assert and ensure macros used by the IXP400 software - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxAssert IXP400 Assertion Macros (IxAssert) API - * - * @brief Assertion support - * - * @{ - */ - -#ifndef IXASSERT_H - -#ifndef __doxygen_HIDE -#define IXASSERT_H -#endif /* __doxygen_HIDE */ - -#include "IxOsalBackward.h" - -#endif /* IXASSERT_H */ - -/** - * @} addtogroup IxAssert - */ - - - diff --git a/drivers/net/npe/include/IxAtmSch.h b/drivers/net/npe/include/IxAtmSch.h deleted file mode 100644 index 7d74771c285..00000000000 --- a/drivers/net/npe/include/IxAtmSch.h +++ /dev/null @@ -1,480 +0,0 @@ -/** - * @file IxAtmSch.h - * - * @date 23-NOV-2001 - * - * @brief Header file for the IXP400 ATM Traffic Shaper - * - * This component demonstrates an ATM Traffic Shaper implementation. It - * will perform shaping on upto 12 ports and total of 44 VCs accross all ports, - * 32 are intended for AAL0/5 and 12 for OAM (1 per port). - * The supported traffic types are;1 rt-VBR VC where PCR = SCR. - * (Effectively CBR) and Up-to 44 VBR VCs. - * - * This component models the ATM ports and VCs and is capable of producing - * a schedule of ATM cells per port which can be supplied to IxAtmdAcc - * for execution on the data path. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - * @sa IxAtmm.h - * - */ - -/** - * @defgroup IxAtmSch IXP400 ATM Transmit Scheduler (IxAtmSch) API - * - * @brief IXP400 ATM scheduler component Public API - * - * @{ - */ - -#ifndef IXATMSCH_H -#define IXATMSCH_H - -#include "IxOsalTypes.h" -#include "IxAtmTypes.h" - -/* - * #defines and macros used in this file. - */ - -/* Return codes */ - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_NOT_ADMITTED - * @brief Indicates that CAC function has rejected VC registration due - * to insufficient line capacity. -*/ -#define IX_ATMSCH_RET_NOT_ADMITTED 2 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_FULL - * @brief Indicates that the VC queue is full, no more demand can be - * queued at this time. - */ -#define IX_ATMSCH_RET_QUEUE_FULL 3 - -/** - * @ingroup IxAtmSch - * - * @def IX_ATMSCH_RET_QUEUE_EMPTY - * @brief Indicates that all VC queues on this port are empty and - * therefore there are no cells to be scheduled at this time. - */ -#define IX_ATMSCH_RET_QUEUE_EMPTY 4 - -/* - * Function declarations - */ - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchInit(void) - * - * @brief This function is used to initialize the ixAtmSch component. It - * should be called before any other IxAtmSch API function. - * - * @param None - * - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler component has been successfully initialized. - * -# The scheduler is ready to accept Port modelling requests. - * - IX_FAIL : Some internal error has prevented the scheduler component - * from initialising. - */ -PUBLIC IX_STATUS -ixAtmSchInit(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule) - * - * @brief This function shall be called first to initialize an ATM port before - * any other ixAtmSch API calls may be made for that port. - * - * @param port @ref IxAtmLogicalPort [in] - The specific port to initialize. Valid - * values range from 0 to IX_UTOPIA_MAX_PORTS - 1, representing a - * maximum of IX_UTOPIA_MAX_PORTS possible ports. - * - * @param portRate unsigned int [in] - Value indicating the upstream capacity - * of the indicated port. The value should be supplied in - * units of ATM (53 bytes) cells per second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @param minCellsToSchedule unsigned int [in] - This parameter specifies the minimum - * number of cells which the scheduler will put in a schedule - * table for this port. This value sets the worst case CDVT for VCs - * on this port i.e. CDVT = 1*minCellsToSchedule/portRate. - * @return - * - IX_SUCCESS : indicates that - * -# The ATM scheduler has been successfully initialized. - * -# The requested port model has been established. - * -# The scheduler is ready to accept VC modelling requests - * on the ATM port. - * - IX_FAIL : indicates the requested port could not be - * initialized. */ -PUBLIC IX_STATUS -ixAtmSchPortModelInitialize( IxAtmLogicalPort port, - unsigned int portRate, - unsigned int minCellsToSchedule); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate) - * - * @brief This function is called to modify the portRate on a - * previously initialized port, typically in the event that - * the line condition of the port changes. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port which is to be - * modified. - * - * @param portRate unsigned int [in] - Value indicating the new upstream - * capacity for this port in cells/second. - * A port rate of 800Kbits/s is the equivalent - * of 1886 cells per second - * - * @return - * - IX_SUCCESS : The port rate has been successfully modified.
- * - IX_FAIL : The port rate could not be modified, either - * because the input data was invalid, or the new port rate is - * insufficient to support established ATM VC contracts on this - * port. - * - * @warning The IxAtmSch component will validate the supplied port - * rate is sufficient to support all established VC - * contracts on the port. If the new port rate is - * insufficient to support all established contracts then - * the request to modify the port rate will be rejected. - * In this event, the user is expected to remove - * established contracts using the ixAtmSchVcModelRemove - * interface and then retry this interface. - * - * @sa ixAtmSchVcModelRemove() */ -PUBLIC IX_STATUS -ixAtmSchPortRateModify( IxAtmLogicalPort port, - unsigned int portRate); - - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId) - * - * @brief A client calls this interface to set up an upstream - * (transmitting) virtual connection model (VC) on the - * specified ATM port. This function also provides the - * virtual * connection admission control (CAC) service to the - * client. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is to be established. - * - * @param *trafficDesc @ref IxAtmTrafficDescriptor [in] - Pointer to a structure - * describing the requested traffic contract of the VC to be - * established. This structure contains the typical ATM - * traffic descriptor values (e.g. PCR, SCR, MBS, CDVT, etc.) - * defined by the ATM standard. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - This value will be filled with the - * port-unique identifier for this virtual connection. A - * valid identification is a non-negative number. - * - * @return - * - IX_SUCCESS : The VC has been successfully established on - * this port. The client may begin to submit demand on this VC. - * - IX_ATMSCH_RET_NOT_ADMITTED : The VC cannot be established - * on this port because there is insufficient upstream capacity - * available to support the requested traffic contract descriptor - * - IX_FAIL :Input data are invalid. VC has not been - * established. - */ -PUBLIC IX_STATUS -ixAtmSchVcModelSetup( IxAtmLogicalPort port, - IxAtmTrafficDescriptor *trafficDesc, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId) - * - * @brief A client calls this interface to set the vcUserConnId for a VC on - * the specified ATM port. This vcUserConnId will default to - * IX_ATM_IDLE_CELLS_CONNID if this function is not called for a VC. - * Hence if the client does not call this function for a VC then only idle - * cells will be scheduled for this VC. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the upstream - * VC is has been established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - This is the unique identifier for this virtual - * connection. A valid identification is a non-negative number and is - * all ports. - * - * @param vcUserConnId @ref IxAtmConnId [in] - The connId is used to refer to a VC in schedule - * table entries. It is treated as the Id by which the scheduler client - * knows the VC. It is used in any communicatations from the Scheduler - * to the scheduler user e.g. schedule table entries. - * - * @return - * - IX_SUCCESS : The id has successfully been set. - * - IX_FAIL :Input data are invalid. connId id is not established. - */ -PUBLIC IX_STATUS -ixAtmSchVcConnIdSet( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - IxAtmConnId vcUserConnId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief Interface called by the client to remove a previously - * established VC on a particular port. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * removed is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be removed. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC has been successfully removed from - * this port. It is no longer modelled on this port. - * - IX_FAIL :Input data are invalid. The VC is still being modeled - * by the traffic shaper. - * - * @sa ixAtmSchVcModelSetup() - */ -PUBLIC IX_STATUS -ixAtmSchVcModelRemove( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells) - * - * @brief The client calls this function to notify IxAtmSch that the - * user of a VC has submitted cells for transmission. - * - * This information is stored, aggregated from a number of calls to - * ixAtmSchVcQueueUpdate and eventually used in the call to - * ixAtmSchTableUpdate. - * - * Normally IxAtmSch will update the VC queue by adding the number of - * cells to the current queue length. However, if IxAtmSch - * determines that the user has over-submitted for the VC and - * exceeded its transmission quota the queue request can be rejected. - * The user should resubmit the request later when the queue has been - * depleted. - * - * This implementation of ixAtmSchVcQueueUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an interrupt handler. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueUpdate callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * updated is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be updated. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @param numberOfCells unsigned int [in] - Indicates how many ATM cells should - * be added to the queue for this VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully updated. - * - IX_ATMSCH_RET_QUEUE_FULL : The VC queue has reached a - * preset limit. This indicates the client has over-submitted - * and exceeded its transmission quota. The request is - * rejected. The VC queue is not updated. The VC user is - * advised to resubmit the request later. - * - IX_FAIL : The input are invalid. No VC queue is updated. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueUpdate( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId, - unsigned int numberOfCells); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId) - * - * @brief The client calls this function to remove all currently - * queued cells from a registered VC. The pending cell count - * for the specified VC is reset to zero. - * - * This interface is structurally compatible with the - * IxAtmdAccSchQueueClear callback type definition required for - * IXP400 ATM scheduler interoperability. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be - * cleared is established. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Identifies the VC to be cleared. This is the - * value returned by the @ref ixAtmSchVcModelSetup call which - * established the relevant VC. - * - * @return - * - IX_SUCCESS : The VC queue has been successfully cleared. - * - IX_FAIL : The input are invalid. No VC queue is modified. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchVcQueueClear( IxAtmLogicalPort port, - IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable) - * - * @brief The client calls this function to request an update of the - * schedule table for a particular ATM port. - * - * This is called when the client decides it needs a new sequence of - * cells to send (probably because the transmit queue is near to - * empty for this ATM port). The scheduler will use its stored - * information on the cells submitted for transmit (i.e. data - * supplied via @ref ixAtmSchVcQueueUpdate function) with the traffic - * descriptor information of all established VCs on the ATM port to - * decide the sequence of cells to be sent and fill the schedule - * table for a period of time into the future. - * - * IxAtmSch will guarantee a minimum of minCellsToSchedule if there - * is at least one cell ready to send. If there are no cells then - * IX_ATMSCH_RET_QUEUE_EMPTY is returned. - * - * This implementation of ixAtmSchTableUpdate uses no operating - * system or external facilities, either directly or indirectly. - * This allows clients to call this function form within an FIQ - * interrupt handler. - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port for which requested - * schedule table is to be generated. - * - * @param maxCells unsigned [in] - Specifies the maximum number of cells - * that must be scheduled in the supplied table during any - * call to the interface. - * - * @param **table @ref IxAtmScheduleTable [out] - A pointer to an area of - * storage is returned which contains the generated - * schedule table. The client should not modify the - * contents of this table. - * - * @return - * - IX_SUCCESS : The schedule table has been published. - * Currently there is at least one VC queue that is nonempty. - * - IX_ATMSCH_RET_QUEUE_EMPTY : Currently all VC queues on - * this port are empty. The schedule table returned is set to - * NULL. The client is not expected to invoke this function - * again until more cells have been submitted on this port - * through the @ref ixAtmSchVcQueueUpdate function. - * - IX_FAIL : The input are invalid. No action is taken. - * - * @warning IxAtmSch assumes that the calling software ensures that - * calls to ixAtmSchVcQueueUpdate, ixAtmSchVcQueueClear and - * ixAtmSchTableUpdate are both self and mutually exclusive - * for the same port. - * - * @warning Subsequent calls to this function for the same port will - * overwrite the contents of previously supplied schedule - * tables. The client must be completely finished with the - * previously supplied schedule table before calling this - * function again for the same port. - * - * @sa ixAtmSchVcQueueUpdate(), ixAtmSchVcQueueClear(), ixAtmSchTableUpdate(). */ -PUBLIC IX_STATUS -ixAtmSchTableUpdate( IxAtmLogicalPort port, - unsigned int maxCells, - IxAtmScheduleTable **rettable); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchShow(void) - * - * @brief Utility function which will print statistics on the current - * and accumulated state of VCs and traffic in the ATM - * scheduler component. Output is sent to the default output - * device. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchShow(void); - -/** - * @ingroup IxAtmSch - * - * @fn ixAtmSchStatsClear(void) - * - * @brief Utility function which will reset all counter statistics in - * the ATM scheduler to zero. - * - * @param none - * @return none - */ -PUBLIC void -ixAtmSchStatsClear(void); - -#endif -/* IXATMSCH_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxAtmTypes.h b/drivers/net/npe/include/IxAtmTypes.h deleted file mode 100644 index 6c8d12f3947..00000000000 --- a/drivers/net/npe/include/IxAtmTypes.h +++ /dev/null @@ -1,385 +0,0 @@ -/** - * @file IxAtmTypes.h - * - * @date 24-MAR-2002 - * - * @brief This file contains Atm types common to a number of Atm components. - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxAtmTypes IXP400 ATM Types (IxAtmTypes) - * - * @brief The common set of types used in many Atm components - * - * @{ */ - -#ifndef IXATMTYPES_H -#define IXATMTYPES_H - -#include "IxNpeA.h" - -/** - * @enum IxAtmLogicalPort - * - * @brief Logical Port Definitions : - * - * Only 1 port is available in SPHY configuration - * 12 ports are enabled in MPHY configuration - * - */ -typedef enum -{ - IX_UTOPIA_PORT_0 = 0, /**< Port 0 */ -#ifdef IX_NPE_MPHYMULTIPORT - IX_UTOPIA_PORT_1, /**< Port 1 */ - IX_UTOPIA_PORT_2, /**< Port 2 */ - IX_UTOPIA_PORT_3, /**< Port 3 */ - IX_UTOPIA_PORT_4, /**< Port 4 */ - IX_UTOPIA_PORT_5, /**< Port 5 */ - IX_UTOPIA_PORT_6, /**< Port 6 */ - IX_UTOPIA_PORT_7, /**< Port 7 */ - IX_UTOPIA_PORT_8, /**< Port 8 */ - IX_UTOPIA_PORT_9, /**< Port 9 */ - IX_UTOPIA_PORT_10, /**< Port 10 */ - IX_UTOPIA_PORT_11, /**< Port 11 */ -#endif /* IX_NPE_MPHY */ - IX_UTOPIA_MAX_PORTS /**< Not a port - just a definition for the - * maximum possible ports - */ -} IxAtmLogicalPort; - -/** - * @def IX_ATM_CELL_PAYLOAD_SIZE - * @brief Size of a ATM cell payload - */ -#define IX_ATM_CELL_PAYLOAD_SIZE (48) - -/** - * @def IX_ATM_CELL_SIZE - * @brief Size of a ATM cell, including header - */ -#define IX_ATM_CELL_SIZE (53) - -/** - * @def IX_ATM_CELL_SIZE_NO_HEC - * @brief Size of a ATM cell, excluding HEC byte - */ -#define IX_ATM_CELL_SIZE_NO_HEC (IX_ATM_CELL_SIZE - 1) - -/** - * @def IX_ATM_OAM_CELL_SIZE_NO_HEC - * @brief Size of a OAM cell, excluding HEC byte - */ -#define IX_ATM_OAM_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - -/** - * @def IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE - * @brief Size of a AAL0 48 Cell payload - */ -#define IX_ATM_AAL0_48_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL5_CELL_PAYLOAD_SIZE - * @brief Size of a AAL5 Cell payload - */ -#define IX_ATM_AAL5_CELL_PAYLOAD_SIZE IX_ATM_CELL_PAYLOAD_SIZE - -/** - * @def IX_ATM_AAL0_52_CELL_SIZE_NO_HEC - * @brief Size of a AAL0 52 Cell, excluding HEC byte - */ -#define IX_ATM_AAL0_52_CELL_SIZE_NO_HEC IX_ATM_CELL_SIZE_NO_HEC - - -/** - * @def IX_ATM_MAX_VPI - * @brief Maximum value of an ATM VPI - */ -#define IX_ATM_MAX_VPI 255 - -/** - * @def IX_ATM_MAX_VCI - * @brief Maximum value of an ATM VCI - */ -#define IX_ATM_MAX_VCI 65535 - - /** - * @def IX_ATM_MAX_NUM_AAL_VCS - * @brief Maximum number of active AAL5/AAL0 VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_VCS 32 - -/** - * @def IX_ATM_MAX_NUM_VC - * @brief Maximum number of active AAL5/AAL0 VCs in the system - * The use of this macro is depreciated, it is retained for - * backward compatiblity. For current software release - * and beyond the define IX_ATM_MAX_NUM_AAL_VC should be used. - */ -#define IX_ATM_MAX_NUM_VC IX_ATM_MAX_NUM_AAL_VCS - - - -/** - * @def IX_ATM_MAX_NUM_OAM_TX_VCS - * @brief Maximum number of active OAM Tx VCs in the system, - * 1 OAM VC per port - */ -#define IX_ATM_MAX_NUM_OAM_TX_VCS IX_UTOPIA_MAX_PORTS - -/** - * @def IX_ATM_MAX_NUM_OAM_RX_VCS - * @brief Maximum number of active OAM Rx VCs in the system, - * 1 OAM VC shared accross all ports - */ -#define IX_ATM_MAX_NUM_OAM_RX_VCS 1 - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_TX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Tx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_TX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_TX_VCS) - -/** - * @def IX_ATM_MAX_NUM_AAL_OAM_RX_VCS - * @brief Maximum number of active AAL5/AAL0/OAM Rx VCs in the system - */ -#define IX_ATM_MAX_NUM_AAL_OAM_RX_VCS (IX_ATM_MAX_NUM_AAL_VCS + IX_ATM_MAX_NUM_OAM_RX_VCS) - -/** - * @def IX_ATM_IDLE_CELLS_CONNID - * @brief VC Id used to indicate idle cells in the returned schedule table. - */ -#define IX_ATM_IDLE_CELLS_CONNID 0 - - -/** - * @def IX_ATM_CELL_HEADER_VCI_GET - * @brief get the VCI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VCI_GET(cellHeader) \ - (((cellHeader) >> 4) & IX_OAM_VCI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_VPI_GET - * @brief get the VPI field from a cell header - */ -#define IX_ATM_CELL_HEADER_VPI_GET(cellHeader) \ - (((cellHeader) >> 20) & IX_OAM_VPI_BITS_MASK); - -/** - * @def IX_ATM_CELL_HEADER_PTI_GET - * @brief get the PTI field from a cell header - */ -#define IX_ATM_CELL_HEADER_PTI_GET(cellHeader) \ - ((cellHeader) >> 1) & IX_OAM_PTI_BITS_MASK; - -/** - * @typedef IxAtmCellHeader - * - * @brief ATM Cell Header, does not contain 4 byte HEC, added by NPE-A - */ -typedef unsigned int IxAtmCellHeader; - - -/** - * @enum IxAtmServiceCategory - * - * @brief Enumerated type representing available ATM service categories. - * For more informatoin on these categories, see "Traffic Management - * Specification" v4.1, published by the ATM Forum - - * http://www.atmforum.com - */ -typedef enum -{ - IX_ATM_CBR, /**< Constant Bit Rate */ - IX_ATM_RTVBR, /**< Real Time Variable Bit Rate */ - IX_ATM_VBR, /**< Variable Bit Rate */ - IX_ATM_UBR, /**< Unspecified Bit Rate */ - IX_ATM_ABR /**< Available Bit Rate (not supported) */ - -} IxAtmServiceCategory; - -/** - * - * @enum IxAtmRxQueueId - * - * @brief Rx Queue Type for RX traffic - * - * IxAtmRxQueueId defines the queues involved for receiving data. - * - * There are two queues to facilitate prioritisation handling - * and processing the 2 queues with different algorithms and - * constraints - * - * e.g. : one queue can carry voice (or time-critical traffic), the - * other queue can carry non-voice traffic - * - */ -typedef enum -{ - IX_ATM_RX_A = 0, /**< RX queue A */ - IX_ATM_RX_B, /**< RX queue B */ - IX_ATM_MAX_RX_STREAMS /**< Maximum number of RX streams */ -} IxAtmRxQueueId; - -/** - * @brief Structure describing an ATM traffic contract for a Virtual - * Connection (VC). - * - * Structure is used to specify the requested traffic contract for a - * VC to the IxAtmSch component using the @ref ixAtmSchVcModelSetup - * interface. - * - * These parameters are defined by the ATM forum working group - * (http://www.atmforum.com). - * - * @note Typical values for a voice channel 64 Kbit/s - * - atmService @a IX_ATM_RTVBR - * - pcr 400 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - scr = pcr - * - * @note Typical values for a data channel 800 Kbit/s - * - atmService @a IX_ATM_UBR - * - pcr 1962 (include IP overhead, and AAL5 trailer) - * - cdvt 5000000 (5 ms) - * - */ -typedef struct -{ - IxAtmServiceCategory atmService; /**< ATM service category */ - unsigned pcr; /**< Peak Cell Rate - cells per second */ - unsigned cdvt; /**< Cell Delay Variation Tolerance - in nanoseconds */ - unsigned scr; /**< Sustained Cell Rate - cells per second */ - unsigned mbs; /**< Max Burst Size - cells */ - unsigned mcr; /**< Minimum Cell Rate - cells per second */ - unsigned mfs; /**< Max Frame Size - cells */ -} IxAtmTrafficDescriptor; - -/** - * @typedef IxAtmConnId - * - * @brief ATM VC data connection identifier. - * - * This is is generated by IxAtmdAcc when a successful connection is - * made on a VC. The is the ID by which IxAtmdAcc knows an active - * VC and should be used in IxAtmdAcc API calls to reference a - * specific VC. - */ -typedef unsigned int IxAtmConnId; - -/** - * @typedef IxAtmSchedulerVcId - * - * @brief ATM VC scheduling connection identifier. - * - * This id is generated and used by ATM Tx controller, generally - * the traffic shaper (e.g. IxAtmSch). The IxAtmdAcc component - * will request one of these Ids whenever a data connection on - * a Tx VC is requested. This ID will be used in callbacks to - * the ATM Transmission Ctrl s/w (e.g. IxAtmm) to reference a - * particular VC. - */ -typedef int IxAtmSchedulerVcId; - -/** - * @typedef IxAtmNpeRxVcId - * - * @brief ATM Rx VC identifier used by the ATM Npe. - * - * This Id is generated by IxAtmdAcc when a successful data connection - * is made on a rx VC. - */ -typedef unsigned int IxAtmNpeRxVcId; - -/** - * @brief ATM Schedule Table entry - * - * This IxAtmScheduleTableEntry is used by an ATM scheduler to inform - * IxAtmdAcc about the data to transmit (in term of cells per VC) - * - * This structure defines - * @li the number of cells to be transmitted (numberOfCells) - * @li the VC connection to be used for transmission (connId). - * - * @note - When the connection Id value is IX_ATM_IDLE_CELLS_CONNID, the - * corresponding number of idle cells will be transmitted to the hardware. - * - */ -typedef struct -{ - IxAtmConnId connId; /**< connection Id - * - * Identifier of VC from which cells are to be transmitted. - * When this valus is IX_ATM_IDLE_CELLS_CONNID, this indicates - * that the system should transmit the specified number - * of idle cells. Unknown connIds result in the transmission - * idle cells. - */ - unsigned int numberOfCells; /**< number of cells to transmit - * - * The number of contiguous cells to schedule from this VC - * at this point. The valid range is from 1 to - * @a IX_ATM_SCHEDULETABLE_MAXCELLS_PER_ENTRY. This - * number can swap over mbufs and pdus. OverSchduling results - * in the transmission of idle cells. - */ -} IxAtmScheduleTableEntry; - -/** - * @brief This structure defines a schedule table which gives details - * on which data (from which VCs) should be transmitted for a - * forthcoming period of time for a particular port and the - * order in which that data should be transmitted. - * - * The schedule table consists of a series of entries each of which - * will schedule one or more cells from a particular registered VC. - * The total number of cells scheduled and the total number of - * entries in the table are also indicated. - * - */ -typedef struct -{ - unsigned tableSize; /**< Number of entries - * - * Indicates the total number of - * entries in the table. - */ - unsigned totalCellSlots; /**< Number of cells - * - * Indicates the total number of ATM - * cells which are scheduled by all the - * entries in the table. - */ - IxAtmScheduleTableEntry *table; /**< Pointer to schedule entries - * - * Pointer to an array - * containing tableSize entries - */ -} IxAtmScheduleTable; - -#endif /* IXATMTYPES_H */ - -/** - * @} defgroup IxAtmTypes - */ - - diff --git a/drivers/net/npe/include/IxAtmdAcc.h b/drivers/net/npe/include/IxAtmdAcc.h deleted file mode 100644 index b37c6150297..00000000000 --- a/drivers/net/npe/include/IxAtmdAcc.h +++ /dev/null @@ -1,1169 +0,0 @@ -/** - * @file IxAtmdAcc.h - * - * @date 07-Nov-2001 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * data functions of the component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccAPI IXP400 ATM Driver Access (IxAtmdAcc) API - * - * @brief The public API for the IXP400 Atm Driver Data component - * - * IxAtmdAcc is the low level interface by which AAL0/AAL5 and - * OAM data gets transmitted to,and received from the Utopia bus. - * - * For AAL0/AAL5 services transmit and receive connections may - * be established independantly for unique combinations of - * port,VPI,and VCI. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * OAM cells cannot be received over the AAL0 service but instead - * are received over a dedicated OAM service. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values defined below. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. Note that AtmdAcc does not validate the cell headers - * in a submitted OAM PDU. - * - * - * - * This part is related to the User datapath processing - * - * @{ - */ - -#ifndef IXATMDACC_H -#define IXATMDACC_H - -#include "IxAtmTypes.h" - -/* ------------------------------------------------------ - AtmdAcc Data Types definition - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_WARNING - * - * @brief Warning return code - * - * This constant is used to tell IxAtmDAcc user about a special case. - * - */ -#define IX_ATMDACC_WARNING 2 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_BUSY - * - * @brief Busy return code - * - * This constant is used to tell IxAtmDAcc user that the request - * is correct, but cannot be processed because the IxAtmAcc resources - * are already used. The user has to retry its request later - * - */ -#define IX_ATMDACC_BUSY 3 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_RESOURCES_STILL_ALLOCATED - * - * @brief Disconnect return code - * - * This constant is used to tell IxAtmDAcc user that the disconnect - * functions are not complete because the resources used by the driver - * are not yet released. The user has to retry the disconnect call - * later. - * - */ -#define IX_ATMDACC_RESOURCES_STILL_ALLOCATED 4 - -/** - * - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_DEFAULT_REPLENISH_COUNT - * - * @brief Default resources usage for RxVcFree replenish mechanism - * - * This constant is used to tell IxAtmDAcc to allocate and use - * the minimum of resources for rx free replenish. - * - * @sa ixAtmdAccRxVcConnect - */ -#define IX_ATMDACC_DEFAULT_REPLENISH_COUNT 0 - - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VPI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - * - * - */ -#define IX_ATMDACC_OAM_TX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_TX_VCI - * - * @brief The reserved value used for the dedicated OAM - * Tx connection. This "well known" value is used by atmdAcc and - * its clients to dsicriminate the OAM channel, and should be chosen so - * that it does not coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_TX_VCI 0 - - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_PORT - * - * @brief The reserved dummy PORT used for all dedicated OAM - * Rx connections. Note that this is not a real port but must - * have a value that lies within the valid range of port values. - */ -#define IX_ATMDACC_OAM_RX_PORT IX_UTOPIA_PORT_0 - - /** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VPI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VPI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VPI will fail. - */ -#define IX_ATMDACC_OAM_RX_VPI 0 - -/** - * @ingroup IxAtmdAccAPI - * - * @def IX_ATMDACC_OAM_RX_VCI - * - * @brief The reserved value value used for the dedicated OAM - * Rx connection. This value should be chosen so that it does not - * coencide with the VCI value used in an AAL0/AAL5 connection. - * Any attempt to connect a service type other than OAM on this VCI will fail. - */ -#define IX_ATMDACC_OAM_RX_VCI 0 - - -/** - * @enum IxAtmdAccPduStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc Pdu status : - * - * IxAtmdAccPduStatus is used during a RX operation to indicate - * the status of the received PDU - * - */ - -typedef enum -{ - IX_ATMDACC_AAL0_VALID = 0, /**< aal0 pdu */ - IX_ATMDACC_OAM_VALID, /**< OAM pdu */ - IX_ATMDACC_AAL2_VALID, /**< aal2 pdu @b reserved for future use */ - IX_ATMDACC_AAL5_VALID, /**< aal5 pdu complete and trailer is valid */ - IX_ATMDACC_AAL5_PARTIAL, /**< aal5 pdu not complete, trailer is missing */ - IX_ATMDACC_AAL5_CRC_ERROR, /**< aal5 pdu not complete, crc error/length error */ - IX_ATMDACC_MBUF_RETURN /**< empty buffer returned to the user */ -} IxAtmdAccPduStatus; - - -/** - * - * @enum IxAtmdAccAalType - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc AAL Service Type : - * - * IxAtmdAccAalType defines the type of traffic to run on this VC - * - */ -typedef enum -{ - IX_ATMDACC_AAL5, /**< ITU-T AAL5 */ - IX_ATMDACC_AAL2, /**< ITU-T AAL2 @b reserved for future use */ - IX_ATMDACC_AAL0_48, /**< AAL0 48 byte payloads (cell header is added by NPE)*/ - IX_ATMDACC_AAL0_52, /**< AAL0 52 byte cell data (HEC is added by NPE) */ - IX_ATMDACC_OAM, /**< OAM cell transport service (HEC is added by NPE)*/ - IX_ATMDACC_MAX_SERVICE_TYPE /**< not a service, used for parameter validation */ -} IxAtmdAccAalType; - -/** - * - * @enum IxAtmdAccClpStatus - * - * @ingroup IxAtmdAccAPI - * - * @brief IxAtmdAcc CLP indication - * - * IxAtmdAccClpStatus defines the CLP status of the current PDU - * - */ -typedef enum -{ - IX_ATMDACC_CLP_NOT_SET = 0, /**< CLP indication is not set */ - IX_ATMDACC_CLP_SET = 1 /**< CLP indication is set */ -} IxAtmdAccClpStatus; - -/** - * @typedef IxAtmdAccUserId - * - * @ingroup IxAtmdAccAPI - * - * @brief User-supplied Id - * - * IxAtmdAccUserId is passed through callbacks and allows the - * IxAtmdAcc user to identify the source of a call back. The range of - * this user-owned Id is [0...2^32-1)]. - * - * The user provides this own Ids on a per-channel basis as a parameter - * in a call to @a ixAtmdAccRxVcConnect() or @a ixAtmdAccRxVcConnect() - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccTxVcConnect - * - */ -typedef unsigned int IxAtmdAccUserId; - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Rx callback prototype - * - * IxAtmdAccRxVcRxCallback is the prototype of the Rx callback user - * function called once per PDU to pass a receive Pdu to a user on a - * partilcular connection. The callback is likely to push the mbufs - * to a protocol layer, and recycle the mbufs for a further use. - * - * @note -This function is called ONLY in the context of - * the @a ixAtmdAccRxDispatch() function - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * - * @param port @ref IxAtmLogicalPort [in] - the port on which this PDU was received - * a logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * @param status @ref IxAtmdAccPduStatus [in] - an indication about the PDU validity. - * In the case of AAL0 the only possibile value is - * AAL0_VALID, in this case the client may optionally determine - * that an rx timeout occured by checking if the mbuf is - * compleletly or only partially filled, the later case - * indicating a timeout. - * In the case of OAM the only possible value is OAM valid. - * The status is set to @a IX_ATMDACC_MBUF_RETURN when - * the mbuf is released during a disconnect process. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. - * For AAL5/AAL0_48 this information - * is set if the clp bit of any rx cell is set - * For AAL0-52/OAM the client may inspect the CLP in individual - * cell headers in the PDU, and this parameter is set to 0. - * @param *mbufPtr @ref IX_OSAL_MBUF [in] - depending on the servive type a pointer to - * an mbuf (AAL5/AAL0/OAM) or mbuf chain (AAL5 only), - * that comprises the complete PDU data. - * - * This parameter is guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccRxVcRxCallback) (IxAtmLogicalPort port, - IxAtmdAccUserId userId, - IxAtmdAccPduStatus status, - IxAtmdAccClpStatus clp, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Callback prototype for free buffer level is low. - * - * IxAtmdAccRxVcFreeLowCallback is the prototype of the user function - * which get called on a per-VC basis, when more mbufs are needed to - * continue the ATM data reception. This function is likely to supply - * more available mbufs by one or many calls to the replenish function - * @a ixAtmdAccRxVcFreeReplenish() - * - * This function is called when the number of available buffers for - * reception is going under the threshold level as defined - * in @a ixAtmdAccRxVcFreeLowCallbackRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param userId @ref IxAtmdAccUserId [in] - user Id provided in the call - * to @a ixAtmdAccRxVcConnect() - * - * @return None - * - */ -typedef void (*IxAtmdAccRxVcFreeLowCallback) (IxAtmdAccUserId userId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @brief Buffer callback prototype. - * - * This function is called to relinguish ownership of a transmitted - * buffer chain to the user. - * - * @note -In the case of a chained mbuf the AmtdAcc component can - * chain many user buffers together and pass ownership to the user in - * one function call. - * - * @param userId @ref IxAtmdAccUserId [in] - user If provided at registration of this - * callback. - * @param mbufPtr @ref IX_OSAL_MBUF [in] - a pointer to mbufs or chain of mbufs and is - * guaranteed not to be a null pointer. - * - */ -typedef void (*IxAtmdAccTxVcBufferReturnCallback) (IxAtmdAccUserId userId, - IX_OSAL_MBUF * mbufPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Initialisation - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccInit (void) - * - * @brief Initialise the IxAtmdAcc Component - * - * This function initialise the IxAtmdAcc component. This function shall - * be called before any other function of the API. Its role is to - * initialise all internal resources of the IxAtmdAcc component. - * - * The ixQmgr component needs to be initialized prior the use of - * @a ixAtmdAccInit() - * - * @param none - * - * Failing to initilialize the IxAtmdAcc API before any use of it will - * result in a failed status. - * If the specified component is not present, a success status will still be - * returned, however, a warning indicating the NPE to download to is not - * present will be issued. - * - * @return @li IX_SUCCESS initialisation is complete (in case of component not - * being present, a warning is clearly indicated) - * @return @li IX_FAIL unable to process this request either - * because this IxAtmdAcc is already initialised - * or some unspecified error has occrred. - */ -PUBLIC IX_STATUS ixAtmdAccInit (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccShow (void) - * - * @brief Show IxAtmdAcc configuration on a per port basis - * - * @param none - * - * @return none - * - * @note - Display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsShow (void) - * - * @brief Show all IxAtmdAcc stats - * - * @param none - * - * @return none - * - * @note - Stats display use printf() and are redirected to stdout - */ -PUBLIC void -ixAtmdAccStatsShow (void); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccStatsReset (void) - * - * @brief Reset all IxAtmdAcc stats - * - * @param none - * - * @return none - * - */ -PUBLIC void -ixAtmdAccStatsReset (void); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ) - * - * @brief Connect to a Aal Pdu receive service for a particular - * port/vpi/vci, and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu receive service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VCC. - * - * The function will setup VC receive service on the specified rx queue. - * - * This function is blocking and makes use internal locks, and hence - * should not be called from an interrupt context. - * - * On return from @a ixAtmdAccRxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * Calling this function for the same combination of Vpi, Vci and more - * than once without calling @a ixAtmdAccRxVcTryDisconnect() will result in a - * failure status. - * - * If this function returns success the user should supply receive - * buffers by calling @a ixAtmdAccRxVcFreeReplenish() and then call - * @a ixAtmdAccRxVcEnable() to begin receiving pdus. - * - * There is a choice of two receive Qs on which the VC pdus could be - * receive. The user must associate the VC with one of these. Essentially - * having two qs allows more flexible system configuration such as have - * high prioriy traffic on one q (e.g. voice) and low priority traffic on - * the other (e.g. data). The high priority Q could be serviced in - * preference to the low priority Q. One queue may be configured to be - * serviced as soon as there is traffic, the other queue may be configured - * to be serviced by a polling mechanism running at idle time. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Received AAL0 PDUs will be be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service and includes an ATM cell header - * (excluding HEC) at the start of each cell. - * - * A single "OAM Rx channel" for all ports may be enabled by - * establishing a dedicated OAM Rx connection. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function prior to enable the port will fail. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcTryDisconnect - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service: AAL5, AAL0_48, AAL0_52, or OAM - * @param rxQueueId @ref IxAtmRxQueueId [in] - this identifieds which of two Qs the VC - * should use.when icoming traffic is processed - * @param userCallbackId @ref IxAtmdAccUserId [in] - user Id used later as a parameter to - * the supplied rxCallback. - * @param rxCallback [in] @ref IxAtmdAccRxVxRxCallback - function called when mbufs are received. - * This parameter cannot be a null pointer. - * @param bufferFreeCallback [in] - function to be called to return - * ownership of buffers to IxAtmdAcc user. - * @param minimumReplenishCount unsigned int [in] - For AAL5/AAL0 the number of free mbufs - * to be used with this channel. Use a high number when the expected traffic - * rate on this channel is high, or when the user's mbufs are small, or when - * the RxVcFreeLow Notification has to be invoked less often. When this - * value is IX_ATMDACC_DEFAULT_REPLENISH_COUNT, the minimum of - * resources will be used. Depending on traffic rate, pdu - * size and mbuf size, rxfree queue size, polling/interrupt rate, this value may - * require to be replaced by a different value in the range 1-128 - * For OAM the rxFree queue size is fixed by atmdAcc and this parameter is ignored. - * @param connIdPtr @ref IxAtmConnId [out] - pointer to a connection Id - * This parameter cannot be a null pointer. - * @param npeVcIdPtr @ref IxAtmNpeRxVcId [out] - pointer to an npe Vc Id - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to IxAtmdAccRxVcConnect - * @return @li IX_ATMDACC_BUSY cannot process this request : - * no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmRxQueueId rxQueueId, - IxAtmdAccUserId userCallbackId, - IxAtmdAccRxVcRxCallback rxCallback, - unsigned int minimumReplenishCount, - IxAtmConnId * connIdPtr, - IxAtmNpeRxVcId * npeVcIdPtr ); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr) - * - * @brief Provide free mbufs for data reception on a connection. - * - * This function provides mbufs for data reception by the hardware. This - * function needs to be called by the user on a regular basis to ensure - * no packet loss. Providing free buffers is a connection-based feature; - * each connection can have different requirements in terms of buffer size - * number of buffers, recycling rate. This function could be invoked from - * within the context of a @a IxAtmdAccRxVcFreeLowCallback() callback - * for a particular VC - * - * Mbufs provided through this function call can be chained. They will be - * unchained internally. A call to this function with chained mbufs or - * multiple calls with unchained mbufs are equivalent, but calls with - * unchained mbufs are more efficients. - * - * Mbufs provided to this interface need to be able to hold at least one - * full cell payload (48/52 bytes, depending on service type). - * Chained buffers with a size less than the size supported by the hardware - * will be returned through the rx callback provided during the connect step. - * - * Failing to invoke this function prior to enabling the RX traffic - * can result in packet loss. - * - * This function is not reentrant for the same connId. - * - * This function does not use system resources and can be - * invoked from an interrupt context. - * - * @note - Over replenish is detected, and extra mbufs are returned through - * the rx callback provided during the connect step. - * - * @note - Mbuf provided to the replenish function should have a length greater or - * equal to 48/52 bytes according to service type. - * - * @note - The memory cache of mMbuf payload should be invalidated prior to Mbuf - * submission. Flushing the Mbuf headers is handled by IxAtmdAcc. - * - * @note - When a chained mbuf is provided, this function process the mbufs - * up to the hardware limit and invokes the user-supplied callback - * to release extra buffers. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as returned from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a mbuf structure to be used for data - * reception. The mbuf pointed to by this parameter can be chained - * to an other mbuf. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcFreeReplenish() - * and the mbuf is now ready to use for incoming traffic. - * @return @li IX_ATMDACC_BUSY cannot process this request because - * the max number of outstanding free buffers has been reached - * or the internal resources have exhausted for this VC. - * The user is responsible for retrying this request later. - * @return @li IX_FAIL cannot process this request because of parameter - * errors or some unspecified internal error has occurred. - * - * @note - It is not always guaranteed the replenish step to be as fast as the - * hardware is consuming Rx Free mbufs. There is nothing in IxAtmdAcc to - * guarantee that replenish reaches the rxFree threshold level. If the - * threshold level is not reached, the next rxFree low notification for - * this channel will not be triggered. - * The preferred ways to replenish can be as follows (depending on - * applications and implementations) : - * @li Replenish in a rxFree low notification until the function - * ixAtmdAccRxVcFreeReplenish() returns IX_ATMDACC_BUSY - * @li Query the queue level using @sa ixAtmdAccRxVcFreeEntriesQuery, then - * , replenish using @a ixAtmdAccRxVcFreeReplenish(), then query the queue - * level again, and replenish if the threshold is still not reached. - * @li Trigger replenish from an other event source and use rxFree starvation - * to throttle the Rx traffic. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeReplenish (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback) - * - * @brief Configure the RX Free threshold value and register a callback - * to handle threshold notifications. - * - * The function ixAtmdAccRxVcFreeLowCallbackRegister sets the threshold value for - * a particular RX VC. When the number of buffers reaches this threshold - * the callback is invoked. - * - * This function should be called once per VC before RX traffic is - * enabled.This function will fail if the curent level of the free buffers - * is equal or less than the threshold value. - * - * @sa ixAtmdAccRxVcFreeLowCallbackRegister - * @sa IxAtmdAccRxVcFreeLowCallback - * @sa ixAtmdAccRxVcFreeReplenish - * @sa ixAtmdAccRxVcFreeEntriesQuery - * @sa ixAtmdAccRxVcConnect - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufs unsigned int [in] - threshold number of buffers. This number - * has to be a power of 2, one of the values 0,1,2,4,8,16,32.... - * The maximum value cannot be more than half of the rxFree queue - * size (which can be retrieved using @a ixAtmdAccRxVcFreeEntriesQuery() - * before any use of the @a ixAtmdAccRxVcFreeReplenish() function) - * @param callback @ref IxAtmdAccRxVcFreeLowCallback [in] - function telling the user that the number of - * free buffers has reduced to the threshold value. - * - * @return @li IX_SUCCESS Threshold set successfully. - * @return @li IX_FAIL parameter error or the current number of free buffers - * is less than or equal to the threshold supplied or some - * unspecified error has occrred. - * - * @note - the callback will be called when the threshold level will drop from - * exactly (numberOfMbufs + 1) to (numberOfMbufs). - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeLowCallbackRegister (IxAtmConnId connId, - unsigned int numberOfMbufs, - IxAtmdAccRxVcFreeLowCallback callback); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr) - * - * @brief Get the number of rx mbufs the system can accept to replenish the - * the rx reception mechanism on a particular channel - * - * The ixAtmdAccRxVcFreeEntriesQuery function is used to retrieve the current - * number of available mbuf entries for reception, on a per-VC basis. This - * function can be used to know the number of mbufs which can be provided - * using @a ixAtmdAccRxVcFreeReplenish(). - * - * This function can be used from a timer context, or can be associated - * with a threshold event, or can be used inside an active polling - * mechanism which is under user control. - * - * This function is reentrant and does not use system resources and can - * be invoked from an interrupt context. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * @param numberOfMbufsPtr unsigned int [out] - Pointer to the number of available entries. - * . This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the current number of mbufs not yet used for incoming traffic - * @return @li IX_FAIL invalid parameter - * - * @sa ixAtmdAccRxVcFreeReplenish - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcFreeEntriesQuery (IxAtmConnId connId, - unsigned int *numberOfMbufsPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcEnable (IxAtmConnId connId) - * - * @brief Start the RX service on a VC. - * - * This functions kicks-off the traffic reception for a particular VC. - * Once invoked, incoming PDUs will be made available by the hardware - * and are eventually directed to the @a IxAtmdAccRxVcRxCallback() callback - * registered for the connection. - * - * If the traffic is already running, this function returns IX_SUCCESS. - * This function can be invoked many times. - * - * IxAtmdAccRxVcFreeLowCallback event will occur only after - * @a ixAtmdAccRxVcEnable() function is invoked. - * - * Before using this function, the @a ixAtmdAccRxVcFreeReplenish() function - * has to be used to replenish the RX Free queue. If not, incoming traffic - * may be discarded.and in the case of interrupt driven reception the - * @a IxAtmdAccRxVcFreeLowCallback() callback may be invoked as a side effect - * during a replenish action. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * For an VC connection this function can be called after a call to - * @a ixAtmdAccRxVcDisable() and should not be called after - * @a ixAtmdAccRxVcTryDisconnect() - * - * @sa ixAtmdAccRxVcDisable - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcFreeReplenish - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call - * to @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcEnable - * @return @li IX_ATMDACC_WARNING the channel is already enabled - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcEnable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcDisable (IxAtmConnId connId) - * - * @brief Stop the RX service on a VC. - * - * This functions stops the traffic reception for a particular VC connection. - * - * Once invoked, incoming Pdus are discarded by the hardware. Any Pdus - * pending will be freed to the user - * - * Hence once this function returns no more receive callbacks will be - * called for that VC. However, buffer free callbacks will be invoked - * until such time as all buffers supplied by the user have been freed - * back to the user - * - * Calling this function doe not invalidate the connId. - * @a ixAtmdAccRxVcEnable() can be invoked to enable Pdu reception again. - * - * If the traffic is already stopped, this function returns IX_SUCCESS. - * - * This function is not reentrant and should not be used inside an - * interrupt context. - * - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxVcEnable - * @sa ixAtmdAccRxVcDisable - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to @a - * IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccRxVcDisable(). - * @return @li IX_ATMDACC_WARNING the channel is already disabled - * @return @li IX_FAIL invalid parameters or some unspecified internal error occured - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcDisable (IxAtmConnId connId); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect a VC from the RX service. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay and - * call again this function many times until a success status is returned. - * - * This function needs internal locks and should not be called from an - * interrupt context - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a IxAtmdAccRxVcConnect() - * - * @return @li IX_SUCCESS successful call to ixAtmdAccRxVcDisable - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. - * @return @li IX_FAIL cannot process this request because of a parameter - * error - * - */ -PUBLIC IX_STATUS ixAtmdAccRxVcTryDisconnect (IxAtmConnId connId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr) - * - * @brief Connect to a Aal Pdu transmit service for a particular - * port/vpi/vci and service type. - * - * This function allows a user to connect to an Aal5/Aal0/OAM Pdu transmit service - * for a particular port/vpi/vci. It registers the callback and allocates - * internal resources and a Connection Id to be used in further API calls - * related to this VC. - * - * The function will setup VC transmit service on the specified on the - * specified port. A connId is the reference by which IxAtmdAcc refers to a - * connected VC. This identifier is the result of a succesful call - * to a connect function. This identifier is invalid after a - * sucessful call to a disconnect function. - * - * This function needs internal locks, and hence should not be called - * from an interrupt context. - * - * On return from @a ixAtmdAccTxVcConnect() with a failure status, the - * connection Id parameter is unspecified. Its value cannot be used. - * - * Calling this function for the same combination of port, Vpi, Vci and - * more than once without calling @a ixAtmdAccTxVcTryDisconnect() will result - * in a failure status. - * - * Two AAL0 services supporting 48 or 52 byte cell data are provided. - * Submitted AAL0 PDUs must be a multiple of the cell data size (48/52). - * AAL0_52 is a raw cell service the client must format - * the PDU with an ATM cell header (excluding HEC) at the start of - * each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * For the OAM service an "OAM Tx channel" may be enabled for a port - * by establishing a single dedicated OAM Tx connection on that port. - * - * The OAM service allows buffers containing 52 byte OAM F4/F5 cells - * to be transmitted and received over the dedicated OAM channels. - * HEC is appended/removed, and CRC-10 performed by the NPE. The OAM - * service offered by AtmdAcc is a raw cell transport service. - * It is assumed that ITU I.610 procedures that make use of this - * service are implemented above AtmdAcc. - * - * Note that the dedicated OAM connections are established on - * reserved VPI,VCI, and (in the case of Rx) port values. - * These values are used purely to descriminate the dedicated OAM channels - * and do not identify a particular OAM F4/F5 flow. F4/F5 flows may be - * realised for particluar VPI/VCIs by manipulating the VPI,VCI - * fields of the ATM cell headers of cells in the buffers passed - * to AtmdAcc. - * - * Calling this function before enabling the port will fail. - * - * @sa ixAtmdAccTxVcTryDisconnect - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - VC identification : logical PHY port - * [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vpi unsigned int [in] - VC identification : ATM Vpi [0..255] or IX_ATMDACC_OAM_VPI - * @param vci unsigned int [in] - VC identification : ATM Vci [0..65535] or IX_ATMDACC_OAM_VCI - * @param aalServiceType @ref IxAtmdAccAalType [in] - type of service AAL5, AAL0_48, AAL0_52, or OAM - * @param userId @ref IxAtmdAccUserId [in] - user id to be used later during callbacks related - * to this channel - * @param bufferFreeCallback @ref IxAtmdAccTxVcBufferReturnCallback [in] - function called when mbufs - * transmission is complete. This parameter cannot be a null - * pointer. - * @param connIdPtr @ref IxAtmConnId [out] - Pointer to a connection Id. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful call to @a IxAtmdAccRxVcConnect(). - * @return @li IX_ATMDACC_BUSY cannot process this request - * because no VC is available - * @return @li IX_FAIL - * parameter error, - * VC already in use, - * attempt to connect AAL service on reserved OAM VPI/VCI, - * attempt to connect OAM service on VPI/VCI other than the reserved OAM VPI/VCI, - * port is not initialised, - * or some other error occurs during processing. - * - * @note - Unscheduled mode is not supported in ixp425 1.0. Therefore, the - * function @a ixAtmdAccPortTxScheduledModeEnable() need to be called - * for this port before any establishing a Tx Connection - */ -PUBLIC IX_STATUS ixAtmdAccTxVcConnect (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmdAccAalType aalServiceType, - IxAtmdAccUserId userId, - IxAtmdAccTxVcBufferReturnCallback bufferFreeCallback, - IxAtmConnId * connIdPtr); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells) - * - * @brief Submit a Pdu for transmission on connection. - * - * A data user calls this function to submit an mbufs containing a Pdu - * to be transmitted. The buffer supplied can be chained and the Pdu it - * contains must be complete. - * - * The transmission behavior of this call depends on the operational mode - * of the port on which the connection is made. - * - * In unscheduled mode the mbuf will be submitted to the hardware - * immediately if sufficent resource is available. Otherwise the function - * will return failure. - * - * In scheduled mode the buffer is queued internally in IxAtmdAcc. The cell - * demand is made known to the traffic shaping entity. Cells from the - * buffers are MUXed onto the port some time later as dictated by the - * traffic shaping entity. The traffic shaping entity does this by sending - * transmit schedules to IxAtmdAcc via @a ixAtmdAccPortTxProcess() function call. - * - * Note that the dedicated OAM channel is scheduled just like any - * other channel. This means that any OAM traffic relating to an - * active AAL0/AAL5 connection will be scheduled independantly of the - * AAL0/AAL5 traffic for that connection. - * - * When transmission is complete, the TX Done mechanism will give the - * owmnership of these buffers back to the customer. The tx done mechanism - * must be in operation before transmission is attempted. - * - * For AAL0/OAM submitted AAL0 PDUs must be a multiple of the cell data - * size (48/52). AAL0_52 and OAM are raw cell services, and the client - * must format the PDU with an ATM cell header (excluding HEC) at the - * start of each cell, note that AtmdAcc does not validate the cell headers in - * a submitted PDU. - * - * - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneDispatch - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * @param mbufPtr @ref IX_OSAL_MBUF [in] - pointer to a chained structure of mbufs to transmit. - * This parameter cannot be a null pointer. - * @param clp @ref IxAtmdAccClpStatus [in] - clp indication for this PDU. All cells of this pdu - * will be sent with the clp bit set - * @param numberOfCells unsigned int [in] - number of cells in the PDU. - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcPduSubmit() - * The pdu pointed by the mbufPtr parameter will be - * transmitted - * @return @li IX_ATMDACC_BUSY unable to process this request because - * internal resources are all used. The caller is responsible - * for retrying this request later. - * @return @li IX_FAIL unable to process this request because of error - * in the parameters (wrong connId supplied, - * or wrong mbuf pointer supplied), the total length of all buffers - * in the chain should be a multiple of the cell size - * ( 48/52 depending on the service type ), - * or unspecified error during processing - * - * @note - This function in not re-entrant for the same VC (e.g. : two - * thread cannot send PDUs for the same VC). But two threads can - * safely call this function with a different connection Id - * - * @note - In unscheduled mode, this function is not re-entrant on a per - * port basis. The size of pdus is limited to 8Kb. - * - * @note - 0-length mbufs should be removed from the chain before submission. - * The total length of the pdu (sdu + padding +trailer) has to be - * updated in the header of the first mbuf of a chain of mbufs. - * - * @note - Aal5 trailer information (UUI, CPI, SDU length) has to be supplied - * before submission. - * - * @note - The payload memory cache should be flushed, if needed, prior to - * transmission. Mbuf headers are flushed by IxAtmdAcc - * - * @note - This function does not use system resources and can be used - * inside an interrupt context - */ -PUBLIC IX_STATUS ixAtmdAccTxVcPduSubmit (IxAtmConnId connId, - IX_OSAL_MBUF * mbufPtr, - IxAtmdAccClpStatus clp, - unsigned int numberOfCells); - -/** - * - * @ingroup IxAtmdAccAPI - * - * @fn ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId) - * - * @brief Disconnect from a Aal Pdu transmit service for a particular - * port/vpi/vci. - * - * This function deregisters the VC and guarantees that all resources - * associated with this VC are free. After its execution, the connection - * Id is not available. - * - * This function will fail until such time as all resources allocated to - * the VC connection have been freed. The user is responsible to delay - * and call again this function many times until a success status is - * returned. - * - * After its execution, the connection Id is not available. - * - * @param connId @ref IxAtmConnId [in] - connection Id as resulted from a succesfull call to - * @a ixAtmdAccTxVcConnect() - * - * @return @li IX_SUCCESS successful call to @a ixAtmdAccTxVcTryDisconnect() - * @return @li IX_ATMDACC_RESOURCES_STILL_ALLOCATED not all resources - * associated with the connection have been freed. This condition will - * disappear after Tx and TxDone is complete for this channel. - * @return @li IX_FAIL unable to process this request because of errors - * in the parameters (wrong connId supplied) - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - If the @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED error does not - * clear after a while, this may be linked to a previous problem - * of cell overscheduling. Diabling the port and retry a disconnect - * will free the resources associated with this channel. - * - * @sa ixAtmdAccPortTxProcess - * - */ -PUBLIC IX_STATUS ixAtmdAccTxVcTryDisconnect (IxAtmConnId connId); - -#endif /* IXATMDACC_H */ - -/** - * @} defgroup IxAtmdAccAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmdAccCtrl.h b/drivers/net/npe/include/IxAtmdAccCtrl.h deleted file mode 100644 index ecbb0059f54..00000000000 --- a/drivers/net/npe/include/IxAtmdAccCtrl.h +++ /dev/null @@ -1,1933 +0,0 @@ -/** - * @file IxAtmdAccCtrl.h - * - * @date 20-Mar-2002 - * - * @brief IxAtmdAcc Public API - * - * This file contains the public API of IxAtmdAcc, related to the - * control functions of the component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ - -/** - * - * @defgroup IxAtmdAccCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get transmitted - * to,and received from the Utopia bus - * - * This part is related to the Control configuration - * - * @{ - */ - -#ifndef IXATMDACCCTRL_H -#define IXATMDACCCTRL_H - -#include "IxAtmdAcc.h" - -/* ------------------------------------------------------ - AtmdAccCtrl Data Types definition - ------------------------------------------------------ */ - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_PORT_DISABLE_IN_PROGRESS -* -* @brief Port enable return code -* -* This constant is used to tell IxAtmDAcc user that the port disable -* functions are not complete. The user can call ixAtmdAccPortDisableComplete() -* to find out when the disable has finished. The port enable can then proceed. -* -*/ -#define IX_ATMDACC_PORT_DISABLE_IN_PROGRESS 5 - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @def IX_ATMDACC_ALLPDUS -* -* @brief All PDUs -* -* This constant is used to tell IxAtmDAcc to process all PDUs from -* the RX queue or the TX Done -* -* @sa IxAtmdAccRxDispatcher -* @sa IxAtmdAccTxDoneDispatcher -* -*/ -#define IX_ATMDACC_ALLPDUS 0xffffffff - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for notification of available PDUs for - * an Rx Q. - * - * This a protoype for a function which is called when there is at - * least one Pdu available for processing on a particular Rx Q. - * - * This function should call @a ixAtmdAccRxDispatch() with - * the aprropriate number of parameters to read and process the Rx Q. - * - * @sa ixAtmdAccRxDispatch - * @sa ixAtmdAccRxVcConnect - * @sa ixAtmdAccRxDispatcherRegister - * - * @param rxQueueId @ref IxAtmRxQueueId [in] indicates which RX queue to has Pdus to process. - * @param numberOfPdusToProcess unsigned int [in] indicates the minimum number of - * PDUs available to process all PDUs from the queue. - * @param reservedPtr unsigned int* [out] pointer to a int location which can - * be written to, but does not retain written values. This is - * provided to make this prototype compatible - * with @a ixAtmdAccRxDispatch() - * - * @return @li int - ignored. - * - */ -typedef IX_STATUS (*IxAtmdAccRxDispatcher) (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @brief Callback prototype for transmitted mbuf when threshold level is - * crossed. - * - * IxAtmdAccTxDoneDispatcher is the prototype of the user function - * which get called when pdus are completely transmitted. This function - * is likely to call the @a ixAtmdAccTxDoneDispatch() function. - * - * This function is called when the number of available pdus for - * reception is crossing the threshold level as defined - * in @a ixAtmdAccTxDoneDispatcherRegister() - * - * This function is called inside an Qmgr dispatch context. No system - * resource or interrupt-unsafe feature should be used inside this - * callback. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set before any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers with @a ixAtmdAccTxDoneDispatch() - * and @a ixAtmdAccTxDoneLevelQuery() functions. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - The current number of pdus currently - * available for recycling - * @param *reservedPtr unsigned int [out] - pointer to a int location which can be - * written to but does not retain written values. This is provided - * to make this prototype compatible - * with @a ixAtmdAccTxDoneDispatch() - * - * @return @li IX_SUCCESS This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. This is provided to make - * this prototype compatible with @a ixAtmdAccTxDoneDispatch() - * - */ -typedef IX_STATUS (*IxAtmdAccTxDoneDispatcher) (unsigned int numberOfPdusToProcess, - unsigned int *reservedPtr); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Notification that the threshold number of scheduled cells -* remains in a port's transmit Q. -* -* The is the prototype for of the user notification function which -* gets called on a per-port basis, when the number of remaining -* scheduled cells to be transmitted decreases to the threshold level. -* The number of cells passed as a parameter can be used for scheduling -* purposes as the maximum number of cells that can be passed in a -* schedule table to the @a ixAtmdAccPortTxProcess() function. -* -* @sa ixAtmdAccPortTxCallbackRegister -* @sa ixAtmdAccPortTxProcess -* @sa ixAtmdAccPortTxFreeEntriesQuery -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* @param numberOfAvailableCells unsigned int [in] - number of available -* cell entries.for the port -* -* @note - This functions shall not use system resources when used -* inside an interrupt context. -* -*/ -typedef void (*IxAtmdAccPortTxLowCallback) (IxAtmLogicalPort port, - unsigned int numberOfAvailableCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief Prototype to submit cells for transmission -* -* IxAtmdAccTxVcDemandUpdateCallback is the prototype of the callback -* function used by AtmD to notify an ATM Scheduler that the user of -* a VC has submitted cells for transmission. -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be updated -* is established -* @param vcId int [in] - Identifies the VC to be updated. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* @param numberOfCells unsigned int [in] - Indicates how many ATM cells should be added -* to the queue for this VC. -* -* @return @li IX_SUCCESS the function is registering the cell demand for -* this VC. -* @return @li IX_FAIL the function cannot register cell for this VC : the -* scheduler maybe overloaded or misconfigured -* -*/ -typedef IX_STATUS (*IxAtmdAccTxVcDemandUpdateCallback) (IxAtmLogicalPort port, - int vcId, - unsigned int numberOfCells); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to remove all currently queued cells from a -* registered VC -* -* IxAtmdAccTxVcDemandClearCallback is the prototype of the function -* to remove all currently queued cells from a registered VC. The -* pending cell count for the specified VC is reset to zero. After the -* use of this callback, the scheduler shall not schedule more cells -* for this VC. -* -* This callback function is called during a VC disconnection -* @a ixAtmdAccTxVcTryDisconnect() -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* @sa ixAtmdAccTxVcTryDisconnect -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM port on which the VC to be cleared -* is established -* @param vcId int [in] - Identifies the VC to be cleared. This is the value -* returned by the @a IxAtmdAccTxSchVcIdGetCallback() call . -* -* @return none -* -*/ -typedef void (*IxAtmdAccTxVcDemandClearCallback) (IxAtmLogicalPort port, - int vcId); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @brief prototype to get a scheduler vc id -* -* IxAtmdAccTxSchVcIdGetCallback is the prototype of the function to get -* a scheduler vcId -* -* @sa IxAtmdAccTxVcDemandUpdateCallback -* @sa IxAtmdAccTxVcDemandClearCallback -* @sa IxAtmdAccTxSchVcIdGetCallback -* @sa ixAtmdAccPortTxScheduledModeEnable -* -* @param port @ref IxAtmLogicalPort [in] - Specifies the ATM logical port on which the VC is -* established -* @param vpi unsigned int [in] - For AAL0/AAL5 specifies the ATM vpi on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VPI. -* @param vci unsigned int [in] - For AAL0/AAL5 specifies the ATM vci on which the -* VC is established. -* For OAM specifies the dedicated "OAM Tx channel" VCI. -* @param connId @ref IxAtmConnId [in] - specifies the IxAtmdAcc connection Id already -* associated with this VC -* @param vcId int* [out] - pointer to a vcId -* -* @return @li IX_SUCCESS the function is returning a Scheduler vcId for this -* VC -* @return @li IX_FAIL the function cannot process scheduling for this VC. -* the contents of vcId is unspecified -* -*/ -typedef IX_STATUS (*IxAtmdAccTxSchVcIdGetCallback) (IxAtmLogicalPort port, - unsigned int vpi, - unsigned int vci, - IxAtmConnId connId, - int *vcId); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to RX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback) - * - * @brief Register a notification callback to be invoked when there is - * at least one entry on a particular Rx queue. - * - * This function registers a callback to be invoked when there is at - * least one entry in a particular queue. The registered callback is - * called every time when the hardware adds one or more pdus to the - * specified Rx queue. - * - * This function cannot be used when a Rx Vc using this queue is - * already existing. - * - * @note -The callback function can be the API function - * @a ixAtmdAccRxDispatch() : every time the threhold level - * of the queue is reached, the ixAtmdAccRxDispatch() is - * invoked to remove all entries from the queue. - * - * @sa ixAtmdAccRxDispatch - * @sa IxAtmdAccRxDispatcher - * - * @param queueId @ref IxAtmRxQueueId [in] RX queue identification - * @param callback @ref IxAtmdAccRxDispatcher [in] function triggering the delivery of incoming - * traffic. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccRxDispatcherRegister() - * @return @li IX_FAIL error in the parameters, or there is an - * already active RX VC for this queue or some unspecified - * internal error occurred. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatcherRegister ( - IxAtmRxQueueId queueId, - IxAtmdAccRxDispatcher callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * - * @brief Control function which executes Rx processing for a particular - * Rx stream. - * - * The @a IxAtmdAccRxDispatch() function is used to process received Pdus - * available from one of the two incoming RX streams. When this function - * is invoked, the incoming traffic (up to the number of PDUs passed as - * a parameter) will be transferred to the IxAtmdAcc users through the - * callback @a IxAtmdAccRxVcRxCallback(), as registered during the - * @a ixAtmdAccRxVcConnect() call. - * - * The user receive callbacks will be executed in the context of this - * function. - * - * Failing to use this function on a regular basis when there is traffic - * will block incoming traffic and can result in Pdus being dropped by - * the hardware. - * - * This should be used to control when received pdus are handed off from - * the hardware to Aal users from a particluar stream. The function can - * be used from a timer context, or can be registered as a callback in - * response to an rx stream threshold event, or can be used inside an - * active polling mechanism which is under user control. - * - * @note - The signature of this function is directly compatible with the - * callback prototype which can be register with @a ixAtmdAccRxDispatcherRegister(). - * - * @sa ixAtmdAccRxDispatcherRegister - * @sa IxAtmdAccRxVcRxCallback - * @sa ixAtmdAccRxVcFreeEntriesQuery - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which RX queue to process. - * @param numberOfPdusToProcess unsigned int [in] - indicates the maxiumum number of PDU to - * remove from the RX queue. A value of IX_ATMDACC_ALLPDUS indicates - * to process all PDUs from the queue. This includes at least the PDUs - * in the queue when the fuction is invoked. Because of real-time - * constraints, there is no guarantee thatthe queue will be empty - * when the function exits. If this parameter is greater than the - * number of entries of the queues, the function will succeed - * and the parameter numberOfPdusProcessedPtr will reflect the exact - * number of PDUs processed. - * @param *numberOfPdusProcessedPtr unsigned int [out] - indicates the actual number of PDU - * processed during this call. This parameter cannot be a null - * pointer. - * - * @return @li IX_SUCCESS the number of PDUs as indicated in - * numberOfPdusProcessedPtr are removed from the RX queue and the VC callback - * are called. - * @return @li IX_FAIL invalid parameters or some unspecified internal - * error occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxDispatch (IxAtmRxQueueId rxQueueId, - unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the number of entries in a particular RX queue. - * - * This function is used to retrieve the number of pdus received by - * the hardware and ready for distribution to users. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of available - * PDUs in the RX queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of incoming pdus waiting in this queue - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxLevelQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr) - * - * @brief Query the size of a particular RX queue. - * - * This function is used to retrieve the number of pdus the system is - * able to queue when reception is complete. - * - * @param rxQueueId @ref IxAtmRxQueueId [in] - indicates which of two RX queues to query. - * @param numberOfPdusPtr unsigned int* [out] - Pointer to store the number of pdus - * the system is able to queue in the RX queue. This parameter - * cannot be a null pointer. - * - * @return @li IX_SUCCESS the value in numberOfPdusPtr specifies the - * number of pdus the system is able to queue. - * @return @li IX_FAIL an error occurs during processing. - * The value in numberOfPdusPtr is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - * - */ -PUBLIC IX_STATUS ixAtmdAccRxQueueSizeQuery (IxAtmRxQueueId rxQueueId, - unsigned int *numberOfPdusPtr); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to TX traffic - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr) - * - * @brief Get the number of available cells the system can accept for - * transmission. - * - * The function is used to retrieve the number of cells that can be - * queued for transmission to the hardware. - * - * This number is based on the worst schedule table where one cell - * is stored in one schedule table entry, depending on the pdus size - * and mbuf size and fragmentation. - * - * This function doesn't use system resources and can be used from a - * timer context, or can be associated with a threshold event, or can - * be used inside an active polling mechanism - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCellsPtr unsigned int* [out] - number of available cells. - * This parameter cannot be a null pointer. - * - * @sa ixAtmdAccPortTxProcess - * - * @return @li IX_SUCCESS numberOfCellsPtr contains the number of cells that can be scheduled - * for this port. - * @return @li IX_FAIL error in the parameters, or some processing error - * occured. - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxFreeEntriesQuery (IxAtmLogicalPort port, - unsigned int *numberOfCellsPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback) - * - * @brief Configure the Tx port threshold value and register a callback to handle - * threshold notifications. - * - * This function sets the threshold in cells - * - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortTxProcess - * @sa ixAtmdAccPortTxFreeEntriesQuery - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param numberOfCells unsigned int [in] - threshold value which triggers the callback - * invocation, This number has to be one of the - * values 0,1,2,4,8,16,32 .... - * The maximum value cannot be more than half of the txVc queue - * size (which can be retrieved using @a ixAtmdAccPortTxFreeEntriesQuery() - * before any Tx traffic is sent for this port) - * @param callback @ref IxAtmdAccPortTxLowCallback [in] - callback function to invoke when the threshold - * level is reached. - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS Successful call to @a ixAtmdAccPortTxCallbackRegister() - * @return @li IX_FAIL error in the parameters, Tx channel already set for this port - * threshold level is not correct or within the range regarding the - * queue size:or unspecified error during processing: - * - * @note - This callback function get called when the threshold level drops from - * (numberOfCells+1) cells to (numberOfCells) cells - * - * @note - This function should be called during system initialisation, - * outside an interrupt context - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxCallbackRegister (IxAtmLogicalPort port, - unsigned int numberOfCells, - IxAtmdAccPortTxLowCallback callback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback) - * - * @brief Put the port into Scheduled Mode - * - * This function puts the specified port into scheduled mode of - * transmission which means an external s/w entity controls the - * transmission of cells on this port. This faciltates traffic shaping on - * the port. - * - * Any buffers submitted on a VC for this port will be queued in IxAtmdAcc. - * The transmission of these buffers to and by the hardware will be driven - * by a transmit schedule submitted regulary in calls to - * @a ixAtmdAccPortTxProcess() by traffic shaping entity. - * - * The transmit schedule is expected to be dynamic in nature based on - * the demand in cells for each VC on the port. Hence the callback - * parameters provided to this function allow IxAtmdAcc to inform the - * shaping entity of demand changes for each VC on the port. - * - * By default a port is in Unscheduled Mode so if this function is not - * called, transmission of data is done without sheduling rules, on a - * first-come, first-out basis. - * - * Once a port is put in scheduled mode it cannot be reverted to - * un-scheduled mode. Note that unscheduled mode is not supported - * in ixp425 1.0 - * - * @note - This function should be called before any VCs have be - * connected on a port. Otherwise this function call will return failure. - * - * @note - This function uses internal locks and should not be called from - * an interrupt context - * - * @sa IxAtmdAccTxVcDemandUpdateCallback - * @sa IxAtmdAccTxVcDemandClearCallback - * @sa IxAtmdAccTxSchVcIdGetCallback - * @sa ixAtmdAccPortTxProcess - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param vcDemandUpdateCallback @ref IxAtmdAccTxVcDemandUpdateCallback [in] - callback function used to update - * the number of outstanding cells for transmission. This parameter - * cannot be a null pointer. - * @param vcDemandClearCallback @ref IxAtmdAccTxVcDemandClearCallback [in] - callback function used to remove all - * clear the number of outstanding cells for a VC. This parameter - * cannot be a null pointer. - * @param vcIdGetCallback @ref IxAtmdAccTxSchVcIdGetCallback [in] - callback function used to exchange vc - * Identifiers between IxAtmdAcc and the entity supplying the - * transmit schedule. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS scheduler registration is complete and the port - * is now in scheduled mode. - * @return @li IX_FAIL failed (wrong parameters, or traffic is already - * enabled on this port, possibly without ATM shaping) - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxScheduledModeEnable (IxAtmLogicalPort port, - IxAtmdAccTxVcDemandUpdateCallback vcDemandUpdateCallback, - IxAtmdAccTxVcDemandClearCallback vcDemandClearCallback, - IxAtmdAccTxSchVcIdGetCallback vcIdGetCallback); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr) - * - * @brief Transmit queue cells to the H/W based on the supplied schedule - * table. - * - * This function @a ixAtmdAccPortTxProcess() process the schedule - * table provided as a parameter to the function. As a result cells are - * sent to the underlaying hardware for transmission. - * - * The schedule table is executed in its entirety or not at all. So the - * onus is on the caller not to submit a table containing more cells than - * can be transmitted at that point. The maximum numbers that can be - * transmitted is guaranteed to be the number of cells as returned by the - * function @a ixAtmdAccPortTxFreeEntriesQuery(). - * - * When the scheduler is invoked on a threshold level, IxAtmdAcc gives the - * minimum number of cells (to ensure the callback will fire again later) - * and the maximum number of cells that @a ixAtmdAccPortTxProcess() - * will be able to process (assuming the ATM scheduler is able - * to produce the worst-case schedule table, i.e. one entry per cell). - * - * When invoked ouside a threshold level, the overall number of cells of - * the schedule table should be less than the number of cells returned - * by the @a ixAtmdAccPortTxFreeEntriesQuery() function. - * - * After invoking the @a ixAtmdAccPortTxProcess() function, it is the - * user choice to query again the queue level with the function - * @a ixAtmdAccPortTxFreeEntriesQuery() and, depending on a new cell - * number, submit an other schedule table. - * - * IxAtmdAcc will check that the number of cells in the schedule table - * is compatible with the current transmit level. If the - * - * Obsolete or invalid connection Id will be silently discarded. - * - * This function is not reentrant for the same port. - * - * This functions doesn't use system resources and can be used inside an - * interrupt context. - * - * This function is used as a response to the hardware requesting more - * cells to transmit. - * - * @sa ixAtmdAccPortTxScheduledModeEnable - * @sa ixAtmdAccPortTxFreeEntriesQuery - * @sa ixAtmdAccPortTxCallbackRegister - * @sa ixAtmdAccPortEnable - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * @param scheduleTablePtr @ref IxAtmScheduleTable* [in] - pointer to a scheduler update table. The - * content of this table is not modified by this function. This - * parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the schedule table process is complete - * and cells are transmitted to the hardware - * @return @li IX_ATMDACC_WARNING : Traffic will be dropped: the schedule table exceed - * the hardware capacity If this error is ignored, further traffic - * and schedule will work correctly. - * Overscheduling does not occur when the schedule table does - * not contain more entries that the number of free entries returned - * by @a ixAtmdAccPortTxFreeEntriesQuery(). - * However, Disconnect attempts just after this error will fail permanently - * with the error code @a IX_ATMDACC_RESOURCES_STILL_ALLOCATED, and it is - * necessary to disable the port to make @a ixAtmdAccTxVcTryDisconnect() - * successful. - * @return @li IX_FAIL a wrong parameter is supplied, or the format of - * the schedule table is invalid, or the port is not Enabled, or - * an internal severe error occured. No cells is transmitted to the hardware - * - * @note - If the failure is linked to an overschedule of data cells - * the result is an inconsistency in the output traffic (one or many - * cells may be missing and the traffic contract is not respected). - * - */ -PUBLIC IX_STATUS ixAtmdAccPortTxProcess (IxAtmLogicalPort port, - IxAtmScheduleTable* scheduleTablePtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr) - * - * @brief Process a number of pending transmit done pdus from the hardware. - * - * As a by-product of Atm transmit operation buffers which transmission - * is complete need to be recycled to users. This function is invoked - * to service the oustanding list of transmitted buffers and pass them - * to VC users. - * - * Users are handed back pdus by invoking the free callback registered - * during the @a ixAtmdAccTxVcConnect() call. - * - * There is a single Tx done stream servicing all active Atm Tx ports - * which can contain a maximum of 64 entries. If this stream fills port - * transmission will stop so this function must be call sufficently - * frequently to ensure no disruption to the transmit operation. - * - * This function can be used from a timer context, or can be associated - * with a TxDone level threshold event (see @a ixAtmdAccTxDoneDispatcherRegister() ), - * or can be used inside an active polling mechanism under user control. - * - * For ease of use the signature of this function is compatible with the - * TxDone threshold event callback prototype. - * - * This functions can be used inside an interrupt context. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa IxAtmdAccTxVcBufferReturnCallback - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdusToProcess unsigned int [in] - maxiumum number of pdus to remove - * from the TX Done queue - * @param *numberOfPdusProcessedPtr unsigned int [out] - number of pdus removed from - * the TX Done queue. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS the number of pdus as indicated in - * numberOfPdusToProcess are removed from the TX Done hardware - * and passed to the user through the Tx Done callback registered - * during a call to @a ixAtmdAccTxVcConnect() - * @return @li IX_FAIL invalid parameters or numberOfPdusProcessedPtr is - * a null pointer or some unspecified internal error occured. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneDispatch (unsigned int numberOfPdusToProcess, - unsigned int *numberOfPdusProcessedPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the current number of transmit pdus ready for - * recycling. - * - * This function is used to get the number of transmitted pdus which - * the hardware is ready to hand back to user. - * - * This function can be used from a timer context, or can be associated - * with a threshold event, on can be used inside an active polling - * mechanism - * - * @sa ixAtmdAccTxDoneDispatch - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus transmitted - * at the time of this function call, and ready for recycling - * This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the number of pdus - * ready for recycling at the time of this function call - * - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneLevelQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr) - * - * @brief Query the TxDone queue size. - * - * This function is used to get the number of pdus which - * the hardware is able to store after transmission is complete - * - * The returned value can be used to set a threshold and enable - * a callback to be notified when the number of pdus is going over - * the threshold. - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * - * @param *numberOfPdusPtr unsigned int [out] - Pointer to the number of pdus the system - * is able to queue after transmission - * - * @return @li IX_SUCCESS numberOfPdusPtr contains the the number of - * pdus the system is able to queue after transmission - * @return @li IX_FAIL wrong parameter (null pointer as parameter).or - * unspecified rocessing error occurs..The value in numberOfPdusPtr - * is unspecified. - * - * @note - This function is reentrant, doesn't use system resources - * and can be used from an interrupt context. - */ -PUBLIC IX_STATUS -ixAtmdAccTxDoneQueueSizeQuery (unsigned int *numberOfPdusPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback) - * - * @brief Configure the Tx Done stream threshold value and register a - * callback to handle threshold notifications. - * - * This function sets the threshold level in term of number of pdus at - * which the supplied notification function should be called. - * - * The higher the threshold value is, the less events will be necessary - * to process transmitted buffers. - * - * Transmitted buffers recycling implementation is a sytem-wide mechanism - * and needs to be set prior any traffic is started. If this threshold - * mechanism is not used, the user is responsible for polling the - * transmitted buffers thanks to @a ixAtmdAccTxDoneDispatch() and - * @a ixAtmdAccTxDoneLevelQuery() functions. - * - * This function should be called during system initialisation outside - * an interrupt context - * - * @sa ixAtmdAccTxDoneDispatcherRegister - * @sa ixAtmdAccTxDoneDispatch - * @sa ixAtmdAccTxDoneLevelQuery - * - * @param numberOfPdus unsigned int [in] - The number of TxDone pdus which triggers the - * callback invocation This number has to be a power of 2, one of the - * values 0,1,2,4,8,16,32 ... - * The maximum value cannot be more than half of the txDone queue - * size (which can be retrieved using @a ixAtmdAccTxDoneQueueSizeQuery()) - * @param notificationCallback @ref IxAtmdAccTxDoneDispatcher [in] - The function to invoke. (This - * parameter can be @a ixAtmdAccTxDoneDispatch()).This - * parameter ust not be a null pointer. - * - * @return @li IX_SUCCESS Successful call to ixAtmdAccTxDoneDispatcherRegister - * @return @li IX_FAIL error in the parameters: - * - * @note - The notificationCallback will be called exactly when the threshold level - * will increase from (numberOfPdus) to (numberOfPdus+1) - * - * @note - If there is no Tx traffic, there is no guarantee that TxDone Pdus will - * be released to the user (when txDone level is permanently under the threshold - * level. One of the preffered way to return resources to the user is to use - * a mix of txDone notifications, used together with a slow - * rate timer and an exclusion mechanism protecting from re-entrancy - * - * @note - The TxDone threshold will only hand back buffers when the threshold level is - * crossed. Setting this threshold to a great number reduce the interrupt rate - * and the cpu load, but also increase the number of outstanding mbufs and has - * a system wide impact when these mbufs are needed by other components. - * - */ -PUBLIC IX_STATUS ixAtmdAccTxDoneDispatcherRegister (unsigned int numberOfPdus, - IxAtmdAccTxDoneDispatcher notificationCallback); - -/* ------------------------------------------------------ - Part of the IxAtmdAcc interface related to Utopia config - ------------------------------------------------------ */ - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @defgroup IxAtmdAccUtopiaCtrlAPI IXP400 ATM Driver Access (IxAtmdAcc) Utopia Control API - * - * @brief The public API for the IXP400 Atm Driver Control component - * - * IxAtmdAcc is the low level interface by which AAL PDU get - * transmitted to,and received from the Utopia bus - * - * This part is related to the UTOPIA configuration. - * - * @{ - */ - -/** - * - * @brief Utopia configuration - * - * This structure is used to set the Utopia parameters - * @li contains the values of Utopia registers, to be set during initialisation - * @li contains debug commands for NPE, to be used during development steps - * - * @note - the exact description of all parameters is done in the Utopia reference - * documents. - * - */ -typedef struct -{ - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxConfig_ - * @brief Utopia Tx Config Register - */ - struct UtTxConfig_ - { - - unsigned int reserved_1:1; /**< [31] These bits are always 0.*/ - unsigned int txInterface:1; /**< [30] Utopia Transmit Interface. The following encoding - * is used to set the Utopia Transmit interface as ATM master - * or PHY slave: - * @li 1 - PHY - * @li 0 - ATM - */ - unsigned int txMode:1; /**< [29] Utopia Transmit Mode. The following encoding is used - * to set the Utopia Transmit mode to SPHY or MPHY: - * @li 1 - SPHY - * @li 0 - MPHY - */ - unsigned int txOctet:1; /**< [28] Utopia Transmit cell transfer protocol. Used to set - * the Utopia cell transfer protocol to Octet-level handshaking. - * Note this is only applicable in SPHY mode. - * @li 1 - Octet-handshaking enabled - * @li 0 - Cell-handshaking enabled - */ - unsigned int txParity:1; /**< [27] Utopia Transmit parity enabled when set. TxEvenParity - * defines the parity format odd/even. - * @li 1 - Enable Parity generation. - * @li 0 - ut_op_prty held low. - */ - unsigned int txEvenParity:1; /**< [26] Utopia Transmit Parity Mode - * @li 1 - Even Parity Generated. - * @li 0 - Odd Parity Generated. - */ - unsigned int txHEC:1; /**< [25] Header Error Check Insertion Mode. Specifies if the transmit - * cell header check byte is calculated and inserted when set. - * @li 1 - Generate HEC. - * @li 0 - Disable HEC generation. - */ - unsigned int txCOSET:1; /**< [24] If enabled the HEC is Exclusive-OR'ed with the value 0x55 before - * being presented on the Utopia bus. - * @li 1 - Enable HEC ExOR with value 0x55 - * @li 0 - Use generated HEC value. - */ - - unsigned int reserved_2:1; /**< [23] These bits are always 0 - */ - unsigned int txCellSize:7; /**< [22:16] Transmit expected cell size. Configures the cell size - * for the transmit module: Values between 52-64 are valid. - */ - unsigned int reserved_3:3; /**< [15:13] These bits are always 0 */ - unsigned int txAddrRange:5; /**< [12:8] When configured as an ATM master in MPHY mode this - * register specifies the upper limit of the PHY polling logical - * range. The number of active PHYs are TxAddrRange + 1. - */ - unsigned int reserved_4:3; /**< [7:5] These bits are always 0 */ - unsigned int txPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } - - utTxConfig; /**< Tx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxStatsConfig_ - * @brief Utopia Tx stats Register - */ - struct UtTxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] or PHY Address[4] */ - - unsigned int pti:3; /**< [3:1] ATM PTI [2:0] or PHY Address[3:1] - @li Note: if VCStatsTxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - - unsigned int clp:1; /**< [0] ATM CLP or PHY Address [0] - @li Note: if VCStatsTxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsTxEnb is set to 0 only the transmit PHY port - address as defined by this register is used for ATM statistics [4:0]. */ - } - - utTxStatsConfig; /**< Tx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxDefineIdle_ - * @brief Utopia Tx idle cells Register - */ - struct UtTxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleTxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleTxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleTxCLP is set to 0 the CLP field is ignored in test.*/ - } - - utTxDefineIdle; /**< Tx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxEnableFields_ - * @brief Utopia Tx ienable fields Register - */ - struct UtTxEnableFields_ - { - - unsigned int defineTxIdleGFC:1; /**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineTxIdlePTI:1; /**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int defineTxIdleCLP:1; /**< [29] This register is used to include or - exclude the CLP field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int phyStatsTxEnb:1; /**< [28] This register is used to enable or disable ATM - statistics gathering based on the specified PHY address as defined - in TxStatsConfig register. - @li 1 - Enable statistics for specified transmit PHY address. - @li 0 - Disable statistics for specified transmit PHY address. */ - - unsigned int vcStatsTxEnb:1; /**< [27] This register is used to change the ATM - statistics-gathering mode from the specified logical PHY address - to a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address */ - - unsigned int vcStatsTxGFC:1; /**< [26] This register is used to include or exclude the GFC - field of the ATM header when ATM VPI/VCI statistics are enabled. - GFC is only available at the UNI and uses the first 4-bits of - the VPI field. - @li 1 - GFC field is valid - @li 0 - GFC field ignored.*/ - - unsigned int vcStatsTxPTI:1; /**< [25] This register is used to include or exclude the PTI - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsTxCLP:1; /**< [24] This register is used to include or exclude the CLP - field of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid - @li 0 - CLP field ignored. */ - - unsigned int reserved_1:3; /**< [23-21] These bits are always 0 */ - - unsigned int txPollStsInt:1; /**< [20] Enable the assertion of the ucp_tx_poll_sts condition - where there is a change in polling status. - @li 1 - ucp_tx_poll_sts asserted whenever there is a change in status - @li 0 - ucp_tx_poll_sts asserted if ANY transmit PHY is available - */ - unsigned int txCellOvrInt:1; /**< [19] Enable TxCellCount overflow CBI Transmit Status condition - assertion. - @li 1 - If TxCellCountOvr is set assert the Transmit Status Condition. - @li 0 - No CBI Transmit Status condition assertion */ - - unsigned int txIdleCellOvrInt:1; /**< [18] Enable TxIdleCellCount overflow Transmit Status Condition - @li 1 - If TxIdleCellCountOvr is set assert the Transmit Status Condition - @li 0 - No CBI Transmit Status condition assertion..*/ - - unsigned int enbIdleCellCnt:1; /**< [17] Enable Transmit Idle Cell Count. - @li 1 - Enable count of Idle cells transmitted. - @li 0 - No count is maintained. */ - - unsigned int enbTxCellCnt:1; /**< [16] Enable Transmit Valid Cell Count of non-idle/non-error cells - @li 1 - Enable count of valid cells transmitted- non-idle/non-error - @li 0 - No count is maintained.*/ - - unsigned int reserved_2:16; /**< [15:0] These bits are always 0 */ - } utTxEnableFields; /**< Tx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable0_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Tx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Tx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Tx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0.*/ - - unsigned int phy3:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable0; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable1_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable1; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable2_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable2; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable3_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable3; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable4_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Tx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Tx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Tx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Tx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Tx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utTxTransTable4; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxTransTable5_ - * @brief Utopia Tx translation table Register - */ - struct UtTxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Tx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utTxTransTable5; /**< Tx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxConfig_ - * @brief Utopia Rx config Register - */ - struct UtRxConfig_ - { - - unsigned int rxInterface:1; /**< [31] Utopia Receive Interface. The following encoding is used - to set the Utopia Receive interface as ATM master or PHY slave: - @li 1 - PHY - @li 0 - ATM */ - - unsigned int rxMode:1; /**< [30] Utopia Receive Mode. The following encoding is used to set - the Utopia Receive mode to SPHY or MPHY: - @li 1 - SPHY - @li 0 - MPHY */ - - unsigned int rxOctet:1; /**< [29] Utopia Receive cell transfer protocol. Used to set the Utopia - cell transfer protocol to Octet-level handshaking. Note this is only - applicable in SPHY mode. - @li 1 - Octet-handshaking enabled - @li 0 - Cell-handshaking enabled */ - - unsigned int rxParity:1; /**< [28] Utopia Receive Parity Checking enable. - @li 1 - Parity checking enabled - @li 0 - Parity checking disabled */ - - unsigned int rxEvenParity:1;/**< [27] Utopia Receive Parity Mode - @li 1 - Check for Even Parity - @li 0 - Check for Odd Parity.*/ - - unsigned int rxHEC:1; /**< [26] RxHEC Header Error Check Mode. Enables/disables cell header - error checking on the received cell header. - @li 1 - HEC checking enabled - @li 0 - HEC checking disabled */ - - unsigned int rxCOSET:1; /**< [25] If enabled the HEC is Exclusive-OR'ed with the value 0x55 - before being tested with the received HEC. - @li 1 - Enable HEC ExOR with value 0x55. - @li 0 - Use generated HEC value.*/ - - unsigned int rxHECpass:1; /**< [24] Specifies if the incoming cell HEC byte should be transferred - after optional processing to the NPE2 Coprocessor Bus Interface or - if it should be discarded. - @li 1 - HEC maintained 53-byte/UDC cell sent to NPE2. - @li 0 - HEC discarded 52-byte/UDC cell sent to NPE2 coprocessor.*/ - - unsigned int reserved_1:1; /**< [23] These bits are always 0 */ - - unsigned int rxCellSize:7; /**< [22:16] Receive cell size. Configures the receive cell size. - Values between 52-64 are valid */ - - unsigned int rxHashEnbGFC:1; /**< [15] Specifies if the VPI field [11:8]/GFC field should be - included in the Hash data input or if the bits should be padded - with 1'b0. - @li 1 - VPI [11:8]/GFC field valid and used in Hash residue calculation. - @li 0 - VPI [11:8]/GFC field padded with 1'b0 */ - - unsigned int rxPreHash:1; /**< [14] Enable Pre-hash value generation. Specifies if the - incoming cell data should be pre-hashed to allow VPI/VCI header look-up - in a hash table. - @li 1 - Pre-hashing enabled - @li 0 - Pre-hashing disabled */ - - unsigned int reserved_2:1; /**< [13] These bits are always 0 */ - - unsigned int rxAddrRange:5; /**< [12:8] In ATM master, MPHY mode, - * this register specifies the upper - * limit of the PHY polling logical range. The number of active PHYs are - * RxAddrRange + 1. - */ - unsigned int reserved_3:3; /**< [7-5] These bits are always 0 .*/ - unsigned int rxPHYAddr:5; /**< [4:0] When configured as a slave in an MPHY system this register - * specifies the physical address of the PHY. - */ - } utRxConfig; /**< Rx config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxStatsConfig_ - * @brief Utopia Rx stats config Register - */ - struct UtRxStatsConfig_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCStatsRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] VCI [15:0] or PHY Address [4] */ - - unsigned int pti:3; /**< [3:1] PTI [2:0] or or PHY Address [3:1] - @li Note: if VCStatsRxPTI is set to 0 the PTI field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - - unsigned int clp:1; /**< [0] CLP [0] or PHY Address [0] - @li Note: if VCStatsRxCLP is set to 0 the CLP field is ignored in test. - @li Note: if VCStatsRxEnb is set to 0 only the PHY port address is used - for statistics gathering.. */ - } utRxStatsConfig; /**< Rx stats config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxDefineIdle_ - * @brief Utopia Rx idle cells config Register - */ - struct UtRxDefineIdle_ - { - - unsigned int vpi:12; /**< [31:20] ATM VPI [11:0] OR GFC [3:0] and VPI [7:0] - @li Note: if VCIdleRxGFC is set to 0 the GFC field is ignored in test. */ - - unsigned int vci:16; /**< [19:4] ATM VCI [15:0] */ - - unsigned int pti:3; /**< [3:1] ATM PTI PTI [2:0] - @li Note: if VCIdleRxPTI is set to 0 the PTI field is ignored in test.*/ - - unsigned int clp:1; /**< [0] ATM CLP [0] - @li Note: if VCIdleRxCLP is set to 0 the CLP field is ignored in test.*/ - } utRxDefineIdle; /**< Rx idle cell config Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxEnableFields_ - * @brief Utopia Rx enable Register - */ - struct UtRxEnableFields_ - { - - unsigned int defineRxIdleGFC:1;/**< [31] This register is used to include or exclude the GFC - field of the ATM header when testing for Idle cells. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored.*/ - - unsigned int defineRxIdlePTI:1;/**< [30] This register is used to include or exclude the PTI - field of the ATM header when testing for Idle cells. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int defineRxIdleCLP:1;/**< [29] This register is used to include or exclude the CLP - field of the ATM header when testing for Idle cells. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored.*/ - - unsigned int phyStatsRxEnb:1;/**< [28] This register is used to enable or disable ATM statistics - gathering based on the specified PHY address as defined in RxStatsConfig - register. - @li 1 - Enable statistics for specified receive PHY address. - @li 0 - Disable statistics for specified receive PHY address.*/ - - unsigned int vcStatsRxEnb:1;/**< [27] This register is used to enable or disable ATM statistics - gathering based on a specific VPI/VCI address. - @li 1 - Enable statistics for specified VPI/VCI address. - @li 0 - Disable statistics for specified VPI/VCI address.*/ - - unsigned int vcStatsRxGFC:1;/**< [26] This register is used to include or exclude the GFC field - of the ATM header when ATM VPI/VCI statistics are enabled. GFC is only - available at the UNI and uses the first 4-bits of the VPI field. - @li 1 - GFC field is valid. - @li 0 - GFC field ignored. */ - - unsigned int vcStatsRxPTI:1;/**< [25] This register is used to include or exclude the PTI field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - PTI field is valid. - @li 0 - PTI field ignored.*/ - - unsigned int vcStatsRxCLP:1;/**< [24] This register is used to include or exclude the CLP field - of the ATM header when ATM VPI/VCI statistics are enabled. - @li 1 - CLP field is valid. - @li 0 - CLP field ignored. */ - - unsigned int discardHecErr:1;/**< [23] Discard cells with an invalid HEC. - @li 1 - Discard cells with HEC errors - @li 0 - Cells with HEC errors are passed */ - - unsigned int discardParErr:1;/**< [22] Discard cells containing parity errors. - @li 1 - Discard cells with parity errors - @li 0 - Cells with parity errors are passed */ - - unsigned int discardIdle:1; /**< [21] Discard Idle Cells based on DefineIdle register values - @li 1 - Discard IDLE cells - @li 0 - IDLE cells passed */ - - unsigned int enbHecErrCnt:1;/**< [20] Enable Receive HEC Error Count. - @li 1 - Enable count of received cells containing HEC errors - @li 0 - No count is maintained. */ - - unsigned int enbParErrCnt:1;/**< [19] Enable Parity Error Count - @li 1 - Enable count of received cells containing Parity errors - @li 0 - No count is maintained. */ - - unsigned int enbIdleCellCnt:1;/**< [18] Enable Receive Idle Cell Count. - @li 1 - Enable count of Idle cells received. - @li 0 - No count is maintained.*/ - - unsigned int enbSizeErrCnt:1;/**< [17] Enable Receive Size Error Count. - @li 1 - Enable count of received cells of incorrect size - @li 0 - No count is maintained. */ - - unsigned int enbRxCellCnt:1;/**< [16] Enable Receive Valid Cell Count of non-idle/non-error cells. - @li 1 - Enable count of valid cells received - non-idle/non-error - @li 0 - No count is maintained. */ - - unsigned int reserved_1:3; /**< [15:13] These bits are always 0 */ - - unsigned int rxCellOvrInt:1; /**< [12] Enable CBI Utopia Receive Status Condition if the RxCellCount - register overflows. - @li 1 - CBI Receive Status asserted. - @li 0 - No CBI Receive Status asserted.*/ - - unsigned int invalidHecOvrInt:1; /**< [11] Enable CBI Receive Status Condition if the InvalidHecCount - register overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidParOvrInt:1; /**< [10] Enable CBI Receive Status Condition if the InvalidParCount - register overflows - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int invalidSizeOvrInt:1; /**< [9] Enable CBI Receive Status Condition if the InvalidSizeCount - register overflows. - @li 1 - CBI Receive Status Condition asserted. - @li 0 - No CBI Receive Status asserted */ - - unsigned int rxIdleOvrInt:1; /**< [8] Enable CBI Receive Status Condition if the RxIdleCount overflows. - @li 1 - CBI Receive Condition asserted. - @li 0 - No CBI Receive Condition asserted */ - - unsigned int reserved_2:3; /**< [7:5] These bits are always 0 */ - - unsigned int rxAddrMask:5; /**< [4:0] This register is used as a mask to allow the user to increase - the PHY receive address range. The register should be programmed with - the address-range limit, i.e. if set to 0x3 the address range increases - to a maximum of 4 addresses. */ - } utRxEnableFields; /**< Rx enable Utopia register */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable0_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable0_ - { - - unsigned int phy0:5; /**< [31-27] Rx Mapping value of logical phy 0 */ - - unsigned int phy1:5; /**< [26-22] Rx Mapping value of logical phy 1 */ - - unsigned int phy2:5; /**< [21-17] Rx Mapping value of logical phy 2 */ - - unsigned int reserved_1:1; /**< [16] These bits are always 0 */ - - unsigned int phy3:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy4:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy5:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable0; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable1_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable1_ - { - - unsigned int phy6:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy7:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy8:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy9:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy10:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy11:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } - - utRxTransTable1; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable2_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable2_ - { - - unsigned int phy12:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy13:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy14:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy15:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy16:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy17:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable2; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable3_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable3_ - { - - unsigned int phy18:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy19:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy20:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy21:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy22:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy23:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable3; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable4_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable4_ - { - - unsigned int phy24:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int phy25:5; /**< [26-22] Rx Mapping value of logical phy 7 */ - - unsigned int phy26:5; /**< [21-17] Rx Mapping value of logical phy 8 */ - - unsigned int reserved_1:1; /**< [16-0] These bits are always 0 */ - - unsigned int phy27:5; /**< [15-11] Rx Mapping value of logical phy 3 */ - - unsigned int phy28:5; /**< [10-6] Rx Mapping value of logical phy 4 */ - - unsigned int phy29:5; /**< [5-1] Rx Mapping value of logical phy 5 */ - - unsigned int reserved_2:1; /**< [0] These bits are always 0 */ - } utRxTransTable4; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxTransTable5_ - * @brief Utopia Rx translation table Register - */ - struct UtRxTransTable5_ - { - - unsigned int phy30:5; /**< [31-27] Rx Mapping value of logical phy 6 */ - - unsigned int reserved_1:27; /**< [26-0] These bits are always 0 */ - - } utRxTransTable5; /**< Rx translation table */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtSysConfig_ - * @brief NPE setup Register - */ - struct UtSysConfig_ - { - - unsigned int reserved_1:2; /**< [31-30] These bits are always 0 */ - unsigned int txEnbFSM:1; /**< [29] Enables the operation ofthe Utopia Transmit FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int rxEnbFSM:1; /**< [28] Enables the operation ofthe Utopia Revieve FSM - * @li 1 - FSM enabled - * @li 0 - FSM inactive - */ - unsigned int disablePins:1; /**< [27] Disable Utopia interface I/O pins forcing the signals to an - * inactive state. Note that this bit is set on reset and must be - * de-asserted - * @li 0 - Normal data transfer - * @li 1 - Utopia interface pins are forced inactive - */ - unsigned int tstLoop:1; /**< [26] Test Loop Back Enable. - * @li Note: For loop back to function RxMode and Tx Mode must both be set - * to single PHY mode. - * @li 0 - Loop back - * @li 1 - Normal operating mode - */ - - unsigned int txReset:1; /**< [25] Resets the Utopia Coprocessor transmit module to a known state. - * @li Note: All transmit configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset transmit modules - */ - - unsigned int rxReset:1; /**< [24] Resets the Utopia Coprocessor receive module to a known state. - * @li Note: All receive configuration and status registers will be reset - * to their reset values. - * @li 0 - Normal operating mode - * @li 1 - Reset receive modules - */ - - unsigned int reserved_2:24; /**< [23-0] These bits are always 0 */ - } utSysConfig; /**< NPE debug config */ - -} -IxAtmdAccUtopiaConfig; - -/** -* -* @brief Utopia status -* -* This structure is used to set/get the Utopia status parameters -* @li contains debug cell counters, to be accessed during a read operation -* -* @note - the exact description of all parameters is done in the Utopia reference -* documents. -* -*/ -typedef struct -{ - - unsigned int utTxCellCount; /**< count of cells transmitted */ - - unsigned int utTxIdleCellCount; /**< count of idle cells transmitted */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtTxCellConditionStatus_ - * @brief Utopia Tx Status Register - */ - struct UtTxCellConditionStatus_ - { - - unsigned int reserved_1:2; /**< [31:30] These bits are always 0 */ - unsigned int txFIFO2Underflow:1; /**< [29] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO underflow - * error condition. - */ - unsigned int txFIFO1Underflow:1; /**< [28] This bit is set if - * 64-byte Transmit FIFO1 indicates a FIFO - * underflow error condition. - */ - unsigned int txFIFO2Overflow:1; /**< [27] This bit is set if 64-byte - * Transmit FIFO2 indicates a FIFO overflow - * error condition. - */ - unsigned int txFIFO1Overflow:1; /**< [26] This bit is set if 64-byte - * Transmit FIFO1 indicates a FIFO overflow - * error condition. - */ - unsigned int txIdleCellCountOvr:1; /**< [25] This bit is set if the - * TxIdleCellCount register overflows. - */ - unsigned int txCellCountOvr:1; /**< [24] This bit is set if the - * TxCellCount register overflows - */ - unsigned int reserved_2:24; /**< [23:0] These bits are always 0 */ - } utTxCellConditionStatus; /**< Tx cells condition status */ - - unsigned int utRxCellCount; /**< count of cell received */ - unsigned int utRxIdleCellCount; /**< count of idle cell received */ - unsigned int utRxInvalidHECount; /**< count of invalid cell - * received because of HEC errors - */ - unsigned int utRxInvalidParCount; /**< count of invalid cell received - * because of parity errors - */ - unsigned int utRxInvalidSizeCount; /**< count of invalid cell - * received because of cell - * size errors - */ - - /** - * @ingroup IxAtmdAccUtopiaCtrlAPI - * @struct UtRxCellConditionStatus_ - * @brief Utopia Rx Status Register - */ - struct UtRxCellConditionStatus_ - { - - unsigned int reserved_1:3; /**< [31:29] These bits are always 0.*/ - unsigned int rxCellCountOvr:1; /**< [28] This bit is set if the RxCellCount register overflows. */ - unsigned int invalidHecCountOvr:1; /**< [27] This bit is set if the InvalidHecCount register overflows.*/ - unsigned int invalidParCountOvr:1; /**< [26] This bit is set if the InvalidParCount register overflows.*/ - unsigned int invalidSizeCountOvr:1; /**< [25] This bit is set if the InvalidSizeCount register overflows.*/ - unsigned int rxIdleCountOvr:1; /**< [24] This bit is set if the RxIdleCount register overflows.*/ - unsigned int reserved_2:4; /**< [23:20] These bits are always 0 */ - unsigned int rxFIFO2Underflow:1; /**< [19] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO underflow error condition. - */ - unsigned int rxFIFO1Underflow:1; /**< [18] This bit is set if 64-byte Receive - * FIFO1 indicates a FIFO underflow error condition - . */ - unsigned int rxFIFO2Overflow:1; /**< [17] This bit is set if 64-byte Receive FIFO2 - * indicates a FIFO overflow error condition. - */ - unsigned int rxFIFO1Overflow:1; /**< [16] This bit is set if 64-byte Receive FIFO1 - * indicates a FIFO overflow error condition. - */ - unsigned int reserved_3:16; /**< [15:0] These bits are always 0. */ - } utRxCellConditionStatus; /**< Rx cells condition status */ - -} IxAtmdAccUtopiaStatus; - -/** - * @} defgroup IxAtmdAccUtopiaCtrlAPI - */ - - /** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr) - * - * @brief Send the configuration structure to the Utopia interface - * - * This function downloads the @a IxAtmdAccUtopiaConfig structure to - * the Utopia and has the following effects - * @li setup the Utopia interface - * @li initialise the NPE - * @li reset the Utopia cell counters and status registers to known values - * - * This action has to be done once at initialisation. A lock is preventing - * the concurrent use of @a ixAtmdAccUtopiaStatusGet() and - * @A ixAtmdAccUtopiaConfigSet() - * - * @param *ixAtmdAccNPEConfigPtr @ref IxAtmdAccUtopiaConfig [in] - pointer to a structure to download to - * Utopia. This parameter cannot be a null pointer. - * - * @return @li IX_SUCCESS successful download - * @return @li IX_FAIL error in the parameters, or configuration is not - * complete or failed - * - * @sa ixAtmdAccUtopiaStatusGet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaConfigSet (const IxAtmdAccUtopiaConfig * - ixAtmdAccUtopiaConfigPtr); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus) - * - * @brief Get the Utopia interface configuration. - * - * This function reads the Utopia registers and the Cell counts - * and fills the @a IxAtmdAccUtopiaStatus structure - * - * A lock is preventing the concurrent - * use of @a ixAtmdAccUtopiaStatusGet() and @A ixAtmdAccUtopiaConfigSet() - * - * @param ixAtmdAccUtopiaStatus @ref IxAtmdAccUtopiaStatus [out] - pointer to structure to be updated from internal - * hardware counters. This parameter cannot be a NULL pointer. - * - * @return @li IX_SUCCESS successful read - * @return @li IX_FAIL error in the parameters null pointer, or - * configuration read is not complete or failed - * - * @sa ixAtmdAccUtopiaConfigSet - * - */ -PUBLIC IX_STATUS ixAtmdAccUtopiaStatusGet (IxAtmdAccUtopiaStatus * - ixAtmdAccUtopiaStatus); - -/** - * - * @ingroup IxAtmdAcc - * - * @fn ixAtmdAccPortEnable (IxAtmLogicalPort port) - * - * @brief enable a PHY logical port - * - * This function enables the transmission over one port. It should be - * called before accessing any resource from this port and before the - * establishment of a VC. - * - * When a port is enabled, the cell transmission to the Utopia interface - * is started. If there is no traffic already running, idle cells are - * sent over the interface. - * - * This function can be called multiple times. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS enable is complete - * @return @li IX_ATMDACC_WARNING port already enabled - * @return @li IX_FAIL enable failed, wrong parameter, or cannot - * initialise this port (the port is maybe already in use, - * or there is a hardware issue) - * - * @note - This function needs internal locks and should not be - * called from an interrupt context - * - * @sa ixAtmdAccPortDisable - * - */ -PUBLIC IX_STATUS ixAtmdAccPortEnable (IxAtmLogicalPort port); - -/** - * - * @ingroup IxAtmdAccCtrlAPI - * - * @fn ixAtmdAccPortDisable (IxAtmLogicalPort port) - * - * @brief disable a PHY logical port - * - * This function disable the transmission over one port. - * - * When a port is disabled, the cell transmission to the Utopia interface - * is stopped. - * - * @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] - * - * @return @li IX_SUCCESS disable is complete - * @return @li IX_ATMDACC_WARNING port already disabled - * @return @li IX_FAIL disable failed, wrong parameter . - * - * @note - This function needs internal locks and should not be called - * from an interrupt context - * - * @note - The response from hardware is done through the txDone mechanism - * to ensure the synchrnisation with tx resources. Therefore, the - * txDone mechanism needs to be serviced to make a PortDisable complete. - * - * @sa ixAtmdAccPortEnable - * @sa ixAtmdAccPortDisableComplete - * @sa ixAtmdAccTxDoneDispatch - * - */ -PUBLIC IX_STATUS ixAtmdAccPortDisable (IxAtmLogicalPort port); - -/** -* -* @ingroup IxAtmdAccCtrlAPI -* -* @fn ixAtmdAccPortDisableComplete (IxAtmLogicalPort port) -* -* @brief disable a PHY logical port -* -* This function indicates if the port disable for a port has completed. This -* function will return true if the port has never been enabled. -* -* @param port @ref IxAtmLogicalPort [in] - logical PHY port [@a IX_UTOPIA_PORT_0 .. @a IX_UTOPIA_MAX_PORTS - 1] -* -* @return @li true disable is complete -* @return @li false disable failed, wrong parameter . -* -* @note - This function needs internal locks and should not be called -* from an interrupt context -* -* @sa ixAtmdAccPortEnable -* @sa ixAtmdAccPortDisable -* -*/ -PUBLIC BOOL ixAtmdAccPortDisableComplete (IxAtmLogicalPort port); - -#endif /* IXATMDACCCTRL_H */ - -/** - * @} defgroup IxAtmdAccCtrlAPI - */ - - diff --git a/drivers/net/npe/include/IxAtmm.h b/drivers/net/npe/include/IxAtmm.h deleted file mode 100644 index 805b8c9bd65..00000000000 --- a/drivers/net/npe/include/IxAtmm.h +++ /dev/null @@ -1,771 +0,0 @@ -/** - * @file IxAtmm.h - * - * @date 3-DEC-2001 - * - * @brief Header file for the IXP400 ATM Manager component (IxAtmm) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - -/** - * @defgroup IxAtmm IXP400 ATM Manager (IxAtmm) API - * - * @brief IXP400 ATM Manager component Public API - * - * @{ - */ - -#ifndef IXATMM_H -#define IXATMM_H - -/* - * Put the user defined include files required - */ -#include "IxAtmSch.h" -#include "IxOsalTypes.h" - -/* - * #defines and macros used in this file. - */ - -/** - * @def IX_ATMM_RET_ALREADY_INITIALIZED - * - * @brief Component has already been initialized - */ -#define IX_ATMM_RET_ALREADY_INITIALIZED 2 - -/** - * @def IX_ATMM_RET_INVALID_PORT - * - * @brief Specified port does not exist or is out of range */ -#define IX_ATMM_RET_INVALID_PORT 3 - -/** - * @def IX_ATMM_RET_INVALID_VC_DESCRIPTOR - * - * @brief The VC description does not adhere to ATM standards */ -#define IX_ATMM_RET_INVALID_VC_DESCRIPTOR 4 - -/** - * @def IX_ATMM_RET_VC_CONFLICT - * - * @brief The VPI/VCI values supplied are either reserved, or they - * conflict with a previously registered VC on this port */ -#define IX_ATMM_RET_VC_CONFLICT 5 - -/** - * @def IX_ATMM_RET_PORT_CAPACITY_IS_FULL - * - * @brief The virtual connection cannot be established on the port - * because the remaining port capacity is not sufficient to - * support it */ -#define IX_ATMM_RET_PORT_CAPACITY_IS_FULL 6 - -/** - * @def IX_ATMM_RET_NO_SUCH_VC - * - * @brief No registered VC, as described by the supplied VCI/VPI or - * VC identifier values, exists on this port */ -#define IX_ATMM_RET_NO_SUCH_VC 7 - -/** - * @def IX_ATMM_RET_INVALID_VC_ID - * - * @brief The specified VC identifier is out of range. */ -#define IX_ATMM_RET_INVALID_VC_ID 8 - -/** - * @def IX_ATMM_RET_INVALID_PARAM_PTR - * - * @brief A pointer parameter was NULL. */ -#define IX_ATMM_RET_INVALID_PARAM_PTR 9 - -/** - * @def IX_ATMM_UTOPIA_SPHY_ADDR - * - * @brief The phy address when in SPHY mode */ -#define IX_ATMM_UTOPIA_SPHY_ADDR 31 - -/** - * @def IX_ATMM_THREAD_PRI_HIGH - * - * @brief The value of high priority thread */ -#define IX_ATMM_THREAD_PRI_HIGH 90 - -/* - * Typedefs whose scope is limited to this file. - */ - -/** @brief Definition for use in the @ref IxAtmmVc structure. - * Indicates the direction of a VC */ -typedef enum -{ - IX_ATMM_VC_DIRECTION_TX=0, /**< Atmm Vc direction transmit*/ - IX_ATMM_VC_DIRECTION_RX, /**< Atmm Vc direction receive*/ - IX_ATMM_VC_DIRECTION_INVALID /**< Atmm Vc direction invalid*/ -} IxAtmmVcDirection; - -/** @brief Definition for use with @ref IxAtmmVcChangeCallback - * callback. Indicates that the event type represented by the - * callback for this VC. */ -typedef enum -{ - IX_ATMM_VC_CHANGE_EVENT_REGISTER=0, /**< Atmm Vc event register*/ - IX_ATMM_VC_CHANGE_EVENT_DEREGISTER, /**< Atmm Vc event de-register*/ - IX_ATMM_VC_CHANGE_EVENT_INVALID /**< Atmm Vc event invalid*/ -} IxAtmmVcChangeEvent; - -/** @brief Definitions for use with @ref ixAtmmUTOPIAInit interface to - * indicate that UTOPIA loopback should be enabled or disabled - * on initialisation. */ -typedef enum -{ - IX_ATMM_UTOPIA_LOOPBACK_DISABLED=0, /**< Atmm Utopia loopback mode disabled*/ - IX_ATMM_UTOPIA_LOOPBACK_ENABLED, /**< Atmm Utopia loopback mode enabled*/ - IX_ATMM_UTOPIA_LOOPBACK_INVALID /**< Atmm Utopia loopback mode invalid*/ -} IxAtmmUtopiaLoopbackMode; - -/** @brief This structure describes the required attributes of a - * virtual connection. -*/ -typedef struct { - unsigned vpi; /**< VPI value of this virtual connection */ - unsigned vci; /**< VCI value of this virtual connection. */ - IxAtmmVcDirection direction; /**< VC direction */ - - /** Traffic descriptor of this virtual connection. This structure - * is defined by the @ref IxAtmSch component. */ - IxAtmTrafficDescriptor trafficDesc; -} IxAtmmVc; - - -/** @brief Definitions for use with @ref ixAtmmUtopiaInit interface to - * indicate that UTOPIA multi-phy/single-phy mode is used. - */ -typedef enum -{ - IX_ATMM_MPHY_MODE = 0, /**< Atmm phy mode mphy*/ - IX_ATMM_SPHY_MODE, /**< Atmm phy mode sphy*/ - IX_ATMM_PHY_MODE_INVALID /**< Atmm phy mode invalid*/ -} IxAtmmPhyMode; - - -/** @brief Structure contains port-specific information required to - * initialize IxAtmm, and specifically, the IXP400 UTOPIA - * Level-2 device. */ -typedef struct { - unsigned reserved_1:11; /**< [31:21] Should be zero */ - unsigned UtopiaTxPhyAddr:5; /**< [20:16] Address of the - * transmit (Tx) PHY for this - * port on the 5-bit UTOPIA - * Level-2 address bus */ - unsigned reserved_2:11; /**< [15:5] Should be zero */ - unsigned UtopiaRxPhyAddr:5; /**< [4:0] Address of the receive - * (Rx) PHY for this port on the - * 5-bit UTOPIA Level-2 - * address bus */ -} IxAtmmPortCfg; - -/** @brief Callback type used with @ref ixAtmmVcChangeCallbackRegister interface - * Defines a callback type which will be used to notify registered - * users of registration/deregistration events on a particular port - * - * @param eventType @ref IxAtmmVcChangeEvent [in] - Event indicating - * whether the VC supplied has been added or - * removed - * - * @param port @ref IxAtmLogicalPort [in] - Specifies the port on which the event has - * occurred - * - * @param vcChanged @ref IxAtmmVc* [in] - Pointer to a structure which gives - * details of the VC which has been added - * or removed on the port - */ -typedef void (*IxAtmmVcChangeCallback) (IxAtmmVcChangeEvent eventType, - IxAtmLogicalPort port, - const IxAtmmVc* vcChanged); - -/* - * Variable declarations global to this file only. Externs are followed by - * static variables. - */ - -/* - * Extern function prototypes - */ - -/* - * Function declarations - */ - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmInit (void) - * - * @brief Interface to initialize the IxAtmm software component. Can - * be called once only. - * - * Must be called before any other IxAtmm API is called. - * - * @param "none" - * - * @return @li IX_SUCCESS : IxAtmm has been successfully initialized. - * Calls to other IxAtmm interfaces may now be performed. - * @return @li IX_FAIL : IxAtmm has already been initialized. - */ -PUBLIC IX_STATUS -ixAtmmInit (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode) - * - * @brief Interface to initialize the UTOPIA Level-2 ATM coprocessor - * for the specified number of physical ports. The function - * must be called before the ixAtmmPortInitialize interface - * can operate successfully. - * - * @param numPorts unsigned [in] - Indicates the total number of logical - * ports that are active on the device. Up to 12 ports are - * supported. - * - * @param phyMode @ref IxAtmmPhyMode [in] - Put the Utopia coprocessor in SPHY - * or MPHY mode. - * - * @param portCfgs[] @ref IxAtmmPortCfg [in] - Pointer to an array of elements - * detailing the UTOPIA specific port characteristics. The - * length of the array must be equal to the number of ports - * activated. ATM ports are referred to by the relevant - * offset in this array in all subsequent IxAtmm interface - * calls. - * - * @param loopbackMode @ref IxAtmmUtopiaLoopbackMode [in] - Value must be one of - * @ref IX_ATMM_UTOPIA_LOOPBACK_ENABLED or @ref - * IX_ATMM_UTOPIA_LOOPBACK_DISABLED indicating whether - * loopback should be enabled on the device. Loopback can - * only be supported on a single PHY, therefore the numPorts - * parameter must be 1 if loopback is enabled. - * - * @return @li IX_SUCCESS : Indicates that the UTOPIA device has been - * successfully initialized for the supplied ports. - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : The UTOPIA device has - * already been initialized. - * @return @li IX_FAIL : The supplied parameters are invalid or have been - * rejected by the UTOPIA-NPE device. - * - * @warning - * This interface may only be called once. - * Port identifiers are assumed to range from 0 to (numPorts - 1) in all - * instances. - * In all subsequent calls to interfaces supplied by IxAtmm, the specified - * port value is expected to represent the offset in the portCfgs array - * specified in this interface. i.e. The first port in this array will - * subsequently be represented as port 0, the second port as port 1, - * and so on.*/ -PUBLIC IX_STATUS -ixAtmmUtopiaInit (unsigned numPorts, - IxAtmmPhyMode phyMode, - IxAtmmPortCfg portCfgs[], - IxAtmmUtopiaLoopbackMode loopbackMode); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief The interface is called following @ref ixAtmmUtopiaInit () - * and before calls to any other IxAtmm interface. It serves - * to activate the registered ATM port with IxAtmm. - * - * The transmit and receive port rates are specified in bits per - * second. This translates to ATM cells per second according to the - * following formula: CellsPerSecond = portRate / (53*8) The - * IXP400 device supports only 53 byte cells. The client shall make - * sure that the off-chip physical layer device has already been - * initialized. - * - * IxAtmm will configure IxAtmdAcc and IxAtmSch to enable scheduling - * on the port. - * - * This interface must be called once for each active port in the - * system. The first time the interface is invoked, it will configure - * the mechanism by which the handling of transmit, transmit-done and - * receive are driven with the IxAtmdAcc component. - * - * This function is reentrant. - * - * @note The minimum tx rate that will be accepted is 424 bit/s which equates - * to 1 cell (53 bytes) per second. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in bits/second. - * - * @return @li IX_SUCCESS : The specificed ATM port has been successfully - * initialized. IxAtmm is ready to accept VC registrations on - * this port. - * - * @return @li IX_ATMM_RET_ALREADY_INITIALIZED : ixAtmmPortInitialize has - * already been called successfully on this port. The current - * call is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not initialize the port because the - * inputs are not understood. - * - * @sa ixAtmmPortEnable, ixAtmmPortDisable - * - */ -PUBLIC IX_STATUS -ixAtmmPortInitialize (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate) - * - * @brief A client may call this interface to change the existing - * port rate (expressed in bits/second) on an established ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies the port which is to be - * initialized. - * - * @param txPortRate unsigned [in] - Value specifies the`` - * transmit port rate for this port in - * bits/second. This value is used by the ATM Scheduler - * component is evaluating VC access requests for the port. - * - * @param rxPortRate unsigned [in] - Value specifies the - * receive port rate for this port in - * bits/second. - * - * @return @li IX_SUCCESS : The indicated ATM port rates have been - * successfully modified. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortModify (IxAtmLogicalPort port, - unsigned txPortRate, - unsigned rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - - * - * @brief The client may call this interface to request details on - * currently registered transmit and receive rates for an ATM - * port. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port from which the - * rate details are requested. - * - * @param *txPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the transmit port - * rate specified in bits/second. - * - * @param *rxPortRate unsigned [out] - Pointer to a value - * which will be filled with the value of the receive port - * rate specified in bits/second. - * - * @return @li IX_SUCCESS : The information requested on the specified - * port has been successfully supplied in the output. - * - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid. The request is rejected. - * - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @return @li IX_FAIL : IxAtmm could not update the port because the - * inputs are not understood, or the interface was called before - * the port was initialized. */ -PUBLIC IX_STATUS -ixAtmmPortQuery (IxAtmLogicalPort port, - unsigned *txPortRate, - unsigned *rxPortRate); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortEnable(IxAtmLogicalPort port) - * - * @brief The client call this interface to enable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is started. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already enabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortDisable */ -PUBLIC IX_STATUS -ixAtmmPortEnable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmPortDisable(IxAtmLogicalPort port) - * - * @brief The client call this interface to disable transmit for an ATM - * port. At initialisation, all the ports are disabled. - * - * @param port @ref IxAtmLogicalPort [in] - Value identifies the port - * - * @return @li IX_SUCCESS : Transmission over this port is stopped. - * - * @return @li IX_FAIL : The port parameter is not valid, or the - * port is already disabled - * - * @note - When a port is disabled, Rx and Tx VC Connect requests will fail - * - * @note - This function call does not stop RX traffic. It is supposed - * that this function is invoked when a serious problem - * is detected (e.g. physical layer broken). Then, the RX traffic - * is not passing. - * - * @note - This function is blocking until the hw acknowledge that the - * transmission is stopped. - * - * @note - This function uses system resources and should not be used - * inside an interrupt context. - * - * @sa ixAtmmPortEnable */ -PUBLIC IX_STATUS -ixAtmmPortDisable(IxAtmLogicalPort port); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId) - * - * @brief This interface is used to register an ATM Virtual - * Connection on the specified ATM port. - * - * Each call to this interface registers a unidirectional virtual - * connection with the parameters specified. If a bi-directional VC - * is needed, the function should be called twice (once for each - * direction, Tx & Rx) where the VPI and VCI and port parameters in - * each call are identical. - * - * With the addition of each new VC to a port, a series of - * callback functions are invoked by the IxAtmm component to notify - * possible external components of the change. The callback functions - * are registered using the @ref ixAtmmVcChangeCallbackRegister interface. - * - * The IxAtmSch component is notified of the registration of transmit - * VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the specified VC is - * to be registered. - * - * @param *vcToAdd @ref IxAtmmVc [in] - Pointer to an @ref IxAtmmVc structure - * containing a description of the VC to be registered. The - * client shall fill the vpi, vci and direction and relevant - * trafficDesc members of this structure before calling this - * function. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which is filled - * with the per-port unique identifier value for this VC. - * This identifier will be required when a request is - * made to deregister or change this VC. VC identifiers - * for transmit VCs will have a value between 0-43, - * i.e. 32 data Tx VCs + 12 OAM Tx Port VCs. - * Receive VCs will have a value between 44-66, - * i.e. 32 data Rx VCs + 1 OAM Rx VC. - * - * @return @li IX_SUCCESS : The VC has been successfully registered on - * this port. The VC is ready for a client to configure IxAtmdAcc - * for receive and transmit operations on the VC. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_INVALID_VC_DESCRIPTOR : The descriptor - * pointed to by vcToAdd is invalid. The registration request - * is rejected. - * @return @li IX_ATMM_RET_VC_CONFLICT : The VC requested conflicts with - * reserved VPI and/or VCI values or with another VC already activated - * on this port. - * @return @li IX_ATMM_RET_PORT_CAPACITY_IS_FULL : The VC cannot be - * registered in the port becuase the port capacity is - * insufficient to support the requested ATM traffic contract. - * The registration request is rejected. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - * @warning IxAtmm has no capability of signaling or negotiating a virtual - * connection. Negotiation of the admission of the VC to the network - * is beyond the scope of this function. This is assumed to be - * performed by the calling client, if appropriate, - * before or after this function is called. - */ -PUBLIC IX_STATUS -ixAtmmVcRegister (IxAtmLogicalPort port, - IxAtmmVc *vcToAdd, - IxAtmSchedulerVcId *vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId) - * - * @brief Function called by a client to deregister a VC from the - * system. - * - * With the removal of each new VC from a port, a series of - * registered callback functions are invoked by the IxAtmm component - * to notify possible external components of the change. The callback - * functions are registered using the @ref ixAtmmVcChangeCallbackRegister. - * - * The IxAtmSch component is notified of the removal of transmit VCs. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * removed is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - VC identifier value of the VC to - * be deregistered. This value was supplied to the client when - the VC was originally registered. This value can also be - queried from the IxAtmm component through the @ref ixAtmmVcQuery - * interface. - * - * @return @li IX_SUCCESS : The specified VC has been successfully - * removed from this port. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_FAIL : There is no registered VC associated with the - * supplied identifier registered on this port. */ -PUBLIC IX_STATUS -ixAtmmVcDeregister (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with the VPI, VCI and - * direction of that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vpi unsigned [in] - ATM VPI value of the requested VC. - * - * @param vci unsigned [in] - ATM VCI value of the requested VC. - * - * @param direction @ref IxAtmmVcDirection [in] - One of @ref - * IX_ATMM_VC_DIRECTION_TX or @ref IX_ATMM_VC_DIRECTION_RX - * indicating the direction (Tx or Rx) of the requested VC. - * - * @param *vcId @ref IxAtmSchedulerVcId [out] - Pointer to an integer value which will be - * filled with the VC identifier value for the requested - * VC (as returned by @ref ixAtmmVcRegister), if it - * exists on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the search criteria (VPI, VCI, direction) - * given. No data is returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - * - */ -PUBLIC IX_STATUS -ixAtmmVcQuery (IxAtmLogicalPort port, - unsigned vpi, - unsigned vci, - IxAtmmVcDirection direction, - IxAtmSchedulerVcId *vcId, - IxAtmmVc *vcDesc); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc) - * - * @brief This interface supplies information about an active VC on a - * particular port when supplied with a vcId for that VC. - * - * @param port @ref IxAtmLogicalPort [in] - Identifies port on which the VC to be - * queried is currently registered. - * - * @param vcId @ref IxAtmSchedulerVcId [in] - Value returned by @ref ixAtmmVcRegister which - * uniquely identifies the requested VC on this port. - * - * @param *vcDesc @ref IxAtmmVc [out] - Pointer to an @ref IxAtmmVc structure - * which will be filled with the specific details of the - * requested VC, if it exists on this port. - * - * @return @li IX_SUCCESS : The specified VC has been found on this port - * and the requested details have been returned. - * @return @li IX_ATMM_RET_INVALID_PORT : The port value indicated in the - * input is not valid or has not been initialized. The request - * is rejected. - * @return @li IX_ATMM_RET_NO_SUCH_VC : No VC exists on the specified - * port which matches the supplied identifier. No data is - * returned. - * @return @li IX_ATMM_RET_INVALID_PARAM_PTR : A pointer parameter was - * NULL. - */ -PUBLIC IX_STATUS -ixAtmmVcIdQuery (IxAtmLogicalPort port, IxAtmSchedulerVcId vcId, IxAtmmVc *vcDesc); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to supply a function to IxAtmm - * which will be called to notify the client if a new VC is - * registered with IxAtmm or an existing VC is removed. - * - * The callback, when invoked, will run within the context of the call - * to @ref ixAtmmVcRegister or @ref ixAtmmVcDeregister which caused - * the change of state. - * - * A maximum of 32 calbacks may be registered in with IxAtmm. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will be invoked by IxAtmm with the appropiate - * parameters for the relevant VC when any VC has been - * registered or deregistered with IxAtmm. - * - * @return @li IX_SUCCESS : The specified callback has been registered - * successfully with IxAtmm and will be invoked when appropriate. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * IxAtmm has already registered 32 and connot accommodate - * any further registrations of this type. The request is - * rejected. - * - * @warning The client must not call either the @ref - * ixAtmmVcRegister or @ref ixAtmmVcDeregister interfaces - * from within the supplied callback function. */ -PUBLIC IX_STATUS ixAtmmVcChangeCallbackRegister (IxAtmmVcChangeCallback callback); - - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback) - * - * @brief This interface is invoked to deregister a previously supplied - * callback function. - * - * @param callback @ref IxAtmmVcChangeCallback [in] - Callback which complies - * with the @ref IxAtmmVcChangeCallback definition. This - * function will removed from the table of callbacks. - * - * @return @li IX_SUCCESS : The specified callback has been deregistered - * successfully from IxAtmm. - * @return @li IX_FAIL : Either the supplied callback is invalid, or - * is not currently registered with IxAtmm. - */ -PUBLIC IX_STATUS -ixAtmmVcChangeCallbackDeregister (IxAtmmVcChangeCallback callback); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaStatusShow (void) - * - * @brief Display utopia status counters - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaStatusShow (void); - -/** - * @ingroup IxAtmm - * - * @fn ixAtmmUtopiaCfgShow (void) - * - * @brief Display utopia information(config registers and status registers) - * - * @param "none" - * - * @return @li IX_SUCCESS : Show function was successful - * @return @li IX_FAIL : Internal failure - */ -PUBLIC IX_STATUS -ixAtmmUtopiaCfgShow (void); - -#endif -/* IXATMM_H */ - -/** @} */ diff --git a/drivers/net/npe/include/IxDmaAcc.h b/drivers/net/npe/include/IxDmaAcc.h deleted file mode 100644 index a62e72cc1b8..00000000000 --- a/drivers/net/npe/include/IxDmaAcc.h +++ /dev/null @@ -1,236 +0,0 @@ -/** - * @file IxDmaAcc.h - * - * @date 15 October 2002 - * - * @brief API of the IXP400 DMA Access Driver Component (IxDma) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/*--------------------------------------------------------------------- - Doxygen group definitions - ---------------------------------------------------------------------*/ - -#ifndef IXDMAACC_H -#define IXDMAACC_H - -#include "IxOsal.h" -#include "IxNpeDl.h" -/** - * @defgroup IxDmaTypes IXP400 DMA Types (IxDmaTypes) - * @brief The common set of types used in the DMA component - * @{ - */ - -/** - * @ingroup IxDmaTypes - * @enum IxDmaReturnStatus - * @brief Dma return status definitions - */ -typedef enum -{ - IX_DMA_SUCCESS = IX_SUCCESS, /**< DMA Transfer Success */ - IX_DMA_FAIL = IX_FAIL, /**< DMA Transfer Fail */ - IX_DMA_INVALID_TRANSFER_WIDTH, /**< Invalid transfer width */ - IX_DMA_INVALID_TRANSFER_LENGTH, /**< Invalid transfer length */ - IX_DMA_INVALID_TRANSFER_MODE, /**< Invalid transfer mode */ - IX_DMA_INVALID_ADDRESS_MODE, /**< Invalid address mode */ - IX_DMA_REQUEST_FIFO_FULL /**< DMA request queue is full */ -} IxDmaReturnStatus; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferMode - * @brief Dma transfer mode definitions - * @note Copy and byte swap, and copy and reverse modes only support multiples of word data length. - */ -typedef enum -{ - IX_DMA_COPY_CLEAR = 0, /**< copy and clear source*/ - IX_DMA_COPY, /**< copy */ - IX_DMA_COPY_BYTE_SWAP, /**< copy and byte swap (endian) */ - IX_DMA_COPY_REVERSE, /**< copy and reverse */ - IX_DMA_TRANSFER_MODE_INVALID /**< Invalid transfer mode */ -} IxDmaTransferMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaAddressingMode - * @brief Dma addressing mode definitions - * @note Fixed source address to fixed destination address addressing mode is not supported. - */ -typedef enum -{ - IX_DMA_INC_SRC_INC_DST = 0, /**< Incremental source address to incremental destination address */ - IX_DMA_INC_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_INC_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_FIX_SRC_FIX_DST, /**< Incremental source address to incremental destination address */ - IX_DMA_ADDRESSING_MODE_INVALID /**< Invalid Addressing Mode */ -} IxDmaAddressingMode; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaTransferWidth - * @brief Dma transfer width definitions - * @Note Fixed addresses (either source or destination) do not support burst transfer width. - */ -typedef enum -{ - IX_DMA_32_SRC_32_DST = 0, /**< 32-bit src to 32-bit dst */ - IX_DMA_32_SRC_16_DST, /**< 32-bit src to 16-bit dst */ - IX_DMA_32_SRC_8_DST, /**< 32-bit src to 8-bit dst */ - IX_DMA_16_SRC_32_DST, /**< 16-bit src to 32-bit dst */ - IX_DMA_16_SRC_16_DST, /**< 16-bit src to 16-bit dst */ - IX_DMA_16_SRC_8_DST, /**< 16-bit src to 8-bit dst */ - IX_DMA_8_SRC_32_DST, /**< 8-bit src to 32-bit dst */ - IX_DMA_8_SRC_16_DST, /**< 8-bit src to 16-bit dst */ - IX_DMA_8_SRC_8_DST, /**< 8-bit src to 8-bit dst */ - IX_DMA_8_SRC_BURST_DST, /**< 8-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_16_SRC_BURST_DST, /**< 16-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_32_SRC_BURST_DST, /**< 32-bit src to burst dst - Not supported for fixed destination address */ - IX_DMA_BURST_SRC_8_DST, /**< burst src to 8-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_16_DST, /**< burst src to 16-bit dst - Not supported for fixed source address */ - IX_DMA_BURST_SRC_32_DST, /**< burst src to 32-bit dst - Not supported for fixed source address*/ - IX_DMA_BURST_SRC_BURST_DST, /**< burst src to burst dst - Not supported for fixed source and destination address -*/ - IX_DMA_TRANSFER_WIDTH_INVALID /**< Invalid transfer width */ -} IxDmaTransferWidth; - -/** - * @ingroup IxDmaTypes - * @enum IxDmaNpeId - * @brief NpeId numbers to identify NPE A, B or C - */ -typedef enum -{ - IX_DMA_NPEID_NPEA = 0, /**< Identifies NPE A */ - IX_DMA_NPEID_NPEB, /**< Identifies NPE B */ - IX_DMA_NPEID_NPEC, /**< Identifies NPE C */ - IX_DMA_NPEID_MAX /**< Total Number of NPEs */ -} IxDmaNpeId; -/* @} */ -/** - * @defgroup IxDmaAcc IXP400 DMA Access Driver (IxDmaAcc) API - * - * @brief The public API for the IXP400 IxDmaAcc component - * - * @{ - */ - -/** - * @ingroup IxDmaAcc - * @brief DMA Request Id type - */ -typedef UINT32 IxDmaAccRequestId; - -/** - * @ingroup IxDmaAcc - * @def IX_DMA_REQUEST_FULL - * @brief DMA request queue is full - * This constant is a return value used to tell the user that the IxDmaAcc - * queue is full. - * - */ -#define IX_DMA_REQUEST_FULL 16 - -/** - * @ingroup IxDmaAcc - * @brief DMA completion notification - * This function is called to notify a client that the DMA has been completed - * @param status @ref IxDmaReturnStatus [out] - reporting to client - * - */ -typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccInit(IxNpeDlNpeId npeId) - * - * @brief Initialise the DMA Access component - * This function will initialise the DMA Access component internals - * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer - * @return @li IX_SUCCESS succesfully initialised the component - * @return @li IX_FAIL Initialisation failed for some unspecified - * internal reason. - */ -PUBLIC IX_STATUS -ixDmaAccInit(IxNpeDlNpeId npeId); - -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth) - * - * @brief Perform DMA transfer - * This function will perform DMA transfer between devices within the - * IXP400 memory map. - * @note The following are restrictions for IxDmaAccDmaTransfer: - * @li The function is non re-entrant. - * @li The function assumes host devices are operating in big-endian mode. - * @li Fixed address does not suport burst transfer width - * @li Fixed source address to fixed destinatiom address mode is not suported - * @li The incrementing source address for expansion bus will not support a burst transfer width and copy and clear mode - * - * @param callback @ref IxDmaAccDmaCompleteCallback [in] - function pointer to be stored and called when the DMA transfer is completed. This cannot be NULL. - * @param SourceAddr UINT32 [in] - Starting address of DMA source. Must be a valid IXP400 memory map address. - * @param DestinationAddr UINT32 [in] - Starting address of DMA destination. Must be a valid IXP400 memory map address. - * @param TransferLength UINT16 [in] - The size of DMA data transfer. The range must be from 1-64Kbyte - * @param TransferMode @ref IxDmaTransferMode [in] - The DMA transfer mode - * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode - * @param TransferWidth @ref IxDmaTransferWidth [in] - The DMA transfer width - * - * @return @li IX_DMA_SUCCESS Notification that the DMA request is succesful - * @return @li IX_DMA_FAIL IxDmaAcc not yet initialised or some internal error has occured - * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid - * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range - * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid - * @return @li IX_DMA_REQUEST_FIFO_FULL IxDmaAcc request queue is full - */ -PUBLIC IxDmaReturnStatus -ixDmaAccDmaTransfer( - IxDmaAccDmaCompleteCallback callback, - UINT32 SourceAddr, - UINT32 DestinationAddr, - UINT16 TransferLength, - IxDmaTransferMode TransferMode, - IxDmaAddressingMode AddressingMode, - IxDmaTransferWidth TransferWidth); -/** - * @ingroup IxDmaAcc - * - * @fn ixDmaAccShow(void) - * - * @brief Display some component information for debug purposes - * Show some internal operation information relating to the DMA service. - * At a minimum the following will show. - * - the number of the DMA pend (in queue) - * @param None - * @return @li None - */ -PUBLIC IX_STATUS -ixDmaAccShow(void); - -#endif /* IXDMAACC_H */ - diff --git a/drivers/net/npe/include/IxEthAcc.h b/drivers/net/npe/include/IxEthAcc.h deleted file mode 100644 index cc7e0106670..00000000000 --- a/drivers/net/npe/include/IxEthAcc.h +++ /dev/null @@ -1,2488 +0,0 @@ -/** @file IxEthAcc.h - * - * @brief this file contains the public API of @ref IxEthAcc component - * - * Design notes: - * The IX_OSAL_MBUF address is to be specified on bits [31-5] and must - * be cache aligned (bits[4-0] cleared) - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthAcc_H -#define IxEthAcc_H - -#include -#include - -/** - * @defgroup IxEthAcc IXP400 Ethernet Access (IxEthAcc) API - * - * @brief ethAcc is a library that does provides access to the internal IXP400 10/100Bt Ethernet MACs. - * - *@{ - */ - -/** - * @ingroup IxEthAcc - * @brief Definition of the Ethernet Access status - */ -typedef enum /* IxEthAccStatus */ -{ - IX_ETH_ACC_SUCCESS = IX_SUCCESS, /**< return success*/ - IX_ETH_ACC_FAIL = IX_FAIL, /**< return fail*/ - IX_ETH_ACC_INVALID_PORT, /**< return invalid port*/ - IX_ETH_ACC_PORT_UNINITIALIZED, /**< return uninitialized*/ - IX_ETH_ACC_MAC_UNINITIALIZED, /**< return MAC uninitialized*/ - IX_ETH_ACC_INVALID_ARG, /**< return invalid arg*/ - IX_ETH_TX_Q_FULL, /**< return tx queue is full*/ - IX_ETH_ACC_NO_SUCH_ADDR /**< return no such address*/ -} IxEthAccStatus; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccPortId - * @brief Definition of the IXP400 Mac Ethernet device. - */ -typedef enum -{ - IX_ETH_PORT_1 = 0, /**< Ethernet Port 1 */ - IX_ETH_PORT_2 = 1 /**< Ethernet port 2 */ - ,IX_ETH_PORT_3 = 2 /**< Ethernet port 3 */ -} IxEthAccPortId; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETH_ACC_NUMBER_OF_PORTS - * - * @brief Definition of the number of ports - * - */ -#ifdef __ixp46X -#define IX_ETH_ACC_NUMBER_OF_PORTS (3) -#else -#define IX_ETH_ACC_NUMBER_OF_PORTS (2) -#endif - -/** - * @ingroup IxEthAcc - * - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * - * @brief Definition of the size of the MAC address - * - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - - -/** - * - * @brief Definition of the IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * @note - * The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< MAC address */ -} IxEthAccMacAddr; - -/** - * @ingroup IxEthAcc - * @def IX_ETH_ACC_NUM_TX_PRIORITIES - * @brief Definition of the number of transmit priorities - * - */ -#define IX_ETH_ACC_NUM_TX_PRIORITIES (8) - -/** - * @ingroup IxEthAcc - * @enum IxEthAccTxPriority - * @brief Definition of the relative priority used to transmit a frame - * - */ -typedef enum -{ - IX_ETH_ACC_TX_PRIORITY_0 = 0, /** STA */ - IX_ETHACC_RX_APTYPE = 0x30 /**< 802.11, AP <=> AP */ -} IxEthAccRxFrameType; - -/** - * @ingroup IxEthAcc - * @enum IxEthAccDuplexMode - * @brief Definition to provision the duplex mode of the MAC. - * - */ -typedef enum -{ - IX_ETH_ACC_FULL_DUPLEX, /**< Full duplex operation of the MAC */ - IX_ETH_ACC_HALF_DUPLEX /**< Half duplex operation of the MAC */ -} IxEthAccDuplexMode; - - -/** - * @ingroup IxEthAcc - * @struct IxEthAccNe - * @brief Definition of service-specific informations. - * - * This structure defines the Ethernet service-specific informations - * and enable QoS and VLAN features. - */ -typedef struct -{ - UINT32 ixReserved_next; /**< reserved for chaining */ - UINT32 ixReserved_lengths; /**< reserved for buffer lengths */ - UINT32 ixReserved_data; /**< reserved for buffer pointer */ - UINT8 ixDestinationPortId; /**< Destination portId for this packet, if known by NPE */ - UINT8 ixSourcePortId; /**< Source portId for this packet */ - UINT16 ixFlags; /**< BitField of option for this frame */ - UINT8 ixQoS; /**< QoS class of the frame */ - UINT8 ixReserved; /**< reserved */ - UINT16 ixVlanTCI; /**< Vlan TCI */ - UINT8 ixDestMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Destination MAC address */ - UINT8 ixSourceMac[IX_IEEE803_MAC_ADDRESS_SIZE]; /**< Source MAC address */ -} IxEthAccNe; - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORT_UNKNOWN - * - * @brief Contents of the field @a IX_ETHACC_NE_DESTPORTID when no - * destination port can be found by the NPE for this frame. - * - */ -#define IX_ETHACC_NE_PORT_UNKNOWN (0xff) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTMAC - * - * @brief The location of the destination MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_DESTMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEMAC - * - * @brief The location of the source MAC address in the Mbuf header. - * - */ -#define IX_ETHACC_NE_SOURCEMAC(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourceMac - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANTCI - * - * @brief The VLAN Tag Control Information associated with this frame - * - * The VLAN Tag Control Information associated with this frame. On Rx - * path, this field is extracted from the packet header. - * On Tx path, the value of this field is inserted in the frame when - * the port is configured to insert or replace vlan tags in the - * egress frames. - * - * @sa IX_ETHACC_NE_FLAGS - */ -#define IX_ETHACC_NE_VLANTCI(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixVlanTCI - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_SOURCEPORTID - * - * @brief The port where this frame came from. - * - * The port where this frame came from. This field is set on receive - * with the port information. This field is ignored on Transmit path. - */ -#define IX_ETHACC_NE_SOURCEPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixSourcePortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_DESTPORTID - * - * @brief The destination port where this frame should be sent. - * - * The destination port where this frame should be sent. - * - * @li In the transmit direction, this field contains the destination port - * and is ignored unless @a IX_ETHACC_NE_FLAG_DST is set. - * - * @li In the receive direction, this field contains the port where the - * destination MAC addresses has been learned. If the destination - * MAC address is unknown, then this value is set to the reserved value - * @a IX_ETHACC_NE_PORT_UNKNOWN - * - */ -#define IX_ETHACC_NE_DESTPORTID(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixDestinationPortId - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_QOS - * - * @brief QualityOfService class (QoS) for this received frame. - * - */ -#define IX_ETHACC_NE_QOS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixQoS - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FLAGS - * - * @brief Bit Mask of the different flags associated with a frame - * - * The flags are the bit-oring combination - * of the following different fields : - * - * @li IP flag (Rx @a IX_ETHACC_NE_IPMASK) - * @li Spanning Tree flag (Rx @a IX_ETHACC_NE_STMASK) - * @li Link layer type (Rx and Tx @a IX_ETHACC_NE_LINKMASK) - * @li VLAN Tagged Frame (Rx @a IX_ETHACC_NE_VLANMASK) - * @li New source MAC address (Rx @a IX_ETHACC_NE_NEWSRCMASK) - * @li Multicast flag (Rx @a IX_ETHACC_NE_MCASTMASK) - * @li Broadcast flag (Rx @a IX_ETHACC_NE_BCASTMASK) - * @li Destination port flag (Tx @a IX_ETHACC_NE_PORTMASK) - * @li Tag/Untag Tx frame (Tx @a IX_ETHACC_NE_TAGMODEMASK) - * @li Overwrite destination port (Tx @a IX_ETHACC_NE_PORTOVERMASK) - * @li Filtered frame (Rx @a IX_ETHACC_NE_STMASK) - * @li VLAN Enabled (Rx and Tx @a IX_ETHACC_NE_VLANENABLEMASK) - */ -#define IX_ETHACC_NE_FLAGS(mBufPtr) ((IxEthAccNe *)&((mBufPtr)->ix_ne))->ixFlags - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_BCASTMASK - * - * @brief This mask defines if a received frame is a broadcast frame. - * - * This mask defines if a received frame is a broadcast frame. - * The BCAST flag is set when the destination MAC address of - * a frame is broadcast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_BCASTMASK (0x1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_MCASTMASK - * - * @brief This mask defines if a received frame is a multicast frame. - * - * This mask defines if a received frame is a multicast frame. - * The MCAST flag is set when the destination MAC address of - * a frame is multicast. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_MCASTMASK (0x1 << 1) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_IPMASK - * - * @brief This mask defines if a received frame is a IP frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS and defines if a received - * frame is a IP frame. The IP flag is set on Rx direction, depending on - * the frame contents. The flag is set when the length/type field of a - * received frame is 0x8000. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_IPMASK (0x1 << 2) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANMASK - * - * @brief This mask defines if a received frame is VLAN tagged. - * - * This mask defines if a received frame is VLAN tagged. - * When set, the Rx frame is VLAN-tagged and the tag value - * is available thru @a IX_ETHACC_NE_VLANID. - * Note that when sending frames which are already tagged - * this flag should be set, to avoid inserting another VLAN tag. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_VLANID - * - */ -#define IX_ETHACC_NE_VLANMASK (0x1 << 3) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_LINKMASK - * - * @brief This mask is the link layer protocol indicator - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * It reflects the state of a frame as it exits an NPE on the Rx path - * or enters an NPE on the Tx path. Its values are as follows: - * @li 0x00 - IEEE802.3 - 8802 (Rx) / IEEE802.3 - 8802 (Tx) - * @li 0x01 - IEEE802.3 - Ethernet (Rx) / IEEE802.3 - Ethernet (Tx) - * @li 0x02 - IEEE802.11 AP -> STA (Rx) / IEEE802.11 STA -> AP (Tx) - * @li 0x03 - IEEE802.11 AP -> AP (Rx) / IEEE802.11 AP->AP (Tx) - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_LINKMASK (0x3 << 4) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_STMASK - * - * @brief This mask defines if a received frame is a Spanning Tree frame. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * On rx direction, it defines if a received if frame is a Spanning Tree frame. - * Setting this fkag on transmit direction overrides the port settings - * regarding the VLAN options and - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_STMASK (0x1 << 6) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_FILTERMASK - * - * @brief This bit indicates whether a frame has been filtered by the Rx service. - * - * This mask applies to @a IX_ETHACC_NE_FLAGS. - * Certain frames, which should normally be fully filtered by the NPE to due - * the destination MAC address being on the same segment as the Rx port are - * still forwarded to the XScale (although the payload is invalid) in order - * to learn the MAC address of the transmitting station, if this is unknown. - * Normally EthAcc will filter and recycle these framess internally and no - * frames with the FILTER bit set will be received by the client. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_FILTERMASK (0x1 << 7) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_PORTMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, a frame - * is transmitted to the destination port as set by the macro - * @a IX_ETHACC_NE_DESTPORTID. If not set, the destination port - * is searched using the destination MAC address. - * - * @note This flag is meaningful only for multiport Network Engines. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_DESTPORTID - * - */ -#define IX_ETHACC_NE_PORTOVERMASK (0x1 << 8) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGMODEMASK - * - * @brief This mask defines the tagging rules to apply to a transmit frame. - * - * This mask defines the tagging rules to apply to a transmit frame - * regardless of the default setting for a port. When used together - * with @a IX_ETHACC_NE_TAGOVERMASK and when set, the - * frame will be tagged prior to transmission. When not set, - * the frame will be untagged prior to transmission. This is accomplished - * irrespective of the Egress tagging rules, constituting a per-frame override. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGOVERMASK - * - */ -#define IX_ETHACC_NE_TAGMODEMASK (0x1 << 9) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_TAGOVERMASK - * - * @brief This mask defines the rule to transmit a frame - * - * This mask defines the rule to transmit a frame. When set, the - * default transmit rules of a port are overriden. - * When not set, the default rules as set by @ref IxEthDB should apply. - * - * @sa IX_ETHACC_NE_FLAGS - * @sa IX_ETHACC_NE_TAGMODEMASK - * - */ -#define IX_ETHACC_NE_TAGOVERMASK (0x1 << 10) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_VLANENABLEMASK - * - * @brief This mask defines if a frame is a VLAN frame or not - * - * When set, frames undergo normal VLAN processing on the Tx path - * (membership filtering, tagging, tag removal etc). If this flag is - * not set, the frame is considered to be a regular non-VLAN frame - * and no VLAN processing will be performed. - * - * Note that VLAN-enabled NPE images will always set this flag in all - * Rx frames, and images which are not VLAN enabled will clear this - * flag for all received frames. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_VLANENABLEMASK (0x1 << 14) - -/** - * @ingroup IxEthAcc - * - * @def IX_ETHACC_NE_NEWSRCMASK - * - * @brief This mask defines if a received frame has been learned. - * - * This mask defines if the source MAC address of a frame is - * already known. If the bit is set, the source MAC address was - * unknown to the NPE at the time the frame was received. - * - * @sa IX_ETHACC_NE_FLAGS - * - */ -#define IX_ETHACC_NE_NEWSRCMASK (0x1 << 15) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the recommanded minimum size of MBUF's submitted - * to the frame receive service. - * - */ -#define IX_ETHACC_RX_MBUF_MIN_SIZE (2048) - -/** - * @ingroup IxEthAcc - * - * @brief This defines the highest MII address of any attached PHYs - * - * The maximum number for PHY address is 31, add on for range checking. - * - */ -#define IXP425_ETH_ACC_MII_MAX_ADDR 32 - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccInit(void) - * - * @brief Initializes the IXP400 Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per module initialization. - * @pre - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Service has failed to initialize. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccInit(void); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccUnload(void) - * - * @brief Unload the Ethernet Access Service. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @return void - * - *
- */ -PUBLIC void ixEthAccUnload(void); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortInit( IxEthAccPortId portId) - * - * @brief Initializes an NPE/Ethernet MAC Port. - * - * The NPE/Ethernet port initialisation includes the following steps - * @li Initialize the NPE/Ethernet MAC hardware. - * @li Verify NPE downloaded and operational. - * @li The NPE shall be available for usage once this API returns. - * @li Verify that the Ethernet port is present before initializing - * - * @li Reentrant - no - * @li ISR Callable - no - * - * This should be called once per mac device. - * The NPE/MAC shall be in disabled state after init. - * - * @pre - * The component must be initialized via @a ixEthAccInit - * The NPE must first be downloaded with the required microcode which supports all - * required features. - * - * Dependant on Services: (Must be initialized before using this service may be initialized) - * ixNPEmh - NPE Message handling service. - * ixQmgr - Queue Manager component. - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS: if the ethernet port is not present, a warning is issued. - * @li @a IX_ETH_ACC_FAIL : The NPE processor has failed to initialize. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortInit(IxEthAccPortId portId); - - -/************************************************************************* - - ##### ## ##### ## ##### ## ##### # # - # # # # # # # # # # # # # # - # # # # # # # # # # # # ###### - # # ###### # ###### ##### ###### # # # - # # # # # # # # # # # # # - ##### # # # # # # # # # # # - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority) - * - * @brief This function shall be used to submit MBUFs buffers for transmission on a particular MAC device. - * - * When the frame is transmitted, the buffer shall be returned thru the - * callback @a IxEthAccPortTxDoneCallback. - * - * In case of over-submitting, the order of the frames on the - * network may be modified. - * - * Buffers shall be not queued for transmission if the port is disabled. - * The port can be enabled using @a ixEthAccPortEnable - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @pre - * @a ixEthAccPortTxDoneCallbackRegister must be called to register a function to allow this service to - * return the buffer to the calling service. - * - * @note - * If the buffer submit fails for any reason the user has retained ownership of the buffer. - * - * @param portId @ref IxEthAccPortId [in] - MAC port ID to transmit Ethernet frame on. - * @param buffer @ref IX_OSAL_MBUF [in] - pointer to an MBUF formatted buffer. Chained buffers are supported for transmission. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is ignored. - * @param priority @ref IxEthAccTxPriority [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Failed to queue frame for transmission. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ - -PUBLIC IxEthAccStatus ixEthAccPortTxFrameSubmit( - IxEthAccPortId portId, - IX_OSAL_MBUF *buffer, - IxEthAccTxPriority priority); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Tx Buffer Done callback. Registered - * via @a ixEthAccTxBufferDoneCallbackRegister - * - * This function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or during the shutdown of - * the port prior to the transmission of a queued frame. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortTxDoneCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Tx mbuf descriptor. - * - * @return void - * - * @note - * The field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified by the access layer and reset to NULL. - * - *
- */ -typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *buffer ); - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the transmitted buffers to return to the user. - * - * This function registers the transmit buffer done function callback for a particular port. - * - * The registered callback function is called once the previously submitted buffer is no longer required by this service. - * It may be returned upon successful transmission of the frame or shutdown of port prior to submission. - * The calling of this registered function is not a guarantee of successful transmission of the buffer. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * The port must be initialized via @a ixEthAccPortInit - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param txCallbackFn @ref IxEthAccPortTxDoneCallback [in] - Function to be called to return transmit buffers to the user. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDoneCallbackRegister(IxEthAccPortId portId, - IxEthAccPortTxDoneCallback txCallbackFn, - UINT32 callbackTag); - - - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches frames to the user level - * via the provided function. The invocation shall be made for each - * frame dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag UINT32 [in] - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf @ref IX_OSAL_MBUF [in] - Pointer to the Rx mbuf header. Mbufs may be chained if - * the frame length is greater than the supplied mbuf length. - * @param reserved [in] - deprecated parameter The information is passed - * thru the IxEthAccNe header destination port ID field - * (@sa IX_ETHACC_NE_DESTPORTID). For backward - * compatibility,the value is equal to IX_ETH_DB_UNKNOWN_PORT (0xff). - * - * @return void - * - * @note - * Buffers may not be filled up to the length supplied in - * @a ixEthAccPortRxFreeReplenish(). The firmware fills - * them to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * The mbuf header contains the following modified field - * @li @a IX_OSAL_MBUF_PKT_LEN is set in the header of the first mbuf and indicates - * the total frame size - * @li @a IX_OSAL_MBUF_MLEN is set each mbuf header and indicates the payload length - * @li @a IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR contains a pointer to the next - * mbuf, or NULL at the end of a chain. - * @li @a IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR is modified. Its value is reset to NULL - * @li @a IX_OSAL_MBUF_FLAGS contains the bit 4 set for a broadcast packet and the bit 5 - * set for a multicast packet. Other bits are unmodified. - * - *
- */ -typedef void (*IxEthAccPortRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF *buffer, UINT32 reserved); - -/** - * @ingroup IxEthAcc - * - * @brief Function prototype for Ethernet Frame Rx callback. Registered via @a ixEthAccPortMultiBufferRxCallbackRegister - * - * It is the responsibility of the user function to free any MBUF's which it receives. - * - * @li Reentrant - yes , The user provided function should be reentrant. - * @li ISR Callable - yes , The user provided function must be callable from an ISR. - * @par - * - * This function dispatches many frames to the user level - * via the provided function. The invocation shall be made for multiple frames - * dequeued from the Ethernet QM queue. The user is required to free any MBUF's - * supplied via this callback. In addition the registered callback must free up MBUF's - * from the receive free queue when the port is disabled - * - * If called several times the latest callback shall be registered for a particular port. - * - * Calling Context : - * @par - * This callback is called in the context of the queue manager dispatch loop @a ixQmgrDispatcherLoopRun - * within the @ref IxQMgrAPI component. The calling context may be from interrupt or high priority thread. - * The decision is system specific. - * - * - * @param callbackTag - This tag is that provided when the callback was registered for a particular MAC - * via @a ixEthAccPortMultiBufferRxCallbackRegister. It allows the same callback to be used for multiple MACs. - * @param mbuf - Pointer to an array of Rx mbuf headers. Mbufs - * may be chained if - * the frame length is greater than the supplied mbuf length. - * The end of the array contains a zeroed entry (NULL pointer). - * - * @return void - * - * @note The mbufs passed to this callback have the same structure than the - * buffers passed to @a IxEthAccPortRxCallback interfac. - * - * @note The usage of this callback is exclusive with the usage of - * @a ixEthAccPortRxCallbackRegister and @a IxEthAccPortRxCallback - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ - -typedef void (*IxEthAccPortMultiBufferRxCallback) (UINT32 callbackTag, IX_OSAL_MBUF **buffer); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is received by this service. - * - * If called several times the latest callback shall be registered for a particular port. - * - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId @ref IxEthAccPortId [in] - Register callback for a particular MAC device. - * @param rxCallbackFn @ref IxEthAccPortRxCallback [in] - Function to be called when Ethernet frames are availble. - * @param callbackTag UINT32 [in] - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortRxCallback rxCallbackFn, - UINT32 callbackTag); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMultiBufferRxCallbackRegister( IxEthAccPortId portId, IxEthAccPortMultiBufferRxCallback rxCallbackFn, UINT32 callbackTag) - * - * @brief Register a callback function to allow - * the reception of frames. - * - * The registered callback function is called once a frame is - * received by this service. If many frames are already received, - * the function is called once. - * - * If called several times the latest callback shall be registered for a particular port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * - * @param portId - Register callback for a particular MAC device. - * @param rxCallbackFn - @a IxEthAccMultiBufferRxCallbackFn - Function to be called when Ethernet frames are availble. - * @param callbackTag - This tag shall be provided to the callback function. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * @li @a IX_ETH_ACC_INVALID_ARG : An argument other than portId is invalid. - * - * @sa ixEthAccPortMultiBufferRxCallbackRegister - * @sa IxEthAccPortMultiBufferRxCallback - * @sa ixEthAccPortRxCallbackRegister - * @sa IxEthAccPortRxCallback - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMultiBufferRxCallbackRegister(IxEthAccPortId portId, - IxEthAccPortMultiBufferRxCallback rxCallbackFn, - UINT32 callbackTag); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer) - * - * @brief This function provides buffers for the Ethernet receive path. - * - * This component does not have a buffer management mechanisms built in. All Rx buffers must be supplied to it - * via this interface. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @param portId @ref IxEthAccPortId [in] - Provide buffers only to specific Rx MAC. - * @param buffer @ref IX_OSAL_MBUF [in] - Provide an MBUF to the Ethernet receive mechanism. - * Buffers size smaller than IX_ETHACC_RX_MBUF_MIN_SIZE may result in poor - * performances and excessive buffer chaining. Buffers - * larger than this size may be suitable for jumbo frames. - * Chained packets are not supported and the field IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR must be NULL. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Buffer has was not able to queue the - * buffer in the receive service. - * @li @a IX_ETH_ACC_FAIL : Buffer size is less than IX_ETHACC_RX_MBUF_MIN_SIZE - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - * @note - * If the buffer replenish operation fails it is the responsibility - * of the user to free the buffer. - * - * @note - * Sufficient buffers must be supplied to the component to maintain - * receive throughput and avoid rx buffer underflow conditions. - * To meet this goal, It is expected that the user preload the - * component with a sufficent number of buffers prior to enabling the - * NPE Ethernet receive path. The recommended minimum number of - * buffers is 8. - * - * @note - * For maximum performances, the mbuf size should be greater - * than the maximum frame size (Ethernet header, payload and FCS) + 64. - * Supplying smaller mbufs to the service results in mbuf - * chaining and degraded performances. The recommended size - * is @a IX_ETHACC_RX_MBUF_MIN_SIZE, which is - * enough to take care of 802.3 frames and "baby jumbo" frames without - * chaining, and "jumbo" frame within chaining. - * - * @note - * Buffers may not be filled up to their length. The firware fills - * them up to the previous 64 bytes boundary. The user has to be aware - * that the length of the received mbufs may be smaller than the length - * of the supplied mbufs. - * - * @warning This function checks the parameters if the NDEBUG - * flag is not defined. Turning on the argument checking (disabled by - * default) results in a lower EthAcc performance as this function - * is part of the data path. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFreeReplenish( IxEthAccPortId portId, IX_OSAL_MBUF *buffer); - - - -/*************************************************************** - - #### #### # # ##### ##### #### # - # # # # ## # # # # # # # - # # # # # # # # # # # # - # # # # # # # ##### # # # - # # # # # ## # # # # # # - #### #### # # # # # #### ###### - - - ##### # ## # # ###### - # # # # # ## # # - # # # # # # # # ##### - ##### # ###### # # # # - # # # # # ## # - # ###### # # # # ###### - -***************************************************************/ - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnable(IxEthAccPortId portId) - * - * @brief This enables an Ethernet port for both Tx and Rx. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must first be initialized via @a ixEthAccPortInit and the MAC address - * must be set using @a ixEthAccUnicastMacAddressSet before enabling it - * The rx and Tx Done callbacks registration via @a - * ixEthAccPortTxDoneCallbackRegister amd @a ixEthAccPortRxCallbackRegister - * has to be done before enabling the traffic. - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDisable(IxEthAccPortId portId) - * - * @brief This disables an Ethernet port for both Tx and Rx. - * - * Free MBufs are returned to the user via the registered callback when the port is disabled - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre The port must be enabled with @a ixEthAccPortEnable, otherwise this - * function has no effect - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is not initialized - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled) - * - * @brief Get the enabled state of a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre The port must first be initialized via @a ixEthAccPortInit - * - * @param portId @ref IxEthAccPortId [in] - Port id to act upon. - * @param enabled BOOL [out] - location to store the state of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortEnabledQuery(IxEthAccPortId portId, BOOL *enabled); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId) - * - * @brief Put the Ethernet MAC device in non-promiscuous mode. - * - * In non-promiscuous mode the MAC filters all frames other than - * destination MAC address which matches the following criteria: - * @li Unicast address provisioned via @a ixEthAccUnicastMacAddressSet - * @li All broadcast frames. - * @li Multicast addresses provisioned via @a ixEthAccMulticastAddressJoin - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeSet - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClear(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId) - * - * @brief Put the MAC device in promiscuous mode. - * - * If the device is in promiscuous mode then all all received frames shall be forwared - * to the NPE for processing. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortPromiscuousModeClear - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSet(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressSet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Configure unicast MAC address for a particular port - * - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastMacAddressGet( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Get unicast MAC address for a particular MAC port - * - * @pre - * The MAC address must first be set via @a ixEthAccMacPromiscuousModeSet - * If the MAC address has not been set, the function returns a - * IX_ETH_ACC_MAC_UNINITIALIZED status - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [out] - Ethernet MAC address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_MAC_UNINITIALIZED : port MAC address is not initialized. - * @li @a IX_ETH_ACC_FAIL : macAddr is invalid. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortUnicastMacAddressGet(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - - - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoin( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Add a multicast address to the MAC address table. - * - * @note - * Due to the operation of the Ethernet MAC multicast filtering mechanism, frames which do not - * have a multicast destination address which were provisioned via this API may be forwarded - * to the NPE's. This is a result of the hardware comparison algorithm used in the destination mac address logic - * within the Ethernet MAC. - * - * See Also: IXP425 hardware development manual. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Error writing to the MAC registers - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoin(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressJoinAll( IxEthAccPortId portId) - * - * @brief Filter all frames with multicast dest. - * - * This function clears the MAC address table, and then sets - * the MAC to forward ALL multicast frames to the NPE. - * Specifically, it forwards all frames whose destination address - * has the LSB of the highest byte set (01:00:00:00:00:00). This - * bit is commonly referred to as the "multicast bit". - * Broadcast frames will still be forwarded. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressJoinAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeave( IxEthAccPortId portId, - IxEthAccMacAddr *macAddr) - * - * @brief Remove a multicast address from the MAC address table. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * @param *macAddr @ref IxEthAccMacAddr [in] - Ethernet Mac address. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_NO_SUCH_ADDR : Failed if MAC address was not in the table. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeave(IxEthAccPortId portId, - IxEthAccMacAddr *macAddr); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressLeaveAll( IxEthAccPortId portId) - * - * @brief This function unconfigures the multicast filtering settings - * - * This function first clears the MAC address table, and then sets - * the MAC as configured by the promiscuous mode current settings. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMulticastAddressLeaveAll(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortUnicastAddressShow(IxEthAccPortId portId) - * - * @brief Displays unicast MAC address - * - * Displays unicast address which is configured using - * @a ixEthAccUnicastMacAddressSet. This function also displays the MAC filter used - * to filter multicast frames. - * - * Other functions modify the MAC filtering - * - * @li @a ixEthAccPortMulticastAddressJoinAll() - all multicast - * frames are forwarded to the application - * @li @a ixEthAccPortMulticastAddressLeaveAll() - rollback the - * effects of @a ixEthAccPortMulticastAddressJoinAll() - * @li @a ixEthAccPortMulticastAddressLeave() - unprovision a new - * filtering address - * @li @a ixEthAccPortMulticastAddressJoin() - provision a new - * filtering address - * @li @a ixEthAccPortPromiscuousModeSet() - all frames are - * forwarded to the application regardless of the multicast - * address provisioned - * @li @a ixEthAccPortPromiscuousModeClear() - frames are forwarded - * to the application following the multicast address provisioned - * - * In all cases, unicast and broadcast addresses are forwarded to - * the application. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShow(IxEthAccPortId portId); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortMulticastAddressShow( IxEthAccPortId portId) - * - * @brief Displays multicast MAC address - * - * Displays multicast address which have been configured using @a ixEthAccMulticastAddressJoin - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - Ethernet port id. - * - * @return void - * - *
- */ -PUBLIC void ixEthAccPortMulticastAddressShow( IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeSet( IxEthAccPortId portId, IxEthAccDuplexMode mode ) - * - * @brief Set the duplex mode for the MAC. - * - * Configure the IXP400 MAC to either full or half duplex. - * - * @note - * The configuration should match that provisioned on the PHY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param mode @ref IxEthAccDuplexMode [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeSet(IxEthAccPortId portId,IxEthAccDuplexMode mode); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortDuplexModeGet( IxEthAccPortId portId, IxEthAccDuplexMode *mode ) - * - * @brief Get the duplex mode for the MAC. - * - * return the duplex configuration of the IXP400 MAC. - * - * @note - * The configuration should match that provisioned on the PHY. - * See @a ixEthAccDuplexModeSet - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * @param *mode @ref IxEthAccDuplexMode [out] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- * - */ -PUBLIC IxEthAccStatus -ixEthAccPortDuplexModeGet(IxEthAccPortId portId,IxEthAccDuplexMode *mode ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingEnable( IxEthAccPortId portId) - * - * @brief Enable padding bytes to be appended to runt frames submitted to - * this port - * - * Enable up to 60 null-bytes padding bytes to be appended to runt frames - * submitted to this port. This is the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @note When Tx padding is enabled, Tx FCS generation is turned on - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendFCSDusable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendPaddingDisable( IxEthAccPortId portId) - * - * @brief Disable padding bytes to be appended to runt frames submitted to - * this port - * - * Disable padding bytes to be appended to runt frames - * submitted to this port. This is not the default behavior of the access - * component. - * - * @warning Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendPaddingDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Enable the appending of Ethernet FCS to all frames submitted to this port - * - * When enabled, the FCS is added to the submitted frames. This is the default - * behavior of the access component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortTxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Disable the appending of Ethernet FCS to all frames submitted to this port. - * - * When disabled, the Ethernet FCS is not added to the submitted frames. - * This is not the default - * behavior of the access component. - * - * @note Since the FCS is not appended to the frame it is expected that the frame submitted to the - * component includes a valid FCS at the end of the data, although this will not be validated. - * - * The component shall forward the frame to the Ethernet MAC WITHOUT modification. - * - * Do not change this behaviour while the port is enabled. - * - * @note Tx FCS append is not disabled while Tx padding is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @sa ixEthAccPortTxFrameAppendPaddingEnable - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxFrameAppendFCSDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSEnable( IxEthAccPortId portId) - * - * @brief Forward frames with FCS included in the receive buffer. - * - * The FCS is not striped from the receive buffer. - * The received frame length includes the FCS size (4 bytes). ie. - * A minimum sized ethernet frame shall have a length of 64bytes. - * - * Frame FCS validity checks are still carried out on all received frames. - * - * This is not the default - * behavior of the access component. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccPortRxFrameAppendFCSDisable( IxEthAccPortId portId) - * - * @brief Do not forward the FCS portion of the received Ethernet frame to the user. - * The FCS is striped from the receive buffer. - * The received frame length does not include the FCS size (4 bytes). - * Frame FCS validity checks are still carried out on all received frames. - * - * This is the default behavior of the component. - * Do not change this behaviour while the port is enabled. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxFrameAppendFCSDisable(IxEthAccPortId portId); - - - - -/** - * @ingroup IxEthAcc - * - * @enum IxEthAccSchedulerDiscipline - * - * @brief Definition for the port scheduling discipline - * - * Select the port scheduling discipline on receive and transmit path - * @li FIFO : No Priority : In this configuration all frames are processed - * in the access component in the strict order in which - * the component received them. - * @li FIFO : Priority : This shall be a very simple priority mechanism. - * Higher prior-ity frames shall be forwarded - * before lower priority frames. There shall be no - * fairness mechanisms applied across different - * priorities. Higher priority frames could starve - * lower priority frames indefinitely. - */ -typedef enum -{ - FIFO_NO_PRIORITY, /** - */ -PUBLIC IxEthAccStatus -ixEthAccTxSchedulingDisciplineSet(IxEthAccPortId portId, - IxEthAccSchedulerDiscipline sched); - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched) - * - * @brief Set the Rx scheduling to one of @a IxEthAccSchedulerDiscipline - * - * The default behavior of the component is @a FIFO_NO_PRIORITY. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param sched : @a IxEthAccSchedulerDiscipline - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Set appropriate discipline. - * @li @a IX_ETH_ACC_FAIL : Invalid/unsupported discipline. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccRxSchedulingDisciplineSet(IxEthAccSchedulerDiscipline sched); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccNpeLoopbackEnable(IxEthAccPortId portId) - * - * @brief Enable NPE loopback - * - * When this loopback mode is enabled all the transmitted frames are - * received on the same port, without payload. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId : ID of the port - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback mode enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId) - * - * @brief Disable NPE loopback - * - * This function is used to disable the NPE loopback if previously - * enabled using ixEthAccNpeLoopbackEnable. - * - * This function is recommended for power-up diagnostic checks and - * should never be used under normal Ethernet traffic operations. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : NPE loopback successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortNpeLoopbackDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxEnable(IxEthAccPortId portId) - * - * @brief Enable Tx on the port - * - * This function is the complement of ixEthAccPortTxDisable and should - * be used only after Tx was disabled. A MAC core reset is required before - * this function is called (see @a ixEthAccPortMacReset). - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortTxDisable(IxEthAccPortId portId) - * - * @brief Disable Tx on the port - * - * This function can be used to disable Tx in the MAC core. - * Tx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortTxEnable. - * Note that using this function is not recommended, except for shutting - * down Tx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Tx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortTxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxEnable(IxEthAccPortId portId) - * - * @brief Enable Rx on the port - * - * This function is the complement of ixEthAccPortRxDisable and should - * be used only after Rx was disabled. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @pre - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully enabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxEnable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortRxDisable(IxEthAccPortId portId) - * - * @brief Disable Rx on the port - * - * This function can be used to disable Rx in the MAC core. - * Rx can be re-enabled, although this is not guaranteed, by performing - * a MAC core reset (@a ixEthAccPortMacReset) and calling ixEthAccPortRxEnable. - * Note that using this function is not recommended, except for shutting - * down Rx for emergency reasons. For proper port shutdown and re-enabling - * see ixEthAccPortEnable and ixEthAccPortDisable. - * - * This function is the recommended usage scenario for emergency security - * shutdown and hardware failure recovery and should never be used for throttling - * traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : Rx successfully disabled - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortRxDisable(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn IxEthAccStatus ixEthAccPortMacReset(IxEthAccPortId portId) - * - * @brief Reset MAC core on the port - * - * This function will perform a MAC core reset (NPE Ethernet coprocessor). - * This function is inherently unsafe and the NPE recovery is not guaranteed - * after this function is called. The proper manner of performing port disable - * and enable (which will reset the MAC as well) is ixEthAccPortEnable/ixEthAccPortDisable. - * - * This function is the recommended usage scenario for hardware failure recovery - * and should never be used for throttling traffic. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @note Calling ixEthAccPortDisable followed by ixEthAccPortEnable is - * guaranteed to restore correct Ethernet Tx/Rx operation. - * - * @param portId : ID of the port - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS : MAC core reset - * @li @a IX_ETH_ACC_FAIL : Invalid port or Ethernet service not initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccPortMacReset(IxEthAccPortId portId); - -/********************************************************************************* - #### ##### ## ##### # #### ##### # #### #### - # # # # # # # # # # # # - #### # # # # # #### # # # #### - # # ###### # # # # # # # - # # # # # # # # # # # # # # # - #### # # # # # #### # # #### #### -**********************************************************************************/ - - -/** - * - * @brief This struct defines the statistics returned by this component. - * - * The component returns MIB2 EthObj variables which are obtained from the - * hardware or maintained by this component. - * - * - */ -typedef struct -{ - UINT32 dot3StatsAlignmentErrors; /**< link error count (rx) */ - UINT32 dot3StatsFCSErrors; /**< link error count (rx) */ - UINT32 dot3StatsInternalMacReceiveErrors; /**< link error count (rx) */ - UINT32 RxOverrunDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxLearnedEntryDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxLargeFramesDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxSTPBlockedDiscards; /**< NPE: discarded frames count(rx) */ - UINT32 RxVLANTypeFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxVLANIdFilterDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxInvalidSourceDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxBlackListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxWhiteListDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 RxUnderflowEntryDiscards; /**< NPE: discarded frames count (rx) */ - UINT32 dot3StatsSingleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsMultipleCollisionFrames; /**< link error count (tx) */ - UINT32 dot3StatsDeferredTransmissions; /**< link error count (tx) */ - UINT32 dot3StatsLateCollisions; /**< link error count (tx) */ - UINT32 dot3StatsExcessiveCollsions; /**< link error count (tx) */ - UINT32 dot3StatsInternalMacTransmitErrors; /**< link error count (tx) */ - UINT32 dot3StatsCarrierSenseErrors; /**< link error count (tx) */ - UINT32 TxLargeFrameDiscards; /**< NPE: discarded frames count (tx) */ - UINT32 TxVLANIdFilterDiscards; /**< NPE: discarded frames count (tx) */ - -}IxEthEthObjStats; - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGet(IxEthAccPortId portId ,IxEthEthObjStats *retStats ) - * - * @brief Returns the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStat - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGet(IxEthAccPortId portId, IxEthEthObjStats *retStats ); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats) - * - * @brief Returns and clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - yes - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * @param retStats @ref IxEthEthObjStats [out] - * @note Please note the user is responsible for cache coheriency of the retStats - * buffer. The data is actually populated via the NPE's. As such cache safe - * memory should be used in the retStats argument. - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMibIIStatsGetClear(IxEthAccPortId portId, IxEthEthObjStats *retStats); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMibIIStatsClear(IxEthAccPortId portId) - * - * @brief Clears the statistics maintained for a port. - * - * @li Reentrant - yes - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : Invalid arguments. - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * @li @a IX_ETH_ACC_PORT_UNINITIALIZED : portId is un-initialized - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMibIIStatsClear(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMacInit(IxEthAccPortId portId) - * - * @brief Initializes the ethernet MAC settings - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @param portId @ref IxEthAccPortId [in] - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_INVALID_PORT : portId is invalid. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMacInit(IxEthAccPortId portId); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccStatsShow(IxEthAccPortId portId) - * - * - * @brief Displays a ports statistics on the standard io console using printf. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param portId @ref IxEthAccPortId [in] - * - * @return void - * - *
- */ -PUBLIC void ixEthAccStatsShow(IxEthAccPortId portId); - -/************************************************************************* - - # # # # # # ##### # #### - ## ## # # ## ## # # # # # - # ## # # # # ## # # # # # # - # # # # # # # # # # # - # # # # # # # # # # # - # # # # # # ##### # #### - -*************************************************************************/ - - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiReadRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 *value) - * - * - * @brief Reads a 16 bit value from a PHY - * - * Reads a 16-bit word from a register of a MII-compliant PHY. Reading - * is performed through the MII management interface. This function returns - * when the read operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to read (0-31) - * @param value UINT16 [in] - the value read from the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to read the register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiReadRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 *value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiWriteRtn (UINT8 phyAddr, - UINT8 phyReg, - UINT16 value) - * - * - * @brief Writes a 16 bit value to a PHY - * - * Writes a 16-bit word from a register of a MII-compliant PHY. Writing - * is performed through the MII management interface. This function returns - * when the write operation has successfully completed, or when a timeout has elapsed. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT8 [in] - the address of the Ethernet PHY (0-31) - * @param phyReg UINT8 [in] - the number of the MII register to write (0-31) - * @param value UINT16 [out] - the value to write to the register - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : failed to write register. - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiWriteRtn (UINT8 phyAddr, UINT8 phyReg, UINT16 value); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiAccessTimeoutSet(UINT32 timeout) - * - * @brief Overrides the default timeout value and retry count when reading or - * writing MII registers using ixEthAccMiiWriteRtn or ixEthAccMiiReadRtn - * - * The default behavior of the component is to use a IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS ms - * timeout (declared as 100 in IxEthAccMii_p.h) and a retry count of IX_ETH_ACC_MII_TIMEOUT_10TH_SECS - * (declared as 5 in IxEthAccMii_p.h). - * - * The MII read and write functions will attempt to read the status of the register up - * to the retry count times, delaying between each attempt with the timeout value. - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre - * - * @param timeout UINT32 [in] - new timeout value, in milliseconds - * @param timeout UINT32 [in] - new retry count (a minimum value of 1 must be used) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid parameter(s) - * - *
- */ -PUBLIC IxEthAccStatus -ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount); - -/** - * @ingroup IxEthAcc - * - * @fn ixEthAccMiiStatsShow (UINT32 phyAddr) - * - * - * @brief Displays detailed information on a specified PHY - * - * Displays the current values of the first eigth MII registers for a PHY, - * - * @li Reentrant - no - * @li ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and - * generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IxEthAccStatus - * @li @a IX_ETH_ACC_SUCCESS - * @li @a IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IxEthAccStatus ixEthAccMiiStatsShow (UINT32 phyAddr); - - - -/******* BOARD SPECIFIC DEPRECATED API *********/ - -/* The following functions are high level functions which rely - * on the properties and interface of some Ethernet PHYs. The - * implementation is hardware specific and has been moved to - * the hardware-specific component IxEthMii. - */ - - #include "IxEthMii.h" - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyScan - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyScan - * - * @note this feature is board specific - * - */ -#define ixEthAccMiiPhyScan(phyPresent) ixEthMiiPhyScan(phyPresent,IXP425_ETH_ACC_MII_MAX_ADDR) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyConfig - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyConfig - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) \ - ixEthMiiPhyConfig(phyAddr,speed100,fullDuplex,autonegotiate) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiPhyReset - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyReset - * - * @note this feature is board specific - */ -#define ixEthAccMiiPhyReset(phyAddr) \ - ixEthMiiPhyReset(phyAddr) - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiLinkStatus - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiLinkStatus - * - * @note this feature is board specific - */ -#define ixEthAccMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) \ - ixEthMiiLinkStatus(phyAddr,linkUp,speed100,fullDuplex,autoneg) - - - -/** - * @ingroup IxEthAcc - * - * @def ixEthAccMiiShow - * - * @brief : deprecated API entry point. This definition - * ensures backward compatibility - * - * See @ref ixEthMiiPhyShow - * - * @note this feature is board specific - */ -#define ixEthAccMiiShow(phyAddr) \ - ixEthMiiPhyShow(phyAddr) - -#endif /* ndef IxEthAcc_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthAccDataPlane_p.h b/drivers/net/npe/include/IxEthAccDataPlane_p.h deleted file mode 100644 index dce43d9a197..00000000000 --- a/drivers/net/npe/include/IxEthAccDataPlane_p.h +++ /dev/null @@ -1,221 +0,0 @@ -/** - * @file IxEthAccDataPlane_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - - - -#ifndef IxEthAccDataPlane_p_H -#define IxEthAccDataPlane_p_H - -#include -#include - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* typedefs global to this file*/ - -typedef struct -{ - IX_OSAL_MBUF *pHead; - IX_OSAL_MBUF *pTail; -}IxEthAccDataPlaneQList; - - -/** - * @struct IxEthAccDataPlaneStats - * @brief Statistics data structure associated with the data plane - * - */ -typedef struct -{ - UINT32 addToSwQ; - UINT32 removeFromSwQ; - UINT32 unchainedTxMBufs; - UINT32 chainedTxMBufs; - UINT32 unchainedTxDoneMBufs; - UINT32 chainedTxDoneMBufs; - UINT32 unchainedRxMBufs; - UINT32 chainedRxMBufs; - UINT32 unchainedRxFreeMBufs; - UINT32 chainedRxFreeMBufs; - UINT32 rxCallbackCounter; - UINT32 rxCallbackBurstRead; - UINT32 txDoneCallbackCounter; - UINT32 unexpectedError; -} IxEthAccDataPlaneStats; - -/** - * @fn ixEthAccMbufFromSwQ - * @brief used during disable steps to convert mbufs from - * swq format, ready to be pushed into hw queues for NPE, - * back into XScale format - */ -IX_OSAL_MBUF *ixEthAccMbufFromSwQ(IX_OSAL_MBUF *mbuf); - -/** - * @fn ixEthAccDataPlaneShow - * @brief Show function (for data plane statistics - */ -void ixEthAccDataPlaneShow(void); - -/* - * lock dataplane when atomic operation is required - */ -#define IX_ETH_ACC_DATA_PLANE_LOCK(arg) arg = ixOsalIrqLock(); -#define IX_ETH_ACC_DATA_PLANE_UNLOCK(arg) ixOsalIrqUnlock(arg); - -/* - * Use MBUF fields - */ -#define IX_ETHACC_NE_SHARED(mBufPtr) \ - ((IxEthAccNe *)&((mBufPtr)->ix_ne)) - -#if 1 - -#define IX_ETHACC_NE_NEXT(mBufPtr) (mBufPtr)->ix_ne.reserved[0] - -/* tm - wrong!! len and pkt_len are in the second word - #define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[3] */ -#define IX_ETHACC_NE_LEN(mBufPtr) (mBufPtr)->ix_ne.reserved[1] - -#define IX_ETHACC_NE_DATA(mBufPtr)(mBufPtr)->ix_ne.reserved[2] - -#else - -#define IX_ETHACC_NE_NEXT(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_next - -#define IX_ETHACC_NE_LEN(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_lengths - -#define IX_ETHACC_NE_DATA(mBufPtr) \ - IX_ETHACC_NE_SHARED(mBufPtr)->ixReserved_data -#endif - -/* - * Use MBUF next pointer field to chain data. - */ -#define IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER(mbuf) (mbuf)->ix_ctrl.ix_chain - - - -#define IX_ETH_ACC_DATAPLANE_IS_Q_EMPTY(mbuf_list) ((mbuf_list.pHead) == NULL) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_HEAD(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add))) = (mbuf_list.pHead);\ - (mbuf_list.pHead) = (mbuf_to_add); \ - } \ - else { \ - (mbuf_list.pTail) = (mbuf_list.pHead) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while(0) - - -#define IX_ETH_ACC_DATAPLANE_ADD_MBUF_TO_Q_TAIL(mbuf_list,mbuf_to_add) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.addToSwQ); \ - if ( (mbuf_list.pHead) == NULL ) \ - { \ - (mbuf_list.pHead) = mbuf_to_add; \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - else { \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_list.pTail)) = (mbuf_to_add); \ - IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_add)) = NULL; \ - } \ - (mbuf_list.pTail) = mbuf_to_add; \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -#define IX_ETH_ACC_DATAPLANE_REMOVE_MBUF_FROM_Q_HEAD(mbuf_list,mbuf_to_rem) \ - do { \ - int lockVal; \ - IX_ETH_ACC_DATA_PLANE_LOCK(lockVal); \ - if ( (mbuf_list.pHead) != NULL ) \ - { \ - IX_ETH_ACC_STATS_INC(ixEthAccDataStats.removeFromSwQ); \ - (mbuf_to_rem) = (mbuf_list.pHead) ; \ - (mbuf_list.pHead) = (IX_ETH_ACC_MBUF_NEXT_PKT_CHAIN_MEMBER((mbuf_to_rem)));\ - } \ - else { \ - (mbuf_to_rem) = NULL; \ - } \ - IX_ETH_ACC_DATA_PLANE_UNLOCK(lockVal); \ - } while (0) - - -/** - * @brief message handler QManager entries for NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_ACC_PORT_TO_NPE_ID(port) \ - ixEthAccPortData[(port)].npeId - -#define IX_ETH_ACC_NPE_TO_PORT_ID(npe) ((npe == 0 ? 2 : (npe == 1 ? 0 : ( npe == 2 ? 1 : -1 )))) - -#define IX_ETH_ACC_PORT_TO_TX_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccTxData.txQueue - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_ID(port) \ - ixEthAccPortData[(port)].ixEthAccRxData.rxFreeQueue - -#define IX_ETH_ACC_PORT_TO_TX_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE : IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE)) - -#define IX_ETH_ACC_PORT_TO_RX_FREE_Q_SOURCE(port) (port == IX_ETH_PORT_1 ? IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE : (port == IX_ETH_PORT_2 ? IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE : IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE )) - -/* Flush the mbufs chain and all data pointed to by the mbuf */ - -#ifndef NDEBUG -#define IX_ETH_ACC_STATS_INC(x) (x++) -#else -#define IX_ETH_ACC_STATS_INC(x) -#endif - -#define IX_ETH_ACC_MAX_TX_FRAMES_TO_SUBMIT 128 - -void ixEthRxFrameQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthRxMultiBufferQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); -void ixEthTxFrameDoneQMCallback(IxQMgrQId qId, IxQMgrCallbackId callbackId); - -#endif /* IxEthAccDataPlane_p_H */ - - -/** - *@} - */ - diff --git a/drivers/net/npe/include/IxEthAccMac_p.h b/drivers/net/npe/include/IxEthAccMac_p.h deleted file mode 100644 index 4eafab25857..00000000000 --- a/drivers/net/npe/include/IxEthAccMac_p.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - - -#ifndef IxEthAccMac_p_H -#define IxEthAccMac_p_H - -#include "IxOsal.h" - -#define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256 -#define IX_ETH_ACC_NUM_PORTS 3 -#define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536 -#define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64) -#define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64 - -/* - * - * MAC register definitions - * - */ -#define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE -#define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE -#define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE - -#define IX_ETH_ACC_MAC_TX_CNTRL1 0x000 -#define IX_ETH_ACC_MAC_TX_CNTRL2 0x004 -#define IX_ETH_ACC_MAC_RX_CNTRL1 0x010 -#define IX_ETH_ACC_MAC_RX_CNTRL2 0x014 -#define IX_ETH_ACC_MAC_RANDOM_SEED 0x020 -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030 -#define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038 -#define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040 -#define IX_ETH_ACC_MAC_TX_DEFER 0x050 -#define IX_ETH_ACC_MAC_RX_DEFER 0x054 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064 -#define IX_ETH_ACC_MAC_SLOT_TIME 0x070 -#define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080 -#define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084 -#define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088 -#define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c -#define IX_ETH_ACC_MAC_MDIO_STS_1 0x090 -#define IX_ETH_ACC_MAC_MDIO_STS_2 0x094 -#define IX_ETH_ACC_MAC_MDIO_STS_3 0x098 -#define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c -#define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0 -#define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4 -#define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8 -#define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC -#define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0 -#define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4 -#define IX_ETH_ACC_MAC_ADDR_1 0x0C0 -#define IX_ETH_ACC_MAC_ADDR_2 0x0C4 -#define IX_ETH_ACC_MAC_ADDR_3 0x0C8 -#define IX_ETH_ACC_MAC_ADDR_4 0x0CC -#define IX_ETH_ACC_MAC_ADDR_5 0x0D0 -#define IX_ETH_ACC_MAC_ADDR_6 0x0D4 -#define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0 -#define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0 -#define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4 -#define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8 -#define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC -#define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100 -#define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104 -#define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC - - -/* - * - *Bit definitions - * - */ - -/* TX Control Register 1*/ - -#define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0) -#define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1) -#define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2) -#define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3) -#define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4) -#define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5) -#define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6) - -/* TX Control Register 2 */ -#define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf - -/* RX Control Register 1 */ -#define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0) -#define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1) -#define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2) -#define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3) -#define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4) -#define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5) -#define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6) -#define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7) - -/* RX Control Register 2 */ -#define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0) - - - -/* Core Control Register */ -#define IX_ETH_ACC_CORE_RESET BIT(0) -#define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1) -#define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2) -#define IX_ETH_ACC_CORE_SEND_JAM BIT(3) -#define IX_ETH_ACC_CORE_MDC_EN BIT(4) - -/* 1st bit of 1st MAC octet */ -#define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) - - -/* - * - * Default values - * - */ - - -#define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \ - IX_ETH_ACC_TX_CNTRL1_RETRY | \ - IX_ETH_ACC_TX_CNTRL1_FCS_EN | \ - IX_ETH_ACC_TX_CNTRL1_2DEFER | \ - IX_ETH_ACC_TX_CNTRL1_PAD_EN) - -#define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f - -#define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \ - | IX_ETH_ACC_RX_CNTRL1_RX_EN) - -#define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0 - -/* Thresholds determined by NPE firmware FS */ -#define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12 -#define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30 - -/* Number of bytes that must be in the tx fifo before - transmission commences*/ -#define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8 - -/* One-part deferral values */ -#define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15 -#define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16 - -/* Two-part deferral values... */ -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08 -#define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07 - -/* This value applies to MII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80 - -/* This value applies to RMII */ -#define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF - -#define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1 -/*The following is a value chosen at random*/ -#define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8 - -/*By default we must configure the MAC to generate the - MDC clock*/ -#define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN) - -#define IXP425_ETH_ACC_MAX_PHY 2 -#define IXP425_ETH_ACC_MAX_AN_ENTRIES 20 -#define IX_ETH_ACC_MAC_RESET_DELAY 1 - -#define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF - -#define IX_ETH_ACC_MAC_MSGID_SHL 24 - -#define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20 -#define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */ -#define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3 -#define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ - -/*Register access macros*/ -#if (CPU == SIMSPARCSOLARIS) -extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val); -extern UINT32 registerReadStub (UINT32 base, UINT32 offset); - -#define REG_WRITE(b,o,v) registerWriteStub(b, o, v) -#define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0) -#else -#define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v) -#define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o))) - -#endif - -void ixEthAccMacUnload(void); -IxEthAccStatus ixEthAccMacMemInit(void); - -/* MAC core loopback */ -IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId); - -/* MAC core traffic control */ -IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId); - -/* NPE software loopback */ -IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId); -IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId); - -#endif /*IxEthAccMac_p_H*/ - diff --git a/drivers/net/npe/include/IxEthAccMii_p.h b/drivers/net/npe/include/IxEthAccMii_p.h deleted file mode 100644 index aff30f00aff..00000000000 --- a/drivers/net/npe/include/IxEthAccMii_p.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file IxEthAccMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccMii_p_H -#define IxEthAccMii_p_H - -/* MII definitions - these have been verified against the LXT971 and LXT972 PHYs*/ - -#define IXP425_ETH_ACC_MII_MAX_REG 32 /* max register per phy */ - -#define IX_ETH_ACC_MII_REG_SHL 16 -#define IX_ETH_ACC_MII_ADDR_SHL 21 - -/* Definitions for MII access routines*/ - -#define IX_ETH_ACC_MII_GO BIT(31) -#define IX_ETH_ACC_MII_WRITE BIT(26) -#define IX_ETH_ACC_MII_TIMEOUT_10TH_SECS 5 -#define IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS 100 -#define IX_ETH_ACC_MII_READ_FAIL BIT(31) - -#define IX_ETH_ACC_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */ -#define IX_ETH_ACC_MII_PHY_NO_DELAY 0x0 /* do not delay */ -#define IX_ETH_ACC_MII_PHY_NULL 0xff /* PHY is not present */ -#define IX_ETH_ACC_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */ - -#ifndef IX_ETH_ACC_MII_MONITOR_DELAY -# define IX_ETH_ACC_MII_MONITOR_DELAY 0x5 /* in seconds */ -#endif - -/* Register definition */ - -#define IX_ETH_ACC_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_ACC_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_ACC_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_ACC_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_ACC_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_ACC_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_ACC_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_ACC_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -IxEthAccStatus ixEthAccMdioShow (void); -IxEthAccStatus ixEthAccMiiInit(void); -void ixEthAccMiiUnload(void); - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthAccQueueAssign_p.h b/drivers/net/npe/include/IxEthAccQueueAssign_p.h deleted file mode 100644 index 65661a0dd5d..00000000000 --- a/drivers/net/npe/include/IxEthAccQueueAssign_p.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file IxEthAccQueueAssign_p.h - * - * @author Intel Corporation - * @date 06-Mar-2002 - * - * @brief Mapping from QMgr Q's to internal assignment - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxQMgr.h" -#include "IxQueueAssignments.h" - -/* Check range of Q's assigned to this component. */ -#if IX_ETH_ACC_RX_FRAME_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID ) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET0_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_ENET1_Q >= (IX_QMGR_MIN_QUEUPP_QID) | \ - IX_ETH_ACC_TX_FRAME_DONE_ETH_Q >= (IX_QMGR_MIN_QUEUPP_QID) -#error "Not all Ethernet Access Queues are betweem 1-31, requires full functionalty Q's unless otherwise validated " -#endif - -/** -* -* @typedef IxEthAccQregInfo -* -* @brief -* -*/ -typedef struct -{ - IxQMgrQId qId; - char *qName; - IxQMgrCallback qCallback; - IxQMgrCallbackId callbackTag; - IxQMgrQSizeInWords qSize; - IxQMgrQEntrySizeInWords qWords; - BOOL qNotificationEnableAtStartup; - IxQMgrSourceId qConditionSource; - IxQMgrWMLevel AlmostEmptyThreshold; - IxQMgrWMLevel AlmostFullThreshold; - -} IxEthAccQregInfo; - -/* - * Prototypes for all QM callbacks. - */ - -/* - * Rx Callbacks - */ -IX_ETH_ACC_PUBLIC -void ixEthRxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxMultiBufferQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthRxFreeQMCallback(IxQMgrQId, IxQMgrCallbackId); - -/* - * Tx Callback. - */ -IX_ETH_ACC_PUBLIC -void ixEthTxFrameQMCallback(IxQMgrQId, IxQMgrCallbackId); - -IX_ETH_ACC_PUBLIC -void ixEthTxFrameDoneQMCallback(IxQMgrQId, IxQMgrCallbackId ); - - -#define IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY (IX_QMGR_Q_PRIORITY_0) /* Highest priority */ - -/* - * Queue watermarks - */ -#define IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_E ) -#define IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE (IX_QMGR_Q_SOURCE_ID_NOT_E ) diff --git a/drivers/net/npe/include/IxEthAcc_p.h b/drivers/net/npe/include/IxEthAcc_p.h deleted file mode 100644 index 1348f4e3c85..00000000000 --- a/drivers/net/npe/include/IxEthAcc_p.h +++ /dev/null @@ -1,301 +0,0 @@ -/** - * @file IxEthAcc_p.h - * - * @author Intel Corporation - * @date 12-Feb-2002 - * - * @brief Internal Header file for IXP425 Ethernet Access component. - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @addtogroup IxEthAccPri - *@{ - */ - -#ifndef IxEthAcc_p_H -#define IxEthAcc_p_H - -/* - * Os/System dependancies. - */ -#include "IxOsal.h" - -/* - * Intermodule dependancies - */ -#include "IxNpeDl.h" -#include "IxQMgr.h" - -#include "IxEthNpe.h" - -/* - * Intra module dependancies - */ - -#include "IxEthAccDataPlane_p.h" -#include "IxEthAccMac_p.h" - - -#define INLINE __inline__ - -#ifdef NDEBUG - -#define IX_ETH_ACC_PRIVATE static - -#else - -#define IX_ETH_ACC_PRIVATE - -#endif /* ndef NDEBUG */ - -#define IX_ETH_ACC_PUBLIC - - -#define IX_ETH_ACC_IS_PORT_VALID(port) ((port) < IX_ETH_ACC_NUMBER_OF_PORTS ? true : false ) - - - -#ifndef NDEBUG -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#else -#define IX_ETH_ACC_FATAL_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_FATAL,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_WARNING_LOG(a,b,c,d,e,f,g) { ixOsalLog ( IX_OSAL_LOG_LVL_WARNING,IX_OSAL_LOG_DEV_STDOUT,a,b,c,d,e,f,g);} -#define IX_ETH_ACC_DEBUG_LOG(a,b,c,d,e,f,g) {} -#endif - -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccInitDataPlane(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrQueuesConfig(void); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccQMgrRxCallbacksRegister(IxQMgrCallback ixQMgrCallback); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccSingleEthNpeCheck(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccQMgrRxQEntryGet(UINT32 *numRxQueueEntries); - -/* prototypes for the private control plane functions (used by the control interface wrapper) */ -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortEnabledQueryPriv(IxEthAccPortId portId, BOOL *enabled); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeClearPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortPromiscuousModeSetPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressSetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastMacAddressGetPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinPriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressJoinAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeavePriv(IxEthAccPortId portId, IxEthAccMacAddr *macAddr); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortMulticastAddressLeaveAllPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortUnicastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC void ixEthAccPortMulticastAddressShowPriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeSetPriv(IxEthAccPortId portId, IxEthAccDuplexMode mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortDuplexModeGetPriv(IxEthAccPortId portId, IxEthAccDuplexMode *mode); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendPaddingDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortTxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSEnablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccPortRxFrameAppendFCSDisablePriv(IxEthAccPortId portId); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccTxSchedulingDisciplineSetPriv(IxEthAccPortId portId, IxEthAccSchedulerDiscipline sched); -IX_ETH_ACC_PUBLIC IxEthAccStatus ixEthAccRxSchedulingDisciplineSetPriv(IxEthAccSchedulerDiscipline sched); - -/** - * @struct ixEthAccRxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 rxFrameClientCallback; - UINT32 rxFreeRepOK; - UINT32 rxFreeRepDelayed; - UINT32 rxFreeRepFromSwQOK; - UINT32 rxFreeRepFromSwQDelayed; - UINT32 rxFreeLateNotificationEnabled; - UINT32 rxFreeLowCallback; - UINT32 rxFreeOverflow; - UINT32 rxFreeLock; - UINT32 rxDuringDisable; - UINT32 rxSwQDuringDisable; - UINT32 rxUnlearnedMacAddress; - UINT32 rxPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 rxUnexpectedError; - UINT32 rxFiltered; -} IxEthAccRxDataStats; - -/** - * @struct IxEthAccTxDataStats - * @brief Stats data structures for data path. - Not obtained from h/w - * - */ -typedef struct -{ - UINT32 txQOK; - UINT32 txQDelayed; - UINT32 txFromSwQOK; - UINT32 txFromSwQDelayed; - UINT32 txLowThreshCallback; - UINT32 txDoneClientCallback; - UINT32 txDoneClientCallbackDisable; - UINT32 txOverflow; - UINT32 txLock; - UINT32 txPriority[IX_ETH_ACC_TX_PRIORITY_7 + 1]; - UINT32 txLateNotificationEnabled; - UINT32 txDoneDuringDisable; - UINT32 txDoneSwQDuringDisable; - UINT32 txUnexpectedError; -} IxEthAccTxDataStats; - -/* port Disable state machine : list of states */ -typedef enum -{ - /* general port states */ - DISABLED = 0, - ACTIVE, - - /* particular Tx/Rx states */ - REPLENISH, - RECEIVE, - TRANSMIT, - TRANSMIT_DONE -} IxEthAccPortDisableState; - -typedef struct -{ - BOOL fullDuplex; - BOOL rxFCSAppend; - BOOL txFCSAppend; - BOOL txPADAppend; - BOOL enabled; - BOOL promiscuous; - BOOL joinAll; - IxOsalMutex ackMIBStatsLock; - IxOsalMutex ackMIBStatsResetLock; - IxOsalMutex MIBStatsGetAccessLock; - IxOsalMutex MIBStatsGetResetAccessLock; - IxOsalMutex npeLoopbackMessageLock; - IxEthAccMacAddr mcastAddrsTable[IX_ETH_ACC_MAX_MULTICAST_ADDRESSES]; - UINT32 mcastAddrIndex; - IX_OSAL_MBUF *portDisableTxMbufPtr; - IX_OSAL_MBUF *portDisableRxMbufPtr; - - volatile IxEthAccPortDisableState portDisableState; - volatile IxEthAccPortDisableState rxState; - volatile IxEthAccPortDisableState txState; - - BOOL initDone; - BOOL macInitialised; -} IxEthAccMacState; - -/** - * @struct IxEthAccRxInfo - * @brief System-wide data structures associated with the data plane. - * - */ -typedef struct -{ - IxQMgrQId higherPriorityQueue[IX_QMGR_MAX_NUM_QUEUES]; /**< higher priority queue list */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Receive Xscale QoS type */ -} IxEthAccInfo; - -/** - * @struct IxEthAccRxDataInfo - * @brief Per Port data structures associated with the receive data plane. - * - */ -typedef struct -{ - IxQMgrQId rxFreeQueue; /**< rxFree Queue for this port */ - IxEthAccPortRxCallback rxCallbackFn; - UINT32 rxCallbackTag; - IxEthAccDataPlaneQList freeBufferList; - IxEthAccPortMultiBufferRxCallback rxMultiBufferCallbackFn; - UINT32 rxMultiBufferCallbackTag; - BOOL rxMultiBufferCallbackInUse; - IxEthAccRxDataStats stats; /**< Receive s/w stats */ -} IxEthAccRxDataInfo; - -/** - * @struct IxEthAccTxDataInfo - * @brief Per Port data structures associated with the transmit data plane. - * - */ -typedef struct -{ - IxEthAccPortTxDoneCallback txBufferDoneCallbackFn; - UINT32 txCallbackTag; - IxEthAccDataPlaneQList txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */ - IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */ - IxQMgrQId txQueue; /**< txQueue for this port */ - IxEthAccTxDataStats stats; /**< Transmit s/w stats */ -} IxEthAccTxDataInfo; - - -/** - * @struct IxEthAccPortDataInfo - * @brief Per Port data structures associated with the port data plane. - * - */ -typedef struct -{ - BOOL portInitialized; - UINT32 npeId; /**< NpeId for this port */ - IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */ - IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */ -} IxEthAccPortDataInfo; - -extern IxEthAccPortDataInfo ixEthAccPortData[]; -#define IX_ETH_IS_PORT_INITIALIZED(port) (ixEthAccPortData[port].portInitialized) - -extern BOOL ixEthAccServiceInit; -#define IX_ETH_ACC_IS_SERVICE_INITIALIZED() (ixEthAccServiceInit == true ) - -/* - * Maximum number of frames to consume from the Rx Frame Q. - */ - -#define IX_ETH_ACC_MAX_RX_FRAME_CONSUME_PER_CALLBACK (128) - -/* - * Max number of times to load the Rx Free Q from callback. - */ -#define IX_ETH_ACC_MAX_RX_FREE_BUFFERS_LOAD (256) /* Set greater than depth of h/w Q + drain time at line rate */ - -/* - * Max number of times to read from the Tx Done Q in one sitting. - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_DONE_CONSUME_PER_CALLBACK (256) - -/* - * Max number of times to take buffers from S/w queues and write them to the H/w Tx - * queues on receipt of a Tx low threshold callback - */ - -#define IX_ETH_ACC_MAX_TX_FRAME_TX_CONSUME_PER_CALLBACK (16) - - -#define IX_ETH_ACC_FLUSH_CACHE(addr,size) IX_OSAL_CACHE_FLUSH((addr),(size)) -#define IX_ETH_ACC_INVALIDATE_CACHE(addr,size) IX_OSAL_CACHE_INVALIDATE((addr),(size)) - - -#define IX_ETH_ACC_MEMSET(start,value,size) memset(start,value,size) - -#endif /* ndef IxEthAcc_p_H */ - - - diff --git a/drivers/net/npe/include/IxEthDB.h b/drivers/net/npe/include/IxEthDB.h deleted file mode 100644 index 9c4a6a4ec44..00000000000 --- a/drivers/net/npe/include/IxEthDB.h +++ /dev/null @@ -1,2349 +0,0 @@ -/** @file IxEthDB.h - * - * @brief this file contains the public API of @ref IxEthDB component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * - */ - -#ifndef IxEthDB_H -#define IxEthDB_H - -#include -#include - -/** - * @defgroup IxEthDB IXP400 Ethernet Database (IxEthDB) API - * - * @brief ethDB is a library that does provides a MAC address database learning/filtering capability - * - *@{ - */ - -#define INLINE __inline__ - -#define IX_ETH_DB_PRIVATE PRIVATE /* imported from IxTypes.h */ - -#define IX_ETH_DB_PUBLIC PUBLIC - -/** - * @brief port ID => message handler NPE id conversion (0 => NPE_B, 1 => NPE_C) - */ -#define IX_ETH_DB_PORT_ID_TO_NPE(id) (id == 0 ? 1 : (id == 1 ? 2 : (id == 2 ? 0 : -1))) - -/** - * @def IX_ETH_DB_NPE_TO_PORT_ID(npe) - * @brief message handler NPE id => port ID conversion (NPE_B => 0, NPE_C => 1) - */ -#define IX_ETH_DB_NPE_TO_PORT_ID(npe) (npe == 0 ? 2 : (npe == 1 ? 0 : (npe == 2 ? 1 : -1))) - -/* temporary define - won't work for Azusa */ -#define IX_ETH_DB_PORT_ID_TO_NPE_LOGICAL_ID(id) (IX_ETH_DB_PORT_ID_TO_NPE(id) << 4) -#define IX_ETH_DB_NPE_LOGICAL_ID_TO_PORT_ID(id) (IX_ETH_DB_NPE_TO_PORT_ID(id >> 4)) - -/** - * @def IX_IEEE803_MAC_ADDRESS_SIZE - * @brief The size of the MAC address - */ -#define IX_IEEE803_MAC_ADDRESS_SIZE (6) - -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief Number of QoS priorities defined by IEEE802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) - -/** - * @enum IxEthDBStatus - * @brief Ethernet Database API return values - */ -typedef enum /* IxEthDBStatus */ -{ - IX_ETH_DB_SUCCESS = IX_SUCCESS, /**< Success */ - IX_ETH_DB_FAIL = IX_FAIL, /**< Failure */ - IX_ETH_DB_INVALID_PORT, /**< Invalid port */ - IX_ETH_DB_PORT_UNINITIALIZED, /**< Port not initialized */ - IX_ETH_DB_MAC_UNINITIALIZED, /**< MAC not initialized */ - IX_ETH_DB_INVALID_ARG, /**< Invalid argument */ - IX_ETH_DB_NO_SUCH_ADDR, /**< Address not found for search or delete operations */ - IX_ETH_DB_NOMEM, /**< Learning database memory full */ - IX_ETH_DB_BUSY, /**< Learning database cannot complete operation, access temporarily blocked */ - IX_ETH_DB_END, /**< Database browser passed the end of the record set */ - IX_ETH_DB_INVALID_VLAN, /**< Invalid VLAN ID (valid range is 0..4094, 0 signifies no VLAN membership, used for priority tagged frames) */ - IX_ETH_DB_INVALID_PRIORITY, /**< Invalid QoS priority/traffic class (valid range for QoS priority is 0..7, valid range for traffic class depends on run-time configuration) */ - IX_ETH_DB_NO_PERMISSION, /**< No permission for attempted operation */ - IX_ETH_DB_FEATURE_UNAVAILABLE, /**< Feature not available (or not enabled) */ - IX_ETH_DB_INVALID_KEY, /**< Invalid search key */ - IX_ETH_DB_INVALID_RECORD_TYPE /**< Invalid record type */ -} IxEthDBStatus; - -/** @brief VLAN ID type, valid range is 0..4094, 0 signifying no VLAN membership */ -typedef UINT32 IxEthDBVlanId; - -/** @brief 802.1Q VLAN tag, contains 3 bits user priority, 1 bit CFI, 12 bits VLAN ID */ -typedef UINT32 IxEthDBVlanTag; - -/** @brief QoS priority/traffic class type, valid range is 0..7, 0 being the lowest */ -typedef UINT32 IxEthDBPriority; - -/** @brief Priority mapping table; 0..7 QoS priorities used to index, table contains traffic classes */ -typedef UINT8 IxEthDBPriorityTable[8]; - -/** @brief A 4096 bit array used to map the complete VLAN ID range */ -typedef UINT8 IxEthDBVlanSet[512]; - -#define IX_ETH_DB_802_1Q_VLAN_MASK (0xFFF) -#define IX_ETH_DB_802_1Q_QOS_MASK (0x7) - -#define IX_ETH_DB_802_1Q_MAX_VLAN_ID (0xFFE) - -/** - * @def IX_ETH_DB_SET_VLAN_ID - * @brief returns the given 802.1Q tag with the VLAN ID field substituted with the given VLAN ID - * - * This macro is used to change the VLAN ID in a 802.1Q tag. - * - * Example: - * - * tag = IX_ETH_DB_SET_VLAN_ID(tag, 32) - * - * inserts the VLAN ID "32" in the given tag. - */ -#define IX_ETH_DB_SET_VLAN_ID(vlanTag, vlanID) (((vlanTag) & 0xF000) | ((vlanID) & IX_ETH_DB_802_1Q_VLAN_MASK)) - -/** -* @def IX_ETH_DB_GET_VLAN_ID -* @brief returns the VLAN ID from the given 802.1Q tag -*/ -#define IX_ETH_DB_GET_VLAN_ID(vlanTag) ((vlanTag) & IX_ETH_DB_802_1Q_VLAN_MASK) - -#define IX_ETH_DB_GET_QOS_PRIORITY(vlanTag) (((vlanTag) >> 13) & IX_ETH_DB_802_1Q_QOS_MASK) - -#define IX_ETH_DB_SET_QOS_PRIORITY(vlanTag, priority) (((vlanTag) & 0x1FFF) | (((priority) & IX_ETH_DB_802_1Q_QOS_MASK) << 13)) - -#define IX_ETH_DB_CHECK_VLAN_TAG(vlanTag) { if(((vlanTag & 0xFFFF0000) != 0) || (IX_ETH_DB_GET_VLAN_ID(vlanTag) > 4094)) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_ETH_DB_CHECK_VLAN_ID(vlanId) { if (vlanId > IX_ETH_DB_802_1Q_MAX_VLAN_ID) return IX_ETH_DB_INVALID_VLAN; } - -#define IX_IEEE802_1Q_VLAN_TPID (0x8100) - -typedef enum -{ - IX_ETH_DB_UNTAGGED_FRAMES = 0x1, /**< Accepts untagged frames */ - IX_ETH_DB_VLAN_TAGGED_FRAMES = 0x2, /**< Accepts tagged frames */ - IX_ETH_DB_PRIORITY_TAGGED_FRAMES = 0x4, /**< Accepts tagged frames with VLAN ID set to 0 (no VLAN membership) */ - IX_ETH_DB_ACCEPT_ALL_FRAMES = - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES /**< Accepts all the frames */ -} IxEthDBFrameFilter; - -typedef enum -{ - IX_ETH_DB_PASS_THROUGH = 0x1, /**< Leave frame as-is */ - IX_ETH_DB_ADD_TAG = 0x2, /**< Add default port VLAN tag */ - IX_ETH_DB_REMOVE_TAG = 0x3 /**< Remove VLAN tag from frame */ -} IxEthDBTaggingAction; - -typedef enum -{ - IX_ETH_DB_FIREWALL_WHITE_LIST = 0x1, /**< Firewall operates in white-list mode (MAC address based admission) */ - IX_ETH_DB_FIREWALL_BLACK_LIST = 0x2 /**< Firewall operates in black-list mode (MAC address based blocking) */ -} IxEthDBFirewallMode; - -typedef enum -{ - IX_ETH_DB_FILTERING_RECORD = 0x01, /**< - *
Filtering record
MAC address static/dynamic type age - *
- */ - IX_ETH_DB_FILTERING_VLAN_RECORD = 0x02, /**< - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag - *
- */ - IX_ETH_DB_WIFI_RECORD = 0x04, /**< - *
WiFi header conversion record
MAC address optional gateway MAC address - *
- */ - IX_ETH_DB_FIREWALL_RECORD = 0x08, /**< - *
Firewall record
MAC address - *
- */ - IX_ETH_DB_GATEWAY_RECORD = 0x10, /**< For internal use only */ - IX_ETH_DB_MAX_RECORD_TYPE_INDEX = 0x10, /**< For internal use only */ - IX_ETH_DB_NO_RECORD_TYPE = 0, /**< None of the registered record types */ - IX_ETH_DB_ALL_FILTERING_RECORDS = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD, /**< All the filtering records */ - IX_ETH_DB_ALL_RECORD_TYPES = IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | - IX_ETH_DB_WIFI_RECORD | IX_ETH_DB_FIREWALL_RECORD /**< All the record types registered within EthDB */ -} IxEthDBRecordType; - -typedef enum -{ - IX_ETH_DB_LEARNING = 0x01, /**< Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records */ - IX_ETH_DB_FILTERING = 0x02, /**< Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature */ - IX_ETH_DB_VLAN_QOS = 0x04, /**< VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes */ - IX_ETH_DB_FIREWALL = 0x08, /**< Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists */ - IX_ETH_DB_SPANNING_TREE_PROTOCOL = 0x10, /**< Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes */ - IX_ETH_DB_WIFI_HEADER_CONVERSION = 0x20 /**< WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data */ -} IxEthDBFeature; - -typedef UINT32 IxEthDBProperty; /**< Property ID type */ - -typedef enum -{ - IX_ETH_DB_INTEGER_PROPERTY = 0x1, /**< 4 byte unsigned integer type */ - IX_ETH_DB_STRING_PROPERTY = 0x2, /**< NULL-terminated string type of maximum 255 characters (including the terminator) */ - IX_ETH_DB_MAC_ADDR_PROPERTY = 0x3, /**< 6 byte MAC address type */ - IX_ETH_DB_BOOL_PROPERTY = 0x4 /**< 4 byte boolean type; can contain only true and false values */ -} IxEthDBPropertyType; - -/* list of supported properties for the IX_ETH_DB_VLAN_QOS feature */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY (0x01) /**< Property identifying number the supported number of traffic classes */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY (0x10) /**< Rx queue assigned to traffic class 0 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY (0x11) /**< Rx queue assigned to traffic class 1 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY (0x12) /**< Rx queue assigned to traffic class 2 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY (0x13) /**< Rx queue assigned to traffic class 3 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY (0x14) /**< Rx queue assigned to traffic class 4 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY (0x15) /**< Rx queue assigned to traffic class 5 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY (0x16) /**< Rx queue assigned to traffic class 6 */ -#define IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY (0x17) /**< Rx queue assigned to traffic class 7 */ - -/* private property used by EthAcc to indicate queue configuration complete */ -#define IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (0x18) - -/** - * - * @brief The IEEE 802.3 Ethernet MAC address structure. - * - * The data should be packed with bytes xx:xx:xx:xx:xx:xx - * - * @note The data must be packed in network byte order. - */ -typedef struct -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; -} IxEthDBMacAddr; - -/** - * @ingroup IxEthDB - * - * @brief Definition of an IXP400 port. - */ -typedef UINT32 IxEthDBPortId; - -/** - * @ingroup IxEthDB - * - * @brief Port dependency map definition - */ -typedef UINT8 IxEthDBPortMap[32]; - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBInit(void) - * - * @brief Initializes the Ethernet learning/filtering database - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored, returning IX_ETH_DB_SUCCESS - * - * @retval IX_ETH_DB_SUCCESS initialization was successful - * @retval IX_ETH_DB_FAIL initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBInit(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUnload(void) - * - * @brief Stops and prepares the EthDB component for unloading. - * - * @retval IX_ETH_DB_SUCCESS de-initialization was successful - * @retval IX_ETH_DB_BUSY de-initialization failed, ports must be disabled first - * @retval IX_ETH_DB_FAIL de-initialization failed (OS error) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUnload(void); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBPortInit(IxEthDBPortId portID) - * - * @brief Initializes a port - * - * This function is called automatically by the Ethernet Access - * ixEthAccPortInit() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the two Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to be initialized - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -void ixEthDBPortInit(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID) - * - * @brief Enables a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortEnable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable processing on - * - * @retval IX_ETH_DB_SUCCESS if enabling is successful - * @retval IX_ETH_DB_FAIL if the enabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_MAC_UNINITIALIZED the MAC address of this port was - * not initialized (only for Ethernet NPEs) - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @pre ixEthDBPortAddressSet needs to be called prior to enabling the port events - * for Ethernet NPEs - * - * @see ixEthDBPortAddressSet - * - * @see IxEthDBPortDefs.h for port definitions - * - * @note calling this function multiple times does not constitute an error; - * redundant calls will be ignored - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID) - * - * @brief Disables processing on a port - * - * This function is called automatically from the Ethernet Access component - * ixEthAccPortDisable() routine for Ethernet NPE ports and should be manually - * called for any user-defined port (any port that is not one of - * the Ethernet NPEs). - * - * @note Calling ixEthAccPortDisable() will disable the respective Ethernet NPE. - * After Ethernet NPEs are disabled they are stopped therefore - * when re-enabled they need to be reset, downloaded with microcode and started. - * For learning to restart working the user needs to call again - * ixEthAccPortUnicastMacAddressSet or ixEthDBUnicastAddressSet - * with the respective port MAC address. - * Residual MAC addresses learnt before the port was disabled are deleted as soon - * as the port is disabled. This only applies to dynamic (learnt) entries, static - * entries do not dissapear when the port is disabled. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to disable processing on - * - * @retval IX_ETH_DB_SUCCESS if disabling is successful - * @retval IX_ETH_DB_FAIL if the disabling was not successful due to - * a message handler error - * @retval IX_ETH_DB_INVALID_PORT if portID is invalid - * - * @note calling this function multiple times after the first time completed successfully - * does not constitute an error; redundant calls will be ignored and return IX_ETH_DB_SUCCESS -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Sets the port MAC address - * - * This function is to be called from the Ethernet Access component top-level - * ixEthDBUnicastAddressSet(). Event processing cannot be enabled for a port - * until its MAC address has been set. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose MAC address is set - * @param macAddr @ref IxEthDBMacAddr [in] - port MAC address - * - * @retval IX_ETH_DB_SUCCESS MAC address was set successfully - * @retval IX_ETH_DB_FAIL MAC address was not set due to a message handler failure - * @retval IX_ETH_DB_INVALID_PORT if the port is not an Ethernet NPE - * - * @see IxEthDBPortDefs.h for port definitions - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize) - * - * @brief Set the maximum frame size supported on the given port ID - * - * This functions set the maximum frame size supported on a specific port ID - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to configure - * @param maximumFrameSize UINT32 [in] - maximum frame size to configure - * - * @retval IX_ETH_DB_SUCCESS the port is configured - * @retval IX_ETH_DB_PORT_UNINITIALIZED the port has not been initialized - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_INVALID_ARG size parameter is out of range - * @retval IX_ETH_DB_NO_PERMISSION selected port is not an Ethernet NPE - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note - * This maximum frame size is used to filter the frames based on their - * destination addresses and the capabilities of the destination port. - * The mximum value that can be set for a NPE port is 16320. - * (IX_ETHNPE_ACC_FRAME_LENGTH_MAX) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortMaximumFrameSizeSet(IxEthDBPortId portID, UINT32 maximumFrameSize); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a static MAC address - * - * Populates the Ethernet learning/filtering database with a static MAC address. The entry will not be subject to aging. - * If there is an entry (static or dynamic) with the corresponding MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the static address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringStaticEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Populate the Ethernet learning/filtering database with a dynamic MAC address - * - * Populates the Ethernet learning/filtering database with a dynamic MAC address. This entry will be subject to normal - * aging function, if aging is enabled on its port. - * If there is an entry (static or dynamic) with the same MAC address on any port this entry will take precedence. - * Any other entry with the same MAC address will be removed. - * - * - Reentrant - yes - * - ISR Callable - yes - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the dynamic address to - * @param macAddr @ref IxEthDBMacAddr [in] - static MAC address to add - * - * @retval IX_ETH_DB_SUCCESS the add was successful - * @retval IX_ETH_DB_FAIL failed to populate the database entry - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDynamicEntryProvision(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address entry from the Ethernet learning/filtering database - * - * @param macAddr IxEthDBMacAddr [in] - MAC address to remove - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the removal was successful - * @retval IX_ETH_DB_NO_SUCH_ADDR failed to remove the address (not in the database) - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_BUSY failed due to a temporary busy condition (i.e. lack of CPU cycles), try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringEntryDelete(IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for the given MAC address and port ID - * - * This functions searches the database for a specific port ID and MAC address. Both the port ID - * and the MAC address have to match in order for the record to be reported as found. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to search for - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortSearch(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the Ethernet learning/filtering database for a MAC address and return the port ID - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record, if found. If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID the address belongs to (populated only on a successful search) - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to search for - * - * @retval IX_ETH_DB_SUCCESS the record exists in the database - * @retval IX_ETH_DB_NO_SUCH_ADDR the record was not found in the database - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr) - * - * @brief Search the filtering database for a MAC address, return the port ID and reset the record age - * - * Searches the database for a MAC address. The function returns the portID for the - * MAC address record and resets the entry age to 0, if found. - * If no match is found the function returns IX_ETH_DB_NO_SUCH_ADDR. - * The portID is only valid if the function finds a match. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS the MAC address was found - * @retval IX_ETH_DB_NO_SUCH_ADDR the MAC address was not found - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or portID pointer argument(s) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringPortUpdatingSearch(IxEthDBPortId *portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_MAINTENANCE_TIME - * - * @brief The @ref ixEthDBDatabaseMaintenance must be called by the user at a frequency of - * IX_ETH_DB_MAINTENANCE_TIME - * - */ -#define IX_ETH_DB_MAINTENANCE_TIME (1 * 60) /* 1 Minute */ - -/** - * @ingroup IxEthDB - * - * @def IX_ETH_DB_LEARNING_ENTRY_AGE_TIME - * - * @brief The define specifies the filtering database age entry time. Static entries older than - * IX_ETH_DB_LEARNING_ENTRY_AGE_TIME +/- IX_ETH_DB_MAINTENANCE_TIME shall be removed. - * - */ -#define IX_ETH_DB_LEARNING_ENTRY_AGE_TIME (15 * 60 ) /* 15 Mins */ - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID) - * - * @brief Disable the aging function for a specific port - * - * @param portID @ref IxEthDBPortId [in] - port ID to disable aging on - * - * - Reentrant - yes - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS aging disabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingDisable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID) - * - * @brief Enable the aging function for a specific port - * - * Enables the aging of dynamic MAC address entries stored in the learning/filtering database - * - * @note The aging function relies on the @ref ixEthDBDatabaseMaintenance being called with a period of - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. - * - * - Reentrant - yes - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to enable aging on - * - * @retval IX_ETH_DB_SUCCESS aging enabled successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE learning feature is disabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortAgingEnable(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBDatabaseMaintenance(void) - * - * @brief Performs a maintenance operation on the Ethernet learning/filtering database - * - * In order to perform a database maintenance this function must be called every - * @ref IX_ETH_DB_MAINTENANCE_TIME seconds. It should be called regardless of whether learning is - * enabled or not. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function call will be ignored if the learning feature is disabled - */ -IX_ETH_DB_PUBLIC -void ixEthDBDatabaseMaintenance(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID) - * - * @brief This function displays the Mac Ethernet MAC address filtering tables. - * - * It displays the MAC address, port ID, entry type (dynamic/static),and age for - * the given port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to display the MAC address entries - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - * @retval IX_ETH_DB_FAIL record browser failed due to an internal busy or lock condition - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShow(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn void ixEthDBFilteringDatabaseShowAll(void) - * - * @brief Displays the MAC address recorded in the filtering database for all registered - * ports (see IxEthDBPortDefs.h), grouped by port ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval void - * - * @note this function is deprecated and kept for compatibility reasons; use @ref ixEthDBFilteringDatabaseShowRecords instead - * - * @see ixEthDBFilteringDatabaseShowRecords - */ -IX_ETH_DB_PUBLIC -void ixEthDBFilteringDatabaseShowAll(void); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter) - * - * @brief This function displays per port database records, given a record type filter - * - * The supported record type filters are: - * - * - IX_ETH_DB_FILTERING_RECORD - displays the non-VLAN filtering records (MAC address, age, static/dynamic) - * - IX_ETH_DB_FILTERING_VLAN_RECORD - displays the VLAN filtering records (MAC address, age, static/dynamic, VLAN ID, CFI, QoS class) - * - IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD - displays the previous two types of records - * - IX_ETH_DB_WIFI_RECORD - displays the WiFi header conversion records (MAC address, optional gateway MAC address) and WiFi header conversion parameters (BBSID, Duration/ID) - * - IX_ETH_DB_FIREWALL_RECORD - displays the firewall MAC address table and firewall operating mode (white list/black list) - * - IX_ETH_DB_ALL_RECORD_TYPES - displays all the record types - * - IX_ETH_DB_NO_RECORD_TYPE - displays only the port status (no records are displayed) - * - * Additionally, the status of each port will be displayed, containg the following information: type, capabilities, enabled status, - * aging enabled status, group membership and maximum frame size. - * - * The port ID can either be an actual port or IX_ETH_DB_ALL_PORTS, in which case the requested information - * will be displayed for all the ports (grouped by port) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID of the port to display information on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param recordFilter record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is invalid - * @retval IX_ETH_DB_PORT_UNINITIALIZED port ID is not initialized - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFilteringDatabaseShowRecords(IxEthDBPortId portID, IxEthDBRecordType recordFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Sets the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap new dependency map (as bitmap, each bit set indicates a port being included) - * - * This function is used to share filtering information between ports. - * By adding a port into another port's dependency map the target port - * filtering data will import the filtering data from the port it depends on. - * Any changes to filtering data for a port - such as adding, updating or removing records - - * will trigger updates in the filtering information for all the ports depending on - * on the updated port. - * - * For example, if ports 2 and 3 are set in the port 0 dependency map the filtering - * information for port 0 will also include the filtering information from ports 2 and 3. - * Adding a record to port 2 will also trigger an update not only on port 2 but also on - * port 0. - * - * The dependency map is a 256 bit array where each bit corresponds to a port corresponding to the - * bit offset (bit 0 - port 0, bit 1 - port 1 etc). Setting a bit to 1 indicates that the corresponding - * port is the port map. For example, a dependency port map of 0x14 consists in the ports with IDs 2 and 4. - * Note that the last bit (offset 255) is reserved and should never be set (it will be automatically - * cleared by the function). - * - * By default, each port has a dependency port map consisting only of itself, i.e. - * - * @verbatim - IxEthDBPortMap portMap; - - // clear all ports from port map - memset(portMap, 0, sizeof (portMap)); - - // include portID in port map - portMap[portID / 8] = 1 << (portID % 8); - @endverbatim - * - * - Reentrant - no - * - ISR Callable - no - * - * @note Setting dependency maps is useful for NPE ports, which benefit from automatic updates - * of filtering information. Setting dependency maps for user-defined ports is not an error - * but will have no actual effect. - * - * @note Including a port in its own dependency map is not compulsory, however note that - * in this case updating the port will not trigger an update on the port itself, which - * might not be the intended behavior - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapSet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap) - * - * @brief Retrieves the dependency port map for a port - * - * @param portID ID of the port to set the dependency map to - * @param dependencyPortMap location where the port dependency map is to be copied - * - * This function will copy the port dependency map to a user specified location. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid dependencyPortMap pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Filtering is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortDependencyMapGet(IxEthDBPortId portID, IxEthDBPortMap dependencyPortMap); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag) - * - * @brief Sets the default 802.1Q VLAN tag for a given port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the default VLAN tag to - * @param vlanTag @ref IxEthDBVlanTag [in] - default 802.1Q VLAN tag - * - * The tag format has 16 bits and it is defined in the IEEE802.1Q specification. - * This tag will be used for tagging untagged frames (if enabled) and classifying - * unexpedited traffic into an internal traffic class (using the user priority field). - * - * - *
802.1Q tag format
3 bits 1 bit 12 bits - *
user priority CFI VID - *
- * - * User Priority : Defines user priority, giving eight (2^3) priority levels. IEEE 802.1P defines - * the operation for these 3 user priority bits - * - * CFI : Canonical Format Indicator is always set to zero for Ethernet switches. CFI is used for - * compatibility reason between Ethernet type network and Token Ring type network. If a frame received - * at an Ethernet port has a CFI set to 1, then that frame should not be forwarded as it is to an untagged port. - * - * VID : VLAN ID is the identification of the VLAN, which is basically used by the standard 802.1Q. - * It has 12 bits and allow the id entification of 4096 (2^12) VLANs. Of the 4096 possible VIDs, a VID of 0 - * is used to identify priority frames and value 4095 (FFF) is reserved, so the maximum possible VLAN - * configurations are 4,094. - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - * - * @note a VLAN ID value of 0 indicates that the port is not part of any VLAN - * @note the value of the cannonical frame indicator (CFI) field is ignored, the - * field being used only in frame tagging operations - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagSet(IxEthDBPortId portID, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the default 802.1Q port VLAN tag for a given port (see also @ref ixEthDBPortVlanTagSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the default VLAN tag from - * @param vlanTag @ref IxEthDBVlanTag [out] - location to write the default port 802.1Q VLAN tag to - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanTag pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanTagGet(IxEthDBPortId portID, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag) - * - * @brief Sets the 802.1Q VLAN tag for a database record - * - * @param macAddr MAC address - * @param vlanTag 802.1Q VLAN tag - * - * This function is used together with @ref ixEthDBVlanTagGet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see below). - * - * VLAN tags can be set only in IX_ETH_DB_FILTERING_RECORD or IX_ETH_DB_FILTERING_VLAN_RECORD type records. - * If to an IX_ETH_DB_FILTERING_RECORD type record is added a VLAN tag the record type is automatically - * changed to IX_ETH_DB_FILTERING_VLAN_RECORD. Once this has occurred the record type will never - * revert to a non-VLAN type (unless deleted and re-added). - * - * Record types used for different purposes (such as IX_ETH_DB_WIFI_RECORD) will be ignored by - * this function. - * - * After using this function to associate a VLAN ID with a MAC address the VLAN ID can be extracted knowing the - * MAC address using @ref ixEthDBVlanTagGet. This mechanism can be used to implement MAC-based VLAN classification - * if a bridging application searches for the VLAN tag when receiving a frame based on the source MAC address - * (contained in the ixp_ne_src_mac field of the buffer header). - * If found in the database, the application can instruct the NPE to tag the frame by writing the VLAN tag - * in the ixp_ne_vlan_tci field of the buffer header. This way the NPE will inspect the Egress tagging - * rule associated with the given VLAN ID on the Tx port and tag the frame if Egress tagging on the VLAN is - * allowed. Additionally, Egress tagging can be forced by setting the ixp_ne_tx_flags.tag_over and - * ixp_ne_tx_flags.tag_mode flags in the buffer header. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note this function will not add a filtering record, it can only be used to update an existing one - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - * @retval IX_ETH_DB_INVALID_VLAN vlanTag argument does not parse to a valid 802.1Q VLAN tag - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagSet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag) - * - * @brief Retrieves the 802.1Q VLAN tag from a database record given the record MAC address - * - * @param macAddr MAC address - * @param vlanTag location to write the record 802.1Q VLAN tag to - * - * @note VLAN tags can be retrieved only from IX_ETH_DB_FILTERING_VLAN_RECORD type records - * - * This function is used together with ixEthDBVlanTagSet to provide MAC-based VLAN classification support. - * Please note that the bridging application must contain specific code to make use of this feature (see @ref ixEthDBVlanTagSet). - * - * - Reentrant - no - * - ISR Callable - no - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or vlanTag pointer - * @retval IX_ETH_DB_NO_SUCH_ADDR a filtering record with the specified MAC address was not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanTagGet(IxEthDBMacAddr *macAddr, IxEthDBVlanTag *vlanTag); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Adds a VLAN ID to a port's VLAN membership table - * - * Adding a VLAN ID to a port's VLAN membership table will cause frames tagged with the specified - * VLAN ID to be accepted by the frame filter, if Ingress VLAN membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to add the VLAN ID membership to - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be added to the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID is always in its own membership table, hence there - * is no need to explicitly add it using this function (although it is not an error - * to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipAdd(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Adds a VLAN ID range to a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be added to the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames with - * VLAN IDs in the specified range will be accepted by the frame filter, if Ingress VLAN - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to add the VLAN membership range into - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case this - * function will behave as @ref ixEthDBPortVlanMembershipAdd - * - * @note A port's default VLAN ID is always in its own membership table, hence there is no need - * to explicitly add it using this function (although it is not an error to do so) - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeAdd(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID) - * - * @brief Removes a VLAN ID from a port's VLAN membership table - * - * Frames tagged with a VLAN ID which is not in a port's VLAN membership table - * will be discarded by the frame filter, if Ingress membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN ID membership from - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be removed from the port membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_VLAN vlanID is not a valid VLAN ID - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (vlanID was set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note A port's default VLAN ID cannot be removed from the port's membership - * table; attempting it will return IX_ETH_DB_NO_PERMISSION - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRemove(IxEthDBPortId portID, IxEthDBVlanId vlanID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax) - * - * @brief Removes a VLAN ID range from a port's VLAN membership table - * - * All the VLAN IDs in the specified range will be removed from the port VLAN - * membership table, including the range start and end VLAN IDs. Tagged frames - * with VLAN IDs in the range will be discarded by the frame filter, if Ingress - * membership filtering is enabled. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to remove the VLAN membership range from - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN ID range - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN ID range - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN the specified VLAN IDs are invalid or do not constitute a range - * @retval IX_ETH_DB_NO_PERMISSION attempted to remove the default VLAN ID - * from the port membership table (both vlanIDMin and vlanIDMax were set to the default port VLAN ID) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Is is valid to use the same VLAN ID for both vlanIDMin and vlanIDMax, in which case - * function will behave as @ref ixEthDBPortVlanMembershipRemove - * - * @note If the given range overlaps the default port VLAN ID this function - * will remove all the VLAN IDs in the range except for the port VLAN ID from its - * own membership table. This situation will be silently dealt with (no error message - * will be returned) as long as the range contains more than one value (i.e. at least - * one other value, apart from the default port VLAN ID). If the function is called - * with the vlanIDMin and vlanIDMax parameters both set to the port default VLAN ID, the - * function will infer that an attempt was specifically made to remove the default port - * VLAN ID from the port membership table, in which case the return value will be - * IX_ETH_DB_NO_PERMISSION. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipRangeRemove(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets a port's VLAN membership table - * - * Sets a port's VLAN membership table from a complete VLAN table containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit must be set if bit 0 is set. - * - * The bit at index 4095 is reserved and should never be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID should always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the VLAN membership table to - * @param vlanSet @ref IxEthDBVlanSet [in] - pointer to the VLAN membership table - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves a port's VLAN membership table - * - * Retrieves the complete VLAN membership table from a port, containing all the possible - * 4096 VLAN IDs. The table format is an array containing 4096 bits (512 bytes), where each bit - * indicates whether the VLAN at that bit index is in the port's membership list (if set) or - * not (unset). - * - * The bit at index 0, indicating VLAN ID 0, indicates no VLAN membership and therefore no - * other bit will be set if bit 0 is set. - * - * The bit at index 4095 is reserved and will not be set (it will be ignored if set). - * - * The bit referencing the same VLAN ID as the default port VLAN ID will always be set, as - * the membership list must contain at least the default port VLAN ID. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the VLAN membership table from - * @param vlanSet @ref IxEthDBVlanSet [out] - pointer a location where the VLAN membership table will be - * written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPortVlanMembershipGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter) - * - * @brief Sets a port's acceptable frame type filter - * - * The acceptable frame type is one (or a combination) of the following values: - * - IX_ETH_DB_ACCEPT_ALL_FRAMES - accepts all the frames - * - IX_ETH_DB_UNTAGGED_FRAMES - accepts untagged frames - * - IX_ETH_DB_VLAN_TAGGED_FRAMES - accepts tagged frames - * - IX_ETH_DB_PRIORITY_TAGGED_FRAMES - accepts tagged frames with VLAN ID set to 0 (no VLAN membership) - * - * Except for using the exact values given above only the following combinations are valid: - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES - * - IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_PRIORITY_TAGGED_FRAMES - * - * Please note that IX_ETH_DB_UNTAGGED_FRAMES | IX_ETH_DB_VLAN_TAGGED_FRAMES is equivalent - * to IX_ETH_DB_ACCEPT_ALL_FRAMES. - * - * - Reentrant - no - * - ISR Callable - no - * - * @note by default the acceptable frame type filter is set to IX_ETH_DB_ACCEPT_ALL_FRAMES - * - * @note setting the acceptable frame type to PRIORITY_TAGGED_FRAMES is internally - * accomplished by changing the frame filter to VLAN_TAGGED_FRAMES and setting the - * VLAN membership list to include only VLAN ID 0; the membership list will need - * to be restored manually to an appropriate value if the acceptable frame type - * filter is changed back to ACCEPT_ALL_FRAMES or VLAN_TAGGED_FRAMES; failure to do so - * will filter all VLAN traffic bar frames tagged with VLAN ID 0 - * - * @param portID @ref IxEthDBPortId [in] - port ID to set the acceptable frame type filter to - * @param frameFilter @ref IxEthDBFrameFilter [in] - acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frame type filter - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeSet(IxEthDBPortId portID, IxEthDBFrameFilter frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter) - * - * @brief Retrieves a port's acceptable frame type filter - * - * For a description of the acceptable frame types see @ref ixEthDBAcceptableFrameTypeSet - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID to retrieve the acceptable frame type filter from - * @param frameFilter @ref IxEthDBFrameFilter [out] - location to store the acceptable frame type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid frameFilter pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBAcceptableFrameTypeGet(IxEthDBPortId portID, IxEthDBFrameFilter *frameFilter); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Sets a port's priority mapping table - * - * The priority mapping table is an 8x2 table mapping a QoS (user) priority into an internal - * traffic class. There are 8 valid QoS priorities (0..7, 0 being the lowest) which can be - * mapped into one of the 4 available traffic classes (0..3, 0 being the lowest). - * If a custom priority mapping table is not specified using this function the following - * default priority table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - port ID of the port to set the priority mapping table to - * @param priorityTable @ref IxEthDBPriorityTable [in] - location of the user priority table - * - * @note The provided table will be copied into internal data structures in EthDB and - * can be deallocated by the called after this function has completed its execution, if - * so desired - * - * @warning The number of available traffic classes differs depending on the NPE images - * and queue configuration. Check IxEthDBQoS.h for up-to-date information on the availability of - * traffic classes. Note that specifiying a traffic class in the priority map which exceeds - * the system availability will produce an IX_ETH_DB_INVALID_PRIORITY return error code and no - * priority will be remapped. - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_INVALID_PRIORITY at least one priority value exceeds - * the current number of available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableSet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable) - * - * @brief Retrieves a port's priority mapping table - * - * The priority mapping table for the given port will be copied in the location - * specified by the caller using "priorityTable" - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID ID @ref IxEthDBPortId [in] - of the port to retrieve the priority mapping table from - * @param priorityTable @ref IxEthDBPriorityTable [out] - pointer to a user specified location where the table will be copied to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid priorityTable pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingTableGet(IxEthDBPortId portID, IxEthDBPriorityTable priorityTable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass) - * - * @brief Sets one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function establishes a mapping between a user (QoS) priority and an internal traffic class. - * The mapping will be saved in the port's priority mapping table. Use this function when not all - * the QoS priorities need remapping (see also @ref ixEthDBPriorityMappingTableSet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [in] - internal traffic class, between 0 and 3 (0 being the lowest) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY userPriority out of range or - * trafficClass is beyond the number of currently available traffic classes - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassSet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass) - * - * @brief Retrieves one QoS/user priority => traffic class mapping in a port's priority mapping table - * - * This function retrieves the internal traffic class associated with a QoS (user) priority from a given - * port's priority mapping table. Use this function when not all the QoS priority mappings are - * required (see also @ref ixEthDBPriorityMappingTableGet) - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to set the mapping to - * @param userPriority @ref IxEthDBPriority [in] - user (QoS) priority, between 0 and 7 (0 being the lowest) - * @param trafficClass @ref IxEthDBPriority [out] - location to write the corresponding internal traffic class to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_PRIORITY invalid userPriority value (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_INVALID_ARG invalid trafficClass pointer argument - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBPriorityMappingClassGet(IxEthDBPortId portID, IxEthDBPriority userPriority, IxEthDBPriority *trafficClass); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and a given VLAN - * - * This function enables or disables Egress VLAN tagging for the given port and VLAN ID. - * If the VLAN tagging for a certain VLAN ID is enabled then all the frames to be - * transmitted on the given port tagged with the same VLAN ID will be transmitted in a tagged format. - * If tagging is not enabled for the given VLAN ID, the VLAN tag from the frames matching - * this VLAN ID will be removed (the frames will be untagged). - * - * VLAN ID 4095 is reserved and should never be used with this function. - * VLAN ID 0 has the special meaning of "No VLAN membership" and it is used in this - * context to allow the port to send priority-tagged frames or not. - * - * By default, no Egress VLAN tagging is enabled on any port. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN, and - * false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled) - * - * @brief Retrieves the Egress VLAN tagging enabling status for a port and VLAN ID - * - * @param portID [in] - ID of the port to extract the Egress VLAN ID tagging status from - * @param vlanID VLAN [in] - ID whose tagging status is to be extracted - * @param enabled [in] - user-specifed location where the status is copied to; following - * the successfull execution of this function the value will be true if Egress VLAN - * tagging is enabled for the given port and VLAN ID, and false otherwise - * - * - Reentrant - no - * - ISR Callable - no - * - * @see ixEthDBEgressVlanEntryTaggingEnabledGet - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range) - * @retval IX_ETH_DB_INVALID_ARG invalid enabled argument pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanEntryTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanId vlanID, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled) - * - * @brief Enables or disables Egress VLAN tagging for a port and given VLAN range - * - * This function is very similar to @ref ixEthDBEgressVlanEntryTaggingEnabledSet with the - * difference that it can manipulate the Egress tagging status on multiple VLAN IDs, - * defined by a contiguous range. Note that both limits in the range are explicitly - * included in the execution of this function. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the VLAN ID Egress tagging on - * @param vlanIDMin @ref IxEthDBVlanId [in] - start of the VLAN range to be matched against outgoing frames - * @param vlanIDMax @ref IxEthDBVlanId [in] - end of the VLAN range to be matched against outgoing frames - * @param enabled BOOL [in] - true to enable Egress VLAN tagging on the port and given VLAN range, - * and false to disable Egress VLAN tagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_VLAN invalid VLAN ID (out of range), or do not constitute a range - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_ETH_DB_NO_PERMISSION attempted to explicitly remove the default port VLAN ID from the tagging table - * @retval IX_FAIL unknown OS or NPE communication error - * - * @note Specifically removing the default port VLAN ID from the Egress tagging table by setting both vlanIDMin and vlanIDMax - * to the VLAN ID portion of the PVID is not allowed by this function and will return IX_ETH_DB_NO_PERMISSION. - * However, this can be circumvented, should the user specifically desire this, by either using a - * larger range (vlanIDMin < vlanIDMax) or by using ixEthDBEgressVlanEntryTaggingEnabledSet. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanRangeTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanId vlanIDMin, IxEthDBVlanId vlanIDMax, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Sets the complete Egress VLAN tagging table for a port - * - * This function is used to set the VLAN tagging/untagging per VLAN ID for a given port - * covering the entire VLAN ID range (0..4094). The vlanSet parameter is a 4096 - * bit array, each bit indicating the Egress behavior for the corresponding VLAN ID. - * If a bit is set then outgoing frames with the corresponding VLAN ID will be transmitted - * with the VLAN tag, otherwise the frame will be transmitted without the VLAN tag. - * - * Bit 0 has a special significance, indicating tagging or tag removal for priority-tagged - * frames. - * - * Bit 4095 is reserved and should never be set (it will be ignored if set). - * - * - Reentrant - no - * - ISR Callable - no - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is set - * @param vlanSet @ref IxEthDBVlanSet [in] - 4096 bit array controlling per-VLAN tagging and untagging - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - * - * @warning This function will automatically add the default port VLAN ID to the Egress tagging table - * every time it is called. The user should manually call ixEthDBEgressVlanEntryTaggingEnabledSet to - * prevent tagging on the default port VLAN ID if the default behavior is not intended. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet) - * - * @brief Retrieves the complete Egress VLAN tagging table from a port - * - * This function copies the 4096 bit table controlling the Egress VLAN tagging into a user specified - * area. Each bit in the array indicates whether tagging for the corresponding VLAN (the bit position - * in the array) is enabled (the bit is set) or not (the bit is unset). - * - * Bit 4095 is reserved and should not be set (it will be ignored if set). - * - * @see ixEthDBEgressVlanTaggingEnabledSet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Egress VLAN tagging behavior is retrieved - * @param vlanSet @ref IxEthDBVlanSet [out] - user location to copy the Egress tagging table into; should have - * room to store 4096 bits (512 bytes) - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid vlanSet pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBEgressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBVlanSet vlanSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction) - * - * @brief Sets the Ingress VLAN tagging behavior for a port - * - * A port's Ingress tagging behavior is controlled by the taggingAction parameter, - * which can take one of the following values: - * - * - IX_ETH_DB_PASS_THROUGH - leaves the frame unchanged (does not add or remove the VLAN tag) - * - IX_ETH_DB_ADD_TAG - adds the VLAN tag if not present, using the default port VID - * - IX_ETH_DB_REMOVE_TAG - removes the VLAN tag if present - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [in] - tagging behavior for the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledSet(IxEthDBPortId portID, IxEthDBTaggingAction taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction) - * - * @brief Retrieves the Ingress VLAN tagging behavior from a port (see @ref ixEthDBIngressVlanTaggingEnabledSet) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port whose Ingress VLAN tagging behavior is set - * @param taggingAction @ref IxEthDBTaggingAction [out] - location where the tagging behavior for the port is written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid taggingAction pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBIngressVlanTaggingEnabledGet(IxEthDBPortId portID, IxEthDBTaggingAction *taggingAction); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables port ID extraction - * - * This feature can be used in the situation when a multi-port device (e.g. a switch) - * is connected to an IXP4xx port and the device can provide incoming frame port - * identification by tagging the TPID field in the Ethernet frame. Enabling - * port extraction will instruct the NPE to copy the TPID field from the frame and - * place it in the ixp_ne_src_port of the ixp_buf header. In addition, - * the NPE restores the TPID field to 0. - * - * If the frame is not tagged the NPE will fill the ixp_ne_src_port with the - * port ID of the MII interface the frame was received from. - * - * The TPID field is the least significant byte of the type/length field, which is - * normally set to 0x8100 for 802.1Q-tagged frames. - * - * This feature is disabled by default. - * - * @param portID ID of the port to configure port ID extraction on - * @param enable true to enable port ID extraction and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE VLAN/QoS feature is not available or not enabled for the port - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBVlanPortExtractionEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet) - * - * @brief Retrieves the feature capability set for a port - * - * This function retrieves the feature capability set for a port or the common capabilities shared between all - * the ports, writing the feature capability set in a user specified location. - * - * The feature capability set will consist of a set formed by OR-ing one or more of the following values: - * - IX_ETH_DB_LEARNING - Learning feature; enables EthDB to learn MAC address (filtering) records, including 802.1Q enabled records - * - IX_ETH_DB_FILTERING - Filtering feature; enables EthDB to communicate with the NPEs for downloading filtering information in the NPEs; depends on the learning feature - * - IX_ETH_DB_VLAN_QOS - VLAN/QoS feature; enables EthDB to configure NPEs to operate in VLAN/QoS aware modes - * - IX_ETH_DB_FIREWALL - Firewall feature; enables EthDB to configure NPEs to operate in firewall mode, using white/black address lists - * - IX_ETH_DB_SPANNING_TREE_PROTOCOL - Spanning tree protocol feature; enables EthDB to configure the NPEs as STP nodes - * - IX_ETH_DB_WIFI_HEADER_CONVERSION - WiFi 802.3 to 802.11 header conversion feature; enables EthDB to handle WiFi conversion data - * - * Note that EthDB provides only the LEARNING feature for non-NPE ports. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to retrieve the capability set for - * (use IX_ETH_DB_ALL_PORTS to retrieve the common capabilities shared between all the ports) - * @param featureSet @ref IxEthDBFeature [out] - location where the capability set will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid featureSet pointer - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureCapabilityGet(IxEthDBPortId portID, IxEthDBFeature *featureSet); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled) - * - * @brief Enables or disables one or more EthDB features - * - * Selects one or more features (see @ref ixEthDBFeatureCapabilityGet for a description of the supported - * features) to be enabled or disabled on the selected port (or all the ports). - * - * Note that some features are mutually incompatible: - * - IX_ETH_DB_FILTERING is incompatible with IX_ETH_DB_WIFI_HEADER_CONVERSION - * - * Also note that some features require other features to be enabled: - * - IX_ETH_DB_FILTERING requires IX_ETH_DB_LEARNING - * - * This function will either enable the entire selected feature set for the selected port (or all the ports), - * in which case it will return IX_ETH_DB_SUCCESS, or in case of error it will not enable any feature at all - * and return an appropriate error message. - * - * The following features are enabled by default (for ports with the respective capability), - * for compatibility reasons with previous versions of CSR: - * - IX_ETH_DB_LEARNING - * - IX_ETH_DB_FILTERING - * - * All other features are disabled by default and require manual enabling using ixEthDBFeatureEnable. - * - * Default settings for VLAN, QoS, Firewall and WiFi header conversion features: - * - * VLAN - * - * When the VLAN/QoS feature is enabled for a port for the first time the default VLAN behavior - * of the port is set to be as permissive (it will accept all the frames) and - * non-interferential (it will not change any frames) as possible: - * - the port VLAN ID (VID) is set to 0 - * - the Ingress acceptable frame filter is set to accept all frames - * - the VLAN port membership is set to the complete VLAN range (0 - 4094) - * - the Ingress tagging mode is set to pass-through (will not change frames) - * - the Egress tagging mode is to send tagged frames in the entire VLAN range (0 - 4094) - * - * Note that further disabling and re-enabling the VLAN feature for a given port will not reset the port VLAN behavior - * to the settings listed above. Any VLAN settings made by the user are kept. - * - * QoS - * - * The following default priority mapping table will be used (as per IEEE 802.1Q and IEEE 802.1D): - * - * - *
QoS traffic classes
QoS priority Default traffic class Traffic type - *
0 1 Best effort, default class for unexpedited traffic - *
1 0 Background traffic - *
2 0 Spare bandwidth - *
3 1 Excellent effort - *
4 2 Controlled load - *
5 2 Video traffic - *
6 3 Voice traffic - *
7 3 Network control - *
- * - * Firewall - * - * The port firewall is configured by default in black-list mode, and the firewall address table is empty. - * This means the firewall will not filter any frames until the feature is configured and the firewall table is - * downloaded to the NPE. - * - * Spanning Tree - * - * The port is set to STP unblocked mode, therefore it will accept all frames until re-configured. - * - * WiFi header conversion - * - * The WiFi header conversion database is empty, therefore no actual header conversion will take place until this - * feature is configured and the conversion table downloaded to the NPE. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port to enable or disable the features on (use IX_ETH_DB_ALL_PORTS for all the ports) - * @param feature @ref IxEthDBFeature [in] - feature or feature set to enable or disable - * @param enabled BOOL [in] - true to enable the feature and false to disable it - * - * @note Certain features, from a functional point of view, cannot be disabled as such at NPE level; - * when such features are set to disabled using the EthDB API they will be configured in such - * a way to determine a behavior equivalent to the feature being disabled. As well as this, disabled - * features cannot be configured or accessed via the EthDB API (except for getting their status). - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_NO_PERMISSION attempted to enable mutually exclusive features, - * or a feature that depends on another feature which is not present or enabled - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE at least one of the features selected is unavailable - * @retval IX_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureEnable(IxEthDBPortId portID, IxEthDBFeature feature, BOOL enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled) - * - * @brief Retrieves the availability and status of a feature set - * - * This function returns the availability and status for a feature set. - * Note that if more than one feature is selected (e.g. IX_ETH_DB_LEARNING | IX_ETH_DB_FILTERING) - * the "present" and "enabled" return values will be set to true only if all the features in the - * feature set are present and enabled (not only some). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - identifier of the feature to retrieve the status for - * @param present BOOL [out] - location where a boolean flag indicating whether this feature is present will be written to - * @param enabled BOOL [out] - location where a boolean flag indicating whether this feature is enabled will be written to - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG either present or enabled pointer argument is invalid - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeatureStatusGet(IxEthDBPortId portID, IxEthDBFeature feature, BOOL *present, BOOL *enabled); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value) - * - * @brief Retrieves the value of a feature property - * - * The EthDB features usually contain feature-specific properties describing or - * controlling how the feature operates. While essential properties (e.g. the - * firewall operating mode) have their own API, secondary properties can be - * retrieved using this function. - * - * Properties can be read-only or read-write. ixEthDBFeaturePropertyGet operates with - * both types of features. - * - * Properties have types associated with them. A descriptor indicating the property - * type is returned in the type argument for convenience. - * - * The currently supported properties and their corresponding features are as follows: - * - * - *
Properties for IX_ETH_DB_VLAN_QOS
Property identifier Property type Property value Read-Only - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_COUNT_PROPERTY IX_ETH_DB_INTEGER_PROPERTY number of internal traffic classes Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 0 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_1_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 1 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_2_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 2 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_3_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 3 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_4_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 4 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_5_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 5 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_6_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 6 Yes - *
IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY IX_ETH_DB_INTEGER_PROPERTY queue assignment for traffic class 7 Yes - *
- * - * @see ixEthDBFeaturePropertySet - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is retrieved - * @param property @ref IxEthDBProperty [in] - property identifier - * @param type @ref IxEthDBPropertyType [out] - location where the property type will be stored - * @param value void [out] - location where the property value will be stored - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, type or value pointer arguments - * @retval IX_ETH_DB_FAIL incorrect property value or unknown error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertyGet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, IxEthDBPropertyType *type, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value) - * - * @brief Sets the value of a feature property - * - * Unlike @ref ixEthDBFeaturePropertyGet, this function operates only with read-write properties - * - * The currently supported properties and their corresponding features are as follows: - * - * - IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE (for IX_ETH_DB_VLAN_QOS): freezes the availability of traffic classes - * to the number of traffic classes currently in use - * - * Note that this function creates deep copies of the property values; once the function is invoked the client - * can free or reuse the memory area containing the original property value. - * - * Copy behavior for different property types is defined as follows: - * - * - IX_ETH_DB_INTEGER_PROPERTY - 4 bytes are copied from the source location - * - IX_ETH_DB_STRING_PROPERTY - the source string will be copied up to the NULL '\0' string terminator, maximum of 255 characters - * - IX_ETH_DB_MAC_ADDR_PROPERTY - 6 bytes are copied from the source location - * - IX_ETH_DB_BOOL_PROPERTY - 4 bytes are copied from the source location; the only allowed values are true (1L) and false (0L) - * - * @see ixEthDBFeaturePropertySet - * - * @warning IX_ETH_DB_QOS_QUEUE_CONFIGURATION_COMPLETE is provided for EthAcc internal use; - * do not attempt to set this property directly - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param feature @ref IxEthDBFeature [in] - EthDB feature for which the property is set - * @param property @ref IxEthDBProperty [in] - property identifier - * @param value void [in] - location where the property value is to be copied from - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid property identifier, value pointer, or invalid property value - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFeaturePropertySet(IxEthDBPortId portID, IxEthDBFeature feature, IxEthDBProperty property, void *value); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType) - * - * @brief Deletes a set of record types from the Ethernet Database - * - * This function deletes all the records of certain types (specified in the recordType filter) - * associated with a port. Additionally, the IX_ETH_DB_ALL_PORTS value can be used as port ID - * to indicate that the specified record types should be deleted for all the ports. - * - * The record type filter can be an ORed combination of the following types: - * - * Record types - * - IX_ETH_DB_FILTERING_RECORD - * - *
Filtering record
MAC address static/dynamic type age
- * - * - IX_ETH_DB_FILTERING_VLAN_RECORD - * - *
VLAN-enabled filtering record
MAC address static/dynamic type age 802.1Q tag
- * - * - IX_ETH_DB_WIFI_RECORD - * - *
WiFi header conversion record
MAC address optional gateway MAC address
- * - * - IX_ETH_DB_FIREWALL_RECORD - * - *
Firewall record
MAC address
- * - IX_ETH_DB_ALL_RECORD_TYPES - * - * Any combination of the above types is valid e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_FILTERING_VLAN_RECORD | IX_ETH_DB_FIREWALL_RECORD), - * - * although some might be redundant (it is not an error to do so) e.g. - * - * (IX_ETH_DB_FILTERING_RECORD | IX_ETH_DB_ALL_RECORD_TYPES) - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param recordType @ref IxEthDBRecordType [in] - record type filter - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid recordType filter - * - * @note If the record type filter contains any unrecognized value (hence the - * IX_ETH_DB_INVALID_ARG error value is returned) no actual records will be deleted. - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBDatabaseClear(IxEthDBPortId portID, IxEthDBRecordType recordType); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds an "Access Point to Station" record to the database, for 802.3 => 802.11 frame - * header conversion - * - * Frame header conversion is controlled by the set of MAC addresses - * added using @ref ixEthDBWiFiStationEntryAdd and @ref ixEthDBWiFiAccessPointEntryAdd. - * Conversion arguments are added using @ref ixEthDBWiFiFrameControlSet, - * @ref ixEthDBWiFiDurationIDSet and @ref ixEthDBWiFiBBSIDSet. - * - * Note that adding the same MAC address twice will not return an error - * (but will not accomplish anything either), while re-adding a record previously added - * as an "Access Point to Access Point" will migrate the record to the "Access Point - * to Station" type. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiStationEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr) - * - * @brief Adds an "Access Point to Access Point" record to the database - * - * @see ixEthDBWiFiStationEntryAdd - * - * Note that adding the same MAC address twice will simply overwrite the previously - * defined gateway MAC address value in the same record, if the record was previously of the - * "Access Point to Access Point" type. - * - * Re-adding a MAC address as "Access Point to Access Point", which was previously added as - * "Access Point to Station" will migrate the record type to "Access Point to Access Point" and - * record the gateway MAC address. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to add - * @param gatewayMacAddr @ref IxEthDBMacAddr [in] - MAC address of the gateway Access Point - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG macAddr is an invalid pointer - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or gatewayMacAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiAccessPointEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr, IxEthDBMacAddr *gatewayMacAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a WiFi station record - * - * This function removes both types of WiFi records ("Access Point to Station" and - * "Access Point to Access Point"). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to remove - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port is not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR specified address was not found in the database - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC address table for 802.3 => 802.11 frame header - * conversion to the NPE - * - * Note that the frame conversion MAC address table must be individually downloaded - * to each NPE for which the frame header conversion feature is enabled (i.e. it - * is not possible to specify IX_ETH_DB_ALL_PORTS). - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiConversionTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl) - * - * @brief Sets the GlobalFrameControl field - * - * The GlobalFrameControl field is a 2-byte value inserted in the Frame Control - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param frameControl UINT16 [in] - GlobalFrameControl value - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiFrameControlSet(IxEthDBPortId portID, UINT16 frameControl); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID) - * - * @brief Sets the GlobalDurationID field - * - * The GlobalDurationID field is a 2-byte value inserted in the Duration/ID - * field for all 802.3 to 802.11 frame header conversions - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param durationID UINT16 [in] - GlobalDurationID field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiDurationIDSet(IxEthDBPortId portID, UINT16 durationID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid) - * - * @brief Sets the BBSID field - * - * The BBSID field is a 6-byte value which - * identifies the infrastructure of the service set managed - * by the Access Point having the IXP400 as its processor. The value - * is written in the BBSID field of the 802.11 frame header. - * The BBSID value is the MAC address of the Access Point. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param bbsid @ref IxEthDBMacAddr [in] - pointer to 6 bytes containing the BSSID - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid bbsid pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE WiFi feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBWiFiBBSIDSet(IxEthDBPortId portID, IxEthDBMacAddr *bbsid); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked) - * - * @brief Sets the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL [in] - true to set the port as STP blocked, false to set it as unblocked - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateSet(IxEthDBPortId portID, BOOL blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked) - * - * @brief Retrieves the STP blocked/unblocked state for a port - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param blocked BOOL * [in] - set to true if the port is STP blocked, false otherwise - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid blocked pointer argument - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Spanning Tree Protocol feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBSpanningTreeBlockingStateGet(IxEthDBPortId portID, BOOL *blocked); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode) - * - * @brief Sets the firewall mode to use white or black listing - * - * When enabled, the NPE MAC address based firewall support operates in two modes: - * - * - white-list mode (MAC address based admission) - * - mode set to IX_ETH_DB_FIREWALL_WHITE_LIST - * - only packets originating from MAC addresses contained in the firewall address list - * are allowed on the Rx path - * - black-list mode (MAC address based blocking) - * - mode set to IX_ETH_DB_FIREWALL_BLACK_LIST - * - packets originating from MAC addresses contained in the firewall address list - * are discarded - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param mode @ref IxEthDBFirewallMode [in] - firewall mode (IX_ETH_DB_FIREWALL_WHITE_LIST or IX_ETH_DB_FIREWALL_BLACK_LIST) - * - * @note by default the firewall operates in black-list mode with an empty address - * list, hence it doesn't filter any packets - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_INVALID_ARGUMENT mode argument is not a valid firewall configuration mode - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error -*/ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallModeSet(IxEthDBPortId portID, IxEthDBFirewallMode mode); - -/** - * @ingroup IxEthDB - * - * @fn ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable) - * - * @brief Enables or disables invalid MAC address filtering - * - * According to IEEE802 it is illegal for a source address to be a multicast - * or broadcast address. If this feature is enabled the NPE inspects the source - * MAC addresses of incoming frames and discards them if invalid addresses are - * detected. - * - * By default this service is enabled, if the firewall feature is supported by the - * NPE image. - * - * @param portID ID of the port - * @param enable true to enable invalid MAC address filtering and false to disable it - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallInvalidAddressFilterEnable(IxEthDBPortId portID, BOOL enable); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Adds a MAC address to the firewall address list - * - * Note that adding the same MAC address twice will not return an error - * but will not actually accomplish anything. - * - * The firewall MAC address list has a limited number of entries; once - * the maximum number of entries has been reached this function will failed - * to add more addresses, returning IX_ETH_DB_NOMEM. - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be added - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NOMEM maximum number of records reached - * @retval IX_ETH_DB_BUSY lock condition or transaction in progress, try again later - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryAdd(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr) - * - * @brief Removes a MAC address from the firewall address list - * - * @param portID @ref IxEthDBPortId [in] - ID of the port - * @param macAddr @ref IxEthDBMacAddr [in] - MAC address to be removed - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR address not found - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallEntryRemove(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID) - * - * @brief Downloads the MAC firewall table to a port - * - * @param portID ID of the port - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID is not a valid port identifier - * @retval IX_ETH_DB_PORT_UNINITIALIZED port not initialized - * @retval IX_ETH_DB_FEATURE_UNAVAILABLE Firewall feature not enabled - * @retval IX_ETH_DB_FAIL unknown OS or NPE communication error - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBFirewallTableDownload(IxEthDBPortId portID); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field) - * - * @brief Adds a user-defined field to a database record - * - * This function associates a user-defined field to a database record. - * The user-defined field is passed as a (void *) parameter, hence it can be used - * for any purpose (such as identifying a structure). Retrieving the user-defined field from - * a record is done using @ref ixEthDBUserFieldGet. Note that EthDB never uses the user-defined - * field for any internal operation and it is not aware of the significance of its contents. The - * field is only stored as a pointer. - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * The user-defined field can be cleared using a NULL field parameter. - * - * @param recordType @ref IxEthDBRecordType [in] - type of record (can be IX_ETH_DB_FILTERING_RECORD, - * IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD or IX_ETH_DB_FIREWALL_RECORD) - * @param portID @ref IxEthDBPortId [in] - ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr @ref IxEthDBMacAddr * [in] - MAC address of the record - * @param vlanID @ref IxEthDBVlanId [in] - VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field void * [in] - user defined field - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr pointer argument - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldSet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void *field); - -/** - * @ingroup IxEthDB - * - * @fn IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portID, IxEthDBVlanId vlanID, void **field) - * - * @brief Retrieves a user-defined field from a database record - * - * The database record is identified using a combination of the given parameters, depending on the record type. - * All the record types require the record MAC address. - * - * - IX_ETH_DB_FILTERING_RECORD requires only the MAC address - * - IX_ETH_DB_VLAN_FILTERING_RECORD requires the MAC address and the VLAN ID - * - IX_ETH_DB_WIFI_RECORD requires the MAC address and the portID - * - IX_ETH_DB_FIREWALL_RECORD requires the MAC address and the portID - * - * Please note that if a parameter is not required it is completely ignored (it does not undergo parameter checking). - * - * If no user-defined field was registered with the specified record then NULL will be written - * at the location specified by field. - * - * @param recordType type of record (can be IX_ETH_DB_FILTERING_RECORD, IX_ETH_DB_FILTERING_VLAN_RECORD, IX_ETH_DB_WIFI_RECORD - * or IX_ETH_DB_FIREWALL_RECORD) - * @param portID ID of the port (required only for WIFI and FIREWALL records) - * @param macAddr MAC address of the record - * @param vlanID VLAN ID of the record (required only for FILTERING_VLAN records) - * @param field location to write the user defined field into - * - * @retval IX_ETH_DB_SUCCESS operation completed successfully - * @retval IX_ETH_DB_INVALID_PORT portID was required but it is not a valid port identifier - * @retval IX_ETH_DB_INVALID_ARG invalid macAddr or field pointer arguments - * @retval IX_ETH_DB_NO_SUCH_ADDR record not found - */ -IX_ETH_DB_PUBLIC -IxEthDBStatus ixEthDBUserFieldGet(IxEthDBRecordType recordType, IxEthDBMacAddr *macAddr, IxEthDBPortId portId, IxEthDBVlanId vlanID, void **field); - -/** - * @} - */ - -#endif /* IxEthDB_H */ diff --git a/drivers/net/npe/include/IxEthDBLocks_p.h b/drivers/net/npe/include/IxEthDBLocks_p.h deleted file mode 100644 index 91ab441b26e..00000000000 --- a/drivers/net/npe/include/IxEthDBLocks_p.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file IxEthAccDBLocks_p.h - * - * @brief Definition of transaction lock stacks and lock utility macros - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthAccDBLocks_p_H -#define IxEthAccDBLocks_p_H - -#include "IxOsPrintf.h" - -/* Lock and lock stacks */ -typedef struct -{ - IxOsalFastMutex* locks[MAX_LOCKS]; - UINT32 stackPointer, basePointer; -} LockStack; - -#define TRY_LOCK(mutex) \ - { \ - if (ixOsalFastMutexTryLock(mutex) != IX_SUCCESS) \ - { \ - return IX_ETH_DB_BUSY; \ - } \ - } - - -#define UNLOCK(mutex) { ixOsalFastMutexUnlock(mutex); } - -#define INIT_STACK(stack) \ - { \ - (stack)->basePointer = 0; \ - (stack)->stackPointer = 0; \ - } - -#define PUSH_LOCK(stack, lock) \ - { \ - if ((stack)->stackPointer == MAX_LOCKS) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on push, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_NOMEM; \ - } \ - \ - if (ixOsalFastMutexTryLock(lock) == IX_SUCCESS) \ - { \ - (stack)->locks[(stack)->stackPointer++] = (lock); \ - } \ - else \ - { \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - } - -#define POP_LOCK(stack) \ - { \ - ixOsalFastMutexUnlock((stack)->locks[--(stack)->stackPointer]); \ - } - -#define UNROLL_STACK(stack) \ - { \ - while ((stack)->stackPointer > (stack)->basePointer) \ - { \ - POP_LOCK(stack); \ - } \ - } - -#define SHIFT_STACK(stack) \ - { \ - if ((stack)->basePointer == MAX_LOCKS - 1) \ - { \ - ERROR_LOG("Ethernet DB: maximum number of elements in a lock stack has been exceeded on shift, heavy chaining?\n"); \ - UNROLL_STACK(stack); \ - \ - return IX_ETH_DB_BUSY; \ - } \ - \ - ixOsalFastMutexUnlock((stack)->locks[(stack)->basePointer++]); \ - } - -#endif /* IxEthAccDBLocks_p_H */ diff --git a/drivers/net/npe/include/IxEthDBLog_p.h b/drivers/net/npe/include/IxEthDBLog_p.h deleted file mode 100644 index b3576236ff4..00000000000 --- a/drivers/net/npe/include/IxEthDBLog_p.h +++ /dev/null @@ -1,203 +0,0 @@ -/** - * @file IxEthDBLog_p.h - * - * @brief definitions of log macros and log configuration - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#include - -#ifdef IX_UNIT_TEST -#define NULL_PRINT_ROUTINE(format, arg...) /* nothing */ -#else -#define NULL_PRINT_ROUTINE if(0) printf -#endif - -/*************************************************** - * Globals * - ***************************************************/ -/* safe to permanently leave these on */ -#define HAS_ERROR_LOG -#define HAS_ERROR_IRQ_LOG -#define HAS_WARNING_LOG - -/*************************************************** - * Log Configuration * - ***************************************************/ - -/* debug output can be turned on unless specifically - declared as a non-debug build */ -#ifndef NDEBUG - -#undef HAS_EVENTS_TRACE -#undef HAS_EVENTS_VERBOSE_TRACE - -#undef HAS_SUPPORT_TRACE -#undef HAS_SUPPORT_VERBOSE_TRACE - -#undef HAS_NPE_TRACE -#undef HAS_NPE_VERBOSE_TRACE -#undef HAS_DUMP_NPE_TREE - -#undef HAS_UPDATE_TRACE -#undef HAS_UPDATE_VERBOSE_TRACE - -#endif /* NDEBUG */ - - -/*************************************************** - * Log Macros * - ***************************************************/ - -/************** Globals ******************/ - -#ifdef HAS_ERROR_LOG - - #define ERROR_LOG printf - -#else - - #define ERROR_LOG NULL_PRINT_ROUTINE - -#endif - -#ifdef HAS_ERROR_IRQ_LOG - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_ERROR, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - -#else - - #define ERROR_IRQ_LOG(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif - -#ifdef HAS_WARNING_LOG - - #define WARNING_LOG printf - -#else - - #define WARNING_LOG NULL_PRINT_ROUTINE - -#endif - -/************** Events *******************/ - -#ifdef HAS_EVENTS_TRACE - - #define IX_ETH_DB_EVENTS_TRACE printf - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_EVENTS_VERBOSE_TRACE - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_EVENTS_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_EVENTS_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_EVENTS_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_IRQ_EVENTS_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_EVENTS_TRACE */ - -/************** Support *******************/ - -#ifdef HAS_SUPPORT_TRACE - - #define IX_ETH_DB_SUPPORT_TRACE printf - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_SUPPORT_VERBOSE_TRACE - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_SUPPORT_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_SUPPORT_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_SUPPORT_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_SUPPORT_TRACE */ - -/************** NPE Adaptor *******************/ - -#ifdef HAS_NPE_TRACE - - #define IX_ETH_DB_NPE_TRACE printf - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) ixOsalLog(IX_OSAL_LOG_LVL_MESSAGE, IX_OSAL_LOG_DEV_STDOUT, format, arg1, arg2, arg3, arg4, arg5, arg6) - - #ifdef HAS_NPE_VERBOSE_TRACE - - #define IX_ETH_DB_NPE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif /* HAS_NPE_VERBOSE_TRACE */ - -#else - - #define IX_ETH_DB_NPE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_VERBOSE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_NPE_IRQ_TRACE(format, arg1, arg2, arg3, arg4, arg5, arg6) /* nothing */ - -#endif /* HAS_NPE_TRACE */ - -#ifdef HAS_DUMP_NPE_TREE - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) ixEthELTDumpTree(eltBaseAddress, eltSize) - -#else - -#define IX_ETH_DB_NPE_DUMP_ELT(eltBaseAddress, eltSize) /* nothing */ - -#endif /* HAS_DUMP_NPE_TREE */ - -/************** Port Update *******************/ - -#ifdef HAS_UPDATE_TRACE - - #define IX_ETH_DB_UPDATE_TRACE printf - - #ifdef HAS_UPDATE_VERBOSE_TRACE - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE printf - - #else - - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - - #endif - -#else /* HAS_UPDATE_VERBOSE_TRACE */ - - #define IX_ETH_DB_UPDATE_TRACE NULL_PRINT_ROUTINE - #define IX_ETH_DB_UPDATE_VERBOSE_TRACE NULL_PRINT_ROUTINE - -#endif /* HAS_UPDATE_TRACE */ diff --git a/drivers/net/npe/include/IxEthDBMessages_p.h b/drivers/net/npe/include/IxEthDBMessages_p.h deleted file mode 100644 index 5907fd59e25..00000000000 --- a/drivers/net/npe/include/IxEthDBMessages_p.h +++ /dev/null @@ -1,234 +0,0 @@ -/** - * @file IxEthDBMessages_p.h - * - * @brief Definitions of NPE messages - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDBMessages_p_H -#define IxEthDBMessages_p_H - -#include -#include -#include "IxEthDB_p.h" - -/* events watched by the Eth event processor */ -#define IX_ETH_DB_MIN_EVENT_ID (IX_ETHNPE_EDB_GETMACADDRESSDATABASE) -#define IX_ETH_DB_MAX_EVENT_ID (IX_ETHNPE_PC_SETAPMACTABLE) - -/* macros to fill and extract data from NPE messages - place any endian conversions here */ -#define RESET_ELT_MESSAGE(message) { memset((void *) &(message), 0, sizeof((message))); } -#define NPE_MSG_ID(msg) ((msg).data[0] >> 24) - -#define FILL_SETPORTVLANTABLEENTRY_MSG(message, portID, setOffset, vlanMembershipSet, ttiSet) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY << 24) | (portID << 16) | (setOffset * 2); \ - message.data[1] = (vlanMembershipSet << 8) | ttiSet; \ - } while (0); - -#define FILL_SETPORTVLANTABLERANGE_MSG(message, portID, offset, length, zone) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE << 24 | portID << 16 | offset << 9 | length << 1; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETDEFAULTRXVID_MSG(message, portID, tpid, vlanTag) \ - do { \ - message.data[0] = (IX_ETHNPE_VLAN_SETDEFAULTRXVID << 24) \ - | (portID << 16); \ - \ - message.data[1] = (tpid << 16) | vlanTag; \ - } while (0); - -#define FILL_SETRXTAGMODE_MSG(message, portID, filterMode, tagMode) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXTAGMODE << 24 \ - | portID << 16 \ - | filterMode << 2 \ - | tagMode; \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETRXQOSENTRY(message, portID, classIndex, trafficClass, aqmQueue) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETRXQOSENTRY << 24 \ - | portID << 16 \ - | classIndex; \ - \ - message.data[1] = trafficClass << 24 \ - | 0x1 << 23 \ - | aqmQueue << 16 \ - | aqmQueue << 4; \ - } while (0); - -#define FILL_SETPORTIDEXTRACTIONMODE(message, portID, enable) \ - do { \ - message.data[0] = IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE << 24 \ - | portID << 16 \ - | (enable ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - - -#define FILL_SETBLOCKINGSTATE_MSG(message, portID, blocked) \ - do { \ - message.data[0] = IX_ETHNPE_STP_SETBLOCKINGSTATE << 24 \ - | portID << 16 \ - | (blocked ? 0x1 : 0x0); \ - \ - message.data[1] = 0; \ - } while (0); - -#define FILL_SETBBSID_MSG(message, portID, bbsid) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETBBSID << 24 \ - | portID << 16 \ - | bbsid->macAddress[0] << 8 \ - | bbsid->macAddress[1]; \ - \ - message.data[1] = bbsid->macAddress[2] << 24 \ - | bbsid->macAddress[3] << 16 \ - | bbsid->macAddress[4] << 8 \ - | bbsid->macAddress[5]; \ - } while (0); - -#define FILL_SETFRAMECONTROLDURATIONID(message, portID, frameControlDurationID) \ - do { \ - message.data[0] = (IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID << 24) | (portID << 16); \ - message.data[1] = frameControlDurationID; \ - } while (0); - -#define FILL_SETAPMACTABLE_MSG(message, zone) \ - do { \ - message.data[0] = IX_ETHNPE_PC_SETAPMACTABLE << 24 \ - | 0 << 8 /* always use index 0 */ \ - | 64; /* 32 entries, 8 bytes each, 4 bytes in a word */ \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETFIREWALLMODE_MSG(message, portID, epDelta, mode, address) \ - do { \ - message.data[0] = IX_ETHNPE_FW_SETFIREWALLMODE << 24 \ - | portID << 16 \ - | (epDelta & 0xFF) << 8 \ - | mode; \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_SETMACADDRESSDATABASE_MSG(message, portID, epDelta, blockCount, address) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETMACADDRESSSDATABASE << 24 \ - | (epDelta & 0xFF) << 8 \ - | (blockCount & 0xFF); \ - \ - message.data[1] = (UINT32) address; \ - } while (0); - -#define FILL_GETMACADDRESSDATABASE(message, npeId, zone) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_GETMACADDRESSDATABASE << 24; \ - message.data[1] = (UINT32) zone; \ - } while (0); - -#define FILL_SETMAXFRAMELENGTHS_MSG(message, portID, maxRxFrameSize, maxTxFrameSize) \ - do { \ - message.data[0] = IX_ETHNPE_SETMAXFRAMELENGTHS << 24 \ - | portID << 16 \ - | ((maxRxFrameSize + 63) / 64) << 8 /* max Rx 64-byte blocks */ \ - | (maxTxFrameSize + 63) / 64; /* max Tx 64-byte blocks */ \ - \ - message.data[1] = maxRxFrameSize << 16 | maxTxFrameSize; \ - } while (0); - -#define FILL_SETPORTADDRESS_MSG(message, portID, macAddress) \ - do { \ - message.data[0] = IX_ETHNPE_EDB_SETPORTADDRESS << 24 \ - | portID << 16 \ - | macAddress[0] << 8 \ - | macAddress[1]; \ - \ - message.data[1] = macAddress[2] << 24 \ - | macAddress[3] << 16 \ - | macAddress[4] << 8 \ - | macAddress[5]; \ - } while (0); - -/* access to a MAC node in the NPE tree */ -#define NPE_NODE_BYTE(eltNodeAddr, offset) (((UINT8 *) (eltNodeAddr))[offset]) - -/* browsing of the implicit linear binary tree structure of the NPE tree */ -#define LEFT_CHILD_OFFSET(offset) ((offset) << 1) -#define RIGHT_CHILD_OFFSET(offset) (((offset) << 1) + 1) - -#define IX_EDB_FLAGS_ACTIVE (0x2) -#define IX_EDB_FLAGS_VALID (0x1) -#define IX_EDB_FLAGS_RESERVED (0xfc) -#define IX_EDB_FLAGS_INACTIVE_VALID (0x1) - -#define IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET (6) -#define IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_WIFI_INDEX_OFFSET (6) -#define IX_EDB_NPE_NODE_WIFI_FLAGS_OFFSET (7) -#define IX_EDB_NPE_NODE_FW_FLAGS_OFFSET (1) -#define IX_EDB_NPE_NODE_FW_RESERVED_OFFSET (6) -#define IX_EDB_NPE_NODE_FW_ADDR_OFFSET (2) - -#define IX_EDB_NPE_NODE_VALID(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_VALID) != 0) -#define IX_EDB_NPE_NODE_ACTIVE(address) ((NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_FLAGS_OFFSET) & IX_EDB_FLAGS_ACTIVE) != 0) -#define IX_EDB_NPE_NODE_PORT_ID(address) (NPE_NODE_BYTE(address, IX_EDB_NPE_NODE_ELT_PORT_ID_OFFSET)) - -/* macros to send messages to the NPEs */ -#define IX_ETHDB_ASYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageSend(npeId, msg, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#define IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result) \ - do { \ - result = ixNpeMhMessageWithResponseSend(npeId, msg, msg.data[0] >> 24, ixEthDBNpeMsgAck, IX_NPEMH_SEND_RETRIES_DEFAULT); \ - \ - if (result == IX_SUCCESS) \ - { \ - result = ixOsalMutexLock(&ixEthDBPortInfo[IX_ETH_DB_NPE_TO_PORT_ID(npeId)].npeAckLock, IX_ETH_DB_NPE_TIMEOUT); \ - \ - if (result != IX_SUCCESS) \ - { \ - ERROR_LOG("DB: NPE failed to respond within %dms\n", IX_ETH_DB_NPE_TIMEOUT); \ - } \ - } \ - else \ - { \ - ERROR_LOG("DB: Failed to send NPE message\n"); \ - } \ - } while (0); - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistory[IX_ETH_DB_NPE_MSG_HISTORY_DEPTH][2]; -extern IX_ETH_DB_PUBLIC UINT32 npeMsgHistoryLen; -#endif - -#define IX_ETHDB_SEND_NPE_MSG(npeId, msg, result) { LOG_NPE_MSG(msg); IX_ETHDB_SYNC_SEND_NPE_MSG(npeId, msg, result); } - -#endif /* IxEthDBMessages_p_H */ diff --git a/drivers/net/npe/include/IxEthDBPortDefs.h b/drivers/net/npe/include/IxEthDBPortDefs.h deleted file mode 100644 index 9f5e4678329..00000000000 --- a/drivers/net/npe/include/IxEthDBPortDefs.h +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file IxEthDBPortDefs.h - * - * @brief Public definition of the ports and port capabilities - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet Database Port Definitions (IxEthDBPortDefs) - * - * @brief IXP400 Public definition of the ports and port capabilities - * - * @{ - */ - -#ifndef IxEthDBPortDefs_H -#define IxEthDBPortDefs_H - -/** - * @brief Port types - currently only Ethernet NPEs are recognized as specific types - * All other (user-defined) ports must be specified as IX_ETH_GENERIC - */ -typedef enum -{ - IX_ETH_GENERIC = 0, /**< generic ethernet port */ - IX_ETH_NPE /**< specific Ethernet NPE */ -} IxEthDBPortType; - -/** - * @brief Port capabilities - used by ixEthAccDatabaseMaintenance to decide whether it - * should manually age entries or not depending on the port capabilities. - * - * Ethernet NPEs have aging capabilities, meaning that they will age the entries - * automatically (by themselves).*/ -typedef enum -{ - IX_ETH_NO_CAPABILITIES = 0, /**< no aging capabilities */ - IX_ETH_ENTRY_AGING = 0x1 /**< aging capabilities present */ -} IxEthDBPortCapability; - -/** - * @brief Port Definition - a structure contains the Port type and capabilities - */ -typedef struct -{ - IxEthDBPortType type; - IxEthDBPortCapability capabilities; -} IxEthDBPortDefinition; - -/** - * @brief Port definitions structure, indexed on the port ID - * @warning Ports 0 and 1 are used by the Ethernet access component therefore - * it is essential to be left untouched. Port 2 here (WAN) is given as - * an example port. The NPE firmware also assumes the NPE B to be - * the port 0 and NPE C to be the port 1. - * - * @note that only 32 ports (0..31) are supported by EthDB - */ -static const IxEthDBPortDefinition ixEthDBPortDefinitions[] = -{ - /* id type capabilities */ - { /* 0 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE B */ - { /* 1 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE C */ - { /* 2 */ IX_ETH_NPE, IX_ETH_NO_CAPABILITIES }, /* Ethernet NPE A */ - { /* 3 */ IX_ETH_GENERIC, IX_ETH_NO_CAPABILITIES }, /* WAN port */ -}; - -/** - * @def IX_ETH_DB_NUMBER_OF_PORTS - * @brief number of supported ports - */ -#define IX_ETH_DB_NUMBER_OF_PORTS ARRAY_SIZE(ixEthDBPortDefinitions) - -/** - * @def IX_ETH_DB_UNKNOWN_PORT - * @brief definition of an unknown port - */ -#define IX_ETH_DB_UNKNOWN_PORT (0xff) - -/** - * @def IX_ETH_DB_ALL_PORTS - * @brief Special port ID indicating all the ports - * @note This port ID can be used only by a subset of the EthDB API; each - * function specifically mentions whether this is a valid parameter as the port ID - */ -#define IX_ETH_DB_ALL_PORTS (IX_ETH_DB_NUMBER_OF_PORTS + 1) - -/** - * @def IX_ETH_DB_PORTS_ASSERTION - * @brief catch invalid port definitions (<2) with a - * compile-time assertion resulting in a duplicate case error. - */ -#define IX_ETH_DB_PORTS_ASSERTION { switch(0) { case 0 : ; case 1 : ; case IX_ETH_DB_NUMBER_OF_PORTS : ; }} - -/** - * @def IX_ETH_DB_CHECK_PORT(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized - */ -#define IX_ETH_DB_CHECK_PORT(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - \ - if (!ixEthDBPortInfo[(portID)].enabled) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ -} - -/** - * @def IX_ETH_DB_CHECK_PORT_ALL(portID) - * @brief safety checks to verify whether the port is invalid or uninitialized; - * tolerates the use of IX_ETH_DB_ALL_PORTS - */ -#define IX_ETH_DB_CHECK_PORT_ALL(portID) \ -{ \ - if ((portID) != IX_ETH_DB_ALL_PORTS) \ - IX_ETH_DB_CHECK_PORT(portID) \ -} - -#endif /* IxEthDBPortDefs_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDBQoS.h b/drivers/net/npe/include/IxEthDBQoS.h deleted file mode 100644 index 6276930dc74..00000000000 --- a/drivers/net/npe/include/IxEthDBQoS.h +++ /dev/null @@ -1,130 +0,0 @@ -/** - * @file IxEthDBQoS.h - * - * @brief Public definitions for QoS traffic classes - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxEthDBPortDefs IXP400 Ethernet QoS definitions - * - * @brief IXP00 Public definitions for QoS traffic classes - * - * @{ - */ - -#ifndef IxEthDBQoS_H -#define IxEthDBQoS_H - -/** - * @def IX_ETH_DB_QUEUE_UNAVAILABLE - * @brief alias to indicate a queue (traffic class) is not available - */ -#define IX_ETH_DB_QUEUE_UNAVAILABLE (0) - -#ifndef IX_IEEE802_1Q_QOS_PRIORITY_COUNT -/** - * @def IX_IEEE802_1Q_QOS_PRIORITY_COUNT - * @brief number of QoS priorities, according to IEEE 802.1Q - */ -#define IX_IEEE802_1Q_QOS_PRIORITY_COUNT (8) -#endif - -/** - * @brief array containing all the supported traffic class configurations - */ -static const -UINT8 ixEthDBQueueAssignments[][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = -{ - { 4, 5, 6, 7, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 15, 16, 17, 18, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 11, 23, 26, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE, IX_ETH_DB_QUEUE_UNAVAILABLE }, - { 4, 5, 6, 7, 8, 9, 10, 11 } - /* add here all other cases of queue configuration structures and update ixEthDBTrafficClassDefinitions to use them */ -}; - -/** - * @brief value used to index the NPE A functionality ID in the traffic class definition table - */ -#define IX_ETH_DB_NPE_A_FUNCTIONALITY_ID_INDEX (0) - -/** - * @brief value used to index the traffic class count in the traffic class definition table - */ -#define IX_ETH_DB_TRAFFIC_CLASS_COUNT_INDEX (1) - -/** - * @brief value used to index the queue assignment index in the traffic class definition table - */ -#define IX_ETH_DB_QUEUE_ASSIGNMENT_INDEX (2) - -/** - * @brief traffic class definitions - * - * This array contains the default traffic class definition configuration, - * as well as any special cases dictated by the functionality ID of NPE A. - * - * The default case should not be removed (otherwise the Ethernet - * components will assert a fatal failure on initialization). - */ -static const -UINT8 ixEthDBTrafficClassDefinitions[][3] = -{ - /* NPE A functionality ID | traffic class count | queue assignment index (points to the queue enumeration in ixEthDBQueueAssignments) */ - { 0x00, 4, 0 }, /* default case - DO NOT REMOVE */ - { 0x04, 4, 1 }, /* NPE A image ID 0.4.0.0 */ - { 0x09, 3, 2 }, /* NPE A image ID 0.9.0.0 */ - { 0x80, 8, 3 }, /* NPE A image ID 10.80.02.0 */ - { 0x81, 8, 3 }, /* NPE A image ID 10.81.02.0 */ - { 0x82, 8, 3 } /* NPE A image ID 10.82.02.0 */ -}; - -/** - * @brief IEEE 802.1Q recommended QoS Priority => traffic class maps - * - * @verbatim - Number of available traffic classes - 1 2 3 4 5 6 7 8 - QoS Priority - 0 0 0 0 1 1 1 1 2 - 1 0 0 0 0 0 0 0 0 - 2 0 0 0 0 0 0 0 1 - 3 0 0 0 1 1 2 2 3 - 4 0 1 1 2 2 3 3 4 - 5 0 1 1 2 3 4 4 5 - 6 0 1 2 3 4 5 5 6 - 7 0 1 2 3 4 5 6 7 - - @endverbatim - */ -static const -UINT8 ixEthIEEE802_1QUserPriorityToTrafficClassMapping[IX_IEEE802_1Q_QOS_PRIORITY_COUNT][IX_IEEE802_1Q_QOS_PRIORITY_COUNT] = - { - { 0, 0, 0, 0, 0, 0, 0, 0 }, /* 1 traffic class available */ - { 0, 0, 0, 0, 1, 1, 1, 1 }, /* 2 traffic classes available */ - { 0, 0, 0, 0, 1, 1, 2, 2 }, /* 3 traffic classes available */ - { 1, 0, 0, 1, 2, 2, 3, 3 }, /* 4 traffic classes available */ - { 1, 0, 0, 1, 2, 3, 4, 4 }, /* 5 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 5 }, /* 6 traffic classes available */ - { 1, 0, 0, 2, 3, 4, 5, 6 }, /* 7 traffic classes available */ - { 2, 0, 1, 3, 4, 5, 6, 7 } /* 8 traffic classes available */ - }; - -#endif /* IxEthDBQoS_H */ - -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthDB_p.h b/drivers/net/npe/include/IxEthDB_p.h deleted file mode 100644 index ddc10a57890..00000000000 --- a/drivers/net/npe/include/IxEthDB_p.h +++ /dev/null @@ -1,686 +0,0 @@ -/** - * @file IxEthDB_p.h - * - * @brief Private MAC learning API - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthDB_p_H -#define IxEthDB_p_H - -#include -#include -#include -#include -#include - -#include "IxEthDBMessages_p.h" -#include "IxEthDBLog_p.h" - -#if (CPU==SIMSPARCSOLARIS) - -/* when running unit tests intLock() won't protect the event queue so we lock it manually */ -#define TEST_FIXTURE_LOCK_EVENT_QUEUE { ixOsalMutexLock(&eventQueueLock, IX_OSAL_WAIT_FOREVER); } -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE { ixOsalMutexUnlock(&eventQueueLock); } - -#else - -#define TEST_FIXTURE_LOCK_EVENT_QUEUE /* nothing */ -#define TEST_FIXTURE_UNLOCK_EVENT_QUEUE /* nothing */ - -#endif /* #if(CPU==SIMSPARCSOLARIS) */ - -#ifndef IX_UNIT_TEST - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER /* nothing */ -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT /* nothing */ - -#else - -extern int dbAccessCounter; -extern int overflowEvent; - -#define TEST_FIXTURE_INCREMENT_DB_CORE_ACCESS_COUNTER { dbAccessCounter++; } -#define TEST_FIXTURE_MARK_OVERFLOW_EVENT { overflowEvent = 1; } - -#endif - -/* code readability markers */ -#define __mempool__ /* memory pool marker */ -#define __lock__ /* hash write locking marker */ -#define __smartpointer__ /* smart pointer marker - warning: use only clone() when duplicating! */ -#define __alignment__ /* marker for data used only as alignment zones */ - -/* constants */ -#define IX_ETH_DB_NPE_TIMEOUT (100) /* NPE response timeout, in ms */ - -/** - * number of hash table buckets - * it should be at least 8x the predicted number of entries for performance - * each bucket needs 8 bytes - */ -#define NUM_BUCKETS (8192) - -/** - * number of hash table buckets to preload when incrementing bucket iterator - * = two cache lines - */ -#define IX_ETHDB_CACHE_LINE_AHEAD (2) - -#define IX_ETHDB_BUCKETPTR_AHEAD ((IX_ETHDB_CACHE_LINE_AHEAD * IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - -#define IX_ETHDB_BUCKET_INDEX_MASK (((IX_OSAL_CACHE_LINE_SIZE)/sizeof(void *)) - 1) - -/* locks */ -#define MAX_LOCKS (20) /**< maximum number of locks used simultaneously, do not tamper with */ - -/* learning tree constants */ -#define INITIAL_ELT_SIZE (8) /**< initial byte size of tree (empty unused root size) */ -#define MAX_ELT_SIZE (512) /**< maximum number of entries (includes unused root) */ -#define MAX_GW_SIZE (32) /**< maximum number of gateway entries (including unused root) */ -#define MAX_FW_SIZE (32) /**< maximum number of firewall entries (including unused root) */ -#define ELT_ENTRY_SIZE (8) /**< entry size, in bytes */ -#define ELT_ROOT_OFFSET (ELT_ENTRY_SIZE) /**< tree root offset, in bytes - node preceeding root is unused */ -#define FULL_ELT_BYTE_SIZE (MAX_ELT_SIZE * ELT_ENTRY_SIZE) /**< full size of tree, in bytes, including unused root */ -#define FULL_GW_BYTE_SIZE (MAX_GW_SIZE * ELT_ENTRY_SIZE) /**< full size of gateway list, in bytes, including unused root */ -#define FULL_FW_BYTE_SIZE (MAX_FW_SIZE * ELT_ENTRY_SIZE) /**< full size of firewall table, in bytes, including unused root */ - -/* maximum size of the VLAN table: - * 4096 bits (one per VLAN) - * 8 bits in one byte - * interleaved VLAN membership and VLAN TTI (*2) */ -#define FULL_VLAN_BYTE_SIZE (4096 / 8 * 2) - -/* upper 9 bits used as set index, lower 3 bits as byte index */ -#define VLAN_SET_OFFSET(vlanID) ((vlanID) >> 3) -#define VLAN_SET_MASK(vlanID) (0x7 - ((vlanID) & 0x7)) - -/* Update zone definitions */ -#define NPE_TREE_MEM_SIZE (4096) /* ((511 entries + 1 unused root) * 8 bytes/entry) */ - -/* check the above value, we rely on 4k */ -#if NPE_TREE_MEM_SIZE != 4096 - #error NPE_TREE_MEM_SIZE is not defined to 4096 bytes! -#endif - -/* Size Filtering limits (Jumbo frame filtering) */ -#define IX_ETHDB_MAX_FRAME_SIZE 65535 /* other ports than NPE ports */ -#define IX_ETHDB_MIN_FRAME_SIZE 1 /* other ports than NPE ports */ -#define IX_ETHDB_MAX_NPE_FRAME_SIZE 16320 /* NPE ports firmware limit */ -#define IX_ETHDB_MIN_NPE_FRAME_SIZE 1 /* NPE ports firmware limit */ -#define IX_ETHDB_DEFAULT_FRAME_SIZE 1522 - -/* memory management pool sizes */ - -/* - * Note: - * - * NODE_POOL_SIZE controls the maximum number of elements in the database at any one time. - * It should be large enough to cover all the search trees of all the ports simultaneously. - * - * MAC_POOL_SIZE should be higher than NODE_POOL_SIZE by at least the total number of MAC addresses - * possible to be held at any time in all the ports. - * - * TREE_POOL_SIZE should follow the same guideline as for MAC_POOL_SIZE. - * - * The database structure described here (2000/4000/4000) is enough for two NPEs holding at most 511 - * entries each plus one PCI NIC holding at most 900 entries. - */ - -#define NODE_POOL_SIZE (2000) /**< number of HashNode objects - also master number of elements in the database; each entry has 16 bytes */ -#define MAC_POOL_SIZE (4000) /**< number of MacDescriptor objects; each entry has 28 bytes */ -#define TREE_POOL_SIZE (4000) /**< number of MacTreeNode objects; each entry has 16 bytes */ - -/* retry policies */ -#define BUSY_RETRY_ENABLED (true) /**< if set to true the API will retry automatically calls returning BUSY */ -#define FOREVER_RETRY (true) /**< if set to true the API will retry forever BUSY calls */ -#define MAX_RETRIES (400) /**< upper retry limit - used only when FOREVER_RETRY is false */ -#define BUSY_RETRY_YIELD (5) /**< ticks to yield for every failed retry */ - -/* event management */ -#define EVENT_QUEUE_SIZE (500) /**< size of the sink collecting events from the Message Handler FIFO */ -#define EVENT_PROCESSING_LIMIT (100) /**< batch processing control size (how many events are extracted from the queue at once) */ - -/* MAC descriptors */ -#define STATIC_ENTRY (true) -#define DYNAMIC_ENTRY (false) - -/* age reset on next maintenance - incrementing by 1 will reset to 0 */ -#define AGE_RESET (0xFFFFFFFF) - -/* dependency maps */ -#define EMPTY_DEPENDENCY_MAP (0) - -/* trees */ -#define RIGHT (1) -#define LEFT (-1) - -/* macros */ -#define IX_ETH_DB_CHECK_PORT_EXISTS(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ -} - -#define IX_ETH_DB_CHECK_PORT_INITIALIZED(portID) \ -{ \ - if ((portID) >= IX_ETH_DB_NUMBER_OF_PORTS) \ - { \ - return IX_ETH_DB_INVALID_PORT; \ - } \ - else \ - { \ - if (!ixEthDBPortInfo[portID].initialized) \ - { \ - return IX_ETH_DB_PORT_UNINITIALIZED; \ - } \ - } \ -} - -/* single NPE check */ -#define IX_ETH_DB_CHECK_SINGLE_NPE(portID) \ - if (ixEthDBSingleEthNpeCheck(portID) != IX_ETH_DB_SUCCESS) \ - { \ - WARNING_LOG("EthDB: port ID %d is unavailable\n",(UINT32) portID); \ - \ - return IX_ETH_DB_INVALID_PORT; \ - } - -/* feature check */ -#define IX_ETH_DB_CHECK_FEATURE(portID, feature) \ - if ((ixEthDBPortInfo[portID].featureStatus & feature) == 0) \ - { \ - return IX_ETH_DB_FEATURE_UNAVAILABLE; \ - } - -/* busy retrying */ -#define BUSY_RETRY(functionCall) \ - { \ - UINT32 retries = 0; \ - IxEthDBStatus br_result; \ - \ - while ((br_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (br_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -#define BUSY_RETRY_WITH_RESULT(functionCall, brwr_result) \ - { \ - UINT32 retries = 0; \ - \ - while ((brwr_result = functionCall) == IX_ETH_DB_BUSY \ - && BUSY_RETRY_ENABLED && (FOREVER_RETRY || ++retries < MAX_RETRIES)) { ixOsalSleep(BUSY_RETRY_YIELD); }; \ - \ - if ((!FOREVER_RETRY && retries == MAX_RETRIES) || (brwr_result == IX_ETH_DB_FAIL)) \ - {\ - ERROR_LOG("Ethernet Learning Database Error: BUSY_RETRY_WITH_RESULT failed at %s:%d\n", __FILE__, __LINE__); \ - }\ - } - -/* iterators */ -#define IS_ITERATOR_VALID(iteratorPtr) ((iteratorPtr)->node != NULL) - -/* dependency port maps */ - -/* Warning: if port indexing starts from 1 replace (portID) with (portID - 1) in DEPENDENCY_MAP (and make sure IX_ETH_DB_NUMBER_OF_PORTS is big enough) */ - -/* gives an empty dependency map */ -#define SET_EMPTY_DEPENDENCY_MAP(map) { int i = 0; for (; i < 32 ; i++) map[i] = 0; } - -#define IS_EMPTY_DEPENDENCY_MAP(result, map) { int i = 0 ; result = true; for (; i < 32 ; i++) if (map[i] != 0) { result = false; break; }} - -/** - * gives a map consisting only of 'portID' - */ -#define SET_DEPENDENCY_MAP(map, portID) {SET_EMPTY_DEPENDENCY_MAP(map); map[portID >> 3] = 1 << (portID & 0x7);} - -/** - * gives a map resulting from joining map1 and map2 - */ -#define JOIN_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] | map2[i]; } - -/** - * gives the map resulting from joining portID and map - */ -#define JOIN_PORT_TO_MAP(map, portID) { map[portID >> 3] |= 1 << (portID & 0x7); } - -/** - * gives the map resulting from excluding portID from map - */ -#define EXCLUDE_PORT_FROM_MAP(map, portID) { map[portID >> 3] &= ~(1 << (portID & 0x7); } - -/** - * returns true if map1 is a subset of map2 and false otherwise - */ -#define IS_MAP_SUBSET(result, map1, map2) { int i = 0; result = true; for (; i < 32 ; i++) if ((map1[i] | map2[i]) != map2[i]) result = false; } - -/** - * returns true is portID is part of map and false otherwise - */ -#define IS_PORT_INCLUDED(portID, map) ((map[portID >> 3] & (1 << (portID & 0x7))) != 0) - -/** - * returns the difference between map1 and map2 (ports included in map1 and not included in map2) - */ -#define DIFF_MAPS(map, map1, map2) { int i = 0; for (; i < 32 ; i++) map[i] = map1[i] ^ (map1[i] & map2[i]); } - -/** - * returns true if the maps collide (have at least one port in common) and false otherwise - */ -#define MAPS_COLLIDE(result, map1, map2) { int i = 0; result = false; for (; i < 32 ; i++) if ((map1[i] & map2[i]) != 0) result = true; } - -/* size (number of ports) of a dependency map */ -#define GET_MAP_SIZE(map, size) { int i = 0, b = 0; size = 0; for (; i < 32 ; i++) { char y = map[i]; for (; b < 8 && (y >>= 1); b++) size += (y & 1); }} - -/* copy map2 into map1 */ -#define COPY_DEPENDENCY_MAP(map1, map2) { memcpy (map1, map2, sizeof (map1)); } - -/* definition of a port map size/port number which cannot be reached (we support at most 32 ports) */ -#define MAX_PORT_SIZE (0xFF) -#define MAX_PORT_NUMBER (0xFF) - -#define IX_ETH_DB_CHECK_REFERENCE(ptr) { if ((ptr) == NULL) { return IX_ETH_DB_INVALID_ARG; } } -#define IX_ETH_DB_CHECK_MAP(portID, map) { if (!IS_PORT_INCLUDED(portID, map)) { return IX_ETH_DB_INVALID_ARG; } } - -/* event queue macros */ -#define EVENT_QUEUE_WRAP(offset) ((offset) >= EVENT_QUEUE_SIZE ? (offset) - EVENT_QUEUE_SIZE : (offset)) - -#define CAN_ENQUEUE(eventQueuePtr) ((eventQueuePtr)->length < EVENT_QUEUE_SIZE) - -#define QUEUE_HEAD(eventQueuePtr) (&(eventQueuePtr)->queue[EVENT_QUEUE_WRAP((eventQueuePtr)->base + (eventQueuePtr)->length)]) - -#define QUEUE_TAIL(eventQueuePtr) (&(eventQueuePtr)->queue[(eventQueuePtr)->base]) - -#define PUSH_UPDATE_QUEUE(eventQueuePtr) { (eventQueuePtr)->length++; } - -#define SHIFT_UPDATE_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = EVENT_QUEUE_WRAP((eventQueuePtr)->base + 1); \ - (eventQueuePtr)->length--; \ - } - -#define RESET_QUEUE(eventQueuePtr) \ - { \ - (eventQueuePtr)->base = 0; \ - (eventQueuePtr)->length = 0; \ - } - -/* node stack macros - used to browse a tree without using a recursive function */ -#define NODE_STACK_INIT(stack) { (stack)->nodeCount = 0; } -#define NODE_STACK_PUSH(stack, node, offset) { (stack)->nodes[(stack)->nodeCount] = (node); (stack)->offsets[(stack)->nodeCount++] = (offset); } -#define NODE_STACK_POP(stack, node, offset) { (node) = (stack)->nodes[--(stack)->nodeCount]; offset = (stack)->offsets[(stack)->nodeCount]; } -#define NODE_STACK_NONEMPTY(stack) ((stack)->nodeCount != 0) - -#ifndef IX_NDEBUG -#define IX_ETH_DB_NPE_MSG_HISTORY_DEPTH (100) -#define LOG_NPE_MSG(msg) \ - do { \ - UINT32 npeMsgHistoryIndex = (npeMsgHistoryLen++) % IX_ETH_DB_NPE_MSG_HISTORY_DEPTH; \ - npeMsgHistory[npeMsgHistoryIndex][0] = msg.data[0]; \ - npeMsgHistory[npeMsgHistoryIndex][1] = msg.data[1]; \ - } while (0); -#else -#define LOG_NPE_MSG() /* nothing */ -#endif - -/* ----------- Data -------------- */ - -/* typedefs */ - -typedef UINT32 (*HashFunction)(void *entity); -typedef BOOL (*MatchFunction)(void *reference, void *entry); -typedef void (*FreeFunction)(void *entry); - -/** - * basic component of a hash table - */ -typedef struct HashNode_t -{ - void *data; /**< specific data */ - struct HashNode_t *next; /**< used for bucket chaining */ - - __mempool__ struct HashNode_t *nextFree; /**< memory pool management */ - - __lock__ IxOsalFastMutex lock; /**< node lock */ -} HashNode; - -/** - * @brief hash table iterator definition - * - * an iterator is an object which can be used - * to browse a hash table - */ -typedef struct -{ - UINT32 bucketIndex; /**< index of the currently iterated bucket */ - HashNode *previousNode; /**< reference to the previously iterated node within the current bucket */ - HashNode *node; /**< reference to the currently iterated node */ -} HashIterator; - -/** - * definition of a MAC descriptor (a database record) - */ - -typedef enum -{ - IX_ETH_DB_WIFI_AP_TO_STA = 0x0, - IX_ETH_DB_WIFI_AP_TO_AP = 0x1 -} IxEthDBWiFiRecordType; - -typedef union -{ - struct - { - UINT32 age; - BOOL staticEntry; /**< true if this address is static (doesn't age) */ - } filteringData; - - struct - { - UINT32 age; - BOOL staticEntry; - UINT32 ieee802_1qTag; - } filteringVlanData; - - struct - { - IxEthDBWiFiRecordType type; /**< AP_TO_AP (0x1) or AP_TO_STA (0x0) */ - UINT32 gwAddressIndex; /**< used only when linearizing the entries for NPE usage */ - UINT8 gwMacAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved2[2]; - } wifiData; -} IxEthDBRecordData; - -typedef struct MacDescriptor_t -{ - UINT8 macAddress[IX_IEEE803_MAC_ADDRESS_SIZE]; - - __alignment__ UINT8 reserved1[2]; - - UINT32 portID; - IxEthDBRecordType type; - IxEthDBRecordData recordData; - - /* used for internal operations, such as NPE linearization */ - void *internal; - - /* custom user data */ - void *user; - - __mempool__ struct MacDescriptor_t *nextFree; /**< memory pool management */ - __smartpointer__ UINT32 refCount; /**< smart pointer reference counter */ -} MacDescriptor; - -/** - * hash table definition - */ -typedef struct -{ - HashNode *hashBuckets[NUM_BUCKETS]; - UINT32 numBuckets; - - __lock__ IxOsalFastMutex bucketLocks[NUM_BUCKETS]; - - HashFunction entryHashFunction; - MatchFunction *matchFunctions; - FreeFunction freeFunction; -} HashTable; - -typedef enum -{ - IX_ETH_DB_MAC_KEY = 1, - IX_ETH_DB_MAC_PORT_KEY = 2, - IX_ETH_DB_MAC_VLAN_KEY = 3, - IX_ETH_DB_MAX_KEY_INDEX = 3 -} IxEthDBSearchKeyType; - -typedef struct MacTreeNode_t -{ - __smartpointer__ MacDescriptor *descriptor; - struct MacTreeNode_t *left, *right; - - __mempool__ struct MacTreeNode_t *nextFree; -} MacTreeNode; - -typedef IxEthDBStatus (*IxEthDBPortUpdateHandler)(IxEthDBPortId portID, IxEthDBRecordType type); - -typedef void (*IxEthDBNoteWriteFn)(void *address, MacTreeNode *node); - -typedef struct -{ - BOOL updateEnabled; /**< true if updates are enabled for port */ - BOOL userControlled; /**< true if the user has manually used ixEthDBPortUpdateEnableSet */ - BOOL treeInitialized; /**< true if the NPE has received an initial tree */ - IxEthDBPortUpdateHandler updateHandler; /**< port update handler routine */ - void *npeUpdateZone; /**< port update memory zone */ - void *npeGwUpdateZone; /**< port update memory zone for gateways */ - void *vlanUpdateZone; /**< port update memory zone for VLAN tables */ - MacTreeNode *searchTree; /**< internal search tree, in MacTreeNode representation */ - BOOL searchTreePendingWrite; /**< true if searchTree holds a tree pending write to the port */ -} PortUpdateMethod; - -typedef struct -{ - IxEthDBPortId portID; /**< port ID */ - BOOL enabled; /**< true if the port is enabled */ - BOOL agingEnabled; /**< true if aging on this port is enabled */ - BOOL initialized; - IxEthDBPortMap dependencyPortMap; /**< dependency port map for this port */ - PortUpdateMethod updateMethod; /**< update method structure */ - BOOL macAddressUploaded; /**< true if the MAC address was uploaded into the port */ - UINT32 maxRxFrameSize; /**< maximum Rx frame size for this port */ - UINT32 maxTxFrameSize; /**< maximum Rx frame size for this port */ - - UINT8 bbsid[6]; - __alignment__ UINT8 reserved[2]; - UINT32 frameControlDurationID; /**< Frame Control - Duration/ID WiFi control */ - - IxEthDBVlanTag vlanTag; /**< default VLAN tag for port */ - IxEthDBPriorityTable priorityTable; /**< QoS <=> internal priority mapping */ - IxEthDBVlanSet vlanMembership; - IxEthDBVlanSet transmitTaggingInfo; - IxEthDBFrameFilter frameFilter; - IxEthDBTaggingAction taggingAction; - - UINT32 npeFrameFilter; - UINT32 npeTaggingAction; - - IxEthDBFirewallMode firewallMode; - BOOL srcAddressFilterEnabled; - - BOOL stpBlocked; - - IxEthDBFeature featureCapability; - IxEthDBFeature featureStatus; - - UINT32 ixEthDBTrafficClassAQMAssignments[IX_IEEE802_1Q_QOS_PRIORITY_COUNT]; - - UINT32 ixEthDBTrafficClassCount; - - UINT32 ixEthDBTrafficClassAvailable; - - - - __lock__ IxOsalMutex npeAckLock; -} PortInfo; - -/* list of port information structures indexed on port Ids */ -extern IX_ETH_DB_PUBLIC PortInfo ixEthDBPortInfo[IX_ETH_DB_NUMBER_OF_PORTS]; - -typedef enum -{ - IX_ETH_DB_ADD_FILTERING_RECORD = 0xFF0001, - IX_ETH_DB_REMOVE_FILTERING_RECORD = 0xFF0002 -} PortEventType; - -typedef struct -{ - UINT32 eventType; - IxEthDBPortId portID; - IxEthDBMacAddr macAddr; - BOOL staticEntry; -} PortEvent; - -typedef struct -{ - PortEvent queue[EVENT_QUEUE_SIZE]; - UINT32 base; - UINT32 length; -} PortEventQueue; - -typedef struct -{ - IxEthDBPortId portID; /**< originating port */ - MacDescriptor *macDescriptors[MAX_ELT_SIZE]; /**< addresses to be synced into db */ - UINT32 addressCount; /**< number of addresses */ -} TreeSyncInfo; - -typedef struct -{ - MacTreeNode *nodes[MAX_ELT_SIZE]; - UINT32 offsets[MAX_ELT_SIZE]; - UINT32 nodeCount; -} MacTreeNodeStack; - -/* Prototypes */ - -/* ----------- Memory management -------------- */ - -IX_ETH_DB_PUBLIC void ixEthDBInitMemoryPools(void); - -IX_ETH_DB_PUBLIC HashNode* ixEthDBAllocHashNode(void); -IX_ETH_DB_PUBLIC void ixEthDBFreeHashNode(HashNode *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBAllocMacDescriptor(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacDescriptor* ixEthDBCloneMacDescriptor(MacDescriptor *macDescriptor); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacDescriptor(MacDescriptor *); - -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBAllocMacTreeNode(void); -IX_ETH_DB_PUBLIC __smartpointer__ MacTreeNode* ixEthDBCloneMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC __smartpointer__ void ixEthDBFreeMacTreeNode(MacTreeNode *); - -IX_ETH_DB_PUBLIC void ixEthDBPoolFreeMacTreeNode(MacTreeNode *); -IX_ETH_DB_PUBLIC UINT32 ixEthDBSearchTreeUsageGet(MacTreeNode *tree); -IX_ETH_DB_PUBLIC int ixEthDBShowMemoryStatus(void); - -/* Hash Table */ -IX_ETH_DB_PUBLIC void ixEthDBInitHash(HashTable *hashTable, UINT32 numBuckets, HashFunction entryHashFunction, MatchFunction *matchFunctions, FreeFunction freeFunction); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAddHashEntry(HashTable *hashTable, void *entry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSearchHashEntry(HashTable *hashTable, int keyType, void *reference, HashNode **searchResult); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeekHashEntry(HashTable *hashTable, int keyType, void *reference); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashNode(HashNode *node); - -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInitHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBIncrementHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemoveEntryAtHashIterator(HashTable *hashTable, HashIterator *iterator); -IX_ETH_DB_PUBLIC void ixEthDBReleaseHashIterator(HashIterator *iterator); - -/* API Support */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortAddressSet(IxEthDBPortId portID, IxEthDBMacAddr *macAddr); -IX_ETH_DB_PUBLIC void ixEthDBMaximumFrameSizeAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* DB Core functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBInit(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBAdd(MacDescriptor *newRecordTemplate, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBRemove(MacDescriptor *templateRecord, IxEthDBPortMap updateTrigger); -IX_ETH_DB_PUBLIC HashNode* ixEthDBSearch(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPeek(IxEthDBMacAddr *macAddress, IxEthDBRecordType typeFilter); - -/* Learning support */ -IX_ETH_DB_PUBLIC UINT32 ixEthDBAddressCompare(UINT8 *mac1, UINT8 *mac2); -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC UINT32 ixEthDBEntryXORHash(void *macDescriptor); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyXORHash(void *macAddress); - -/* Port updates */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBNPEUpdateHandler(IxEthDBPortId portID, IxEthDBRecordType type); -IX_ETH_DB_PUBLIC void ixEthDBUpdatePortLearningTrees(IxEthDBPortMap triggerPorts); -IX_ETH_DB_PUBLIC void ixEthDBNPEAccessRequest(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBUpdateLock(void); -IX_ETH_DB_PUBLIC void ixEthDBUpdateUnlock(void); -IX_ETH_DB_PUBLIC MacTreeNode* ixEthDBQuery(MacTreeNode *searchTree, IxEthDBPortMap query, IxEthDBRecordType recordFilter, UINT32 maximumEntries); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFirewallUpdate(IxEthDBPortId portID, void *address, UINT32 epDelta); - -/* Init/unload */ -IX_ETH_DB_PUBLIC void ixEthDBPortSetAckCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBEventProcessorInit(void); -IX_ETH_DB_PUBLIC void ixEthDBPortInit(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortEnable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortDisable(IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasInit(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBMatchMethodsRegister(MatchFunction *matchFunctions); -IX_ETH_DB_PUBLIC UINT32 ixEthDBRecordSerializeMethodsRegister(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBUpdateTypeRegister(BOOL *typeArray); -IX_ETH_DB_PUBLIC void ixEthDBNPEUpdateAreasUnload(void); -IX_ETH_DB_PUBLIC void ixEthDBFeatureCapabilityScan(void); -IX_ETH_DB_PUBLIC UINT32 ixEthDBKeyTypeRegister(UINT32 *keyType); - -/* Event processing */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBDefaultEventCallbackEnable(IxEthDBPortId portID, BOOL enable); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerAddPortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID, BOOL staticEntry); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBTriggerRemovePortUpdate(IxEthDBMacAddr *macAddr, IxEthDBPortId portID); -IX_ETH_DB_PUBLIC void ixEthDBNPEEventCallback(IxNpeMhNpeId npeID, IxNpeMhMessage msg); - -/* NPE adaptor */ -IX_ETH_DB_PUBLIC void ixEthDBGetMacDatabaseCbk(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNpeMsgAck(IxNpeMhNpeId npeID, IxNpeMhMessage msg); -IX_ETH_DB_PUBLIC void ixEthDBNPESyncScan(IxEthDBPortId portID, void *eltBaseAddress, UINT32 eltSize); -IX_ETH_DB_PUBLIC void ixEthDBNPETreeWrite(IxEthDBRecordType type, UINT32 totalSize, void *baseAddress, MacTreeNode *tree, UINT32 *blocks, UINT32 *startIndex); -IX_ETH_DB_PUBLIC void ixEthDBNPEGatewayNodeWrite(void *address, MacTreeNode *node); - -/* Other public API functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStartLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBStopLearningFunction(void); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortUpdateEnableSet(IxEthDBPortId portID, BOOL enableUpdate); - -/* Maximum Tx/Rx public functions */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumRxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumRxFrameSize); -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBFilteringPortMaximumTxFrameSizeSet(IxEthDBPortId portID, UINT32 maximumTxFrameSize); - -/* VLAN-related */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBPortVlanTableSet(IxEthDBPortId portID, IxEthDBVlanSet portVlanTable, IxEthDBVlanSet vlanSet); - -/* Record search */ -IX_ETH_DB_PUBLIC BOOL ixEthDBAddressRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBVlanRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBPortRecordMatch(void *untypedReference, void *untypedEntry); -IX_ETH_DB_PUBLIC BOOL ixEthDBNullMatch(void *reference, void *entry); -IX_ETH_DB_PUBLIC HashNode* ixEthDBPortSearch(IxEthDBMacAddr *macAddress, IxEthDBPortId portID, IxEthDBRecordType typeFilter); -IX_ETH_DB_PUBLIC HashNode* ixEthDBVlanSearch(IxEthDBMacAddr *macAddress, IxEthDBVlanId vlanID, IxEthDBRecordType typeFilter); - -/* Utilities */ -IX_ETH_DB_PUBLIC const char* mac2string(const unsigned char *mac); -IX_ETH_DB_PUBLIC void showHashInfo(void); -IX_ETH_DB_PUBLIC int ixEthDBAnalyzeHash(void); -IX_ETH_DB_PUBLIC const char* errorString(IxEthDBStatus error); -IX_ETH_DB_PUBLIC int numHashElements(void); -IX_ETH_DB_PUBLIC void zapHashtable(void); -IX_ETH_DB_PUBLIC BOOL ixEthDBCheckSingleBitValue(UINT32 value); - -/* Single Eth NPE Check */ -IX_ETH_DB_PUBLIC IxEthDBStatus ixEthDBSingleEthNpeCheck(IxEthDBPortId portId); - -#endif /* IxEthDB_p_H */ - diff --git a/drivers/net/npe/include/IxEthMii.h b/drivers/net/npe/include/IxEthMii.h deleted file mode 100644 index 8d7de3d4ce2..00000000000 --- a/drivers/net/npe/include/IxEthMii.h +++ /dev/null @@ -1,246 +0,0 @@ -/** - * @file IxEthMii.h - * - * @brief this file contains the public API of @ref IxEthMii component - * - * Design notes : - * The main intent of this API is to inplement MII high level fonctionalitoes - * to support the codelets provided with the IXP400 software releases. It - * superceedes previous interfaces provided with @ref IxEThAcc component. - * - * This API has been tested with the PHYs provided with the - * IXP400 development platforms. It may not work for specific Ethernet PHYs - * used on specific boards. - * - * This source code detects and interface the LXT972, LXT973 and KS6995 - * Ethernet PHYs. - * - * This source code should be considered as an example which may need - * to be adapted for different hardware implementations. - * - * It is strongly recommended to use public domain and GPL utilities - * like libmii, mii-diag for MII interface support. - * - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_H -#define IxEthMii_H - -#include - -/** - * @defgroup IxEthMii IXP400 Ethernet Phy Access (IxEthMii) API - * - * @brief ethMii is a library that does provides access to the - * Ethernet PHYs - * - *@{ - */ - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount) - * - * @brief Scan the MDIO bus for PHYs - * This function scans PHY addresses 0 through 31, and sets phyPresent[n] to - * true if a phy is discovered at address n. - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyPresent BOOL [in] - boolean array of IXP425_ETH_ACC_MII_MAX_ADDR entries - * @param maxPhyCount UINT32 [in] - number of PHYs to search for (the scan will stop when - * the indicated number of PHYs is found). - * - * @return IX_STATUS - * - IX_ETH_ACC_SUCCESS - * - IX_ETH_ACC_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate) - * - * - * @brief Configure a PHY - * Configure a PHY's speed, duplex and autonegotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - * @param speed100 BOOL [in] - set to true for 100Mbit/s operation, false for 10Mbit/s - * @param fullDuplex BOOL [in] - set to true for Full Duplex, false for Half Duplex - * @param autonegotiate BOOL [in] - set to true to enable autonegotiation - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyConfig(UINT32 phyAddr, - BOOL speed100, - BOOL fullDuplex, - BOOL autonegotiate); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackEnable(UINT32 phyAddr) - * - * - * @brief Enable PHY Loopback in a specific Eth MII port - * - * @note When PHY Loopback is enabled, frames sent out to the PHY from the - * IXP400 will be looped back to the IXP400. They will not be transmitted out - * on the wire. - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackEnable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyLoopbackDisable(UINT32 phyAddr) - * - * - * @brief Disable PHY Loopback in a specific Eth MII port - * - * - Reentrant - no - * - ISR Callable - no - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - *
- */ -PUBLIC IX_STATUS -ixEthMiiPhyLoopbackDisable (UINT32 phyAddr); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyReset(UINT32 phyAddr) - * - * @brief Reset a PHY - * Reset a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr); - - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg) - * - * @brief Retrieve the current status of a PHY - * Retrieve the link, speed, duplex and autonegotiation status of a PHY - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * @param linkUp BOOL [out] - set to true if the link is up - * @param speed100 BOOL [out] - set to true indicates 100Mbit/s, false indicates 10Mbit/s - * @param fullDuplex BOOL [out] - set to true indicates Full Duplex, false indicates Half Duplex - * @param autoneg BOOL [out] - set to true indicates autonegotiation is enabled, false indicates autonegotiation is disabled - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiLinkStatus(UINT32 phyAddr, - BOOL *linkUp, - BOOL *speed100, - BOOL *fullDuplex, - BOOL *autoneg); - -/** - * @ingroup IxEthMii - * - * @fn ixEthMiiPhyShow (UINT32 phyAddr) - * - * - * @brief Display information on a specified PHY - * Display link status, speed, duplex and Auto Negotiation status - * - * - Reentrant - no - * - ISR Callable - no - * - * @pre The MAC on Ethernet Port 2 (NPE C) must be initialised, and generating the MDIO clock. - * - * @param phyAddr UINT32 [in] - the address of the Ethernet PHY (0-31) - * - * @return IX_STATUS - * - IX_SUCCESS - * - IX_FAIL : invalid arguments. - * - *
- */ -PUBLIC IX_STATUS ixEthMiiPhyShow (UINT32 phyAddr); - -#endif /* ndef IxEthMii_H */ -/** - *@} - */ diff --git a/drivers/net/npe/include/IxEthMii_p.h b/drivers/net/npe/include/IxEthMii_p.h deleted file mode 100644 index 0c48a6971a9..00000000000 --- a/drivers/net/npe/include/IxEthMii_p.h +++ /dev/null @@ -1,161 +0,0 @@ -/** - * @file IxEthMii_p.h - * - * @author Intel Corporation - * @date - * - * @brief MII Header file - * - * Design Notes: - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -#ifndef IxEthMii_p_H -#define IxEthMii_p_H - - -/* MII definitions - these have been verified against the LXT971 and - LXT972 PHYs*/ - -#define IX_ETH_MII_MAX_REG_NUM 0x20 /* max number of registers */ - -#define IX_ETH_MII_CTRL_REG 0x0 /* Control Register */ -#define IX_ETH_MII_STAT_REG 0x1 /* Status Register */ -#define IX_ETH_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */ -#define IX_ETH_MII_PHY_ID2_REG 0x3 /* PHY identifier 2 Register */ -#define IX_ETH_MII_AN_ADS_REG 0x4 /* Auto-Negotiation */ - /* Advertisement Register */ -#define IX_ETH_MII_AN_PRTN_REG 0x5 /* Auto-Negotiation */ - /* partner ability Register */ -#define IX_ETH_MII_AN_EXP_REG 0x6 /* Auto-Negotiation */ - /* Expansion Register */ -#define IX_ETH_MII_AN_NEXT_REG 0x7 /* Auto-Negotiation */ - /* next-page transmit Register */ - -#define IX_ETH_MII_STAT2_REG 0x11 /* Status Register 2*/ - - -/* MII control register bit */ - -#define IX_ETH_MII_CR_COLL_TEST 0x0080 /* collision test */ -#define IX_ETH_MII_CR_FDX 0x0100 /* FDX =1, half duplex =0 */ -#define IX_ETH_MII_CR_RESTART 0x0200 /* restart auto negotiation */ -#define IX_ETH_MII_CR_ISOLATE 0x0400 /* isolate PHY from MII */ -#define IX_ETH_MII_CR_POWER_DOWN 0x0800 /* power down */ -#define IX_ETH_MII_CR_AUTO_EN 0x1000 /* auto-negotiation enable */ -#define IX_ETH_MII_CR_100 0x2000 /* 0 = 10mb, 1 = 100mb */ -#define IX_ETH_MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ -#define IX_ETH_MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ -#define IX_ETH_MII_CR_NORM_EN 0x0000 /* just enable the PHY */ -#define IX_ETH_MII_CR_DEF_0_MASK 0xca7f /* they must return zero */ -#define IX_ETH_MII_CR_RES_MASK 0x007f /* reserved bits, return zero */ - -/* MII Status register bit definitions */ - -#define IX_ETH_MII_SR_LINK_STATUS 0x0004 /* link Status -- 1 = link */ -#define IX_ETH_MII_SR_AUTO_SEL 0x0008 /* auto speed select capable */ -#define IX_ETH_MII_SR_REMOTE_FAULT 0x0010 /* Remote fault detect */ -#define IX_ETH_MII_SR_AUTO_NEG 0x0020 /* auto negotiation complete */ -#define IX_ETH_MII_SR_10T_HALF_DPX 0x0800 /* 10BaseT HD capable */ -#define IX_ETH_MII_SR_10T_FULL_DPX 0x1000 /* 10BaseT FD capable */ -#define IX_ETH_MII_SR_TX_HALF_DPX 0x2000 /* TX HD capable */ -#define IX_ETH_MII_SR_TX_FULL_DPX 0x4000 /* TX FD capable */ -#define IX_ETH_MII_SR_T4 0x8000 /* T4 capable */ -#define IX_ETH_MII_SR_ABIL_MASK 0xff80 /* abilities mask */ -#define IX_ETH_MII_SR_EXT_CAP 0x0001 /* extended capabilities */ - - -/* LXT971/2 Status 2 register bit definitions */ -#define IX_ETH_MII_SR2_100 0x4000 -#define IX_ETH_MII_SR2_TX 0x2000 -#define IX_ETH_MII_SR2_RX 0x1000 -#define IX_ETH_MII_SR2_COL 0x0800 -#define IX_ETH_MII_SR2_LINK 0x0400 -#define IX_ETH_MII_SR2_FD 0x0200 -#define IX_ETH_MII_SR2_AUTO 0x0100 -#define IX_ETH_MII_SR2_AUTO_CMPLT 0x0080 -#define IX_ETH_MII_SR2_POLARITY 0x0020 -#define IX_ETH_MII_SR2_PAUSE 0x0010 -#define IX_ETH_MII_SR2_ERROR 0x0008 - -/* MII Link Code word bit definitions */ - -#define IX_ETH_MII_BP_FAULT 0x2000 /* remote fault */ -#define IX_ETH_MII_BP_ACK 0x4000 /* acknowledge */ -#define IX_ETH_MII_BP_NP 0x8000 /* nexp page is supported */ - -/* MII Next Page bit definitions */ - -#define IX_ETH_MII_NP_TOGGLE 0x0800 /* toggle bit */ -#define IX_ETH_MII_NP_ACK2 0x1000 /* acknowledge two */ -#define IX_ETH_MII_NP_MSG 0x2000 /* message page */ -#define IX_ETH_MII_NP_ACK1 0x4000 /* acknowledge one */ -#define IX_ETH_MII_NP_NP 0x8000 /* nexp page will follow */ - -/* MII Expansion Register bit definitions */ - -#define IX_ETH_MII_EXP_FAULT 0x0010 /* parallel detection fault */ -#define IX_ETH_MII_EXP_PRTN_NP 0x0008 /* link partner next-page able */ -#define IX_ETH_MII_EXP_LOC_NP 0x0004 /* local PHY next-page able */ -#define IX_ETH_MII_EXP_PR 0x0002 /* full page received */ -#define IX_ETH_MII_EXP_PRT_AN 0x0001 /* link partner auto neg able */ - -/* technology ability field bit definitions */ - -#define IX_ETH_MII_TECH_10BASE_T 0x0020 /* 10Base-T */ -#define IX_ETH_MII_TECH_10BASE_FD 0x0040 /* 10Base-T Full Duplex */ -#define IX_ETH_MII_TECH_100BASE_TX 0x0080 /* 100Base-TX */ -#define IX_ETH_MII_TECH_100BASE_TX_FD 0x0100 /* 100Base-TX Full Duplex */ - -#define IX_ETH_MII_TECH_100BASE_T4 0x0200 /* 100Base-T4 */ -#define IX_ETH_MII_ADS_TECH_MASK 0x1fe0 /* technology abilities mask */ -#define IX_ETH_MII_TECH_MASK IX_ETH_MII_ADS_TECH_MASK -#define IX_ETH_MII_ADS_SEL_MASK 0x001f /* selector field mask */ - -#define IX_ETH_MII_AN_FAIL 0x10 /* auto-negotiation fail */ -#define IX_ETH_MII_STAT_FAIL 0x20 /* errors in the status register */ -#define IX_ETH_MII_PHY_NO_ABLE 0x40 /* the PHY lacks some abilities */ - -/* Definitions for MII access routines*/ - -#define IX_ETH_MII_GO BIT(31) -#define IX_ETH_MII_WRITE BIT(26) -#define IX_ETH_MII_TIMEOUT_10TH_SECS (5) -#define IX_ETH_MII_10TH_SEC_IN_MILLIS (100) -#define IX_ETH_MII_READ_FAIL BIT(31) - -/* When we reset the PHY we delay for 2 seconds to allow the reset to - complete*/ -#define IX_ETH_MII_RESET_DELAY_MS (2000) -#define IX_ETH_MII_RESET_POLL_MS (50) - -#define IX_ETH_MII_REG_SHL 16 -#define IX_ETH_MII_ADDR_SHL 21 - -/* supported PHYs */ -#define IX_ETH_MII_LXT971_PHY_ID 0x001378E0 -#define IX_ETH_MII_LXT972_PHY_ID 0x001378E2 -#define IX_ETH_MII_LXT973_PHY_ID 0x00137A10 -#define IX_ETH_MII_LXT973A3_PHY_ID 0x00137A11 -#define IX_ETH_MII_KS8995_PHY_ID 0x00221450 -#define IX_ETH_MII_LXT9785_PHY_ID 0x001378FF - - -#define IX_ETH_MII_INVALID_PHY_ID 0x00000000 -#define IX_ETH_MII_UNKNOWN_PHY_ID 0xffffffff - -#endif /*IxEthAccMii_p_H*/ diff --git a/drivers/net/npe/include/IxEthNpe.h b/drivers/net/npe/include/IxEthNpe.h deleted file mode 100644 index 20bfa76c363..00000000000 --- a/drivers/net/npe/include/IxEthNpe.h +++ /dev/null @@ -1,671 +0,0 @@ -#ifndef __doxygen_HIDE /* This file is not part of the API */ - -/** - * @file IxEthNpe.h - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxEthNpe IXP400 Ethernet NPE (IxEthNpe) API - * - * @brief Contains the API for Ethernet NPE. - * - * All messages given to NPE, get back an acknowledgment. The acknowledgment - * is identical to the message sent to the NPE (except for NPE_GETSTATUS message). - * - * @{ - */ - - -/*-------------------------------------------------------------------------- - * APB Message IDs - XScale->NPE - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS - * - * @brief Request from the XScale client for the NPE to return the firmware - * version of the currently executing image. - * - * Acknowledgment message id is same as the request message id. - * NPE returns the firmware version ID to XScale. - */ -#define IX_ETHNPE_NPE_GETSTATUS 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS - * - * @brief Request from the XScale client for the NPE to set the Ethernet - * port's port ID and MAC address. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE - * - * @brief Request from XScale client to the NPE requesting upload of - * Ethernet Filtering Database or Header Conversion Database from NPE's - * data memory to XScale accessible SDRAM. - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE - * - * @brief Request from XScale client to the NPE requesting download of - * Ethernet Filtering Database or Header Conversion Database from SDRAM - * to the NPE's datamemory. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE 0x03 - -/** - * @def IX_ETHNPE_GETSTATS - * - * @brief Request from the XScale client for the current MAC port statistics - * data to be written to the (empty) statistics structure and the specified - * location in externa memory. - */ -#define IX_ETHNPE_GETSTATS 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS - * - * @brief Request from the XScale client to the NPE to reset all of its internal - * MAC port statistics state variables. - * - * As a side effect, this message entails an implicit request that the NPE - * write the current MAC port statistics into the MAC statistics structure - * at the specified location in external memory. - */ -#define IX_ETHNPE_RESETSTATS 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS - * - * @brief Request from the XScale client to the NPE to configure maximum framelengths - * and block sizes in receive and transmit direction. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE - * - * @brief Request from the XScale client to the NPE to configure VLAN frame type - * filtering and VLAN the tagging mode for the receiver. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID - * - * @brief Request from the XScale client to the NPE to set receiver's default - * VLAN tag (PVID)and internal traffic class. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for 8 consecutive VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE - * - * @brief Request from the XScale client to the NPE to configure VLAN Port - * membership and Tx tagging for a range of VLANID's. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY - * - * @brief Request from the XScale client to the NPE to map a user priority - * to QoS class and an AQM queue number. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE - * - * @brief Request from the XScale client to the NPE to enable or disable - * portID extraction from VLAN-tagged frames for the specified port. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE - * - * @brief Request from the XScale client to the NPE to block or unblock - * forwarding for spanning tree BPDUs. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE - * - * @brief Request from the XScale client to the NPE to configure firewall - * services modes of operation and/or download Ethernet Firewall Database from - * SDRAM to NPE. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID - * - * @brief Request from the XScale client to the NPE to set global frame control - * and duration/ID field for the 802.3 to 802.11 protocol header conversion - * service. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID - * - * @brief Request from the XScale client to the NPE to set global BBSID field - * value for the 802.3 to 802.11 protocol header conversion service. - */ -#define IX_ETHNPE_PC_SETBBSID 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE - * - * @brief Request from the XScale client to the NPE to update a block/section/ - * range of the AP MAC Address Table. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE - * - * @brief Turn on or off the NPE frame loopback. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE (0x12) - -/*-------------------------------------------------------------------------- - * APB Message IDs - NPE->XScale - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_NPE_GETSTATUS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_NPE_GETSTATUS message. NPE firmware version - * id is returned in the message. - */ -#define IX_ETHNPE_NPE_GETSTATUS_ACK 0x00 - -/** - * @def IX_ETHNPE_EDB_SETPORTADDRESS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETPORTADDRESS message. - */ -#define IX_ETHNPE_EDB_SETPORTADDRESS_ACK 0x01 - -/** - * @def IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_GETMACADDRESSDATABASE message - */ -#define IX_ETHNPE_EDB_GETMACADDRESSDATABASE_ACK 0x02 - -/** - * @def IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_EDB_SETMACADDRESSSDATABASE message. - */ -#define IX_ETHNPE_EDB_SETMACADDRESSSDATABASE_ACK 0x03 - -/** - * @def IX_ETHNPE_GETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_GETSTATS message. - */ -#define IX_ETHNPE_GETSTATS_ACK 0x04 - -/** - * @def IX_ETHNPE_RESETSTATS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_RESETSTATS message. - */ -#define IX_ETHNPE_RESETSTATS_ACK 0x05 - -/** - * @def IX_ETHNPE_SETMAXFRAMELENGTHS_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETMAXFRAMELENGTHS message. - */ -#define IX_ETHNPE_SETMAXFRAMELENGTHS_ACK 0x06 - -/** - * @def IX_ETHNPE_VLAN_SETRXTAGMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXTAGMODE message. - */ -#define IX_ETHNPE_VLAN_SETRXTAGMODE_ACK 0x07 - -/** - * @def IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETDEFAULTRXVID message. - */ -#define IX_ETHNPE_VLAN_SETDEFAULTRXVID_ACK 0x08 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLEENTRY_ACK 0x09 - -/** - * @def IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE message. - */ -#define IX_ETHNPE_VLAN_SETPORTVLANTABLERANGE_ACK 0x0A - -/** - * @def IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETRXQOSENTRY message. - */ -#define IX_ETHNPE_VLAN_SETRXQOSENTRY_ACK 0x0B - -/** - * @def IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE message. - */ -#define IX_ETHNPE_VLAN_SETPORTIDEXTRACTIONMODE_ACK 0x0C - -/** - * @def IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_STP_SETBLOCKINGSTATE message. - */ -#define IX_ETHNPE_STP_SETBLOCKINGSTATE_ACK 0x0D - -/** - * @def IX_ETHNPE_FW_SETFIREWALLMODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_FW_SETFIREWALLMODE message. - */ -#define IX_ETHNPE_FW_SETFIREWALLMODE_ACK 0x0E - -/** - * @def IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID message. - */ -#define IX_ETHNPE_PC_SETFRAMECONTROLDURATIONID_ACK 0x0F - -/** - * @def IX_ETHNPE_PC_SETBBSID_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETBBSID message. - */ -#define IX_ETHNPE_PC_SETBBSID_ACK 0x10 - -/** - * @def IX_ETHNPE_PC_SETAPMACTABLE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_PC_SETAPMACTABLE message. - */ -#define IX_ETHNPE_PC_SETAPMACTABLE_ACK 0x11 - -/** - * @def IX_ETHNPE_SETLOOPBACK_MODE_ACK - * - * @brief Acknowledgment to IX_ETHNPE_SETLOOPBACK_MODE message. - */ -#define IX_ETHNPE_SETLOOPBACK_MODE_ACK (0x12) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field boundary definitions - *------------------------------------------------------------------------*/ - -/** - * @def MASK(hi,lo) - * - * @brief Macro for mask - */ -#define MASK(hi,lo) (((1 << (1 + ((hi) - (lo)))) - 1) << (lo)) - -/** - * @def BITS(x,hi,lo) - * - * @brief Macro for bits - */ -#define BITS(x,hi,lo) (((x) & MASK(hi,lo)) >> (lo)) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK - * - * @brief QMgr Queue LENGTH field mask - */ -#define IX_ETHNPE_QM_Q_RXENET_LENGTH_MASK 0x3fff - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_R - * - * @brief QMgr Queue FLAG field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_FLAG_R 20 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_FLAG_MASK - * - * @brief QMgr Queue FLAG field mask - * - * Multicast bit : BIT(4) - * Broadcast bit : BIT(5) - * IP bit : BIT(6) (linux only) - * - */ -#ifdef __vxworks -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x30 -#else -#define IX_ETHNPE_QM_Q_FIELD_FLAG_MASK 0x70 -#endif - - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_L - * - * @brief QMgr Queue NPE ID field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_L 1 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_NPEID_R - * - * @brief QMgr Queue NPE ID field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_NPEID_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_L - * - * @brief QMgr Queue Priority field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_L 2 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_PRIOR_R - * - * @brief QMgr Queue Priority field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_PRIOR_R 0 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_L - * - * @brief QMgr Queue Address field left boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_L 31 - -/** - * @def IX_ETHNPE_QM_Q_FIELD_ADDR_R - * - * @brief QMgr Queue Address field right boundary - */ -#define IX_ETHNPE_QM_Q_FIELD_ADDR_R 5 - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field masks - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK - * - * @brief Macro to mask the Address field of the FreeEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the RxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK - * - * @brief Macro to mask the Priority field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnet Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK - * - * @brief Macro to mask the NPE ID field of the TxEnetDone Queue Manager Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK - * - * @brief Macro to mask the Mbuf Address field of the TxEnetDone Queue Manager - * Entry - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK \ - MASK (IX_ETHNPE_QM_Q_FIELD_ADDR_L, \ - IX_ETHNPE_QM_Q_FIELD_ADDR_R) - -/*-------------------------------------------------------------------------- - * Queue Manager Queue entry bit field value extraction macros - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of FreeNet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_FREEENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_FREEENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of RxEnet Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; - * Set to 1 for entries originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_RXENET_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) - * - * @brief Extraction macro for Port ID field of RxEnet Queue Manager Entry - * - * 0-5: Assignable (by the XScale client) to any of the physical ports. - * 6: It is reserved - * 7: Indication that the NPE did not find the associated frame's destination MAC address within - * its internal filtering database. - */ -#define IX_ETHNPE_QM_Q_RXENET_PORTID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PORTID_L, \ - IX_ETHNPE_QM_Q_Field_PortID_R) - -/** - * @def IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of RxEnet Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_RXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_RXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) - * - * @brief Extraction macro for Priority field of TxEnet Queue Manager Entry - * - * Priority of the packet (as described in IEEE 802.1D). This field is - * cleared upon return from the Ethernet NPE to the TxEnetDone queue. - */ -#define IX_ETHNPE_QM_Q_TXENET_PRIOR_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_PRIOR_L, \ - IX_ETHNPE_QM_Q_FIELD_PRIOR_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of Queue Manager TxEnet Queue - * Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENET_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENET_ADDR_MASK) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) - * - * @brief Extraction macro for NPE ID field of TxEnetDone Queue Manager Entry - * - * Set to 0 for entries originating from the Eth0 NPE; set to 1 for en-tries - * originating from the Eth1 NPE. - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_NPEID_VAL(x) \ - BITS (x, IX_ETHNPE_QM_Q_FIELD_NPEID_L, \ - IX_ETHNPE_QM_Q_FIELD_NPEID_R) - -/** - * @def IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) - * - * @brief Extraction macro for Address field of TxEnetDone Queue Manager Entry - * - * Pointer to an mbuf buffer descriptor - */ -#define IX_ETHNPE_QM_Q_TXENETDONE_ADDR_VAL(x) \ - ((x) & IX_ETHNPE_QM_Q_TXENETDONE_ADDR_MASK) - - -/*-------------------------------------------------------------------------- - * NPE limits - *------------------------------------------------------------------------*/ - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN - * - * @brief Macro to check the minimum length of a rx free buffer - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MIN (64) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - * - * @brief Mask to apply to the mbuf length before submitting it to the NPE - * (the NPE handles only rx free mbufs which are multiple of 64) - * - * @sa IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_LENGTH_MASK (~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) - * - * @brief Round up to get the size necessary to receive without chaining - * the frames which are (size) bytes (the NPE operates by multiple of 64) - * e.g. To receive 1514 bytes frames, the size of the buffers in replenish - * has to be at least (1514+63)&(~63) = 1536 bytes. - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_UP(size) (((size) + 63) & ~63) - -/** - * @def IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) - * - * @brief Round down to apply to the mbuf length before submitting - * it to the NPE. (the NPE operates by multiple of 64) - * - */ -#define IX_ETHNPE_ACC_RXFREE_BUFFER_ROUND_DOWN(size) ((size) & ~63) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_MAX - * - * @brief maximum mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_MAX - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_MAX (16320) - -/** - * @def IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - * - * @brief default mbuf length supported by the NPE - * - * @sa IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT - */ -#define IX_ETHNPE_ACC_FRAME_LENGTH_DEFAULT (1522) - -/** - * @def IX_ETHNPE_ACC_LENGTH_OFFSET - * - * @brief Offset of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_LENGTH_OFFSET 16 - -/** - * @def IX_ETHNPE_ACC_PKTLENGTH_MASK - * - * @brief Mask of the cluster length field in the word shared with the NPEs - */ -#define IX_ETHNPE_ACC_PKTLENGTH_MASK 0x3fff - - -/** - *@} - */ - -#endif /* __doxygen_HIDE */ diff --git a/drivers/net/npe/include/IxFeatureCtrl.h b/drivers/net/npe/include/IxFeatureCtrl.h deleted file mode 100644 index 987b00b5620..00000000000 --- a/drivers/net/npe/include/IxFeatureCtrl.h +++ /dev/null @@ -1,718 +0,0 @@ -/** - * @file IxFeatureCtrl.h - * - * @date 30-Jan-2003 - - * @brief This file contains the public API of the IXP400 Feature Control - * component. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxFeatureCtrlAPI IXP400 Feature Control (IxFeatureCtrl) API - * - * @brief The Public API for the IXP400 Feature Control. - * - * @{ - */ - -#ifndef IXFEATURECTRL_H -#define IXFEATURECTRL_H - -/* - * User defined include files - */ -#include "IxOsal.h" - -/* - * #defines and macros - */ - -/************************************************************* - * The following are IxFeatureCtrlComponentCheck return values. - ************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_DISABLED - * - * @brief Hardware Component is disabled/unavailable. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_COMPONENT_ENABLED - * - * @brief Hardware Component is available. - * Return status by ixFeatureCtrlComponentCheck() - */ -#define IX_FEATURE_CTRL_COMPONENT_ENABLED 1 - -/*********************************************************************************** - * Product ID in XScale CP15 - Register 0 - * - It contains information on the maximum XScale Core Frequency and - * Silicon Stepping. - * - XScale Core Frequency Id indicates only the maximum XScale frequency - * achievable and not the running XScale frequency (maybe stepped down). - * - The register is read by using ixFeatureCtrlProductIdRead. - * - Usage example: - * productId = ixFeatureCtrlProductIdRead(); - * if( (productId & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) == - * IX_FEATURE_CTRL_SILICON_TYPE_A0 ) - * if( (productId & IX_FEATURE_CTRL_XSCALE_FREQ_MASK) == - * IX_FEATURE_CTRL_XSCALE_FREQ_533 ) - * - * 31 28 27 24 23 20 19 16 15 12 11 9 8 4 3 0 - * -------------------------------------------------------------------------------- - * | 0x6 | 0x9 | 0x0 | 0x5 | 0x4 | Device ID | XScale Core Freq Id | Si Stepping Id | - * -------------------------------------------------------------------------------- - * - * Maximum Achievable XScale Core Frequency Id : 533MHz - 0x1C - * 400MHz - 0x1D - * 266MHz - 0x1F - * - * THE CORE FREQUENCY ID IS NOT APPLICABLE TO IXP46X <\b> - * - * The above is applicable to IXP42X only. CP15 in IXP46X does not contain any - * Frequency ID. - * - * Si Stepping Id : A - 0x0 - * B - 0x1 - * - * XScale Core freq Id - Device ID [11:9] : IXP42X - 0x0 - * IXP46X - 0x1 - *************************************************************************************/ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_A0 - * - * @brief This is the value of A0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_A0 0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_TYPE_B0 - * - * @brief This is the value of B0 Silicon in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_TYPE_B0 1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_SILICON_STEPPING_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_SILICON_STEPPING_MASK 0xF - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_MASK - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_MASK (0x7) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET - * - * @brief This is the mask of silicon stepping in product ID. - */ -#define IX_FEATURE_CTRL_DEVICE_TYPE_OFFSET 9 - - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_533 - * - * @brief This is the value of 533MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_533 ((0x1C)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_400 - * - * @brief This is the value of 400MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_400 ((0x1D)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_266 - * - * @brief This is the value of 266MHz XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_266 ((0x1F)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURE_CTRL_XSCALE_FREQ_MASK - * - * @brief This is the mask of XScale Core in product ID. - */ -#define IX_FEATURE_CTRL_XSCALE_FREQ_MASK ((0xFF)<<4) - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_32PHY - * - * @brief Maximum UTOPIA PHY available is 32. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_32PHY 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_16PHY - * - * @brief Maximum UTOPIA PHY available is 16. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_16PHY 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_8PHY - * - * @brief Maximum UTOPIA PHY available to is 8. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_8PHY 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_UTOPIA_4PHY - * - * @brief Maximum UTOPIA PHY available to is 4. - * - */ -#define IX_FEATURECTRL_REG_UTOPIA_4PHY 0x3 - -#ifdef __ixp46X - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_533FREQ - * - * @brief Maximum frequency available to IXP46x is 533 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_533FREQ 0x0 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_667FREQ - * - * @brief Maximum frequency available to IXP46x is 667 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_667FREQ 0x1 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_400FREQ - * - * @brief Maximum frequency available to IXP46x is 400 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_400FREQ 0x2 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_REG_XSCALE_266FREQ - * - * @brief Maximum frequency available to IXP46x is 266 MHz. - * - */ -#define IX_FEATURECTRL_REG_XSCALE_266FREQ 0x3 - -#endif /* __ixp46X */ - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_NOT_AVAILABLE 0x0000 - -/** - * @ingroup IxFeatureCtrlAPI - * - * @def IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE - * - * @brief Component selected is not available for device - * - */ -#define IX_FEATURECTRL_COMPONENT_ALWAYS_AVAILABLE 0xffff - -/** - * @defgroup IxFeatureCtrlSwConfig Software Configuration for Access Component - * - * @ingroup IxFeatureCtrlAPI - * - * @brief This section describes software configuration in access component. The - * configuration can be changed at run-time. ixFeatureCtrlSwConfigurationCheck( ) - * will be used across applicable access component to check the configuration. - * ixFeatureCtrlSwConfigurationWrite( ) is used to write the software configuration. - * - * @note All software configurations are default to be enabled. - * - * @{ - */ -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_DISABLED - * - * @brief Software configuration is disabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_DISABLED 0 - -/** - * @ingroup IxFeatureCtrlSwConfig - * - * @def IX_FEATURE_CTRL_SWCONFIG_ENABLED - * - * @brief Software configuration is enabled. - * - */ -#define IX_FEATURE_CTRL_SWCONFIG_ENABLED 1 - -/** - * Section for enums - **/ - -/** - * @ingroup IxFeatureCtrlBuildDevice - * - * @enum IxFeatureCtrlBuildDevice - * - * @brief Indicates software build type. - * - * Default build type is IXP42X - * - */ -typedef enum -{ - IX_FEATURE_CTRL_SW_BUILD_IXP42X = 0, /** - * - if(IX_FEATURE_CTRL_COMPONENT_DISABLED != - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0))
- * - if(IX_FEATURE_CTRL_COMPONENT_ENABLED == - * ixFeatureCtrlComponentCheck(IX_FEATURECTRL_PCI))
- * - * This function is typically called during component initialization time. - * - * @param componentType @ref IxFeatureCtrlComponentType [in] - the type of a component as - * defined above as IX_FEATURECTRL_XXX (Exp: IX_FEATURECTRL_PCI, IX_FEATURECTRL_ETH0) - - * - * @return - * - IX_FEATURE_CTRL_COMPONENT_ENABLED if component is available - * - IX_FEATURE_CTRL_COMPONENT_DISABLED if component is unavailable - */ -PUBLIC IX_STATUS -ixFeatureCtrlComponentCheck (IxFeatureCtrlComponentType componentType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IxFeatureCtrlProductId ixFeatureCtrlProductIdRead (void) - * - * @brief This function will return IXP400 product ID i.e. CP15, - * Register 0. - * - * @return - * - IxFeatureCtrlProductId - the value of product ID. - * - */ -PUBLIC IxFeatureCtrlProductId -ixFeatureCtrlProductIdRead (void) ; - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn IX_STATUS ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType) - * - * @brief This function checks whether the specified software configuration is - * enabled or disabled. - * - * Usage Example:
- * - if(IX_FEATURE_CTRL_SWCONFIG_DISABLED != - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - if(IX_FEATURE_CTRL_SWCONFIG_ENABLED == - * ixFeatureCtrlSwConfigurationCheck(IX_FEATURECTRL_ETH_LEARNING))
- * - * This function is typically called during access component initialization time. - * - * @param swConfigType @ref IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * - * @return - * - IX_FEATURE_CTRL_SWCONFIG_ENABLED if software configuration is enabled. - * - IX_FEATURE_CTRL_SWCONFIG_DISABLED if software configuration is disabled. - */ -PUBLIC IX_STATUS -ixFeatureCtrlSwConfigurationCheck (IxFeatureCtrlSwConfig swConfigType); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled) - * - * @brief This function enable/disable the specified software configuration. - * - * Usage Example:
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, true) is used - * to enable Ethernet Learning Feature
- * - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false) is used - * to disable Ethernet Learning Feature
- * - * @param swConfigType IxFeatureCtrlSwConfig [in] - the type of a software configuration - * defined in IxFeatureCtrlSwConfig enumeration. - * @param enabled BOOL [in] - To enable(true) / disable (false) the specified software - * configuration. - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlSwConfigurationWrite (IxFeatureCtrlSwConfig swConfigType, BOOL enabled); - -/** - * @ingroup IxFeatureCtrlAPI - * - * @fn void ixFeatureCtrlIxp400SwVersionShow (void) - * - * @brief This function shows the current software release information for IXP400 - * - * @return none - * - */ -PUBLIC void -ixFeatureCtrlIxp400SwVersionShow (void); - -#endif /* IXFEATURECTRL_H */ - -/** - * @} defgroup IxFeatureCtrlAPI - */ diff --git a/drivers/net/npe/include/IxHssAcc.h b/drivers/net/npe/include/IxHssAcc.h deleted file mode 100644 index da71c420238..00000000000 --- a/drivers/net/npe/include/IxHssAcc.h +++ /dev/null @@ -1,1292 +0,0 @@ -/** - * @file IxHssAcc.h - * - * @date 07-DEC-2001 - * - * @brief This file contains the public API of the IXP400 HSS Access - * component - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/* ------------------------------------------------------ - Doxygen group definitions - ------------------------------------------------------ */ -/** - * @defgroup IxHssAccAPI IXP400 HSS Access (IxHssAcc) API - * - * @brief The public API for the IXP400 HssAccess component - * - * IxHssAcc is the access layer to the HSS packetised and channelised - * services - * - * Design Notes
- *
    - *
  • When a packet-pipe is configured for 56Kbps RAW mode, byte alignment of - * the transmitted data is not preserved. All raw data that is transmitted - * will be received in proper order by the receiver, but the first bit of - * the packet may be seen at any offset within a byte; all subsequent bytes - * will have the same offset for the duration of the packet. The same offset - * also applies to all subsequent packets received on the packet-pipe too. - * (Similar results will occur for data received from remote end.) While - * this behavior will also occur for 56Kbps HDLC mode, the HDLC - * encoding/decoding will preserve the original byte alignment at the - * receiver end. - *
- * - * 56Kbps Packetised Service Bandwidth Limitation
- *
    - *
  • IxHssAcc supports 56Kbps packetised service at a maximum aggregate rate - * for all HSS ports/HDLC channels of 12.288Mbps[1] in each direction, i.e. - * it supports 56Kbps packetised service on up to 8 T1 trunks. It does - * not support 56Kbps packetised service on 8 E1 trunks (i.e. 4 trunks per - * HSS port) unless those trunks are running 'fractional E1' with maximum - * aggregate rate of 12.288 Mbps in each direction.
    - * [1] 12.288Mbps = 1.536Mbp * 8 T1 - *
- * @{ */ - -#ifndef IXHSSACC_H -#define IXHSSACC_H - -#include "IxOsal.h" - -/* - * #defines for function return types, etc. - */ - -/** - * @def IX_HSSACC_TSLOTS_PER_HSS_PORT - * - * @brief The max number of TDM timeslots supported per HSS port - 4E1's = - * 32x4 = 128 - */ -#define IX_HSSACC_TSLOTS_PER_HSS_PORT 128 - -/* ----------------------------------------------------------- - The following are HssAccess return values returned through - service interfaces. The globally defined IX_SUCCESS (0) and - IX_FAIL (1) in IxOsalTypes.h are also used. - ----------------------------------------------------------- */ -/** - * @def IX_HSSACC_PARAM_ERR - * - * @brief HssAccess function return value for a parameter error - */ -#define IX_HSSACC_PARAM_ERR 2 - -/** - * @def IX_HSSACC_RESOURCE_ERR - * - * @brief HssAccess function return value for a resource error - */ -#define IX_HSSACC_RESOURCE_ERR 3 - -/** - * @def IX_HSSACC_PKT_DISCONNECTING - * - * @brief Indicates that a disconnect call is progressing and will - * disconnect soon - */ -#define IX_HSSACC_PKT_DISCONNECTING 4 - -/** - * @def IX_HSSACC_Q_WRITE_OVERFLOW - * - * @brief Indicates that an attempt to Tx or to replenish an - * RxFree Q failed due to Q overflow. - */ -#define IX_HSSACC_Q_WRITE_OVERFLOW 5 - -/* ------------------------------------------------------------------- - The following errors are HSS/NPE errors returned on error retrieval - ------------------------------------------------------------------- */ -/** - * @def IX_HSSACC_NO_ERROR - * - * @brief HSS port no error present - */ -#define IX_HSSACC_NO_ERROR 0 - -/** - * @def IX_HSSACC_TX_FRM_SYNC_ERR - * - * @brief HSS port TX Frame Sync error - */ -#define IX_HSSACC_TX_FRM_SYNC_ERR 1 - -/** - * @def IX_HSSACC_TX_OVER_RUN_ERR - * - * @brief HSS port TX over-run error - */ -#define IX_HSSACC_TX_OVER_RUN_ERR 2 - -/** - * @def IX_HSSACC_CHANNELISED_SW_TX_ERR - * - * @brief NPE software error in channelised TX - */ -#define IX_HSSACC_CHANNELISED_SW_TX_ERR 3 - -/** - * @def IX_HSSACC_PACKETISED_SW_TX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_TX_ERR 4 - -/** - * @def IX_HSSACC_RX_FRM_SYNC_ERR - * - * @brief HSS port RX Frame Sync error - */ -#define IX_HSSACC_RX_FRM_SYNC_ERR 5 - -/** - * @def IX_HSSACC_RX_OVER_RUN_ERR - * - * @brief HSS port RX over-run error - */ -#define IX_HSSACC_RX_OVER_RUN_ERR 6 - -/** - * @def IX_HSSACC_CHANNELISED_SW_RX_ERR - * - * @brief NPE software error in channelised RX - */ -#define IX_HSSACC_CHANNELISED_SW_RX_ERR 7 - -/** - * @def IX_HSSACC_PACKETISED_SW_RX_ERR - * - * @brief NPE software error in packetised TX - */ -#define IX_HSSACC_PACKETISED_SW_RX_ERR 8 - -/* ----------------------------------- - Packetised service specific defines - ----------------------------------- */ - -/** - * @def IX_HSSACC_PKT_MIN_RX_MBUF_SIZE - * - * @brief Minimum size of the Rx mbuf in bytes which the client must supply - * to the component. - */ -#define IX_HSSACC_PKT_MIN_RX_MBUF_SIZE 64 - -/* -------------------------------------------------------------------- - Enumerated Types - these enumerated values may be used in setting up - the contents of hardware registers - -------------------------------------------------------------------- */ -/** - * @enum IxHssAccHssPort - * @brief The HSS port ID - There are two identical ports (0-1). - * - */ -typedef enum -{ - IX_HSSACC_HSS_PORT_0, /**< HSS Port 0 */ - IX_HSSACC_HSS_PORT_1, /**< HSS Port 1 */ - IX_HSSACC_HSS_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHssPort; - -/** - * @enum IxHssAccHdlcPort - * @brief The HDLC port ID - There are four identical HDLC ports (0-3) per - * HSS port and they correspond to the 4 E1/T1 trunks. - * - */ -typedef enum -{ - IX_HSSACC_HDLC_PORT_0, /**< HDLC Port 0 */ - IX_HSSACC_HDLC_PORT_1, /**< HDLC Port 1 */ - IX_HSSACC_HDLC_PORT_2, /**< HDLC Port 2 */ - IX_HSSACC_HDLC_PORT_3, /**< HDLC Port 3 */ - IX_HSSACC_HDLC_PORT_MAX /**< Delimiter for error checks */ -} IxHssAccHdlcPort; - -/** - * @enum IxHssAccTdmSlotUsage - * @brief The HSS TDM stream timeslot assignment types - * - */ -typedef enum -{ - IX_HSSACC_TDMMAP_UNASSIGNED, /**< Unassigned */ - IX_HSSACC_TDMMAP_HDLC, /**< HDLC - packetised */ - IX_HSSACC_TDMMAP_VOICE56K, /**< Voice56K - channelised */ - IX_HSSACC_TDMMAP_VOICE64K, /**< Voice64K - channelised */ - IX_HSSACC_TDMMAP_MAX /**< Delimiter for error checks */ -} IxHssAccTdmSlotUsage; - -/** - * @enum IxHssAccFrmSyncType - * @brief The HSS frame sync pulse type - * - */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_ACTIVE_LOW, /**< Frame sync is sampled low */ - IX_HSSACC_FRM_SYNC_ACTIVE_HIGH, /**< sampled high */ - IX_HSSACC_FRM_SYNC_FALLINGEDGE, /**< sampled on a falling edge */ - IX_HSSACC_FRM_SYNC_RISINGEDGE, /**< sampled on a rising edge */ - IX_HSSACC_FRM_SYNC_TYPE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncType; - -/** - * @enum IxHssAccFrmSyncEnable - * @brief The IxHssAccFrmSyncEnable determines how the frame sync pulse is - * used - * */ -typedef enum -{ - IX_HSSACC_FRM_SYNC_INPUT, /**< Frame sync is sampled as an input */ - IX_HSSACC_FRM_SYNC_INVALID_VALUE, /**< 1 is not used */ - IX_HSSACC_FRM_SYNC_OUTPUT_FALLING, /**< Frame sync is an output generated - off a falling clock edge */ - IX_HSSACC_FRM_SYNC_OUTPUT_RISING, /**< Frame sync is an output generated - off a rising clock edge */ - IX_HSSACC_FRM_SYNC_ENABLE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmSyncEnable; - -/** - * @enum IxHssAccClkEdge - * @brief IxHssAccClkEdge is used to determine the clk edge to use for - * framing and data - * - */ -typedef enum -{ - IX_HSSACC_CLK_EDGE_FALLING, /**< Clock sampled off a falling edge */ - IX_HSSACC_CLK_EDGE_RISING, /**< Clock sampled off a rising edge */ - IX_HSSACC_CLK_EDGE_MAX /**< Delimiter for error checks */ -} IxHssAccClkEdge; - -/** - * @enum IxHssAccClkDir - * @brief The HSS clock direction - * - */ -typedef enum -{ - IX_HSSACC_SYNC_CLK_DIR_INPUT, /**< Clock is an input */ - IX_HSSACC_SYNC_CLK_DIR_OUTPUT, /**< Clock is an output */ - IX_HSSACC_SYNC_CLK_DIR_MAX /**< Delimiter for error checks */ -} IxHssAccClkDir; - -/** - * @enum IxHssAccFrmPulseUsage - * @brief The HSS frame pulse usage - * - */ -typedef enum -{ - IX_HSSACC_FRM_PULSE_ENABLED, /**< Generate/Receive frame pulses */ - IX_HSSACC_FRM_PULSE_DISABLED, /**< Disregard frame pulses */ - IX_HSSACC_FRM_PULSE_MAX /**< Delimiter for error checks */ -} IxHssAccFrmPulseUsage; - -/** - * @enum IxHssAccDataRate - * @brief The HSS Data rate in relation to the clock - * - */ -typedef enum -{ - IX_HSSACC_CLK_RATE, /**< Data rate is at the configured clk speed */ - IX_HSSACC_HALF_CLK_RATE, /**< Data rate is half the configured clk speed */ - IX_HSSACC_DATA_RATE_MAX /**< Delimiter for error checks */ -} IxHssAccDataRate; - -/** - * @enum IxHssAccDataPolarity - * @brief The HSS data polarity type - * - */ -typedef enum -{ - IX_HSSACC_DATA_POLARITY_SAME, /**< Don't invert data between NPE and - HSS FIFOs */ - IX_HSSACC_DATA_POLARITY_INVERT, /**< Invert data between NPE and HSS - FIFOs */ - IX_HSSACC_DATA_POLARITY_MAX /**< Delimiter for error checks */ -} IxHssAccDataPolarity; - -/** - * @enum IxHssAccBitEndian - * @brief HSS Data endianness - * - */ -typedef enum -{ - IX_HSSACC_LSB_ENDIAN, /**< TX/RX Least Significant Bit first */ - IX_HSSACC_MSB_ENDIAN, /**< TX/RX Most Significant Bit first */ - IX_HSSACC_ENDIAN_MAX /**< Delimiter for the purposes of error checks */ -} IxHssAccBitEndian; - - -/** - * @enum IxHssAccDrainMode - * @brief Tx pin open drain mode - * - */ -typedef enum -{ - IX_HSSACC_TX_PINS_NORMAL, /**< Normal mode */ - IX_HSSACC_TX_PINS_OPEN_DRAIN, /**< Open Drain mode */ - IX_HSSACC_TX_PINS_MAX /**< Delimiter for error checks */ -} IxHssAccDrainMode; - -/** - * @enum IxHssAccSOFType - * @brief HSS start of frame types - * - */ -typedef enum -{ - IX_HSSACC_SOF_FBIT, /**< Framing bit transmitted and expected on rx */ - IX_HSSACC_SOF_DATA, /**< Framing bit not transmitted nor expected on rx */ - IX_HSSACC_SOF_MAX /**< Delimiter for error checks */ -} IxHssAccSOFType; - -/** - * @enum IxHssAccDataEnable - * @brief IxHssAccDataEnable is used to determine whether or not to drive - * the data pins - * - */ -typedef enum -{ - IX_HSSACC_DE_TRI_STATE, /**< TRI-State the data pins */ - IX_HSSACC_DE_DATA, /**< Push data out the data pins */ - IX_HSSACC_DE_MAX /**< Delimiter for error checks */ -} IxHssAccDataEnable; - -/** - * @enum IxHssAccTxSigType - * @brief IxHssAccTxSigType is used to determine how to drive the data pins - * - */ -typedef enum -{ - IX_HSSACC_TXSIG_LOW, /**< Drive the data pins low */ - IX_HSSACC_TXSIG_HIGH, /**< Drive the data pins high */ - IX_HSSACC_TXSIG_HIGH_IMP, /**< Drive the data pins with high impedance */ - IX_HSSACC_TXSIG_MAX /**< Delimiter for error checks */ -} IxHssAccTxSigType; - -/** - * @enum IxHssAccFbType - * @brief IxHssAccFbType determines how to drive the Fbit - * - * @warning This will only be used for T1 @ 1.544MHz - * - */ -typedef enum -{ - IX_HSSACC_FB_FIFO, /**< Fbit is dictated in FIFO */ - IX_HSSACC_FB_HIGH_IMP, /**< Fbit is high impedance */ - IX_HSSACC_FB_MAX /**< Delimiter for error checks */ -} IxHssAccFbType; - -/** - * @enum IxHssAcc56kEndianness - * @brief 56k data endianness when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KE_BIT_7_UNUSED, /**< High bit is unused */ - IX_HSSACC_56KE_BIT_0_UNUSED, /**< Low bit is unused */ - IX_HSSACC_56KE_MAX /**< Delimiter for error checks */ -} IxHssAcc56kEndianness; - -/** - * @enum IxHssAcc56kSel - * @brief 56k data transmission type when using the 56k type - * - */ -typedef enum -{ - IX_HSSACC_56KS_32_8_DATA, /**< 32/8 bit data */ - IX_HSSACC_56KS_56K_DATA, /**< 56K data */ - IX_HSSACC_56KS_MAX /**< Delimiter for error checks */ -} IxHssAcc56kSel; - - -/** - * @enum IxHssAccClkSpeed - * @brief IxHssAccClkSpeed represents the HSS clock speeds available - * - */ -typedef enum -{ - IX_HSSACC_CLK_SPEED_512KHZ, /**< 512KHz */ - IX_HSSACC_CLK_SPEED_1536KHZ, /**< 1.536MHz */ - IX_HSSACC_CLK_SPEED_1544KHZ, /**< 1.544MHz */ - IX_HSSACC_CLK_SPEED_2048KHZ, /**< 2.048MHz */ - IX_HSSACC_CLK_SPEED_4096KHZ, /**< 4.096MHz */ - IX_HSSACC_CLK_SPEED_8192KHZ, /**< 8.192MHz */ - IX_HSSACC_CLK_SPEED_MAX /**< Delimiter for error checking */ -} IxHssAccClkSpeed; - -/** - * @enum IxHssAccPktStatus - * @brief Indicates the status of packets passed to the client - * - */ -typedef enum -{ - IX_HSSACC_PKT_OK, /**< Error free.*/ - IX_HSSACC_STOP_SHUTDOWN_ERROR, /**< Errored due to stop or shutdown - occurrance.*/ - IX_HSSACC_HDLC_ALN_ERROR, /**< HDLC alignment error */ - IX_HSSACC_HDLC_FCS_ERROR, /**< HDLC Frame Check Sum error.*/ - IX_HSSACC_RXFREE_Q_EMPTY_ERROR, /**< RxFree Q became empty - while receiving this packet.*/ - IX_HSSACC_HDLC_MAX_FRAME_SIZE_EXCEEDED, /**< HDLC frame size - received is greater than - max specified at connect.*/ - IX_HSSACC_HDLC_ABORT_ERROR, /**< HDLC frame received is invalid due to an - abort sequence received.*/ - IX_HSSACC_DISCONNECT_IN_PROGRESS /**< Packet returned - because a disconnect is in progress */ -} IxHssAccPktStatus; - - -/** - * @enum IxHssAccPktCrcType - * @brief HDLC CRC type - * - */ -typedef enum -{ - IX_HSSACC_PKT_16_BIT_CRC = 16, /**< 16 bit CRC is being used */ - IX_HSSACC_PKT_32_BIT_CRC = 32 /**< 32 bit CRC is being used */ -} IxHssAccPktCrcType; - -/** - * @enum IxHssAccPktHdlcIdleType - * @brief HDLC idle transmission type - * - */ -typedef enum -{ - IX_HSSACC_HDLC_IDLE_ONES, /**< idle tx/rx will be a succession of ones */ - IX_HSSACC_HDLC_IDLE_FLAGS /**< idle tx/rx will be repeated flags */ -} IxHssAccPktHdlcIdleType; - -/** - * @brief Structure containing HSS port configuration parameters - * - * Note: All of these are used for TX. Only some are specific to RX. - * - */ -typedef struct -{ - IxHssAccFrmSyncType frmSyncType; /**< frame sync pulse type (tx/rx) */ - IxHssAccFrmSyncEnable frmSyncIO; /**< how the frame sync pulse is - used (tx/rx) */ - IxHssAccClkEdge frmSyncClkEdge; /**< frame sync clock edge type - (tx/rx) */ - IxHssAccClkEdge dataClkEdge; /**< data clock edge type (tx/rx) */ - IxHssAccClkDir clkDirection; /**< clock direction (tx/rx) */ - IxHssAccFrmPulseUsage frmPulseUsage; /**< whether to use the frame sync - pulse or not (tx/rx) */ - IxHssAccDataRate dataRate; /**< data rate in relation to the - clock (tx/rx) */ - IxHssAccDataPolarity dataPolarity; /**< data polarity type (tx/rx) */ - IxHssAccBitEndian dataEndianness; /**< data endianness (tx/rx) */ - IxHssAccDrainMode drainMode; /**< tx pin open drain mode (tx) */ - IxHssAccSOFType fBitUsage; /**< start of frame types (tx/rx) */ - IxHssAccDataEnable dataEnable; /**< whether or not to drive the data - pins (tx) */ - IxHssAccTxSigType voice56kType; /**< how to drive the data pins for - voice56k type (tx) */ - IxHssAccTxSigType unassignedType; /**< how to drive the data pins for - unassigned type (tx) */ - IxHssAccFbType fBitType; /**< how to drive the Fbit (tx) */ - IxHssAcc56kEndianness voice56kEndian;/**< 56k data endianness when using - the 56k type (tx) */ - IxHssAcc56kSel voice56kSel; /**< 56k data transmission type when - using the 56k type (tx) */ - unsigned frmOffset; /**< frame pulse offset in bits wrt - the first timeslot (0-1023) (tx/rx) */ - unsigned maxFrmSize; /**< frame size in bits (1-1024) - (tx/rx) */ -} IxHssAccPortConfig; - -/** - * @brief Structure containing HSS configuration parameters - * - */ -typedef struct -{ - IxHssAccPortConfig txPortConfig; /**< HSS tx port configuration */ - IxHssAccPortConfig rxPortConfig; /**< HSS rx port configuration */ - unsigned numChannelised; /**< The number of channelised - timeslots (0-32) */ - unsigned hssPktChannelCount; /**< The number of packetised - clients (0 - 4) */ - UINT8 channelisedIdlePattern; /**< The byte to be transmitted on - channelised service when there - is no client data to tx */ - BOOL loopback; /**< The HSS loopback state */ - unsigned packetizedIdlePattern; /**< The data to be transmitted on - packetised service when there is - no client data to tx */ - IxHssAccClkSpeed clkSpeed; /**< The HSS clock speed */ -} IxHssAccConfigParams; - -/** - * @brief This structure contains 56Kbps, HDLC-mode configuration parameters - * - */ -typedef struct -{ - BOOL hdlc56kMode; /**< 56kbps(true)/64kbps(false) HDLC */ - IxHssAcc56kEndianness hdlc56kEndian; /**< 56kbps data endianness - - ignored if hdlc56kMode is false*/ - BOOL hdlc56kUnusedBitPolarity0; /**< The polarity '0'(true)/'1'(false) of the unused - bit while in 56kbps mode - - ignored if hdlc56kMode is false*/ -} IxHssAccHdlcMode; - -/** - * @brief This structure contains information required by the NPE to - * configure the HDLC co-processor - * - */ -typedef struct -{ - IxHssAccPktHdlcIdleType hdlcIdleType; /**< What to transmit when a HDLC port is idle */ - IxHssAccBitEndian dataEndian; /**< The HDLC data endianness */ - IxHssAccPktCrcType crcType; /**< The CRC type to be used for this HDLC port */ -} IxHssAccPktHdlcFraming; - -/** - * @typedef UINT32 IxHssAccPktUserId - * - * @brief The client supplied value which will be supplied as a parameter - * with a given callback. - * - * This value will be passed into the ixHssAccPktPortConnect function once each - * with given callbacks. This value will then be passed back to the client - * as one of the parameters to each of these callbacks, - * when these callbacks are called. - */ -typedef UINT32 IxHssAccPktUserId; - - -/** - * @typedef IxHssAccLastErrorCallback - * @brief Prototype of the clients function to accept notification of the - * last error - * - * This function is registered through the config. The client will initiate - * the last error retrieval. The HssAccess component will send a message to - * the NPE through the NPE Message Handler. When a response to the read is - * received, the NPE Message Handler will callback the HssAccess component - * which will execute this function in the same IxNpeMh context. The client - * will be passed the last error and the related service port (packetised - * 0-3, channelised 0) - * - * @param lastHssError unsigned [in] - The last Hss error registered that - * has been registered. - * @param servicePort unsigned [in] - This is the service port number. - * (packetised 0-3, channelised 0) - * - * @return void - */ -typedef void (*IxHssAccLastErrorCallback) (unsigned lastHssError, - unsigned servicePort); - -/** - * @typedef IxHssAccPktRxCallback - * @brief Prototype of the clients function to accept notification of - * packetised rx - * - * This function is registered through the ixHssAccPktPortConnect. hssPktAcc will pass - * received data in the form of mbufs to the client. The mbuf passed back - * to the client could contain a chain of buffers, depending on the packet - * size received. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contains the - * payload received. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been received. - * @param rxUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktRxCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId rxUserId); - -/** - * @typedef IxHssAccPktRxFreeLowCallback - * @brief Prototype of the clients function to accept notification of - * requirement of more Rx Free buffers - * - * The client can choose to register a callback of this type when - * calling a connecting. This function is registered through the ixHssAccPktPortConnect. - * If defined, the access layer will provide the trigger for - * this callback. The callback will be responsible for supplying mbufs to - * the access layer for use on the receive path from the HSS using - * ixHssPktAccFreeBufReplenish. - * - * @return void - */ -typedef void (*IxHssAccPktRxFreeLowCallback) (IxHssAccPktUserId rxFreeLowUserId); - -/** - * @typedef IxHssAccPktTxDoneCallback - * @brief Prototype of the clients function to accept notification of - * completion with Tx buffers - * - * This function is registered through the ixHssAccPktPortConnect. It enables - * the hssPktAcc to pass buffers back to the client - * when transmission is complete. - * - * @param *buffer @ref IX_OSAL_MBUF [in] - This is the mbuf which contained - * the payload that was for Tx. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * @param pktStatus @ref IxHssAccPktStatus [in] - This is the status of the - * mbuf that has been transmitted. - * @param txDoneUserId @ref IxHssAccPktUserId [in] - This is the client supplied value - * passed in at ixHssAccPktPortConnect time which is now returned to the client. - * - * @return void - */ -typedef void (*IxHssAccPktTxDoneCallback) (IX_OSAL_MBUF *buffer, - unsigned numHssErrs, - IxHssAccPktStatus pktStatus, - IxHssAccPktUserId txDoneUserId); - -/** - * @typedef IxHssAccChanRxCallback - * @brief Prototype of the clients function to accept notification of - * channelised rx - * - * This callback, if defined by the client in the connect, will get called - * in the context of an IRQ. The IRQ will be triggered when the hssSyncQMQ - * is not empty. The queued entry will be dequeued and this function will - * be executed. - * - * @param hssPortId @ref IxHssAccHssPort - The HSS port Id. There are two - * identical ports (0-1). - * @param txOffset unsigned [in] - an offset indicating from where within - * the txPtrList the NPE is currently transmitting from. - * @param rxOffset unsigned [in] - an offset indicating where within the - * receive buffers the NPE has just written the received data to. - * @param numHssErrs unsigned [in] - This is the number of hssErrors - * the Npe has received - * - * @return void - */ -typedef void (*IxHssAccChanRxCallback) (IxHssAccHssPort hssPortId, - unsigned rxOffset, - unsigned txOffset, - unsigned numHssErrs); - -/* - * Prototypes for interface functions. - */ - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback) - * - * @brief Initialise a HSS port. No channelised or packetised connections - * should exist in the HssAccess layer while this interface is being called. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *configParams @ref IxHssAccConfigParams [in] - A pointer to the HSS - * configuration structure - * @param *tdmMap @ref IxHssAccTdmSlotUsage [in] - A pointer to an array of size - * IX_HSSACC_TSLOTS_PER_HSS_PORT, defining the slot usage over the HSS port - * @param lastHssErrorCallback @ref IxHssAccLastErrorCallback [in] - Client - * callback to report last error - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPortInit (IxHssAccHssPort hssPortId, - IxHssAccConfigParams *configParams, - IxHssAccTdmSlotUsage *tdmMap, - IxHssAccLastErrorCallback lastHssErrorCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccLastErrorRetrievalInitiate ( - IxHssAccHssPort hssPortId) - * - * @brief Initiate the retrieval of the last HSS error. The HSS port - * should be configured before attempting to call this interface. - * - * @param hssPortId @ref IxHssAccHssPort [in] - the HSS port ID - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccLastErrorRetrievalInitiate (IxHssAccHssPort hssPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccInit () - * - * @brief This function is responsible for initialising resources for use - * by the packetised and channelised clients. It should be called after - * HSS NPE image has been downloaded into NPE-A and before any other - * HssAccess interface is called. - * No other HssAccPacketised interface should be called while this interface - * is being processed. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccInit (void); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId) - * - * @brief This function is responsible for connecting a client to one of - * the 4 available HDLC ports. The HSS port should be configured before - * attempting a connect. No other HssAccPacketised interface should be - * called while this connect is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port and - * it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param hdlcFraming BOOL [in] - This value determines whether the service - * will use HDLC data or the debug, raw data type i.e. no HDLC processing - * @param hdlcMode @ref IxHssAccHdlcMode [in] - This structure contains 56Kbps, HDLC-mode - * configuration parameters - * @param hdlcBitInvert BOOL [in] - This value determines whether bit inversion - * will occur between HDLC and HSS co-processors i.e. post-HDLC processing for - * transmit and pre-HDLC processing for receive, for the specified HDLC Termination - * Point - * @param blockSizeInWords unsigned [in] - The max tx/rx block size - * @param rawIdleBlockPattern UINT32 [in] - Tx idle pattern in raw mode - * @param hdlcTxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for TX - * @param hdlcRxFraming @ref IxHssAccPktHdlcFraming [in] - This structure contains - * the following information required by the NPE to configure the HDLC - * co-processor for RX - * @param frmFlagStart unsigned - Number of flags to precede to - * transmitted flags (0-2). - * @param rxCallback @ref IxHssAccPktRxCallback [in] - Pointer to - * the clients packet receive function. - * @param rxUserId @ref IxHssAccPktUserId [in] - The client supplied rx value - * to be passed back as an argument to the supplied rxCallback - * @param rxFreeLowCallback @ref IxHssAccPktRxFreeLowCallback [in] - Pointer to - * the clients Rx free buffer request function. If NULL, assume client will - * trigger independently. - * @param rxFreeLowUserId @ref IxHssAccPktUserId [in] - The client supplied RxFreeLow value - * to be passed back as an argument to the supplied rxFreeLowCallback - * @param txDoneCallback @ref IxHssAccPktTxDoneCallback [in] - Pointer to the - * clients Tx done callback function - * @param txDoneUserId @ref IxHssAccPktUserId [in] - The client supplied txDone value - * to be passed back as an argument to the supplied txDoneCallback - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - */ -PUBLIC IX_STATUS -ixHssAccPktPortConnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - BOOL hdlcFraming, - IxHssAccHdlcMode hdlcMode, - BOOL hdlcBitInvert, - unsigned blockSizeInWords, - UINT32 rawIdleBlockPattern, - IxHssAccPktHdlcFraming hdlcTxFraming, - IxHssAccPktHdlcFraming hdlcRxFraming, - unsigned frmFlagStart, - IxHssAccPktRxCallback rxCallback, - IxHssAccPktUserId rxUserId, - IxHssAccPktRxFreeLowCallback rxFreeLowCallback, - IxHssAccPktUserId rxFreeLowUserId, - IxHssAccPktTxDoneCallback txDoneCallback, - IxHssAccPktUserId txDoneUserId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for enabling a packetised service - * for the specified HSS/HDLC port combination. It enables the RX flow. The - * client must have already connected to a packetised service and is responsible - * for ensuring an adequate amount of RX mbufs have been supplied to the access - * component before enabling the packetised service. This function must be called - * on a given port before any call to ixHssAccPktPortTx on the same port. - * No other HssAccPacketised interface should be called while this interface is - * being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to enable the service - * on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortEnable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * @fn IX_STATUS ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disabling a packetised service - * for the specified HSS/HDLC port combination. It disables the RX flow. - * The client must have already connected to and enabled a packetised service - * for the specified HDLC port. This disable interface can be called before a - * disconnect, but is not required to. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - The port id (0,1,2,3) to disable - * the service on. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisable (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is responsible for disconnecting a client from one - * of the 4 available HDLC ports. It is not required that the Rx Flow - * has been disabled before calling this function. If the RX Flow has not been - * disabled, the disconnect will disable it before proceeding with the - * disconnect. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PKT_DISCONNECTING The function has initiated the disconnecting - * procedure but it has not completed yet. - */ -PUBLIC IX_STATUS -ixHssAccPktPortDisconnect (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn BOOL ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId) - * - * @brief This function is called to check if a given HSS/HDLC port - * combination is in a connected state or not. This function may be called - * at any time to determine a ports state. No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * to disconnect and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * - * @return - * - true The state of this HSS/HDLC port combination is disconnected, - * so if a disconnect was called, it is now completed. - * - false The state of this HSS/HDLC port combination is connected, - * so if a disconnect was called, it is not yet completed. - */ -PUBLIC BOOL -ixHssAccPktPortIsDisconnectComplete (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId); - - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls at regular intervals to provide - * mbufs to the access component for RX. A connection should exist for - * the specified hssPortId/hdlcPortId combination before attempting to call this - * interface. Also, the connection should not be in a disconnecting state. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a free mbuf to filled with payload. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - */ -PUBLIC IX_STATUS -ixHssAccPktPortRxFreeReplenish (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer) - * - * @brief Function which the client calls when it wants to transmit - * packetised data. An enabled connection should exist on the specified - * hssPortId/hdlcPortId combination before attempting to call this interface. - * No other HssAccPacketised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param hdlcPortId @ref IxHssAccHdlcPort [in] - This is the number of the HDLC port - * and it corresponds to the physical E1/T1 trunk i.e. 0, 1, 2, 3 - * @param *buffer @ref IX_OSAL_MBUF [in] - A pointer to a chain of mbufs which the - * client has filled with the payload - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - * - IX_HSSACC_RESOURCE_ERR The function did not execute successfully due - * to a resource error. See note. - * - IX_HSSACC_Q_WRITE_OVERFLOW The function did not succeed due to a Q - * overflow - * - * @note IX_HSSACC_RESOURCE_ERR is returned when a free descriptor cannot be - * obtained to send the chain of mbufs to the NPE. This is a normal scenario. - * HssAcc has a pool of descriptors and this error means that they are currently - * all in use. - * The recommended approach to this is to retry until a descriptor becomes free - * and the packet is successfully transmitted. - * Alternatively, the user could wait until the next IxHssAccPktTxDoneCallback - * callback is triggered, and then retry, as it is this event that causes a - * transmit descriptor to be freed. - */ -PUBLIC IX_STATUS -ixHssAccPktPortTx (IxHssAccHssPort hssPortId, - IxHssAccHdlcPort hdlcPortId, - IX_OSAL_MBUF *buffer); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback) - * - * @brief This function allows the client to connect to the Tx/Rx NPE - * Channelised Service. There can only be one client per HSS port. The - * client is responsible for ensuring that the HSS port is configured - * appropriately before its connect request. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param bytesPerTSTrigger unsigned [in] - The NPE will trigger the access - * component after bytesPerTSTrigger have been received for all trunk - * timeslots. This figure is a multiple of 8 e.g. 8 for 1ms trigger, 16 for - * 2ms trigger. - * @param *rxCircular UINT8 [in] - A pointer to memory allocated by the - * client to be filled by data received. The buffer at this address is part - * of a pool of buffers to be accessed in a circular fashion. This address - * will be written to by the NPE. Therefore, it needs to be a physical address. - * @param numRxBytesPerTS unsigned [in] - The number of bytes allocated per - * timeslot within the receive memory. This figure will depend on the - * latency of the system. It needs to be deep enough for data to be read by - * the client before the NPE re-writes over that memory e.g. if the client - * samples at a rate of 40bytes per timeslot, numRxBytesPerTS may need to - * be 40bytes * 3. This would give the client 3 * 5ms of time before - * received data is over-written. - * @param *txPtrList UINT32 [in] - The address of an area of contiguous - * memory allocated by the client to be populated with pointers to data for - * transmission. Each pointer list contains a pointer per active channel. - * The txPtrs will point to data to be transmitted by the NPE. Therefore, - * they must point to physical addresses. - * @param numTxPtrLists unsigned [in] - The number of pointer lists in - * txPtrList. This figure is dependent on jitter. - * @param numTxBytesPerBlk unsigned [in] - The size of the Tx data, in - * bytes, that each pointer within the PtrList points to. - * @param rxCallback @ref IxHssAccChanRxCallback [in] - A client function - * pointer to be called back to handle the actual tx/rx of channelised - * data. If this is not NULL, an ISR will call this function. If this - * pointer is NULL, it implies that the client will use a polling mechanism - * to detect when the tx and rx of channelised data is to occur. The client - * will use hssChanAccStatus for this. - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ - -PUBLIC IX_STATUS -ixHssAccChanConnect (IxHssAccHssPort hssPortId, - unsigned bytesPerTSTrigger, - UINT8 *rxCircular, - unsigned numRxBytesPerTS, - UINT32 *txPtrList, - unsigned numTxPtrLists, - unsigned numTxBytesPerBlk, - IxHssAccChanRxCallback rxCallback); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortEnable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for enabling a channelised service - * for the specified HSS port. It enables the NPE RX flow. The client must - * have already connected to a channelised service before enabling the - * channelised service. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortEnable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanPortDisable (IxHssAccHssPort hssPortId) - * - * @brief This function is responsible for disabling a channelised service - * for the specified HSS port. It disables the NPE RX flow. The client must - * have already connected to and enabled a channelised service for the - * specified HSS port. This disable interface can be called before a - * disconnect, but is not required to. No other HssAccChannelised - * interface should be called while this interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanPortDisable (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanDisconnect (IxHssAccHssPort hssPortId) - * - * @brief This function allows the client to Disconnect from a channelised - * service. If the NPE RX Flow has not been disabled, the disconnect will - * disable it before proceeding with other disconnect functionality. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanDisconnect (IxHssAccHssPort hssPortId); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn IX_STATUS ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs) - * - * @brief This function is called by the client to query whether or not - * channelised data has been received. If there is, hssChanAcc will return - * the details in the output parameters. An enabled connection should - * exist on the specified hssPortId before attempting to call this interface. - * No other HssAccChannelised interface should be called while this - * interface is being processed. - * - * @param hssPortId @ref IxHssAccHssPort [in] - The HSS port Id. There are two - * identical ports (0-1). - * @param *dataRecvd BOOL [out] - This BOOL indicates to the client whether - * or not the access component has read any data for the client. If - * false, the other output parameters will not have been written to. - * @param *rxOffset unsigned [out] - An offset to indicate to the client - * where within the receive buffers the NPE has just written the received - * data to. - * @param *txOffset unsigned [out] - An offset to indicate to the client - * from where within the txPtrList the NPE is currently transmitting from - * @param *numHssErrs unsigned [out] - The total number of HSS port errors - * since initial port configuration - * - * - * @return - * - IX_SUCCESS The function executed successfully - * - IX_FAIL The function did not execute successfully - * - IX_HSSACC_PARAM_ERR The function did not execute successfully due to a - * parameter error - */ -PUBLIC IX_STATUS -ixHssAccChanStatusQuery (IxHssAccHssPort hssPortId, - BOOL *dataRecvd, - unsigned *rxOffset, - unsigned *txOffset, - unsigned *numHssErrs); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccShow (void) - * - * @brief This function will display the current state of the IxHssAcc - * component. The output is sent to stdout. - * - * @return void - */ -PUBLIC void -ixHssAccShow (void); - -/** - * - * @ingroup IxHssAccAPI - * - * @fn void ixHssAccStatsInit (void) - * - * @brief This function will reset the IxHssAcc statistics. - * - * @return void - */ -PUBLIC void -ixHssAccStatsInit (void); - -#endif /* IXHSSACC_H */ - -/** - * @} defgroup IxHssAcc - */ diff --git a/drivers/net/npe/include/IxI2cDrv.h b/drivers/net/npe/include/IxI2cDrv.h deleted file mode 100644 index 033154046fc..00000000000 --- a/drivers/net/npe/include/IxI2cDrv.h +++ /dev/null @@ -1,843 +0,0 @@ -/** - * @file IxI2cDrv.h - * - * @brief Header file for the IXP400 I2C Driver (IxI2cDrv) - * - * @version $Revision: 0.1 $ - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxI2cDrv IXP400 I2C Driver(IxI2cDrv) API - * - * @brief IXP400 I2C Driver Public API - * - * @{ - */ -#ifndef IXI2CDRV_H -#define IXI2CDRV_H - -#ifdef __ixp46X -#include "IxOsal.h" - -/* - * Section for #define - */ - -/** - * @ingroup IxI2cDrv - * @brief The interval of micro/mili seconds the IXP will wait before it polls for - * status from the ixI2cIntrXferStatus; Every 20us is 1 byte @ - * 400Kbps and 4 bytes @ 100Kbps. This is dependent on delay type selected - * through the API ixI2cDrvDelayTypeSelect. - */ -#define IX_I2C_US_POLL_FOR_XFER_STATUS 20 - -/** - * @ingroup IxI2cDrv - * @brief The number of tries that will be attempted to call a callback - * function if the callback does not or is unable to resolve the - * issue it is called to resolve - */ -#define IX_I2C_NUM_OF_TRIES_TO_CALL_CALLBACK_FUNC 10 - - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Rx full bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_RX_FULL 0x100 - -/** - * @ingroup IxI2cDrv - * @brief Number of tries slave will poll the IDBR Tx empty bit before it - * gives up - */ -#define IX_I2C_NUM_TO_POLL_IDBR_TX_EMPTY 0x100 - -/* - * Section for enum - */ - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cMasterStatus - * - * @brief The master status - transfer complete, bus error or arbitration loss - */ -typedef enum -{ - IX_I2C_MASTER_XFER_COMPLETE = IX_SUCCESS, - IX_I2C_MASTER_XFER_BUS_ERROR, - IX_I2C_MASTER_XFER_ARB_LOSS -} IxI2cMasterStatus; - - -/** - * @ingroup IxI2cDrv - * - * @enum IX_I2C_STATUS - * - * @brief The status that can be returned in a I2C driver initialization - */ -typedef enum -{ - IX_I2C_SUCCESS = IX_SUCCESS, /**< Success status */ - IX_I2C_FAIL, /**< Fail status */ - IX_I2C_NOT_SUPPORTED, /**< hardware does not have dedicated I2C hardware */ - IX_I2C_NULL_POINTER, /**< parameter passed in is NULL */ - IX_I2C_INVALID_SPEED_MODE_ENUM_VALUE, /**< speed mode selected is invalid */ - IX_I2C_INVALID_FLOW_MODE_ENUM_VALUE, /**< flow mode selected is invalid */ - IX_I2C_SLAVE_ADDR_CB_MISSING, /**< slave callback is NULL */ - IX_I2C_GEN_CALL_CB_MISSING, /**< general callback is NULL */ - IX_I2C_INVALID_SLAVE_ADDR, /**< invalid slave address specified */ - IX_I2C_INT_BIND_FAIL, /**< interrupt bind fail */ - IX_I2C_INT_UNBIND_FAIL, /**< interrupt unbind fail */ - IX_I2C_NOT_INIT, /**< I2C is not initialized yet */ - IX_I2C_MASTER_BUS_BUSY, /**< master detected a I2C bus busy */ - IX_I2C_MASTER_ARB_LOSS, /**< master experienced arbitration loss */ - IX_I2C_MASTER_XFER_ERROR, /**< master experienced a transfer error */ - IX_I2C_MASTER_BUS_ERROR, /**< master detected a I2C bus error */ - IX_I2C_MASTER_NO_BUFFER, /**< no buffer provided for master transfer */ - IX_I2C_MASTER_INVALID_XFER_MODE, /**< xfer mode selected is invalid */ - IX_I2C_SLAVE_ADDR_NOT_DETECTED, /**< polled slave addr not detected */ - IX_I2C_GEN_CALL_ADDR_DETECTED, /**< polling detected general call */ - IX_I2C_SLAVE_READ_DETECTED, /**< polling detected slave read request */ - IX_I2C_SLAVE_WRITE_DETECTED, /**< polling detected slave write request */ - IX_I2C_SLAVE_NO_BUFFER, /**< no buffer provided for slave transfers */ - IX_I2C_DATA_SIZE_ZERO, /**< data size transfer is zero - invalid */ - IX_I2C_SLAVE_WRITE_BUFFER_EMPTY, /**< slave buffer is used till empty */ - IX_I2C_SLAVE_WRITE_ERROR, /**< slave write experienced an error */ - IX_I2C_SLAVE_OR_GEN_READ_BUFFER_FULL, /**< slave buffer is filled up */ - IX_I2C_SLAVE_OR_GEN_READ_ERROR /**< slave read experienced an error */ -} IX_I2C_STATUS; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cSpeedMode - * - * @brief Type of speed modes supported by the I2C hardware. - */ -typedef enum -{ - IX_I2C_NORMAL_MODE = 0x0, - IX_I2C_FAST_MODE -} IxI2cSpeedMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cXferMode - * - * @brief Used for indicating it is a repeated start or normal transfer - */ -typedef enum -{ - IX_I2C_NORMAL = 0x0, - IX_I2C_REPEATED_START -} IxI2cXferMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cFlowMode - * - * @brief Used for indicating it is a poll or interrupt mode - */ -typedef enum -{ - IX_I2C_POLL_MODE = 0x0, - IX_I2C_INTERRUPT_MODE -} IxI2cFlowMode; - -/** - * @ingroup IxI2cDrv - * - * @enum IxI2cDelayMode - * - * @brief Used for selecting looping delay or OS scheduler delay - */ -typedef enum -{ - IX_I2C_LOOP_DELAY = 1, /**< delay in microseconds */ - IX_I2C_SCHED_DELAY /**< delay in miliseconds */ -} IxI2cDelayMode; - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its receive. The parameter that is passed will - * provide the status of the read (success, arb loss, or bus - * error), the transfer mode (normal or repeated start, the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterReadCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when the master - * has completed its transmit. The parameter that is passed will - * provide the status of the write (success, arb loss, or buss - * error), the transfer mode (normal or repeated start), the - * buffer pointer and number of bytes transferred. - */ -typedef void (*IxI2cMasterWriteCallbackP)(IxI2cMasterStatus, IxI2cXferMode, char*, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a read. The parameters - * that is passed will provide the read status, buffer pointer, - * buffer size, and the bytes received. When a start of a read - * is initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cSlaveReadCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a slave - * address detected in interrupt mode for a write. The parameters - * that is passed will provide the write status, buffer pointer, - * buffer size, and the bytes received. When a start of a write is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer and to fill it with data. - * While transmitting, if the data in the buffer empties, this - * callback will be called to request for more data to be filled in - * the same or new buffer. When the transmit is complete, this - * callback will be called to free the memory or other actions to - * be taken. - */ -typedef void (*IxI2cSlaveWriteCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/** - * @ingroup IxI2cDrv - * - * @brief The pointer to the function that will be called when a general - * call detected in interrupt mode for a read. The parameters that - * is passed will provide the read status, buffer pointer, buffer - * size, and the bytes received. When a start of a read is - * initiated there will be no buffer allocated and this callback - * will be called to request for a buffer. While receiving, if the - * buffer gets filled, this callback will be called to request for - * a new buffer while sending the filled buffer's pointer and size, - * and data size received. When the receive is complete, this - * callback will be called to process the data and free the memory - * by passing the buffer's pointer and size, and data size received. - */ -typedef void (*IxI2cGenCallCallbackP)(IX_I2C_STATUS, char*, UINT32, UINT32); - -/* - * Section for struct - */ - -/** - * @brief contains all the variables required to initialize the I2C unit - * - * Structure to be filled and used for calling initialization - */ -typedef struct -{ - IxI2cSpeedMode I2cSpeedSelect; /** - * NOTE: 1) An individual callback is to be registered for each Slave and Master - * Auxiliary Time Stamp registers. Thus to register for both Master and Slave time - * stamp interrupts either the same callback or two separate callbacks the API has - * to be invoked twice. - * 2) On the IXDP465 Development Platform, the Auxiliary Timestamp signal for - * slave mode is tied to GPIO 8 pin. This signal is software routed by default to - * PCI for backwards compatibility with the IXDP425 Development Platform. This - * routing must be disabled for the auxiliary slave time stamp register to work - * properly. The following commands may be used to accomplish this. However, refer - * to the IXDP465 Development Platform Users Guide or the BSP/LSP documentation for - * more specific information. - * - * For Linux (at the Redboot prompt i.e., before loading zImage): - * mfill -b 0x54100000 -1 -l 1 -p 8 - * mfill -b 0x54100001 -1 -l 1 -p 0x7f - * For vxWorks, at the prompt: - * intDisable(25) - * ixdp400FpgaIODetach(8) - * - * - * @li Re-entrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for callback or - invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptEnable(IxTimeSyncAccAuxMode auxMode, - IxTimeSyncAccAuxTimeCallback auxTimeCallback); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimeInterruptDisable( - IxTimeSyncAccAuxMode auxMode) - * - * @brief Disables the interrupt for the indicated mode of Auxiliary Time Stamp - * in the IEEE 1588 hardware assist block - * - * @param auxMode [in] - Auxiliary time stamp mode (slave or master) using which - * the interrupt will be disabled. - * - * This API will disable the Auxiliary Time Stamp Interrupt (Master or Slave) - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Invalid parameters passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimeInterruptDisable(IxTimeSyncAccAuxMode auxMode); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccAuxTimePoll( - IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime) - * - * @brief Poll for the Auxiliary Time Stamp captured for the mode indicated - * (Master or Slave) - * - * @param auxMode [in] - Auxiliary Snapshot Register (Slave or Master) to be checked - * @param auxPollFlag [out] - true if the time stamp captured in auxiliary - snapshot register - * false if the time stamp not captured in - auxiliary snapshot register - * @param auxTime [out] - Copy the current Auxiliary Snapshot Register value into the - * client provided buffer - * - * Polls for the Time stamp in the appropriate Auxiliary Snapshot Registers based - * on the mode specified. Return true and the contents of the Auxiliary snapshot, - * if it is available else return false. - * - * Please refer to the note #2 of the API @ref ixTimeSyncAccAuxTimeInterruptEnable - * for more information for Auxiliary Slave mode. - * - * @li Re-entrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - Null parameter passed for auxPollFlag, - callback or invalid auxiliary snapshot mode - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - * @li IX_TIMESYNCACC_INTERRUPTMODEINUSE - Interrupt mode in use - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccAuxTimePoll(IxTimeSyncAccAuxMode auxMode, - BOOL *auxPollFlag, - IxTimeSyncAccTimeValue *auxTime); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccReset(void) - * - * @brief Resets the IEEE 1588 hardware assist block - * - * Sets the reset bit in the IEEE1588 silicon which fully resets the silicon block - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccStatsGet(IxTimeSyncAccStats - *timeSyncStats) - * - * @brief Returns the IxTimeSyncAcc Statistics in the client supplied buffer - * - * @param timeSyncStats [out] - TimeSync statistics counter values - * - * This API will return the statistics of the received or transmitted messages. - * - * NOTE: 1) These counters are updated only when the client polls for the time - * stamps or interrupt are enabled. This is because the IxTimeSyncAcc module - * does not either transmit or receive messages and does only run the code - * when explicit requests received by client application. - * - * 2) These statistics reflect the number of valid PTP messages exchanged - * in Master and Slave modes but includes all the messages (including valid - * non-PTP messages) while operating in the Any mode. - * - * @li Reentrant : no - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_INVALIDPARAM - NULL parameter passed - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccStatsGet(IxTimeSyncAccStats *timeSyncStats); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn void ixTimeSyncAccStatsReset(void) - * - * @brief Reset Time Sync statistics - * - * This API will reset the statistics counters of the TimeSync access layer. - * - * @li Reentrant : yes - * @li ISR Callable: no - * - * @return @li None - */ -PUBLIC void -ixTimeSyncAccStatsReset(void); - -/** - * @ingroup IxTimeSyncAcc - * - * @fn IxTimeSyncAccStatus ixTimeSyncAccShow(void) - * - * @brief Displays the Time Sync current status - * - * This API will display status on the current configuration of the IEEE - * 1588 hardware assist block, contents of the various time stamp registers, - * outstanding interrupts and/or events. - * - * Note that this is intended for debug only, and in contrast to the other - * functions, it does not clear the any of the status bits associated with - * active timestamps and so is passive in its nature. - * - * @li Reentrant : yes - * @li ISR Callable : no - * - * @return @li IX_TIMESYNCACC_SUCCESS - Operation is successful - * @li IX_TIMESYNCACC_FAILED - Internal error occurred - */ -PUBLIC IxTimeSyncAccStatus -ixTimeSyncAccShow(void); - -#endif /* __ixp46X */ -#endif /* IXTIMESYNCACC_H */ - -/** - * @} defgroup IxTimeSyncAcc - */ - diff --git a/drivers/net/npe/include/IxTimerCtrl.h b/drivers/net/npe/include/IxTimerCtrl.h deleted file mode 100644 index a865b933a32..00000000000 --- a/drivers/net/npe/include/IxTimerCtrl.h +++ /dev/null @@ -1,239 +0,0 @@ -/** - * @file IxTimerCtrl.h - * @brief - * This is the header file for the Timer Control component. - * - * The timer callback control component provides a mechanism by which different - * client components can start a timer and have a supplied callback function - * invoked when the timer expires. - * The callbacks are all dispatched from one thread inside this component. - * Any component that needs to be called periodically should use this facility - * rather than create its own task with a sleep loop. - * - * @par - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxTimerCtrl IXP400 Timer Control (IxTimerCtrl) API - * - * @brief The public API for the IXP400 Timer Control Component. - * - * @{ - */ - -#ifndef IxTimerCtrl_H -#define IxTimerCtrl_H - - -#include "IxTypes.h" -/* #include "Ossl.h" */ - -/* - * #defines and macros used in this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_NO_FREE_TIMERS - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * all available timer resources are used. - */ -#define IX_TIMERCTRL_NO_FREE_TIMERS 2 - - -/** - * @ingroup IxTimerCtrl - * - * @def IX_TIMERCTRL_PARAM_ERROR - * - * @brief Timer schedule return code. - * - * Indicates that the request to start a timer failed because - * the client has supplied invalid parameters. - */ -#define IX_TIMERCTRL_PARAM_ERROR 3 - - -/* - * Typedefs whose scope is limited to this file. - */ - -/** - * @ingroup IxTimerCtrl - * - * @brief A typedef for a pointer to a timer callback function. - * @para void * - This parameter is supplied by the client when the - * timer is started and passed back to the client in the callback. - * @note in general timer callback functions should not block or - * take longer than 100ms. This constraint is required to ensure that - * higher priority callbacks are not held up. - * All callbacks are called from the same thread. - * This thread is a shared resource. - * The parameter passed is provided when the timer is scheduled. - */ -typedef void (*IxTimerCtrlTimerCallback)(void *userParam); - - -/** - * @ingroup IxTimerCtrl - * - * @brief List used to identify the users of timers. - * @note The order in this list indicates priority. Components appearing - * higher in the list will be given priority over components lower in the - * list. When adding components, please insert at an appropriate position - * for priority ( i.e values should be less than IxTimerCtrlMaxPurpose ) . - */ -typedef enum -{ - IxTimerCtrlAdslPurpose, - /* Insert new purposes above this line only - */ - IxTimerCtrlMaxPurpose -} -IxTimerCtrlPurpose; - - -/* - * Function definition - */ - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * This function - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param relativeTime UINT32 [in] - time relative to now in milliseconds after which the callback - * will be called. The time must be greater than the duration of one OS tick. - * @param *timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlSchedule(IxTimerCtrlTimerCallback func, - void *userParam, - IxTimerCtrlPurpose purpose, - UINT32 relativeTime, - unsigned *timerId ); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ) - * - * @brief Schedules a callback function to be called after a period of "time". - * The callback function should not block or run for more than 100ms. - * - * @param func @ref IxTimerCtrlTimerCallback [in] - the callback function to be called. - * @param userParam void [in] - a parameter to send to the callback function, can be NULL. - * @param purpose @ref IxTimerCtrlPurpose [in] - the purpose of the callback, internally this component will - * decide the priority of callbacks with different purpose. - * @param interval UINT32 [in] - the interval in milliseconds between calls to func. - * @param timerId unsigned [out] - An id for the callback scheduled. - * This id can be used to cancel the callback. - * @return - * @li IX_SUCCESS - The timer was started successfully. - * @li IX_TIMERCTRL_NO_FREE_TIMERS - The timer was not started because the maximum number - * of running timers has been exceeded. - * @li IX_TIMERCTRL_PARAM_ERROR - The timer was not started because the client has supplied - * a NULL callback func, or the requested timeout is less than one OS tick. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlScheduleRepeating(IxTimerCtrlTimerCallback func, - void *param, - IxTimerCtrlPurpose purpose, - UINT32 interval, - unsigned *timerId ); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlCancel (unsigned id) - * - * @brief Cancels a scheduled callback. - * - * @param id unsigned [in] - the id of the callback to be cancelled. - * @return - * @li IX_SUCCESS - The timer was successfully stopped. - * @li IX_FAIL - The id parameter did not corrrespond to any running timer.. - * @note This function is re-entrant. The function accesses a list of running timers - * and may suspend the calling thread if this list is being accesed by another thread. - */ -PUBLIC IX_STATUS -ixTimerCtrlCancel (unsigned id); - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlInit(void) - * - * @brief Initialise the Timer Control Component. - * @return - * @li IX_SUCCESS - The timer control component initialized successfully. - * @li IX_FAIL - The timer control component initialization failed, - * or the component was already initialized. - * @note This must be done before any other API function is called. - * This function should be called once only and is not re-entrant. - */ -PUBLIC IX_STATUS -ixTimerCtrlInit(void); - - -/** - * @ingroup IxTimerCtrl - * - * @fn ixTimerCtrlShow( void ) - * - * @brief Display the status of the Timer Control Component. - * @return void - * @note Displays a list of running timers. - * This function is not re-entrant. This function does not suspend the calling thread. - */ -PUBLIC void -ixTimerCtrlShow( void ); - -#endif /* IXTIMERCTRL_H */ - diff --git a/drivers/net/npe/include/IxTypes.h b/drivers/net/npe/include/IxTypes.h deleted file mode 100644 index f936a50bb38..00000000000 --- a/drivers/net/npe/include/IxTypes.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file IxTypes.h (Replaced by OSAL) - * - * @date 28-NOV-2001 - - * @brief This file contains basic types used by the IXP400 software - * - * Design Notes: - * This file shall only include fundamental types and definitions to be - * shared by all the IXP400 components. - * Please DO NOT add component-specific types here. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxTypes IXP400 Types (IxTypes) - * - * @brief Basic data types used by the IXP400 project - * - * @{ - */ - -#ifndef IxTypes_H - -#ifndef __doxygen_HIDE - -#define IxTypes_H - -#endif /* __doxygen_HIDE */ - - -/* WR51880: Undefined data types workaround for backward compatibility */ -#ifdef __linux -#ifndef __INCvxTypesOldh -typedef int (*FUNCPTR)(void); -typedef int STATUS; -#define OK (0) -#define ERROR (-1) -#endif -#endif - -#include "IxOsalBackward.h" - -#endif /* IxTypes_H */ - -/** - * @} addtogroup IxTypes - */ diff --git a/drivers/net/npe/include/IxUART.h b/drivers/net/npe/include/IxUART.h deleted file mode 100644 index ff23b22fe78..00000000000 --- a/drivers/net/npe/include/IxUART.h +++ /dev/null @@ -1,434 +0,0 @@ -/** - * @file IxUART.h - * - * @date 12-OCT-01 - * - * @brief Public header for the Intel IXP400 internal UART, generic driver. - * - * Design Notes: - * This driver allows you to perform the following functions: - * Device Initialization, - * send/receive characters. - * - * Perform Uart IOCTL for the following: - * Set/Get the current baud rate, - * set parity, - * set the number of Stop bits, - * set the character Length (5,6,7,8), - * enable/disable Hardware flow control. - * - * Only Polled mode is supported for now. - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- -*/ - -/** - * @defgroup IxUARTAccAPI IXP400 UART Access (IxUARTAcc) API - * - * @brief IXP400 UARTAcc Driver Public API - * - * @{ - */ - - -/* Defaults */ - -/** - * @defgroup DefaultDefines Defines for Default Values - * - * @brief Default values which can be used for UART configuration - * - * @sa ixUARTDev - */ - -/** - * @def IX_UART_DEF_OPTS - * - * @brief The default hardware options to set the UART to - - * no flow control, 8 bit word, 1 stop bit, no parity - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_OPTS (CLOCAL | CS8) - -/** - * @def IX_UART_DEF_XMIT - * - * @brief The default UART FIFO size - must be no bigger than 64 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_XMIT 64 - -/** - * @def IX_UART_DEF_BAUD - * - * @brief The default UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_DEF_BAUD 9600 - -/** - * @def IX_UART_MIN_BAUD - * - * @brief The minimum UART baud rate - 9600 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MIN_BAUD 9600 - -/** - * @def IX_UART_MAX_BAUD - * - * @brief The maximum UART baud rate - 926100 - * - * @ingroup DefaultDefines - */ -#define IX_UART_MAX_BAUD 926100 - -/** - * @def IX_UART_XTAL - * - * @brief The UART clock speed - * - * @ingroup DefaultDefines - */ -#define IX_UART_XTAL 14745600 - - - -/* IOCTL commands (Request codes) */ - -/** - * @defgroup IoctlCommandDefines Defines for IOCTL Commands - * - * @brief IOCTL Commands (Request codes) which can be used - * with @ref ixUARTIoctl - */ - - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_SET - * - * @brief Set the baud rate - */ -#define IX_BAUD_SET 0 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_BAUD_GET - * - * @brief Get the baud rate - */ -#define IX_BAUD_GET 1 - -/** - * @ingroup IoctlCommandDefines - * @def IX_MODE_SET - * @brief Set the UART mode of operation - */ -#define IX_MODE_SET 2 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_MODE_GET - * - * @brief Get the current UART mode of operation - */ -#define IX_MODE_GET 3 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_SET - * - * @brief Set the UART device options - */ -#define IX_OPTS_SET 4 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_OPTS_GET - * - * @brief Get the UART device options - */ -#define IX_OPTS_GET 5 - -/** - * @ingroup IoctlCommandDefines - * - * @def IX_STATS_GET - * - * @brief Get the UART statistics - */ -#define IX_STATS_GET 6 - - -/* POSIX style ioctl arguments */ - -/** - * @defgroup IoctlArgDefines Defines for IOCTL Arguments - * - * @brief POSIX style IOCTL arguments which can be used - * with @ref ixUARTIoctl - * - * @sa ixUARTMode - */ - - -/** - * @ingroup IoctlArgDefines - * - * @def CLOCAL - * - * @brief Software flow control - */ -#ifdef CLOCAL -#undef CLOCAL -#endif -#define CLOCAL 0x1 - -/** - * @ingroup IoctlArgDefines - * - * @def CREAD - * - * @brief Enable interrupt receiver - */ -#ifdef CREAD -#undef CREAD -#endif -#define CREAD 0x2 - -/** - * @ingroup IoctlArgDefines - * - * @def CSIZE - * - * @brief Characters size - */ -#ifdef CSIZE -#undef CSIZE -#endif -#define CSIZE 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def CS5 - * - * @brief 5 bits - */ -#ifdef CS5 -#undef CS5 -#endif -#define CS5 0x0 - -/** - * @ingroup IoctlArgDefines - * - * @def CS6 - * - * @brief 6 bits - */ -#ifdef CS6 -#undef CS6 -#endif -#define CS6 0x4 - -/** - * @ingroup IoctlArgDefines - * - * @def CS7 - * - * @brief 7 bits - */ -#ifdef CS7 -#undef CS7 -#endif -#define CS7 0x8 - -/** - * @ingroup IoctlArgDefines - * - * @def CS8 - * - * @brief 8 bits - */ -#ifdef CS8 -#undef CS8 -#endif -#define CS8 0xc - -/** - * @ingroup IoctlArgDefines - * - * @def STOPB - * - * @brief Send two stop bits (else one) - */ -#define STOPB 0x20 - -/** - * @ingroup IoctlArgDefines - * - * @def PARENB - * - * @brief Parity detection enabled (else disabled) - */ -#ifdef PARENB -#undef PARENB -#endif -#define PARENB 0x40 - -/** - * @ingroup IoctlArgDefines - * - * @def PARODD - * - * @brief Odd parity (else even) - */ -#ifdef PARODD -#undef PARODD -#endif -#define PARODD 0x80 - -/** - * @enum ixUARTMode - * @brief The mode to set to UART to. - */ -typedef enum -{ - INTERRUPT=0, /**< Interrupt mode */ - POLLED, /**< Polled mode */ - LOOPBACK /**< Loopback mode */ -} ixUARTMode; - -/** - * @struct ixUARTStats - * @brief Statistics for the UART. - */ -typedef struct -{ - UINT32 rxCount; - UINT32 txCount; - UINT32 overrunErr; - UINT32 parityErr; - UINT32 framingErr; - UINT32 breakErr; -} ixUARTStats; - -/** - * @struct ixUARTDev - * @brief Device descriptor for the UART. - */ -typedef struct -{ - UINT8 *addr; /**< device base address */ - ixUARTMode mode; /**< interrupt, polled or loopback */ - int baudRate; /**< baud rate */ - int freq; /**< UART clock frequency */ - int options; /**< hardware options */ - int fifoSize; /**< FIFO xmit size */ - - ixUARTStats stats; /**< device statistics */ -} ixUARTDev; - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTInit(ixUARTDev* pUART) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * - * @brief Initialise the UART. This puts the chip in a quiescent state. - * - * @pre The base address for the UART must contain a valid value. - * Also the baud rate and hardware options must contain sensible values - * otherwise the defaults will be used as defined in ixUART.h - * - * @post UART is initialized and ready to send and receive data. - * - * @note This function should only be called once per device. - * - * @retval IX_SUCCESS - UART device successfully initialised. - * @retval IX_FAIL - Critical error, device not initialised. - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTInit(ixUARTDev* pUART); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar) - * - * @param pUART @ref ixUARTDev [out] - pointer to UART structure describing our device. - * @param outChar int [out] - character to transmit. - * - * @brief Transmit a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully transmitted. - * @retval IX_FAIL - output buffer is full (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollOutput(ixUARTDev* pUART, int outChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param *inChar char [in] - character read from the device. - * - * @brief Receive a character in polled mode. - * - * @pre UART device must be initialised. - * - * @retval IX_SUCCESS - character was successfully read. - * @retval IX_FAIL - input buffer empty (try again). - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTPollInput(ixUARTDev* pUART, char *inChar); - -/** - * @ingroup IxUARTAccAPI - * - * @fn IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg) - * - * @param pUART @ref ixUARTDev [in] - pointer to UART structure describing our device. - * @param cmd int [in] - an ioctl request code. - * @param arg void* [in] - optional argument used to set the device mode, - * baud rate, and hardware options. - * - * @brief Perform I/O control routines on the device. - * - * @retval IX_SUCCESS - requested feature was set/read successfully. - * @retval IX_FAIL - error setting/reading the requested feature. - * - * @sa IoctlCommandDefines - * @sa IoctlArgDefines - ***************************************************************************/ -PUBLIC IX_STATUS ixUARTIoctl(ixUARTDev* pUART, int cmd, void* arg); - -/** - * @} defgroup IxUARTAcc - */ diff --git a/drivers/net/npe/include/IxVersionId.h b/drivers/net/npe/include/IxVersionId.h deleted file mode 100644 index 1769dcda45b..00000000000 --- a/drivers/net/npe/include/IxVersionId.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file IxVersionId.h - * - * @date 22-Aug-2002 - * - * @brief This file contains the IXP400 Software version identifier - * - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - */ - -/** - * @defgroup IxVersionId IXP400 Version ID (IxVersionId) - * - * @brief Version Identifiers - * - * @{ - */ - -#ifndef IXVERSIONID_H -#define IXVERSIONID_H - -/** - * @brief Version Identifier String - * - * This string will be updated with each customer release of the IXP400 - * Software. - */ -#define IX_VERSION_ID "2_0" - -/** - * This string will be updated with each customer release of the IXP400 - * ADSL driver package. - */ -#define IX_VERSION_ADSL_ID "1_12" - - -/** - * This string will be updated with each customer release of the IXP400 - * USB Client driver package. - */ -#define IX_VERSION_USBRNDIS_ID "1_9" - -/** - * This string will be updated with each customer release of the IXP400 - * I2C Linux driver package. - */ -#define IX_VERSION_I2C_LINUX_ID "1_0" - -/** - * @brief Linux Ethernet Driver Patch Version Identifier String - * - * This string will be updated with each release of Linux Ethernet Patch - */ -#define LINUX_ETHERNET_DRIVER_PATCH_ID "1_4" - -/** - * @brief Linux Integration Patch Version Identifier String - * - * This String will be updated with each release of Linux Integration Patch - */ -#define LINUX_INTEGRATION_PATCH_ID "1_3" - -/** - * @brief Linux Ethernet Readme version Identifier String - * - * This string will be updated with each release of Linux Ethernet Readme - */ -#define LINUX_ETHERNET_README_ID "1_3" - -/** - * @brief Linux Integration Readme version Identifier String - * - * This string will be updated with each release of Linux Integration Readme - */ - -#define LINUX_INTEGRATION_README_ID "1_3" - -/** - * @brief Linux I2C driver Readme version Identifier String - * - * This string will be updated with each release of Linux I2C Driver Readme - */ -#define LINUX_I2C_DRIVER_README_ID "1_0" - -/** - * @brief ixp425_eth_update_nf_bridge.patch version Identifier String - * - * This string will be updated with each release of ixp425_eth_update_nf_bridge. -patch - * - */ - -#define IXP425_ETH_UPDATE_NF_BRIDGE_ID "1_3" - -/** - * @brief Internal Release Identifier String - * - * This string will be updated with each internal release (SQA drop) - * of the IXP400 Software. - */ -#define IX_VERSION_INTERNAL_ID "SQA3_5" - -/** - * @brief Compatible Tornado Version Identifier - */ -#define IX_VERSION_COMPATIBLE_TORNADO "Tornado2_2_1-PNE2_0" - -/** - * @brief Compatible Linux Version Identifier - */ -#define IX_VERSION_COMPATIBLE_LINUX "MVL3_1" - - -#endif /* IXVERSIONID_H */ - -/** - * @} addtogroup IxVersionId - */ diff --git a/drivers/net/npe/include/ix_error.h b/drivers/net/npe/include/ix_error.h deleted file mode 100644 index 4c599996cf9..00000000000 --- a/drivers/net/npe/include/ix_error.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_error.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file will describe the basic error type and support functions that - * will be used by the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:19:03 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_ERROR_H__) -#define __IX_ERROR_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_ERROR_H__) */ - diff --git a/drivers/net/npe/include/ix_macros.h b/drivers/net/npe/include/ix_macros.h deleted file mode 100644 index b4cf7602ae6..00000000000 --- a/drivers/net/npe/include/ix_macros.h +++ /dev/null @@ -1,242 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_macros.h - * - * = DESCRIPTION - * This file will define the basic preprocessor macros that are going to be used - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:41:05 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_MACROS_H__) -#define __IX_MACROS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK16 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 16 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 16 bit mask that will extract the bit field from a 16 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK16( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask16)((((ix_uint16)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint16)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD16 - * - * DESCRIPTION: Extracts a bit field from 16 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_PackedData16) & IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD16 - * - * DESCRIPTION: This macro will create a temporary 16 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint16 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD16( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint16)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit)) - -/** - * MACRO NAME: IX_SET_BIT_FIELD16 - * - * DESCRIPTION: Sets a new value for a bit field from a 16 bit unsigned integer. - * - * @Param: - IN arg_PackedData16 a 16 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new vale of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData16. - */ -#define IX_SET_BIT_FIELD16( \ - arg_PackedData16, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData16 = (((ix_uint16)(arg_PackedData16) & \ - ~(IX_BIT_FIELD_MASK16(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD16(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - -/** - * MACRO NAME: IX_BIT_FIELD_MASK32 - * - * DESCRIPTION: Builds the mask required to extract the bit field from a 32 bit unsigned integer value. - * - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a 32 bit mask that will extract the bit field from a 32 bit unsigned integer value. - */ -#define IX_BIT_FIELD_MASK32( \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - ((ix_bit_mask32)((((ix_uint32)1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - \ - (ix_uint32)1) << arg_FieldLSBBit)) - - - -/** - * MACRO NAME: IX_GET_BIT_FIELD32 - * - * DESCRIPTION: Extracts a bit field from 32 bit unsigned integer. The returned value is normalized in - * in the sense that will be right aligned. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the value of the bit field. The value can be from 0 to (1 << (arg_FieldMSBBit + 1 - - * arg_FieldLSBBit)) - 1. - */ -#define IX_GET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_PackedData32) & IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) >> \ - arg_FieldLSBBit) - - - - -/** - * MACRO NAME: IX_MAKE_BIT_FIELD32 - * - * DESCRIPTION: This macro will create a temporary 32 bit value with the bit field - * desired set to the desired value. - * - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns a temporary ix_uint32 value that has the bit field set to the appropriate value. - */ -#define IX_MAKE_BIT_FIELD32( \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (((ix_uint32)(arg_BitFieldValue) << arg_FieldLSBBit) & \ - IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit)) - - -/** - * MACRO NAME: IX_SET_BIT_FIELD32 - * - * DESCRIPTION: Sets a new value for a bit field from a 32 bit unsigned integer. - * - * @Param: - IN arg_PackedData32 a 32 bit unsigned integer that contains the bit field of interest. - * @Param: - IN arg_BitFieldValue is the new value of the bit field. The value can be from 0 to - * (1 << (arg_FieldMSBBit + 1 - arg_FieldLSBBit)) - 1. - * @Param: - IN arg_FieldLSBBit an unsigned integer value representing the position of the least significant - * bit of the bit field. - * @Param: - IN arg_FieldMSBBit an unsigned integer value representing the position of the most significant - * bit of the bit field. - * - * @Return: Returns the updated value of arg_PackedData32. - */ -#define IX_SET_BIT_FIELD32( \ - arg_PackedData32, \ - arg_BitFieldValue, \ - arg_FieldLSBBit, \ - arg_FieldMSBBit \ - ) \ - (arg_PackedData32 = (((ix_uint32)(arg_PackedData32) & \ - ~(IX_BIT_FIELD_MASK32(arg_FieldLSBBit, arg_FieldMSBBit))) | \ - IX_MAKE_BIT_FIELD32(arg_BitFieldValue, arg_FieldLSBBit, arg_FieldMSBBit))) - - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_MACROS_H__) */ diff --git a/drivers/net/npe/include/ix_os_type.h b/drivers/net/npe/include/ix_os_type.h deleted file mode 100644 index e14d561c281..00000000000 --- a/drivers/net/npe/include/ix_os_type.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_os_type.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file provides protable symbol definitions for the current OS type. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:43:30 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_OS_TYPE_H__) -#define __IX_OS_TYPE_H__ - -#include "IxOsalBackward.h" - -#endif /* end !defined(__IX_OS_TYPE_H__) */ - diff --git a/drivers/net/npe/include/ix_ossl.h b/drivers/net/npe/include/ix_ossl.h deleted file mode 100644 index eaa2629b8d0..00000000000 --- a/drivers/net/npe/include/ix_ossl.h +++ /dev/null @@ -1,136 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OSSL Abstraction layer header file - * - * = FILENAME - * ix_ossl.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains the prototypes of OS-independent wrapper - * functions which allow the programmer not to be tied to a specific - * operating system. The OSSL functions can be divided into three classes: - * - * 1) synchronization-related wrapper functions around thread system calls - * 2) thread-related wrapper functions around thread calls - * 3) transactor/workbench osapi calls -- defined in osApi.h - * - * Both 1 and 2 classes of functions provide Thread Management, Thread - * Synchronization, Mutual Exclusion and Timer primitives. Namely, - * creation and deletion functions as well as the standard "wait" and - * "exit". Additionally, a couple of utility functions which enable to - * pause the execution of a thread are also provided. - * - * The 3rd class provides a slew of other OSAPI functions to handle - * Transactor/WorkBench OS calls. - * - * - * OSSL Thread APIs: - * The OSSL thread functions that allow for thread creation, - * get thread id, thread deletion and set thread priroity. - * - * ix_ossl_thread_create - * ix_ossl_thread_get_id - * ix_ossl_thread_exit - * ix_ossl_thread_kill - * ix_ossl_thread_set_priority - * ix_ossl_thread__delay - * - * OSSL Semaphore APIs: - * The OSSL semaphore functions that allow for initialization, - * posting, waiting and deletion of semaphores. - * - * ix_ossl_sem_init - * ix_ossl_sem_fini - * ix_ossl_sem_take - * ix_ossl_sem_give - * ix_ossl_sem_flush - * - * OSSL Mutex APIs: - * The OSSL wrapper functions that allow for initialization, - * posting, waiting and deletion of mutexes. - * - * ix_ossl_mutex_init - * ix_ossl_mutex_fini - * ix_ossl_mutex_lock - * ix_ossl_mutex_unlock - * - * OSSL Timer APIs: - * The timer APIs provide sleep and get time functions. - * - * ix_ossl_sleep - * ix_ossl_sleep_tick - * ix_ossl_time_get - * - * OSAPIs for Transactor/WorkBench: - * These OSAPI functions are used for transator OS calls. - * They are defined in osApi.h. - * - * Sem_Init - * Sem_Destroy - * Sem_Wait - * Sem_Wait - * Thread_Create - * Thread_Cancel - * Thread_SetPriority - * delayMs - * delayTick - * - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = ACKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - * 02/22/2002 : Renamed osapi.h os_api.h - * Moved OS header file includes from OSSL.h to os_api.h - * Moved OS specific datatypes to os_api.h - * Modified data types, macros and functions as per - * 'C' coding guidelines. - * - * - * ============================================================================ - */ - -#ifndef _IX_OSSL_H -#ifndef __doxygen_hide -#define _IX_OSSL_H -#endif /* __doxygen_hide */ - -#include "IxOsalBackward.h" - -#endif /* _IX_OSSL_H */ - -/** - * @} defgroup IxOSSL - */ diff --git a/drivers/net/npe/include/ix_symbols.h b/drivers/net/npe/include/ix_symbols.h deleted file mode 100644 index 0006b227c64..00000000000 --- a/drivers/net/npe/include/ix_symbols.h +++ /dev/null @@ -1,82 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_symbols.h - * - * = DESCRIPTION - * This file declares all the global preprocessor symbols required by - * the IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/23/2002 10:41:13 AM - creation time - * ============================================================================ - */ - -#if !defined(__IX_SYMBOLS_H__) -#define __IX_SYMBOLS_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - -/** - * The IX_EXPORT_FUNCTION symbol will be used for compilation on different platforms. - * We are planning to provide a simulation version of the library that should work - * with the Transactor rather than the hardware. This implementation will be done on - * WIN32 in the form of a DLL that will need to export functions and symbols. - */ -#if (_IX_OS_TYPE_ == _IX_OS_WIN32_) -# if defined(_IX_LIB_INTERFACE_IMPLEMENTATION_) -# define IX_EXPORT_FUNCTION __declspec( dllexport ) -# elif defined(_IX_LIB_INTERFACE_IMPORT_DLL_) -# define IX_EXPORT_FUNCTION __declspec( dllimport ) -# else -# define IX_EXPORT_FUNCTION extern -# endif -#elif (_IX_OS_TYPE_ == _IX_OS_WINCE_) -# define IX_EXPORT_FUNCTION __declspec(dllexport) -#else -# define IX_EXPORT_FUNCTION extern -#endif - - -/** - * This symbols should be defined when we want to build for a multithreaded environment - */ -#define _IX_MULTI_THREADED_ 1 - - -/** - * This symbol should be defined in the case we to buils for a multithreaded environment - * but we want that our modules to work as if they are used in a single threaded environment. - */ -/* #define _IX_RM_EXPLICIT_SINGLE_THREADED_ 1 */ - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_SYMBOLS_H__) */ diff --git a/drivers/net/npe/include/ix_types.h b/drivers/net/npe/include/ix_types.h deleted file mode 100644 index 6945506049e..00000000000 --- a/drivers/net/npe/include/ix_types.h +++ /dev/null @@ -1,184 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = FILENAME - * ix_types.h - * - * = DESCRIPTION - * This file will define generic types that will guarantee the protability - * between different architectures and compilers. It should be used the entire - * IXA SDK Framework API. - * - * = AUTHOR - * Intel Corporation - * - * = CHANGE HISTORY - * 4/22/2002 4:44:17 PM - creation time - * ============================================================================ - */ - -#if !defined(__IX_TYPES_H__) -#define __IX_TYPES_H__ - - -#if defined(__cplusplus) -extern "C" -{ -#endif /* end defined(__cplusplus) */ - - -/** - * Define generic integral data types that will guarantee the size. - */ - -/** - * TYPENAME: ix_int8 - * - * DESCRIPTION: This type defines an 8 bit signed integer value. - * - */ -typedef signed char ix_int8; - - -/** - * TYPENAME: ix_uint8 - * - * DESCRIPTION: This type defines an 8 bit unsigned integer value. - * - */ -typedef unsigned char ix_uint8; - - -/** - * TYPENAME: ix_int16 - * - * DESCRIPTION: This type defines an 16 bit signed integer value. - * - */ -typedef signed short int ix_int16; - - -/** - * TYPENAME: ix_uint16 - * - * DESCRIPTION: This type defines an 16 bit unsigned integer value. - * - */ -typedef unsigned short int ix_uint16; - - -/** - * TYPENAME: ix_int32 - * - * DESCRIPTION: This type defines an 32 bit signed integer value. - * - */ -typedef signed int ix_int32; - - -/** - * TYPENAME: ix_uint32 - * - * DESCRIPTION: This type defines an 32 bit unsigned integer value. - * - */ -#ifndef __wince -typedef unsigned int ix_uint32; -#else -typedef unsigned long ix_uint32; -#endif - -/** - * TYPENAME: ix_int64 - * - * DESCRIPTION: This type defines an 64 bit signed integer value. - * - */ -#ifndef __wince -__extension__ typedef signed long long int ix_int64; -#endif - -/** - * TYPENAME: ix_uint64 - * - * DESCRIPTION: This type defines an 64 bit unsigned integer value. - * - */ -#ifndef __wince -__extension__ typedef unsigned long long int ix_uint64; -#endif - - -/** - * TYPENAME: ix_bit_mask8 - * - * DESCRIPTION: This is a generic type for a 8 bit mask. - */ -typedef ix_uint8 ix_bit_mask8; - - -/** - * TYPENAME: ix_bit_mask16 - * - * DESCRIPTION: This is a generic type for a 16 bit mask. - */ -typedef ix_uint16 ix_bit_mask16; - - -/** - * TYPENAME: ix_bit_mask32 - * - * DESCRIPTION: This is a generic type for a 32 bit mask. - */ -typedef ix_uint32 ix_bit_mask32; - - -/** - * TYPENAME: ix_bit_mask64 - * - * DESCRIPTION: This is a generic type for a 64 bit mask. - */ -#ifndef __wince -typedef ix_uint64 ix_bit_mask64; -#endif - - -/** - * TYPENAME: ix_handle - * - * DESCRIPTION: This type defines a generic handle. - * - */ -typedef ix_uint32 ix_handle; - - - -/** - * DESCRIPTION: This symbol defines a NULL handle - * - */ -#define IX_NULL_HANDLE ((ix_handle)0) - - -#if defined(__cplusplus) -} -#endif /* end defined(__cplusplus) */ - -#endif /* end !defined(__IX_TYPES_H__) */ diff --git a/drivers/net/npe/include/npe.h b/drivers/net/npe/include/npe.h deleted file mode 100644 index 1c6ae26ddce..00000000000 --- a/drivers/net/npe/include/npe.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2005 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef NPE_H -#define NPE_H - -/* - * defines... - */ -#define CONFIG_SYS_NPE_NUMS 1 -#ifdef CONFIG_HAS_ETH1 -#undef CONFIG_SYS_NPE_NUMS -#define CONFIG_SYS_NPE_NUMS 2 -#endif - -#define NPE_NUM_PORTS 3 -#define ACTIVE_PORTS 1 - -#define NPE_PKT_SIZE 1600 - -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS 64 -#define CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS 2 - -#define NPE_MBUF_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - sizeof(IX_OSAL_MBUF) * ACTIVE_PORTS) - -#define NPE_PKT_POOL_SIZE \ - ((CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS + \ - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS) * \ - NPE_PKT_SIZE * ACTIVE_PORTS) - -#define NPE_MEM_POOL_SIZE (NPE_MBUF_POOL_SIZE + NPE_PKT_POOL_SIZE) - -#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */ - -/* - * structs... - */ -struct npe { - u8 active; /* NPE active */ - u8 eth_id; /* IX_ETH_PORT_1 or IX_ETH_PORT_2 */ - u8 phy_no; /* which PHY (0 - 31) */ - u8 mac_address[6]; - - IX_OSAL_MBUF *rxQHead; - IX_OSAL_MBUF *txQHead; - - u8 *tx_pkts; - u8 *rx_pkts; - IX_OSAL_MBUF *rx_mbufs; - IX_OSAL_MBUF *tx_mbufs; - - int print_speed; - - int rx_read; - int rx_write; - int rx_len[PKTBUFSRX]; -}; - -/* - * prototypes... - */ -extern int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); - -#endif /* ifndef NPE_H */ diff --git a/drivers/net/npe/include/os_datatypes.h b/drivers/net/npe/include/os_datatypes.h deleted file mode 100644 index def891b8620..00000000000 --- a/drivers/net/npe/include/os_datatypes.h +++ /dev/null @@ -1,58 +0,0 @@ -/** - * ============================================================================ - * = COPYRIGHT - * - * @par - * IXP400 SW Release version 2.0 - * - * -- Copyright Notice -- - * - * @par - * Copyright 2001-2005, Intel Corporation. - * All rights reserved. - * - * @par - * SPDX-License-Identifier: BSD-3-Clause - * @par - * -- End of Copyright Notice -- - * = PRODUCT - * Intel(r) IXP425 Software Release - * - * = LIBRARY - * OSSL - Operating System Services Library - * - * = MODULE - * OS Specific Data Types header file - * - * = FILENAME - * OSSL.h (Replaced by OSAL) - * - * = DESCRIPTION - * This file contains definitions and encapsulations for OS specific data types. These - * encapsulated data types are used by OSSL header files and OS API functions. - * - * - ********************************************************************** - * - * - * = AUTHOR - * Intel Corporation - * - * = AKNOWLEDGEMENTS - * - * - * = CREATION TIME - * 1/8/2002 1:53:42 PM - * - * = CHANGE HISTORY - - * ============================================================================ - */ - -#ifndef _OS_DATATYPES_H -#define _OS_DATATYPES_H - -#include "IxOsalBackward.h" - -#endif /* _OS_DATATYPES_H */ - diff --git a/drivers/net/npe/miiphy.c b/drivers/net/npe/miiphy.c deleted file mode 100644 index 002fb8113b2..00000000000 --- a/drivers/net/npe/miiphy.c +++ /dev/null @@ -1,101 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0 IBM-pibs - */ -/*-----------------------------------------------------------------------------+ - | - | File Name: miiphy.c - | - | Function: This module has utilities for accessing the MII PHY through - | the EMAC3 macro. - | - | Author: Mark Wisner - | - | Change Activity- - | - | Date Description of Change BY - | --------- --------------------- --- - | 05-May-99 Created MKW - | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to - | better match OPB speed. Also modified delay times. JWB - | 29-Jul-99 Added Full duplex support MKW - | 24-Aug-99 Removed printf from dp83843_duplex() JWB - | 19-Jul-00 Ported to esd cpci405 sr - | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS - | - | - +-----------------------------------------------------------------------------*/ - -#include -#include -#include "IxOsal.h" -#include "IxEthAcc.h" -#include "IxEthAcc_p.h" -#include "IxEthAccMac_p.h" -#include "IxEthAccMii_p.h" - -/***********************************************************/ -/* Dump out to the screen PHY regs */ -/***********************************************************/ - -void miiphy_dump (char *devname, unsigned char addr) -{ - unsigned long i; - unsigned short data; - - - for (i = 0; i < 0x1A; i++) { - if (miiphy_read (devname, addr, i, &data)) { - printf ("read error for reg %lx\n", i); - return; - } - printf ("Phy reg %lx ==> %4x\n", i, data); - - /* jump to the next set of regs */ - if (i == 0x07) - i = 0x0f; - - } /* end for loop */ -} /* end dump */ - - -/***********************************************************/ -/* (Re)start autonegotiation */ -/***********************************************************/ -int phy_setup_aneg (char *devname, unsigned char addr) -{ - unsigned short ctl, adv; - - /* Setup standard advertise */ - miiphy_read (devname, addr, MII_ADVERTISE, &adv); - adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | - LPA_100FULL | LPA_100HALF | LPA_10FULL | - LPA_10HALF); - miiphy_write (devname, addr, MII_ADVERTISE, adv); - - /* Start/Restart aneg */ - miiphy_read (devname, addr, MII_BMCR, &ctl); - ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); - miiphy_write (devname, addr, MII_BMCR, ctl); - - return 0; -} - - -int npe_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) -{ - u16 val; - - ixEthAccMiiReadRtn(addr, reg, &val); - *value = val; - - return 0; -} /* phy_read */ - - -int npe_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - ixEthAccMiiWriteRtn(addr, reg, value); - return 0; -} /* phy_write */ diff --git a/drivers/net/npe/npe.c b/drivers/net/npe/npe.c deleted file mode 100644 index 00b381ec4a4..00000000000 --- a/drivers/net/npe/npe.c +++ /dev/null @@ -1,680 +0,0 @@ -/* - * (C) Copyright 2005-2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#if 0 -#define DEBUG /* define for debug output */ -#endif - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -static IxQMgrDispatcherFuncPtr qDispatcherFunc = NULL; -static int npe_exists[NPE_NUM_PORTS]; -static int npe_used[NPE_NUM_PORTS]; - -/* A little extra so we can align to cacheline. */ -static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1]; -static u8 *npe_alloc_end; -static u8 *npe_alloc_free; - -static void *npe_alloc(int size) -{ - static int count = 0; - void *p = NULL; - - size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1); - count++; - - if ((npe_alloc_free + size) < npe_alloc_end) { - p = npe_alloc_free; - npe_alloc_free += size; - } else { - printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size); - } - return p; -} - -/* Not interrupt safe! */ -static void mbuf_enqueue(IX_OSAL_MBUF **q, IX_OSAL_MBUF *new) -{ - IX_OSAL_MBUF *m = *q; - - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(new) = NULL; - - if (m) { - while(IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m)) - m = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = new; - } else - *q = new; -} - -/* Not interrupt safe! */ -static IX_OSAL_MBUF *mbuf_dequeue(IX_OSAL_MBUF **q) -{ - IX_OSAL_MBUF *m = *q; - if (m) - *q = IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m); - return m; -} - -static void reset_tx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->txQHead = NULL; - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS; i++) { - m = &p_npe->tx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->tx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - mbuf_enqueue(&p_npe->txQHead, m); - } -} - -static void reset_rx_mbufs(struct npe* p_npe) -{ - IX_OSAL_MBUF *m; - int i; - - p_npe->rxQHead = NULL; - - HAL_DCACHE_INVALIDATE(p_npe->rx_pkts, NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - - for (i = 0; i < CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS; i++) { - m = &p_npe->rx_mbufs[i]; - - memset(m, 0, sizeof(*m)); - - IX_OSAL_MBUF_MDATA(m) = (void *)&p_npe->rx_pkts[i * NPE_PKT_SIZE]; - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - printf("ixEthAccPortRxFreeReplenish failed for port %d\n", p_npe->eth_id); - break; - } - } -} - -static void init_rx_mbufs(struct npe* p_npe) -{ - p_npe->rxQHead = NULL; - - p_npe->rx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->rx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_RX_DESCRIPTORS); - if (p_npe->rx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_rx_mbufs(p_npe); -} - -static void init_tx_mbufs(struct npe* p_npe) -{ - p_npe->tx_pkts = npe_alloc(NPE_PKT_SIZE * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_pkts == NULL) { - printf("alloc of packets failed.\n"); - return; - } - - p_npe->tx_mbufs = (IX_OSAL_MBUF *) - npe_alloc(sizeof(IX_OSAL_MBUF) * - CONFIG_DEVS_ETH_INTEL_NPE_MAX_TX_DESCRIPTORS); - if (p_npe->tx_mbufs == NULL) { - printf("alloc of mbufs failed.\n"); - return; - } - - reset_tx_mbufs(p_npe); -} - -/* Convert IX_ETH_PORT_n to IX_NPEMH_NPEID_NPEx */ -static int __eth_to_npe(int eth_id) -{ - switch(eth_id) { - case IX_ETH_PORT_1: - return IX_NPEMH_NPEID_NPEB; - - case IX_ETH_PORT_2: - return IX_NPEMH_NPEID_NPEC; - - case IX_ETH_PORT_3: - return IX_NPEMH_NPEID_NPEA; - } - return 0; -} - -/* Poll the CSR machinery. */ -static void npe_poll(int eth_id) -{ - if (qDispatcherFunc != NULL) { - ixNpeMhMessagesReceive(__eth_to_npe(eth_id)); - (*qDispatcherFunc)(IX_QMGR_QUELOW_GROUP); - } -} - -/* ethAcc RX callback */ -static void npe_rx_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - struct npe* p_npe = (struct npe *)cbTag; - - if (IX_OSAL_MBUF_MLEN(m) > 0) { - mbuf_enqueue(&p_npe->rxQHead, m); - - if (p_npe->rx_write == ((p_npe->rx_read-1) & (PKTBUFSRX-1))) { - debug("Rx overflow: rx_write=%d rx_read=%d\n", - p_npe->rx_write, p_npe->rx_read); - } else { - debug("Received message #%d (len=%d)\n", p_npe->rx_write, - IX_OSAL_MBUF_MLEN(m)); - memcpy((void *)NetRxPackets[p_npe->rx_write], IX_OSAL_MBUF_MDATA(m), - IX_OSAL_MBUF_MLEN(m)); - p_npe->rx_len[p_npe->rx_write] = IX_OSAL_MBUF_MLEN(m); - p_npe->rx_write++; - if (p_npe->rx_write == PKTBUFSRX) - p_npe->rx_write = 0; - -#ifdef CONFIG_PRINT_RX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; i<60; i++) { - debug("%02x ", *ptr++); - } - debug("\n"); - } -#endif - } - - m = mbuf_dequeue(&p_npe->rxQHead); - } else { - debug("Received frame with length 0!!!\n"); - m = mbuf_dequeue(&p_npe->rxQHead); - } - - /* Now return mbuf to NPE */ - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - if(ixEthAccPortRxFreeReplenish(p_npe->eth_id, m) != IX_SUCCESS) { - debug("npe_rx_callback: Error returning mbuf.\n"); - } -} - -/* ethAcc TX callback */ -static void npe_tx_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - struct npe* p_npe = (struct npe *)cbTag; - - debug("%s\n", __FUNCTION__); - - IX_OSAL_MBUF_MLEN(m) = IX_OSAL_MBUF_PKT_LEN(m) = NPE_PKT_SIZE; - IX_OSAL_MBUF_NEXT_BUFFER_IN_PKT_PTR(m) = NULL; - IX_OSAL_MBUF_FLAGS(m) = 0; - - mbuf_enqueue(&p_npe->txQHead, m); -} - - -static int npe_set_mac_address(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - IxEthAccMacAddr npeMac; - - debug("%s\n", __FUNCTION__); - - /* Set MAC address */ - memcpy(npeMac.macAddress, dev->enetaddr, 6); - - if (ixEthAccPortUnicastMacAddressSet(p_npe->eth_id, &npeMac) != IX_ETH_ACC_SUCCESS) { - printf("Error setting unicast address! %02x:%02x:%02x:%02x:%02x:%02x\n", - npeMac.macAddress[0], npeMac.macAddress[1], - npeMac.macAddress[2], npeMac.macAddress[3], - npeMac.macAddress[4], npeMac.macAddress[5]); - return 0; - } - - return 1; -} - -/* Boot-time CSR library initialization. */ -static int npe_csr_load(void) -{ - int i; - - if (ixQMgrInit() != IX_SUCCESS) { - debug("Error initialising queue manager!\n"); - return 0; - } - - ixQMgrDispatcherLoopGet(&qDispatcherFunc); - - if(ixNpeMhInitialize(IX_NPEMH_NPEINTERRUPTS_YES) != IX_SUCCESS) { - printf("Error initialising NPE Message handler!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_1] && npe_exists[IX_ETH_PORT_1] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEB_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-B!\n"); - return 0; - } - - if (npe_used[IX_ETH_PORT_2] && npe_exists[IX_ETH_PORT_2] && - ixNpeDlNpeInitAndStart(IX_NPEDL_NPEIMAGE_NPEC_ETH_LEARN_FILTER_SPAN_FIREWALL_VLAN_QOS) - != IX_SUCCESS) { - printf("Error downloading firmware to NPE-C!\n"); - return 0; - } - - /* don't need this for U-Boot */ - ixFeatureCtrlSwConfigurationWrite(IX_FEATURECTRL_ETH_LEARNING, false); - - if (ixEthAccInit() != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet access driver!\n"); - return 0; - } - - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (!npe_used[i] || !npe_exists[i]) - continue; - if (ixEthAccPortInit(i) != IX_ETH_ACC_SUCCESS) { - printf("Error initialising Ethernet port%d!\n", i); - } - if (ixEthAccTxSchedulingDisciplineSet(i, FIFO_NO_PRIORITY) != IX_ETH_ACC_SUCCESS) { - printf("Error setting scheduling discipline for port %d.\n", i); - } - if (ixEthAccPortRxFrameAppendFCSDisable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error disabling RX FCS for port %d.\n", i); - } - if (ixEthAccPortTxFrameAppendFCSEnable(i) != IX_ETH_ACC_SUCCESS) { - printf("Error enabling TX FCS for port %d.\n", i); - } - } - - return 1; -} - -static int npe_init(struct eth_device *dev, bd_t * bis) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - u16 reg_short; - int speed; - int duplex; - - debug("%s: 1\n", __FUNCTION__); - -#ifdef CONFIG_MII_NPE0_FIXEDLINK - if (0 == p_npe->eth_id) { - speed = CONFIG_MII_NPE0_SPEED; - duplex = CONFIG_MII_NPE0_FULLDUPLEX ? FULL : HALF; - } else -#endif -#ifdef CONFIG_MII_NPE1_FIXEDLINK - if (1 == p_npe->eth_id) { - speed = CONFIG_MII_NPE1_SPEED; - duplex = CONFIG_MII_NPE1_FULLDUPLEX ? FULL : HALF; - } else -#endif - { - miiphy_read(dev->name, p_npe->phy_no, MII_BMSR, ®_short); - - /* - * Wait if PHY is capable of autonegotiation and - * autonegotiation is not complete - */ - if ((reg_short & BMSR_ANEGCAPABLE) && - !(reg_short & BMSR_ANEGCOMPLETE)) { - puts("Waiting for PHY auto negotiation to complete"); - i = 0; - while (!(reg_short & BMSR_ANEGCOMPLETE)) { - /* - * Timeout reached ? - */ - if (i > PHY_AUTONEGOTIATE_TIMEOUT) { - puts(" TIMEOUT !\n"); - break; - } - - if ((i++ % 1000) == 0) { - putc('.'); - miiphy_read(dev->name, p_npe->phy_no, - MII_BMSR, ®_short); - } - udelay(1000); /* 1 ms */ - } - puts(" done\n"); - /* another 500 ms (results in faster booting) */ - udelay(500000); - } - speed = miiphy_speed(dev->name, p_npe->phy_no); - duplex = miiphy_duplex(dev->name, p_npe->phy_no); - } - - if (p_npe->print_speed) { - p_npe->print_speed = 0; - printf ("ENET Speed is %d Mbps - %s duplex connection\n", - (int) speed, (duplex == HALF) ? "HALF" : "FULL"); - } - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - /* initialize mbuf pool */ - init_rx_mbufs(p_npe); - init_tx_mbufs(p_npe); - - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register RX callback!\n"); - return -1; - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - printf("can't register TX callback!\n"); - return -1; - } - - npe_set_mac_address(dev); - - if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - printf("can't enable port!\n"); - return -1; - } - - p_npe->active = 1; - - return 0; -} - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ -/* Uninitialize CSR library. */ -static void npe_csr_unload(void) -{ - ixEthAccUnload(); - ixEthDBUnload(); - ixNpeMhUnload(); - ixQMgrUnload(); -} - -/* callback which is used by ethAcc to recover RX buffers when stopping */ -static void npe_rx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m, IxEthAccPortId portid) -{ - debug("%s\n", __FUNCTION__); -} - -/* callback which is used by ethAcc to recover TX buffers when stopping */ -static void npe_tx_stop_callback(u32 cbTag, IX_OSAL_MBUF *m) -{ - debug("%s\n", __FUNCTION__); -} -#endif - -static void npe_halt(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - int i; - - debug("%s\n", __FUNCTION__); - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(100); - } - -#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */ - if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering rx callback!\n"); - } - - if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_stop_callback, - (u32)p_npe) != IX_ETH_ACC_SUCCESS) { - debug("Error registering tx callback!\n"); - } - - if (ixEthAccPortDisable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) { - debug("npe_stop: Error disabling NPEB!\n"); - } - - /* Delay to give time for recovery of mbufs */ - for (i = 0; i < 100; i++) { - npe_poll(p_npe->eth_id); - udelay(10000); - } - - /* - * For U-Boot only, we are probably launching Linux or other OS that - * needs a clean slate for its NPE library. - */ -#if 0 /* test-only */ - for (i = 0; i < IX_ETH_ACC_NUMBER_OF_PORTS; i++) { - if (npe_used[i] && npe_exists[i]) - if (ixNpeDlNpeStopAndReset(__eth_to_npe(i)) != IX_SUCCESS) - printf("Failed to stop and reset NPE B.\n"); - } -#endif - -#endif - p_npe->active = 0; -} - - -static int npe_send(struct eth_device *dev, void *packet, int len) -{ - struct npe *p_npe = (struct npe *)dev->priv; - u8 *dest; - int err; - IX_OSAL_MBUF *m; - - debug("%s\n", __FUNCTION__); - m = mbuf_dequeue(&p_npe->txQHead); - dest = IX_OSAL_MBUF_MDATA(m); - IX_OSAL_MBUF_PKT_LEN(m) = IX_OSAL_MBUF_MLEN(m) = len; - IX_OSAL_MBUF_NEXT_PKT_IN_CHAIN_PTR(m) = NULL; - - memcpy(dest, (char *)packet, len); - - if ((err = ixEthAccPortTxFrameSubmit(p_npe->eth_id, m, IX_ETH_ACC_TX_DEFAULT_PRIORITY)) - != IX_ETH_ACC_SUCCESS) { - printf("npe_send: Can't submit frame. err[%d]\n", err); - mbuf_enqueue(&p_npe->txQHead, m); - return 0; - } - -#ifdef DEBUG_PRINT_TX_FRAMES - { - u8 *ptr = IX_OSAL_MBUF_MDATA(m); - int i; - - for (i=0; ieth_id); - - return len; -} - -static int npe_rx(struct eth_device *dev) -{ - struct npe *p_npe = (struct npe *)dev->priv; - - debug("%s\n", __FUNCTION__); - npe_poll(p_npe->eth_id); - - debug("%s: rx_write=%d rx_read=%d\n", __FUNCTION__, p_npe->rx_write, p_npe->rx_read); - while (p_npe->rx_write != p_npe->rx_read) { - debug("Reading message #%d\n", p_npe->rx_read); - NetReceive(NetRxPackets[p_npe->rx_read], p_npe->rx_len[p_npe->rx_read]); - p_npe->rx_read++; - if (p_npe->rx_read == PKTBUFSRX) - p_npe->rx_read = 0; - } - - return 0; -} - -int npe_initialize(bd_t * bis) -{ - static int virgin = 0; - struct eth_device *dev; - int eth_num = 0; - struct npe *p_npe = NULL; - uchar enetaddr[6]; - - for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) { - - /* See if we can actually bring up the interface, otherwise, skip it */ -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) { - if (!eth_getenv_enetaddr("eth1addr", enetaddr)) - continue; - } else -#endif - if (!eth_getenv_enetaddr("ethaddr", enetaddr)) - continue; - - /* Allocate device structure */ - dev = (struct eth_device *)malloc(sizeof(*dev)); - if (dev == NULL) { - printf ("%s: Cannot allocate eth_device %d\n", __FUNCTION__, eth_num); - return -1; - } - memset(dev, 0, sizeof(*dev)); - - /* Allocate our private use data */ - p_npe = (struct npe *)malloc(sizeof(struct npe)); - if (p_npe == NULL) { - printf("%s: Cannot allocate private hw data for eth_device %d", - __FUNCTION__, eth_num); - free(dev); - return -1; - } - memset(p_npe, 0, sizeof(struct npe)); - - p_npe->eth_id = eth_num; - memcpy(dev->enetaddr, enetaddr, 6); -#ifdef CONFIG_HAS_ETH1 - if (eth_num == 1) - p_npe->phy_no = CONFIG_PHY1_ADDR; - else -#endif - p_npe->phy_no = CONFIG_PHY_ADDR; - - sprintf(dev->name, "NPE%d", eth_num); - dev->priv = (void *)p_npe; - dev->init = npe_init; - dev->halt = npe_halt; - dev->send = npe_send; - dev->recv = npe_rx; - - p_npe->print_speed = 1; - - if (0 == virgin) { - virgin = 1; - - if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP42X) { - switch (ixFeatureCtrlProductIdRead() & IX_FEATURE_CTRL_SILICON_STEPPING_MASK) { - case IX_FEATURE_CTRL_SILICON_TYPE_B0: - default: /* newer than B0 */ - /* - * If it is B0 or newer Silicon, we - * only enable port when its - * corresponding Eth Coprocessor is - * available. - */ - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - break; - case IX_FEATURE_CTRL_SILICON_TYPE_A0: - /* - * If it is A0 Silicon, we enable both as both Eth Coprocessors - * are available. - */ - npe_exists[IX_ETH_PORT_1] = true; - npe_exists[IX_ETH_PORT_2] = true; - break; - } - } else if (ixFeatureCtrlDeviceRead() == IX_FEATURE_CTRL_DEVICE_TYPE_IXP46X) { - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH0) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_1] = true; - - if (ixFeatureCtrlComponentCheck(IX_FEATURECTRL_ETH1) == - IX_FEATURE_CTRL_COMPONENT_ENABLED) - npe_exists[IX_ETH_PORT_2] = true; - } - - npe_used[IX_ETH_PORT_1] = 1; - npe_used[IX_ETH_PORT_2] = 1; - - npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool); - npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool + - CONFIG_SYS_CACHELINE_SIZE - 1) - & ~(CONFIG_SYS_CACHELINE_SIZE - 1)); - - if (!npe_csr_load()) - return 0; - } - - eth_register(dev); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write); -#endif - - } /* end for each supported device */ - - return 1; -} -- cgit v1.2.3 From f8d1086851409ee16344932ef367b8a05c365b09 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Jan 2014 00:21:38 +0100 Subject: ARM: serial: Remove the IXP UART driver This driver is no longer used, remove it. Signed-off-by: Marek Vasut Cc: Albert Aribaud Cc: Michael Schwingen Cc: Tom Rini --- doc/driver-model/UDM-serial.txt | 4 -- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_ixp.c | 130 ---------------------------------------- 4 files changed, 137 deletions(-) delete mode 100644 drivers/serial/serial_ixp.c (limited to 'drivers') diff --git a/doc/driver-model/UDM-serial.txt b/doc/driver-model/UDM-serial.txt index 279e941fc03..ed804a8e7e5 100644 --- a/doc/driver-model/UDM-serial.txt +++ b/doc/driver-model/UDM-serial.txt @@ -101,10 +101,6 @@ III) Analysis of in-tree drivers No support for CONFIG_SERIAL_MULTI. Simple conversion possible. This driver might be removed in favor of serial_mxc.c . - serial_ixp.c - ------------ - No support for CONFIG_SERIAL_MULTI. Simple conversion possible. - serial_ks8695.c --------------- No support for CONFIG_SERIAL_MULTI. Simple conversion possible. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6b4cadefdbd..85374fad8ff 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -18,7 +18,6 @@ obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_IXP_SERIAL) += serial_ixp.o obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df2b84aaafd..ed1643f7b5f 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -150,7 +150,6 @@ serial_initfunc(oc_serial_initialize); serial_initfunc(sandbox_serial_initialize); serial_initfunc(clps7111_serial_initialize); serial_initfunc(imx_serial_initialize); -serial_initfunc(ixp_serial_initialize); serial_initfunc(ks8695_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); serial_initfunc(max3100_serial_initialize); @@ -243,7 +242,6 @@ void serial_initialize(void) sandbox_serial_initialize(); clps7111_serial_initialize(); imx_serial_initialize(); - ixp_serial_initialize(); ks8695_serial_initialize(); lh7a40x_serial_initialize(); max3100_serial_initialize(); diff --git a/drivers/serial/serial_ixp.c b/drivers/serial/serial_ixp.c deleted file mode 100644 index b9d0f5bfa52..00000000000 --- a/drivers/serial/serial_ixp.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * 14.7456 MHz - * Baud Rate = -------------- - * 16 x Divisor - */ -#define SERIAL_CLOCK 921600 - -DECLARE_GLOBAL_DATA_PTR; - -static void ixp_serial_setbrg(void) -{ - unsigned int quot = 0; - int uart = CONFIG_SYS_IXP425_CONSOLE; - - if ((gd->baudrate <= SERIAL_CLOCK) && (SERIAL_CLOCK % gd->baudrate == 0)) - quot = SERIAL_CLOCK / gd->baudrate; - else - hang (); - - IER(uart) = 0; /* Disable for now */ - FCR(uart) = 0; /* No fifos enabled */ - - /* set baud rate */ - LCR(uart) = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - DLL(uart) = quot & 0xff; - DLH(uart) = quot >> 8; - LCR(uart) = LCR_WLS0 | LCR_WLS1; -#ifdef CONFIG_SERIAL_RTS_ACTIVE - MCR(uart) = MCR_RTS; /* set RTS active */ -#else - MCR(uart) = 0; /* set RTS inactive */ -#endif - IER(uart) = IER_UUE; -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -static int ixp_serial_init(void) -{ - serial_setbrg (); - - return (0); -} - - -/* - * Output a single byte to the serial port. - */ -static void ixp_serial_putc(const char c) -{ - /* wait for room in the tx FIFO on UART */ - while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - THR(CONFIG_SYS_IXP425_CONSOLE) = c; - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_tstc(void) -{ - return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR; -} - -/* - * Read a single byte from the serial port. Returns 1 on success, 0 - * otherwise. When the function is succesfull, the character read is - * written into its argument c. - */ -static int ixp_serial_getc(void) -{ - while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR)) - WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */ - - return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff; -} - -static struct serial_device ixp_serial_drv = { - .name = "ixp_serial", - .start = ixp_serial_init, - .stop = NULL, - .setbrg = ixp_serial_setbrg, - .putc = ixp_serial_putc, - .puts = default_serial_puts, - .getc = ixp_serial_getc, - .tstc = ixp_serial_tstc, -}; - -void ixp_serial_initialize(void) -{ - serial_register(&ixp_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ixp_serial_drv; -} -- cgit v1.2.3 From f016f8ca3d503af004a649de1c704d5ddf3def22 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Feb 2014 02:43:45 +0100 Subject: usb: mv_udc: Rename to ci_udc The mv_udc is not marvell-specific anymore. The mv_udc is used to drive generic ChipIdea CI13xxx series OTG cores, so rename the driver to ci_udc instead. Signed-off-by: Marek Vasut Cc: Eric Nelson Cc: Stefano Babic --- board/boundary/nitrogen6x/nitrogen6x.c | 2 +- drivers/serial/usbtty.h | 4 +- drivers/usb/gadget/Makefile | 2 +- drivers/usb/gadget/ci_udc.c | 737 +++++++++++++++++++++++++++++++++ drivers/usb/gadget/ci_udc.h | 115 +++++ drivers/usb/gadget/gadget_chips.h | 8 +- drivers/usb/gadget/mv_udc.c | 737 --------------------------------- drivers/usb/gadget/mv_udc.h | 115 ----- include/configs/nitrogen6x.h | 2 +- include/configs/sansa_fuze_plus.h | 2 +- include/configs/xfi3.h | 2 +- include/usb/ci_udc.h | 14 + include/usb/mv_udc.h | 14 - 13 files changed, 877 insertions(+), 877 deletions(-) create mode 100644 drivers/usb/gadget/ci_udc.c create mode 100644 drivers/usb/gadget/ci_udc.h delete mode 100644 drivers/usb/gadget/mv_udc.c delete mode 100644 drivers/usb/gadget/mv_udc.h create mode 100644 include/usb/ci_udc.h delete mode 100644 include/usb/mv_udc.h (limited to 'drivers') diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c index 3f4cfa1a29a..d9c05b07bfa 100644 --- a/board/boundary/nitrogen6x/nitrogen6x.c +++ b/board/boundary/nitrogen6x/nitrogen6x.c @@ -389,7 +389,7 @@ int board_eth_init(bd_t *bis) } #endif -#ifdef CONFIG_MV_UDC +#ifdef CONFIG_CI_UDC /* For otg ethernet*/ usb_eth_initialize(bis); #endif diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h index 819dec663f4..21a3ef4d97e 100644 --- a/drivers/serial/usbtty.h +++ b/drivers/serial/usbtty.h @@ -20,8 +20,8 @@ #include #elif defined(CONFIG_DW_UDC) #include -#elif defined(CONFIG_MV_UDC) -#include +#elif defined(CONFIG_CI_UDC) +#include #endif #include diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index f13b172a667..804a2bd412d 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -21,7 +21,7 @@ endif ifdef CONFIG_USB_ETHER obj-y += ether.o obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o -obj-$(CONFIG_MV_UDC) += mv_udc.o +obj-$(CONFIG_CI_UDC) += ci_udc.o obj-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o else # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c new file mode 100644 index 00000000000..14b1e9b8bf1 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.c @@ -0,0 +1,737 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Back ported to the 8xx platform (from the 8260 platform) by + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../host/ehci.h" +#include "ci_udc.h" + +/* + * Check if the system has too long cachelines. If the cachelines are + * longer then 128b, the driver will not be able flush/invalidate data + * cache over separate QH entries. We use 128b because one QH entry is + * 64b long and there are always two QH list entries for each endpoint. + */ +#if ARCH_DMA_MINALIGN > 128 +#error This driver can not work on systems with caches longer than 128b +#endif + +#ifndef DEBUG +#define DBG(x...) do {} while (0) +#else +#define DBG(x...) printf(x) +static const char *reqname(unsigned r) +{ + switch (r) { + case USB_REQ_GET_STATUS: return "GET_STATUS"; + case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; + case USB_REQ_SET_FEATURE: return "SET_FEATURE"; + case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; + case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; + case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; + case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; + case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; + case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; + case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; + default: return "*UNKNOWN*"; + } +} +#endif + +static struct usb_endpoint_descriptor ep0_out_desc = { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = 0, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static struct usb_endpoint_descriptor ep0_in_desc = { + .bLength = sizeof(struct usb_endpoint_descriptor), + .bDescriptorType = USB_DT_ENDPOINT, + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; + +static int ci_pullup(struct usb_gadget *gadget, int is_on); +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); +static int ci_ep_disable(struct usb_ep *ep); +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags); +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); + +static struct usb_gadget_ops ci_udc_ops = { + .pullup = ci_pullup, +}; + +static struct usb_ep_ops ci_ep_ops = { + .enable = ci_ep_enable, + .disable = ci_ep_disable, + .queue = ci_ep_queue, + .alloc_request = ci_ep_alloc_request, + .free_request = ci_ep_free_request, +}; + +/* Init values for USB endpoints. */ +static const struct usb_ep ci_ep_init[2] = { + [0] = { /* EP 0 */ + .maxpacket = 64, + .name = "ep0", + .ops = &ci_ep_ops, + }, + [1] = { /* EP 1..n */ + .maxpacket = 512, + .name = "ep-", + .ops = &ci_ep_ops, + }, +}; + +static struct ci_drv controller = { + .gadget = { + .name = "ci_udc", + .ops = &ci_udc_ops, + .is_dualspeed = 1, + }, +}; + +/** + * ci_get_qh() - return queue head for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in) +{ + return &controller.epts[(ep_num * 2) + dir_in]; +} + +/** + * ci_get_qtd() - return queue item for endpoint + * @ep_num: Endpoint number + * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) + * + * This function returns the QH associated with particular endpoint + * and it's direction. + */ +static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in) +{ + return controller.items[(ep_num * 2) + dir_in]; +} + +/** + * ci_flush_qh - flush cache over queue head + * @ep_num: Endpoint number + * + * This function flushes cache over QH for particular endpoint. + */ +static void ci_flush_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + const uint32_t start = (uint32_t)head; + const uint32_t end = start + 2 * sizeof(*head); + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qh - invalidate cache over queue head + * @ep_num: Endpoint number + * + * This function invalidates cache over QH for particular endpoint. + */ +static void ci_invalidate_qh(int ep_num) +{ + struct ept_queue_head *head = ci_get_qh(ep_num, 0); + uint32_t start = (uint32_t)head; + uint32_t end = start + 2 * sizeof(*head); + + invalidate_dcache_range(start, end); +} + +/** + * ci_flush_qtd - flush cache over queue item + * @ep_num: Endpoint number + * + * This function flushes cache over qTD pair for particular endpoint. + */ +static void ci_flush_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + flush_dcache_range(start, end); +} + +/** + * ci_invalidate_qtd - invalidate cache over queue item + * @ep_num: Endpoint number + * + * This function invalidates cache over qTD pair for particular endpoint. + */ +static void ci_invalidate_qtd(int ep_num) +{ + struct ept_queue_item *item = ci_get_qtd(ep_num, 0); + const uint32_t start = (uint32_t)item; + const uint32_t end_raw = start + 2 * sizeof(*item); + const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); + + invalidate_dcache_range(start, end); +} + +static struct usb_request * +ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + return &ci_ep->req; +} + +static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req) +{ + return; +} + +static void ep_enable(int num, int in, int maxpacket) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n; + + n = readl(&udc->epctrl[num]); + if (in) + n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); + else + n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); + + if (num != 0) { + struct ept_queue_head *head = ci_get_qh(num, in); + + head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; + ci_flush_qh(num); + } + writel(n, &udc->epctrl[num]); +} + +static int ci_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + int num, in; + num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (desc->bEndpointAddress & USB_DIR_IN) != 0; + ci_ep->desc = desc; + + if (num) { + int max = get_unaligned_le16(&desc->wMaxPacketSize); + + if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) + max = 64; + if (ep->maxpacket != max) { + DBG("%s: from %d to %d\n", __func__, + ep->maxpacket, max); + ep->maxpacket = max; + } + } + ep_enable(num, in, ep->maxpacket); + DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); + return 0; +} + +static int ci_ep_disable(struct usb_ep *ep) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + + ci_ep->desc = NULL; + return 0; +} + +static int ci_bounce(struct ci_ep *ep, int in) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba; + + /* Input buffer address is not aligned. */ + if (addr & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* Input buffer length is not aligned. */ + if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) + goto align; + + /* The buffer is well aligned, only flush cache. */ + ep->b_len = ep->req.length; + ep->b_buf = ep->req.buf; + goto flush; + +align: + /* Use internal buffer for small payloads. */ + if (ep->req.length <= 64) { + ep->b_len = 64; + ep->b_buf = ep->b_fast; + } else { + ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); + ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); + if (!ep->b_buf) + return -ENOMEM; + } + if (in) + memcpy(ep->b_buf, ep->req.buf, ep->req.length); + +flush: + ba = (uint32_t)ep->b_buf; + flush_dcache_range(ba, ba + ep->b_len); + + return 0; +} + +static void ci_debounce(struct ci_ep *ep, int in) +{ + uint32_t addr = (uint32_t)ep->req.buf; + uint32_t ba = (uint32_t)ep->b_buf; + + if (in) { + if (addr == ba) + return; /* not a bounce */ + goto free; + } + invalidate_dcache_range(ba, ba + ep->b_len); + + if (addr == ba) + return; /* not a bounce */ + + memcpy(ep->req.buf, ep->b_buf, ep->req.length); +free: + /* Large payloads use allocated buffer, free it. */ + if (ep->b_buf != ep->b_fast) + free(ep->b_buf); +} + +static int ci_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep); + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_item *item; + struct ept_queue_head *head; + int bit, num, len, in, ret; + num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + item = ci_get_qtd(num, in); + head = ci_get_qh(num, in); + len = req->length; + + ret = ci_bounce(ci_ep, in); + if (ret) + return ret; + + item->next = TERMINATE; + item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; + item->page0 = (uint32_t)ci_ep->b_buf; + item->page1 = ((uint32_t)ci_ep->b_buf & 0xfffff000) + 0x1000; + ci_flush_qtd(num); + + head->next = (unsigned) item; + head->info = 0; + + DBG("ept%d %s queue len %x, buffer %p\n", + num, in ? "in" : "out", len, ci_ep->b_buf); + ci_flush_qh(num); + + if (in) + bit = EPT_TX(num); + else + bit = EPT_RX(num); + + writel(bit, &udc->epprime); + + return 0; +} + +static void handle_ep_complete(struct ci_ep *ep) +{ + struct ept_queue_item *item; + int num, in, len; + num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; + in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; + if (num == 0) + ep->desc = &ep0_out_desc; + item = ci_get_qtd(num, in); + ci_invalidate_qtd(num); + + if (item->info & 0xff) + printf("EP%d/%s FAIL info=%x pg0=%x\n", + num, in ? "in" : "out", item->info, item->page0); + + len = (item->info >> 16) & 0x7fff; + ep->req.length -= len; + ci_debounce(ep, in); + + DBG("ept%d %s complete %x\n", + num, in ? "in" : "out", len); + ep->req.complete(&ep->ep, &ep->req); + if (num == 0) { + ep->req.length = 0; + usb_ep_queue(&ep->ep, &ep->req, 0); + ep->desc = &ep0_in_desc; + } +} + +#define SETUP(type, request) (((type) << 8) | (request)) + +static void handle_setup(void) +{ + struct usb_request *req = &controller.ep[0].req; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + struct ept_queue_head *head; + struct usb_ctrlrequest r; + int status = 0; + int num, in, _num, _in, i; + char *buf; + head = ci_get_qh(0, 0); /* EP0 OUT */ + + ci_invalidate_qh(0); + memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); + writel(EPT_RX(0), &udc->epstat); + DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), + r.bRequestType, r.bRequest, r.wIndex, r.wValue); + + switch (SETUP(r.bRequestType, r.bRequest)) { + case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): + _num = r.wIndex & 15; + _in = !!(r.wIndex & 0x80); + + if ((r.wValue == 0) && (r.wLength == 0)) { + req->length = 0; + for (i = 0; i < NUM_ENDPOINTS; i++) { + struct ci_ep *ep = &controller.ep[i]; + + if (!ep->desc) + continue; + num = ep->desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (ep->desc->bEndpointAddress + & USB_DIR_IN) != 0; + if ((num == _num) && (in == _in)) { + ep_enable(num, in, ep->ep.maxpacket); + usb_ep_queue(controller.gadget.ep0, + req, 0); + break; + } + } + } + return; + + case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): + /* + * write address delayed (will take effect + * after the next IN txn) + */ + writel((r.wValue << 25) | (1 << 24), &udc->devaddr); + req->length = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + + case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): + req->length = 2; + buf = (char *)req->buf; + buf[0] = 1 << USB_DEVICE_SELF_POWERED; + buf[1] = 0; + usb_ep_queue(controller.gadget.ep0, req, 0); + return; + } + /* pass request up to the gadget driver */ + if (controller.driver) + status = controller.driver->setup(&controller.gadget, &r); + else + status = -ENODEV; + + if (!status) + return; + DBG("STALL reqname %s type %x value %x, index %x\n", + reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); + writel((1<<16) | (1 << 0), &udc->epctrl[0]); +} + +static void stop_activity(void) +{ + int i, num, in; + struct ept_queue_head *head; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + writel(readl(&udc->epcomp), &udc->epcomp); + writel(readl(&udc->epstat), &udc->epstat); + writel(0xffffffff, &udc->epflush); + + /* error out any pending reqs */ + for (i = 0; i < NUM_ENDPOINTS; i++) { + if (i != 0) + writel(0, &udc->epctrl[i]); + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + head = ci_get_qh(num, in); + head->info = INFO_ACTIVE; + ci_flush_qh(num); + } + } +} + +void udc_irq(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n = readl(&udc->usbsts); + writel(n, &udc->usbsts); + int bit, i, num, in; + + n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); + if (n == 0) + return; + + if (n & STS_URI) { + DBG("-- reset --\n"); + stop_activity(); + } + if (n & STS_SLI) + DBG("-- suspend --\n"); + + if (n & STS_PCI) { + int max = 64; + int speed = USB_SPEED_FULL; + + bit = (readl(&udc->portsc) >> 26) & 3; + DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); + if (bit == 2) { + speed = USB_SPEED_HIGH; + max = 512; + } + controller.gadget.speed = speed; + for (i = 1; i < NUM_ENDPOINTS; i++) { + if (controller.ep[i].ep.maxpacket > max) + controller.ep[i].ep.maxpacket = max; + } + } + + if (n & STS_UEI) + printf("\n", readl(&udc->epcomp)); + + if ((n & STS_UI) || (n & STS_UEI)) { + n = readl(&udc->epstat); + if (n & EPT_RX(0)) + handle_setup(); + + n = readl(&udc->epcomp); + if (n != 0) + writel(n, &udc->epcomp); + + for (i = 0; i < NUM_ENDPOINTS && n; i++) { + if (controller.ep[i].desc) { + num = controller.ep[i].desc->bEndpointAddress + & USB_ENDPOINT_NUMBER_MASK; + in = (controller.ep[i].desc->bEndpointAddress + & USB_DIR_IN) != 0; + bit = (in) ? EPT_TX(num) : EPT_RX(num); + if (n & bit) + handle_ep_complete(&controller.ep[i]); + } + } + } +} + +int usb_gadget_handle_interrupts(void) +{ + u32 value; + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + value = readl(&udc->usbsts); + if (value) + udc_irq(); + + return value; +} + +static int ci_pullup(struct usb_gadget *gadget, int is_on) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + if (is_on) { + /* RESET */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); + udelay(200); + + writel((unsigned)controller.epts, &udc->epinitaddr); + + /* select DEVICE mode */ + writel(USBMODE_DEVICE, &udc->usbmode); + + writel(0xffffffff, &udc->epflush); + + /* Turn on the USB connection by enabling the pullup resistor */ + writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); + } else { + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(gadget); + } + + return 0; +} + +void udc_disconnect(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + /* disable pullup */ + stop_activity(); + writel(USBCMD_FS2, &udc->usbcmd); + udelay(800); + if (controller.driver) + controller.driver->disconnect(&controller.gadget); +} + +static int ci_udc_probe(void) +{ + struct ept_queue_head *head; + uint8_t *imem; + int i; + + const int num = 2 * NUM_ENDPOINTS; + + const int eplist_min_align = 4096; + const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); + const int eplist_raw_sz = num * sizeof(struct ept_queue_head); + const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); + + const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); + const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); + const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); + const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; + + /* The QH list must be aligned to 4096 bytes. */ + controller.epts = memalign(eplist_align, eplist_sz); + if (!controller.epts) + return -ENOMEM; + memset(controller.epts, 0, eplist_sz); + + /* + * Each qTD item must be 32-byte aligned, each qTD touple must be + * cacheline aligned. There are two qTD items for each endpoint and + * only one of them is used for the endpoint at time, so we can group + * them together. + */ + controller.items_mem = memalign(ilist_align, ilist_sz); + if (!controller.items_mem) { + free(controller.epts); + return -ENOMEM; + } + memset(controller.items_mem, 0, ilist_sz); + + for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { + /* + * Configure QH for each endpoint. The structure of the QH list + * is such that each two subsequent fields, N and N+1 where N is + * even, in the QH list represent QH for one endpoint. The Nth + * entry represents OUT configuration and the N+1th entry does + * represent IN configuration of the endpoint. + */ + head = controller.epts + i; + if (i < 2) + head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) + | CONFIG_ZLT | CONFIG_IOS; + else + head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) + | CONFIG_ZLT; + head->next = TERMINATE; + head->info = 0; + + imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); + if (i & 1) + imem += sizeof(struct ept_queue_item); + + controller.items[i] = (struct ept_queue_item *)imem; + + if (i & 1) { + ci_flush_qh(i - 1); + ci_flush_qtd(i - 1); + } + } + + INIT_LIST_HEAD(&controller.gadget.ep_list); + + /* Init EP 0 */ + memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init)); + controller.ep[0].desc = &ep0_in_desc; + controller.gadget.ep0 = &controller.ep[0].ep; + INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); + + /* Init EP 1..n */ + for (i = 1; i < NUM_ENDPOINTS; i++) { + memcpy(&controller.ep[i].ep, &ci_ep_init[1], + sizeof(*ci_ep_init)); + list_add_tail(&controller.ep[i].ep.ep_list, + &controller.gadget.ep_list); + } + + return 0; +} + +int usb_gadget_register_driver(struct usb_gadget_driver *driver) +{ + struct ci_udc *udc; + int ret; + + if (!driver) + return -EINVAL; + if (!driver->bind || !driver->setup || !driver->disconnect) + return -EINVAL; + if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) + return -EINVAL; + + ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); + if (ret) + return ret; + + ret = ci_udc_probe(); + if (!ret) { + udc = (struct ci_udc *)controller.ctrl->hcor; + + /* select ULPI phy */ + writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); + } + + ret = driver->bind(&controller.gadget); + if (ret) { + DBG("driver->bind() returned %d\n", ret); + return ret; + } + controller.driver = driver; + + return 0; +} + +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) +{ + return 0; +} diff --git a/drivers/usb/gadget/ci_udc.h b/drivers/usb/gadget/ci_udc.h new file mode 100644 index 00000000000..42f6ef4ab30 --- /dev/null +++ b/drivers/usb/gadget/ci_udc.h @@ -0,0 +1,115 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * + * Licensed under the GPL-2 or later. + */ +#ifndef __GADGET__CI_UDC_H__ +#define __GADGET__CI_UDC_H__ + +#define NUM_ENDPOINTS 6 + +struct ci_udc { +#define MICRO_8FRAME 0x8 +#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) +#define USBCMD_FS2 (1 << 15) +#define USBCMD_RST (1 << 1) +#define USBCMD_RUN (1) + u32 usbcmd; /* 0x140 */ +#define STS_SLI (1 << 8) +#define STS_URI (1 << 6) +#define STS_PCI (1 << 2) +#define STS_UEI (1 << 1) +#define STS_UI (1 << 0) + u32 usbsts; /* 0x144 */ + u32 pad1[3]; + u32 devaddr; /* 0x154 */ + u32 epinitaddr; /* 0x158 */ + u32 pad2[10]; +#define PTS_ENABLE 2 +#define PTS(x) (((x) & 0x3) << 30) +#define PFSC (1 << 24) + u32 portsc; /* 0x184 */ + u32 pad3[8]; +#define USBMODE_DEVICE 2 + u32 usbmode; /* 0x1a8 */ + u32 epstat; /* 0x1ac */ +#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) +#define EPT_RX(x) (1 << ((x) & 0xffff)) + u32 epprime; /* 0x1b0 */ + u32 epflush; /* 0x1b4 */ + u32 pad4; + u32 epcomp; /* 0x1bc */ +#define CTRL_TXE (1 << 23) +#define CTRL_TXR (1 << 22) +#define CTRL_RXE (1 << 7) +#define CTRL_RXR (1 << 6) +#define CTRL_TXT_BULK (2 << 18) +#define CTRL_RXT_BULK (2 << 2) + u32 epctrl[16]; /* 0x1c0 */ +}; + +struct ci_ep { + struct usb_ep ep; + struct list_head queue; + const struct usb_endpoint_descriptor *desc; + + struct usb_request req; + uint8_t *b_buf; + uint32_t b_len; + uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); +}; + +struct ci_drv { + struct usb_gadget gadget; + struct usb_gadget_driver *driver; + struct ehci_ctrl *ctrl; + struct ept_queue_head *epts; + struct ept_queue_item *items[2 * NUM_ENDPOINTS]; + uint8_t *items_mem; + struct ci_ep ep[NUM_ENDPOINTS]; +}; + +struct ept_queue_head { + unsigned config; + unsigned current; /* read-only */ + + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved_0; + + unsigned char setup_data[8]; + + unsigned reserved_1; + unsigned reserved_2; + unsigned reserved_3; + unsigned reserved_4; +}; + +#define CONFIG_MAX_PKT(n) ((n) << 16) +#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ +#define CONFIG_IOS (1 << 15) /* IRQ on setup */ + +struct ept_queue_item { + unsigned next; + unsigned info; + unsigned page0; + unsigned page1; + unsigned page2; + unsigned page3; + unsigned page4; + unsigned reserved; +}; + +#define TERMINATE 1 +#define INFO_BYTES(n) ((n) << 16) +#define INFO_IOC (1 << 15) +#define INFO_ACTIVE (1 << 7) +#define INFO_HALTED (1 << 6) +#define INFO_BUFFER_ERROR (1 << 5) +#define INFO_TX_ERROR (1 << 3) +#endif diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index aa54b8547e7..cc94771e32f 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -144,10 +144,10 @@ #define gadget_is_m66592(g) 0 #endif -#ifdef CONFIG_MV_UDC -#define gadget_is_mv(g) (!strcmp("mv_udc", (g)->name)) +#ifdef CONFIG_CI_UDC +#define gadget_is_ci(g) (!strcmp("ci_udc", (g)->name)) #else -#define gadget_is_mv(g) 0 +#define gadget_is_ci(g) 0 #endif #ifdef CONFIG_USB_GADGET_FOTG210 @@ -219,7 +219,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget) return 0x19; else if (gadget_is_m66592(gadget)) return 0x20; - else if (gadget_is_mv(gadget)) + else if (gadget_is_ci(gadget)) return 0x21; else if (gadget_is_fotg210(gadget)) return 0x22; diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c deleted file mode 100644 index da41738653e..00000000000 --- a/drivers/usb/gadget/mv_udc.c +++ /dev/null @@ -1,737 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - * - * Back ported to the 8xx platform (from the 8260 platform) by - * Murray.Jensen@cmst.csiro.au, 27-Jan-01. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../host/ehci.h" -#include "mv_udc.h" - -/* - * Check if the system has too long cachelines. If the cachelines are - * longer then 128b, the driver will not be able flush/invalidate data - * cache over separate QH entries. We use 128b because one QH entry is - * 64b long and there are always two QH list entries for each endpoint. - */ -#if ARCH_DMA_MINALIGN > 128 -#error This driver can not work on systems with caches longer than 128b -#endif - -#ifndef DEBUG -#define DBG(x...) do {} while (0) -#else -#define DBG(x...) printf(x) -static const char *reqname(unsigned r) -{ - switch (r) { - case USB_REQ_GET_STATUS: return "GET_STATUS"; - case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE"; - case USB_REQ_SET_FEATURE: return "SET_FEATURE"; - case USB_REQ_SET_ADDRESS: return "SET_ADDRESS"; - case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR"; - case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR"; - case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION"; - case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION"; - case USB_REQ_GET_INTERFACE: return "GET_INTERFACE"; - case USB_REQ_SET_INTERFACE: return "SET_INTERFACE"; - default: return "*UNKNOWN*"; - } -} -#endif - -static struct usb_endpoint_descriptor ep0_out_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = 0, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static struct usb_endpoint_descriptor ep0_in_desc = { - .bLength = sizeof(struct usb_endpoint_descriptor), - .bDescriptorType = USB_DT_ENDPOINT, - .bEndpointAddress = USB_DIR_IN, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -static int mv_pullup(struct usb_gadget *gadget, int is_on); -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc); -static int mv_ep_disable(struct usb_ep *ep); -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags); -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req); - -static struct usb_gadget_ops mv_udc_ops = { - .pullup = mv_pullup, -}; - -static struct usb_ep_ops mv_ep_ops = { - .enable = mv_ep_enable, - .disable = mv_ep_disable, - .queue = mv_ep_queue, - .alloc_request = mv_ep_alloc_request, - .free_request = mv_ep_free_request, -}; - -/* Init values for USB endpoints. */ -static const struct usb_ep mv_ep_init[2] = { - [0] = { /* EP 0 */ - .maxpacket = 64, - .name = "ep0", - .ops = &mv_ep_ops, - }, - [1] = { /* EP 1..n */ - .maxpacket = 512, - .name = "ep-", - .ops = &mv_ep_ops, - }, -}; - -static struct mv_drv controller = { - .gadget = { - .name = "mv_udc", - .ops = &mv_udc_ops, - .is_dualspeed = 1, - }, -}; - -/** - * mv_get_qh() - return queue head for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in) -{ - return &controller.epts[(ep_num * 2) + dir_in]; -} - -/** - * mv_get_qtd() - return queue item for endpoint - * @ep_num: Endpoint number - * @dir_in: Direction of the endpoint (IN = 1, OUT = 0) - * - * This function returns the QH associated with particular endpoint - * and it's direction. - */ -static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in) -{ - return controller.items[(ep_num * 2) + dir_in]; -} - -/** - * mv_flush_qh - flush cache over queue head - * @ep_num: Endpoint number - * - * This function flushes cache over QH for particular endpoint. - */ -static void mv_flush_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - const uint32_t start = (uint32_t)head; - const uint32_t end = start + 2 * sizeof(*head); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qh - invalidate cache over queue head - * @ep_num: Endpoint number - * - * This function invalidates cache over QH for particular endpoint. - */ -static void mv_invalidate_qh(int ep_num) -{ - struct ept_queue_head *head = mv_get_qh(ep_num, 0); - uint32_t start = (uint32_t)head; - uint32_t end = start + 2 * sizeof(*head); - - invalidate_dcache_range(start, end); -} - -/** - * mv_flush_qtd - flush cache over queue item - * @ep_num: Endpoint number - * - * This function flushes cache over qTD pair for particular endpoint. - */ -static void mv_flush_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - flush_dcache_range(start, end); -} - -/** - * mv_invalidate_qtd - invalidate cache over queue item - * @ep_num: Endpoint number - * - * This function invalidates cache over qTD pair for particular endpoint. - */ -static void mv_invalidate_qtd(int ep_num) -{ - struct ept_queue_item *item = mv_get_qtd(ep_num, 0); - const uint32_t start = (uint32_t)item; - const uint32_t end_raw = start + 2 * sizeof(*item); - const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN); - - invalidate_dcache_range(start, end); -} - -static struct usb_request * -mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - return &mv_ep->req; -} - -static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req) -{ - return; -} - -static void ep_enable(int num, int in, int maxpacket) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n; - - n = readl(&udc->epctrl[num]); - if (in) - n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK); - else - n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK); - - if (num != 0) { - struct ept_queue_head *head = mv_get_qh(num, in); - - head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT; - mv_flush_qh(num); - } - writel(n, &udc->epctrl[num]); -} - -static int mv_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - int num, in; - num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (desc->bEndpointAddress & USB_DIR_IN) != 0; - mv_ep->desc = desc; - - if (num) { - int max = get_unaligned_le16(&desc->wMaxPacketSize); - - if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL)) - max = 64; - if (ep->maxpacket != max) { - DBG("%s: from %d to %d\n", __func__, - ep->maxpacket, max); - ep->maxpacket = max; - } - } - ep_enable(num, in, ep->maxpacket); - DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket); - return 0; -} - -static int mv_ep_disable(struct usb_ep *ep) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - - mv_ep->desc = NULL; - return 0; -} - -static int mv_bounce(struct mv_ep *ep, int in) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba; - - /* Input buffer address is not aligned. */ - if (addr & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* Input buffer length is not aligned. */ - if (ep->req.length & (ARCH_DMA_MINALIGN - 1)) - goto align; - - /* The buffer is well aligned, only flush cache. */ - ep->b_len = ep->req.length; - ep->b_buf = ep->req.buf; - goto flush; - -align: - /* Use internal buffer for small payloads. */ - if (ep->req.length <= 64) { - ep->b_len = 64; - ep->b_buf = ep->b_fast; - } else { - ep->b_len = roundup(ep->req.length, ARCH_DMA_MINALIGN); - ep->b_buf = memalign(ARCH_DMA_MINALIGN, ep->b_len); - if (!ep->b_buf) - return -ENOMEM; - } - if (in) - memcpy(ep->b_buf, ep->req.buf, ep->req.length); - -flush: - ba = (uint32_t)ep->b_buf; - flush_dcache_range(ba, ba + ep->b_len); - - return 0; -} - -static void mv_debounce(struct mv_ep *ep, int in) -{ - uint32_t addr = (uint32_t)ep->req.buf; - uint32_t ba = (uint32_t)ep->b_buf; - - if (in) { - if (addr == ba) - return; /* not a bounce */ - goto free; - } - invalidate_dcache_range(ba, ba + ep->b_len); - - if (addr == ba) - return; /* not a bounce */ - - memcpy(ep->req.buf, ep->b_buf, ep->req.length); -free: - /* Large payloads use allocated buffer, free it. */ - if (ep->b_buf != ep->b_fast) - free(ep->b_buf); -} - -static int mv_ep_queue(struct usb_ep *ep, - struct usb_request *req, gfp_t gfp_flags) -{ - struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep); - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_item *item; - struct ept_queue_head *head; - int bit, num, len, in, ret; - num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - item = mv_get_qtd(num, in); - head = mv_get_qh(num, in); - len = req->length; - - ret = mv_bounce(mv_ep, in); - if (ret) - return ret; - - item->next = TERMINATE; - item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE; - item->page0 = (uint32_t)mv_ep->b_buf; - item->page1 = ((uint32_t)mv_ep->b_buf & 0xfffff000) + 0x1000; - mv_flush_qtd(num); - - head->next = (unsigned) item; - head->info = 0; - - DBG("ept%d %s queue len %x, buffer %p\n", - num, in ? "in" : "out", len, mv_ep->b_buf); - mv_flush_qh(num); - - if (in) - bit = EPT_TX(num); - else - bit = EPT_RX(num); - - writel(bit, &udc->epprime); - - return 0; -} - -static void handle_ep_complete(struct mv_ep *ep) -{ - struct ept_queue_item *item; - int num, in, len; - num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0; - if (num == 0) - ep->desc = &ep0_out_desc; - item = mv_get_qtd(num, in); - mv_invalidate_qtd(num); - - if (item->info & 0xff) - printf("EP%d/%s FAIL info=%x pg0=%x\n", - num, in ? "in" : "out", item->info, item->page0); - - len = (item->info >> 16) & 0x7fff; - ep->req.length -= len; - mv_debounce(ep, in); - - DBG("ept%d %s complete %x\n", - num, in ? "in" : "out", len); - ep->req.complete(&ep->ep, &ep->req); - if (num == 0) { - ep->req.length = 0; - usb_ep_queue(&ep->ep, &ep->req, 0); - ep->desc = &ep0_in_desc; - } -} - -#define SETUP(type, request) (((type) << 8) | (request)) - -static void handle_setup(void) -{ - struct usb_request *req = &controller.ep[0].req; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - struct ept_queue_head *head; - struct usb_ctrlrequest r; - int status = 0; - int num, in, _num, _in, i; - char *buf; - head = mv_get_qh(0, 0); /* EP0 OUT */ - - mv_invalidate_qh(0); - memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest)); - writel(EPT_RX(0), &udc->epstat); - DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest), - r.bRequestType, r.bRequest, r.wIndex, r.wValue); - - switch (SETUP(r.bRequestType, r.bRequest)) { - case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE): - _num = r.wIndex & 15; - _in = !!(r.wIndex & 0x80); - - if ((r.wValue == 0) && (r.wLength == 0)) { - req->length = 0; - for (i = 0; i < NUM_ENDPOINTS; i++) { - struct mv_ep *ep = &controller.ep[i]; - - if (!ep->desc) - continue; - num = ep->desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (ep->desc->bEndpointAddress - & USB_DIR_IN) != 0; - if ((num == _num) && (in == _in)) { - ep_enable(num, in, ep->ep.maxpacket); - usb_ep_queue(controller.gadget.ep0, - req, 0); - break; - } - } - } - return; - - case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS): - /* - * write address delayed (will take effect - * after the next IN txn) - */ - writel((r.wValue << 25) | (1 << 24), &udc->devaddr); - req->length = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - - case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS): - req->length = 2; - buf = (char *)req->buf; - buf[0] = 1 << USB_DEVICE_SELF_POWERED; - buf[1] = 0; - usb_ep_queue(controller.gadget.ep0, req, 0); - return; - } - /* pass request up to the gadget driver */ - if (controller.driver) - status = controller.driver->setup(&controller.gadget, &r); - else - status = -ENODEV; - - if (!status) - return; - DBG("STALL reqname %s type %x value %x, index %x\n", - reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex); - writel((1<<16) | (1 << 0), &udc->epctrl[0]); -} - -static void stop_activity(void) -{ - int i, num, in; - struct ept_queue_head *head; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - writel(readl(&udc->epcomp), &udc->epcomp); - writel(readl(&udc->epstat), &udc->epstat); - writel(0xffffffff, &udc->epflush); - - /* error out any pending reqs */ - for (i = 0; i < NUM_ENDPOINTS; i++) { - if (i != 0) - writel(0, &udc->epctrl[i]); - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - head = mv_get_qh(num, in); - head->info = INFO_ACTIVE; - mv_flush_qh(num); - } - } -} - -void udc_irq(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - unsigned n = readl(&udc->usbsts); - writel(n, &udc->usbsts); - int bit, i, num, in; - - n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); - if (n == 0) - return; - - if (n & STS_URI) { - DBG("-- reset --\n"); - stop_activity(); - } - if (n & STS_SLI) - DBG("-- suspend --\n"); - - if (n & STS_PCI) { - int max = 64; - int speed = USB_SPEED_FULL; - - bit = (readl(&udc->portsc) >> 26) & 3; - DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full"); - if (bit == 2) { - speed = USB_SPEED_HIGH; - max = 512; - } - controller.gadget.speed = speed; - for (i = 1; i < NUM_ENDPOINTS; i++) { - if (controller.ep[i].ep.maxpacket > max) - controller.ep[i].ep.maxpacket = max; - } - } - - if (n & STS_UEI) - printf("\n", readl(&udc->epcomp)); - - if ((n & STS_UI) || (n & STS_UEI)) { - n = readl(&udc->epstat); - if (n & EPT_RX(0)) - handle_setup(); - - n = readl(&udc->epcomp); - if (n != 0) - writel(n, &udc->epcomp); - - for (i = 0; i < NUM_ENDPOINTS && n; i++) { - if (controller.ep[i].desc) { - num = controller.ep[i].desc->bEndpointAddress - & USB_ENDPOINT_NUMBER_MASK; - in = (controller.ep[i].desc->bEndpointAddress - & USB_DIR_IN) != 0; - bit = (in) ? EPT_TX(num) : EPT_RX(num); - if (n & bit) - handle_ep_complete(&controller.ep[i]); - } - } - } -} - -int usb_gadget_handle_interrupts(void) -{ - u32 value; - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - - value = readl(&udc->usbsts); - if (value) - udc_irq(); - - return value; -} - -static int mv_pullup(struct usb_gadget *gadget, int is_on) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - if (is_on) { - /* RESET */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd); - udelay(200); - - writel((unsigned)controller.epts, &udc->epinitaddr); - - /* select DEVICE mode */ - writel(USBMODE_DEVICE, &udc->usbmode); - - writel(0xffffffff, &udc->epflush); - - /* Turn on the USB connection by enabling the pullup resistor */ - writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd); - } else { - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(gadget); - } - - return 0; -} - -void udc_disconnect(void) -{ - struct mv_udc *udc = (struct mv_udc *)controller.ctrl->hcor; - /* disable pullup */ - stop_activity(); - writel(USBCMD_FS2, &udc->usbcmd); - udelay(800); - if (controller.driver) - controller.driver->disconnect(&controller.gadget); -} - -static int mvudc_probe(void) -{ - struct ept_queue_head *head; - uint8_t *imem; - int i; - - const int num = 2 * NUM_ENDPOINTS; - - const int eplist_min_align = 4096; - const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN); - const int eplist_raw_sz = num * sizeof(struct ept_queue_head); - const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN); - - const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32); - const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item); - const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN); - const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz; - - /* The QH list must be aligned to 4096 bytes. */ - controller.epts = memalign(eplist_align, eplist_sz); - if (!controller.epts) - return -ENOMEM; - memset(controller.epts, 0, eplist_sz); - - /* - * Each qTD item must be 32-byte aligned, each qTD touple must be - * cacheline aligned. There are two qTD items for each endpoint and - * only one of them is used for the endpoint at time, so we can group - * them together. - */ - controller.items_mem = memalign(ilist_align, ilist_sz); - if (!controller.items_mem) { - free(controller.epts); - return -ENOMEM; - } - memset(controller.items_mem, 0, ilist_sz); - - for (i = 0; i < 2 * NUM_ENDPOINTS; i++) { - /* - * Configure QH for each endpoint. The structure of the QH list - * is such that each two subsequent fields, N and N+1 where N is - * even, in the QH list represent QH for one endpoint. The Nth - * entry represents OUT configuration and the N+1th entry does - * represent IN configuration of the endpoint. - */ - head = controller.epts + i; - if (i < 2) - head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE) - | CONFIG_ZLT | CONFIG_IOS; - else - head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) - | CONFIG_ZLT; - head->next = TERMINATE; - head->info = 0; - - imem = controller.items_mem + ((i >> 1) * ilist_ent_sz); - if (i & 1) - imem += sizeof(struct ept_queue_item); - - controller.items[i] = (struct ept_queue_item *)imem; - - if (i & 1) { - mv_flush_qh(i - 1); - mv_flush_qtd(i - 1); - } - } - - INIT_LIST_HEAD(&controller.gadget.ep_list); - - /* Init EP 0 */ - memcpy(&controller.ep[0].ep, &mv_ep_init[0], sizeof(*mv_ep_init)); - controller.ep[0].desc = &ep0_in_desc; - controller.gadget.ep0 = &controller.ep[0].ep; - INIT_LIST_HEAD(&controller.gadget.ep0->ep_list); - - /* Init EP 1..n */ - for (i = 1; i < NUM_ENDPOINTS; i++) { - memcpy(&controller.ep[i].ep, &mv_ep_init[1], - sizeof(*mv_ep_init)); - list_add_tail(&controller.ep[i].ep.ep_list, - &controller.gadget.ep_list); - } - - return 0; -} - -int usb_gadget_register_driver(struct usb_gadget_driver *driver) -{ - struct mv_udc *udc; - int ret; - - if (!driver) - return -EINVAL; - if (!driver->bind || !driver->setup || !driver->disconnect) - return -EINVAL; - if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH) - return -EINVAL; - - ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl); - if (ret) - return ret; - - ret = mvudc_probe(); - if (!ret) { - udc = (struct mv_udc *)controller.ctrl->hcor; - - /* select ULPI phy */ - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc); - } - - ret = driver->bind(&controller.gadget); - if (ret) { - DBG("driver->bind() returned %d\n", ret); - return ret; - } - controller.driver = driver; - - return 0; -} - -int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) -{ - return 0; -} diff --git a/drivers/usb/gadget/mv_udc.h b/drivers/usb/gadget/mv_udc.h deleted file mode 100644 index c7d8b33984c..00000000000 --- a/drivers/usb/gadget/mv_udc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * - * Licensed under the GPL-2 or later. - */ -#ifndef __GADGET__MV_UDC_H__ -#define __GADGET__MV_UDC_H__ - -#define NUM_ENDPOINTS 6 - -struct mv_udc { -#define MICRO_8FRAME 0x8 -#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16) -#define USBCMD_FS2 (1 << 15) -#define USBCMD_RST (1 << 1) -#define USBCMD_RUN (1) - u32 usbcmd; /* 0x140 */ -#define STS_SLI (1 << 8) -#define STS_URI (1 << 6) -#define STS_PCI (1 << 2) -#define STS_UEI (1 << 1) -#define STS_UI (1 << 0) - u32 usbsts; /* 0x144 */ - u32 pad1[3]; - u32 devaddr; /* 0x154 */ - u32 epinitaddr; /* 0x158 */ - u32 pad2[10]; -#define PTS_ENABLE 2 -#define PTS(x) (((x) & 0x3) << 30) -#define PFSC (1 << 24) - u32 portsc; /* 0x184 */ - u32 pad3[8]; -#define USBMODE_DEVICE 2 - u32 usbmode; /* 0x1a8 */ - u32 epstat; /* 0x1ac */ -#define EPT_TX(x) (1 << (((x) & 0xffff) + 16)) -#define EPT_RX(x) (1 << ((x) & 0xffff)) - u32 epprime; /* 0x1b0 */ - u32 epflush; /* 0x1b4 */ - u32 pad4; - u32 epcomp; /* 0x1bc */ -#define CTRL_TXE (1 << 23) -#define CTRL_TXR (1 << 22) -#define CTRL_RXE (1 << 7) -#define CTRL_RXR (1 << 6) -#define CTRL_TXT_BULK (2 << 18) -#define CTRL_RXT_BULK (2 << 2) - u32 epctrl[16]; /* 0x1c0 */ -}; - -struct mv_ep { - struct usb_ep ep; - struct list_head queue; - const struct usb_endpoint_descriptor *desc; - - struct usb_request req; - uint8_t *b_buf; - uint32_t b_len; - uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN); -}; - -struct mv_drv { - struct usb_gadget gadget; - struct usb_gadget_driver *driver; - struct ehci_ctrl *ctrl; - struct ept_queue_head *epts; - struct ept_queue_item *items[2 * NUM_ENDPOINTS]; - uint8_t *items_mem; - struct mv_ep ep[NUM_ENDPOINTS]; -}; - -struct ept_queue_head { - unsigned config; - unsigned current; /* read-only */ - - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved_0; - - unsigned char setup_data[8]; - - unsigned reserved_1; - unsigned reserved_2; - unsigned reserved_3; - unsigned reserved_4; -}; - -#define CONFIG_MAX_PKT(n) ((n) << 16) -#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */ -#define CONFIG_IOS (1 << 15) /* IRQ on setup */ - -struct ept_queue_item { - unsigned next; - unsigned info; - unsigned page0; - unsigned page1; - unsigned page2; - unsigned page3; - unsigned page4; - unsigned reserved; -}; - -#define TERMINATE 1 -#define INFO_BYTES(n) ((n) << 16) -#define INFO_IOC (1 << 15) -#define INFO_ACTIVE (1 << 7) -#define INFO_HALTED (1 << 6) -#define INFO_BUFFER_ERROR (1 << 5) -#define INFO_TX_ERROR (1 << 3) -#endif diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index f4ff5cd1b5c..e44ec88f71b 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -31,7 +31,7 @@ #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_MXC_GPIO -#define CONFIG_MV_UDC +#define CONFIG_CI_UDC #define CONFIG_USBD_HS #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h index a85eb1c3fc2..8cce34af763 100644 --- a/include/configs/sansa_fuze_plus.h +++ b/include/configs/sansa_fuze_plus.h @@ -56,7 +56,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h index 022bc95927b..8e6b3653644 100644 --- a/include/configs/xfi3.h +++ b/include/configs/xfi3.h @@ -55,7 +55,7 @@ #define CONFIG_EHCI_MXS_PORT0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_MV_UDC /* ChipIdea CI13xxx UDC */ +#define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */ #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_ETHER diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h new file mode 100644 index 00000000000..0dee50461e8 --- /dev/null +++ b/include/usb/ci_udc.h @@ -0,0 +1,14 @@ +/* + * Copyright 2011, Marvell Semiconductor Inc. + * Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __CI_UDC_H__ +#define __CI_UDC_H__ + +#define EP_MAX_PACKET_SIZE 0x200 +#define EP0_MAX_PACKET_SIZE 64 +#endif /* __CI_UDC_H__ */ diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h deleted file mode 100644 index f6c7b5e8987..00000000000 --- a/include/usb/mv_udc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright 2011, Marvell Semiconductor Inc. - * Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -#ifndef __MV_UDC_H__ -#define __MV_UDC_H__ - -#define EP_MAX_PACKET_SIZE 0x200 -#define EP0_MAX_PACKET_SIZE 64 -#endif /* __MV_UDC_H__ */ -- cgit v1.2.3 From c83a35f65250a8bdb519cb26680437e5c93d133d Mon Sep 17 00:00:00 2001 From: Novasys Ingenierie Date: Wed, 27 Nov 2013 09:03:01 +0100 Subject: fpga: zynq: Correct fpga load when buf is not aligned When ARCH_DMA_MINALIGN is greater than header size of the bit file, and buf is not aligned, new_buf address became greater then buf_start address and the load_word loop corrupts bit file data. A work around is to decrease new_buf of ARCH_DMA_MINALIGN, it might corrupt data before buf but permits to load correctly. Signed-off-by: Stany MARCEL Signed-off-by: Michal Simek --- drivers/fpga/zynqpl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers') diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 1effbadda90..15900c9ef26 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -187,6 +187,16 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) { u32 *new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN); + /* + * This might be dangerous but permits to flash if + * ARCH_DMA_MINALIGN is greater than header size + */ + if (new_buf > buf_start) { + debug("%s: Aligned buffer is after buffer start\n", + __func__); + new_buf -= ARCH_DMA_MINALIGN; + } + printf("%s: Align buffer at %x to %x(swap %d)\n", __func__, (u32)buf_start, (u32)new_buf, swap); -- cgit v1.2.3 From 819ca38fa70da85a14b4328d1511146e6c59eb32 Mon Sep 17 00:00:00 2001 From: Aaron Wu Date: Wed, 23 Nov 2011 11:23:56 +0800 Subject: blackfin: Initialize the EMAC VLAN with proper default value EMAC_VLANx regs is not properly initiallized in u-boot, once it's overwrite in the kernel when DSA enabled, hot reset will lead to bringing up EMAC fail in u-boot. Signed-off-by: Aaron Wu Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/mach-common/bits/emac.h | 3 +++ drivers/net/bfin_mac.c | 2 ++ 2 files changed, 5 insertions(+) (limited to 'drivers') diff --git a/arch/blackfin/include/asm/mach-common/bits/emac.h b/arch/blackfin/include/asm/mach-common/bits/emac.h index 7a43bbb1a39..4c9bc9dc571 100644 --- a/arch/blackfin/include/asm/mach-common/bits/emac.h +++ b/arch/blackfin/include/asm/mach-common/bits/emac.h @@ -217,4 +217,7 @@ #define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ #define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ +/*default value for EMAC_VLANx reg*/ +#define EMAC_VLANX_DEF_VAL 0xFFFF + #endif diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 0ffd59d4978..42e208cfb60 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -259,6 +259,8 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) *opmode = 0; bfin_write_EMAC_MMC_CTL(RSTC | CROLL); + bfin_write_EMAC_VLAN1(EMAC_VLANX_DEF_VAL); + bfin_write_EMAC_VLAN2(EMAC_VLANX_DEF_VAL); /* Initialize the TX DMA channel registers */ bfin_write_DMA2_X_COUNT(0); -- cgit v1.2.3 From 74cb708d5853854d28547b917d4b8a5588ee7324 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 13 Jan 2014 13:28:38 +0400 Subject: net/designware: add explicit reset of {tx|rx}_currdescnum Driver "init" function might be called multiple times. On every "init" Tx/Rx buffer descriptors are initialized: "descs_init" -> "{tx|rx}_descs_init". In its turn those init functions set MAC's "{tx|rx}desclistaddr" to point on the first buffer descriptor in the list. So CPU to start operation from the first buffer descriptor as well after every "init" we have to reset "{tx|rx}_currdescnum". Cc: Joe Hershberger Cc: Vipin Kumar Cc: Stefan Roese Cc: Mischa Jonker Signed-off-by: Alexey Brodkin --- drivers/net/designware.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 22155b4d949..186808943ab 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -52,6 +52,7 @@ static void tx_descs_init(struct eth_device *dev) desc_p->dmamac_next = &desc_table_p[0]; writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); + priv->tx_currdescnum = 0; } static void rx_descs_init(struct eth_device *dev) @@ -79,6 +80,7 @@ static void rx_descs_init(struct eth_device *dev) desc_p->dmamac_next = &desc_table_p[0]; writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); + priv->rx_currdescnum = 0; } static void descs_init(struct eth_device *dev) -- cgit v1.2.3 From 92a190aaab3536d695c51e0739f925910eb49889 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 22 Jan 2014 20:54:06 +0400 Subject: net/designware - switch driver to phylib usage With this change driver will benefit from existing phylib and thus custom phy functionality implemented in the driver will go away: * Instantiation of the driver is now much shorter - 2 parameters instead of 4. * Simplified phy management/functoinality in driver is replaced with rich functionality of phylib. * Support of custom phy initialization is now done with existing "board_phy_config". Note that after this change some previously used config options (driver-specific PHY configuration) will be obsolete and they are simply substituted with similar options of phylib. For example: * CONFIG_DW_AUTONEG - no need in this one. Autonegotiation is enabled by default. * CONFIG_DW_SEARCH_PHY - if one wants to specify attached phy explicitly CONFIG_PHY_ADDR board config option has to be used, otherwise automatically the first discovered on MDIO bus phy will be used I believe there's no need now in "doc/README.designware_eth" because user only needs to instantiate the driver with "designware_initialize" whose prototype exists in "include/netdev.h". Cc: Joe Hershberger Cc: Vipin Kumar Cc: Stefan Roese Cc: Mischa Jonker Cc: Shiraz Hashim Cc: Albert ARIBAUD Cc: Amit Virdi Cc: Sonic Zhang Signed-off-by: Alexey Brodkin --- board/bf609-ezkit/bf609-ezkit.c | 4 +- board/spear/spear300/spear300.c | 3 +- board/spear/spear310/spear310.c | 3 +- board/spear/spear320/spear320.c | 3 +- board/spear/spear600/spear600.c | 3 +- board/spear/x600/x600.c | 25 +-- doc/README.designware_eth | 25 --- drivers/net/designware.c | 460 +++++++++++++--------------------------- drivers/net/designware.h | 18 +- include/configs/bf609-ezkit.h | 3 +- include/configs/spear-common.h | 4 +- include/configs/spear6xx_evb.h | 3 + include/netdev.h | 2 +- 13 files changed, 177 insertions(+), 379 deletions(-) delete mode 100644 doc/README.designware_eth (limited to 'drivers') diff --git a/board/bf609-ezkit/bf609-ezkit.c b/board/bf609-ezkit/bf609-ezkit.c index cfc64fe51d6..43a43306bbc 100644 --- a/board/bf609-ezkit/bf609-ezkit.c +++ b/board/bf609-ezkit/bf609-ezkit.c @@ -41,12 +41,12 @@ int board_eth_init(bd_t *bis) if (CONFIG_DW_PORTS & 1) { static const unsigned short pins[] = P_RMII0; if (!peripheral_request_list(pins, "emac0")) - ret += designware_initialize(0, EMAC0_MACCFG, 1, 0); + ret += designware_initialize(EMAC0_MACCFG, 0); } if (CONFIG_DW_PORTS & 2) { static const unsigned short pins[] = P_RMII1; if (!peripheral_request_list(pins, "emac1")) - ret += designware_initialize(1, EMAC1_MACCFG, 1, 0); + ret += designware_initialize(EMAC1_MACCFG, 0); } return ret; diff --git a/board/spear/spear300/spear300.c b/board/spear/spear300/spear300.c index e25aba2f287..6b6bd9f29d5 100644 --- a/board/spear/spear300/spear300.c +++ b/board/spear/spear300/spear300.c @@ -53,8 +53,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/spear310/spear310.c b/board/spear/spear310/spear310.c index 70f9aa16eaa..a4c6a8edb0d 100644 --- a/board/spear/spear310/spear310.c +++ b/board/spear/spear310/spear310.c @@ -54,8 +54,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear320/spear320.c b/board/spear/spear320/spear320.c index f6b1fdd0e63..ab732a724c7 100644 --- a/board/spear/spear320/spear320.c +++ b/board/spear/spear320/spear320.c @@ -65,8 +65,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DESIGNWARE_ETH) u32 interface = PHY_INTERFACE_MODE_MII; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif #if defined(CONFIG_MACB) diff --git a/board/spear/spear600/spear600.c b/board/spear/spear600/spear600.c index e996a0e381e..8472002f749 100644 --- a/board/spear/spear600/spear600.c +++ b/board/spear/spear600/spear600.c @@ -51,8 +51,7 @@ int board_eth_init(bd_t *bis) #if defined(CONFIG_DW_AUTONEG) interface = PHY_INTERFACE_MODE_GMII; #endif - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_DW0_PHY, - interface) >= 0) + if (designware_initialize(CONFIG_SPEAR_ETHBASE, interface) >= 0) ret++; #endif return ret; diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c index 044d2049ef8..b8edfcd071f 100644 --- a/board/spear/x600/x600.c +++ b/board/spear/x600/x600.c @@ -67,31 +67,32 @@ void board_nand_init(void) fsmc_nand_init(nand); } -int designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) +int board_phy_config(struct phy_device *phydev) { /* Extended PHY control 1, select GMII */ - mii_write(dev, phy_addr, 23, 0x0020); + phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); /* Software reset necessary after GMII mode selction */ - dw_reset_phy(dev); + phy_reset(phydev); /* Enable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0001); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0001); /* 17e: Enhanced LED behavior, needs to be written twice */ - mii_write(dev, phy_addr, 17, 0x09ff); - mii_write(dev, phy_addr, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x09ff); /* 16e: Enhanced LED method select */ - mii_write(dev, phy_addr, 16, 0xe0ea); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0xe0ea); /* Disable extended page register access */ - mii_write(dev, phy_addr, 31, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 31, 0x0000); /* Enable clock output pin */ - mii_write(dev, phy_addr, 18, 0x0049); + phy_write(phydev, MDIO_DEVAD_NONE, 18, 0x0049); + + if (phydev->drv->config) + phydev->drv->config(phydev); return 0; } @@ -100,7 +101,7 @@ int board_eth_init(bd_t *bis) { int ret = 0; - if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + if (designware_initialize(CONFIG_SPEAR_ETHBASE, PHY_INTERFACE_MODE_GMII) >= 0) ret++; diff --git a/doc/README.designware_eth b/doc/README.designware_eth deleted file mode 100644 index 25ec6bd9699..00000000000 --- a/doc/README.designware_eth +++ /dev/null @@ -1,25 +0,0 @@ -This driver supports Designware Ethernet Controller provided by Synopsis. - -The driver is enabled by CONFIG_DESIGNWARE_ETH. - -The driver has been developed and tested on SPEAr platforms. By default, the -MDIO interface works at 100/Full. #defining the below options in board -configuration file changes this behavior. - -Call an subroutine from respective board/.../board.c -designware_initialize(u32 id, ulong base_addr, u32 phy_addr); - -The various options suported by the driver are -1. CONFIG_DW_ALTDESCRIPTOR - Define this to use the Alternate/Enhanced Descriptor configurations. -1. CONFIG_DW_AUTONEG - Define this to autonegotiate with the host before proceeding with mac - level configuration. This obviates the definitions of CONFIG_DW_SPEED10M - and CONFIG_DW_DUPLEXHALF. -2. CONFIG_DW_SPEED10M - Define this to change the default behavior from 100Mbps to 10Mbps. -3. CONFIG_DW_DUPLEXHALF - Define this to change the default behavior from Full Duplex to Half. -4. CONFIG_DW_SEARCH_PHY - Define this to search the phy address. This would overwrite the value - passed as 3rd arg from designware_initialize routine. diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 186808943ab..44c1e350ced 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -17,7 +17,75 @@ #include #include "designware.h" -static int configure_phy(struct eth_device *dev); +#if !defined(CONFIG_PHYLIB) +# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB" +#endif + +static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK); + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) + return readl(&mac_p->miidata); + udelay(10); + }; + + return -1; +} + +static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct eth_mac_regs *mac_p = bus->priv; + ulong start; + u16 miiaddr; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + writel(val, &mac_p->miidata); + miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | + ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; + + writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int dw_mdio_init(char *name, struct eth_mac_regs *mac_regs_p) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -1; + } + + bus->read = dw_mdio_read; + bus->write = dw_mdio_write; + sprintf(bus->name, name); + + bus->priv = (void *)mac_regs_p; + + return mdio_register(bus); +} static void tx_descs_init(struct eth_device *dev) { @@ -83,53 +151,59 @@ static void rx_descs_init(struct eth_device *dev) priv->rx_currdescnum = 0; } -static void descs_init(struct eth_device *dev) +static int dw_write_hwaddr(struct eth_device *dev) { - tx_descs_init(dev); - rx_descs_init(dev); + struct dw_eth_dev *priv = dev->priv; + struct eth_mac_regs *mac_p = priv->mac_regs_p; + u32 macid_lo, macid_hi; + u8 *mac_id = &dev->enetaddr[0]; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, &mac_p->macaddr0hi); + writel(macid_lo, &mac_p->macaddr0lo); + + return 0; } -static int mac_reset(struct eth_device *dev) +static void dw_adjust_link(struct eth_mac_regs *mac_p, + struct phy_device *phydev) { - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - struct eth_dma_regs *dma_p = priv->dma_regs_p; + u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; - ulong start; - int timeout = CONFIG_MACRESET_TIMEOUT; + if (!phydev->link) { + printf("%s: No link.\n", phydev->dev->name); + return; + } - writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); + if (phydev->speed != 1000) + conf |= MII_PORTSELECT; - if (priv->interface != PHY_INTERFACE_MODE_RGMII) - writel(MII_PORTSELECT, &mac_p->conf); + if (phydev->speed == 100) + conf |= FES_100; - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&dma_p->busmode) & DMAMAC_SRST)) - return 0; + if (phydev->duplex) + conf |= FULLDPLXMODE; - /* Try again after 10usec */ - udelay(10); - }; + writel(conf, &mac_p->conf); - return -1; + printf("Speed: %d, %s duplex%s\n", phydev->speed, + (phydev->duplex) ? "full" : "half", + (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); } -static int dw_write_hwaddr(struct eth_device *dev) +static void dw_eth_halt(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; - u32 macid_lo, macid_hi; - u8 *mac_id = &dev->enetaddr[0]; + struct eth_dma_regs *dma_p = priv->dma_regs_p; - macid_lo = mac_id[0] + (mac_id[1] << 8) + \ - (mac_id[2] << 16) + (mac_id[3] << 24); - macid_hi = mac_id[4] + (mac_id[5] << 8); + writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); + writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); - writel(macid_hi, &mac_p->macaddr0hi); - writel(macid_lo, &mac_p->macaddr0lo); - - return 0; + phy_shutdown(priv->phydev); } static int dw_eth_init(struct eth_device *dev, bd_t *bis) @@ -137,55 +211,43 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; - u32 conf; + unsigned int start; - if (priv->phy_configured != 1) - configure_phy(dev); + writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); - /* Print link status only once */ - if (!priv->link_printed) { - printf("ENET Speed is %d Mbps - %s duplex connection\n", - priv->speed, (priv->duplex == HALF) ? "HALF" : "FULL"); - priv->link_printed = 1; - } + start = get_timer(0); + while (readl(&dma_p->busmode) & DMAMAC_SRST) { + if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) + return -1; - /* Reset ethernet hardware */ - if (mac_reset(dev) < 0) - return -1; + mdelay(100); + }; - /* Resore the HW MAC address as it has been lost during MAC reset */ + /* Soft reset above clears HW address registers. + * So we have to set it here once again */ dw_write_hwaddr(dev); - writel(FIXEDBURST | PRIORXTX_41 | BURST_16, - &dma_p->busmode); - - writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | - TXSECONDFRAME, &dma_p->opmode); + rx_descs_init(dev); + tx_descs_init(dev); - conf = FRAMEBURSTENABLE | DISABLERXOWN; + writel(FIXEDBURST | PRIORXTX_41 | BURST_16, &dma_p->busmode); - if (priv->speed != 1000) - conf |= MII_PORTSELECT; + writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, + &dma_p->opmode); - if ((priv->interface != PHY_INTERFACE_MODE_MII) && - (priv->interface != PHY_INTERFACE_MODE_GMII)) { + writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); - if (priv->speed == 100) - conf |= FES_100; + /* Start up the PHY */ + if (phy_startup(priv->phydev)) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return -1; } - if (priv->duplex == FULL) - conf |= FULLDPLXMODE; - - writel(conf, &mac_p->conf); + dw_adjust_link(mac_p, priv->phydev); - descs_init(dev); - - /* - * Start/Enable xfer at dma as well as mac level - */ - writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); - writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); + if (!priv->phydev->link) + return -1; writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); @@ -267,251 +329,30 @@ static int dw_eth_recv(struct eth_device *dev) return length; } -static void dw_eth_halt(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - - mac_reset(dev); - priv->tx_currdescnum = priv->rx_currdescnum = 0; -} - -static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val) +static int dw_phy_init(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int timeout = CONFIG_MDIO_TIMEOUT; - - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK); - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - *val = readl(&mac_p->miidata); - return 0; - } + struct phy_device *phydev; + int mask = 0xffffffff; - /* Try again after 10usec */ - udelay(10); - }; - - return -1; -} - -static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val) -{ - struct dw_eth_dev *priv = dev->priv; - struct eth_mac_regs *mac_p = priv->mac_regs_p; - ulong start; - u32 miiaddr; - int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; - u16 value; - - writel(val, &mac_p->miidata); - miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \ - ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; - - writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); - - start = get_timer(0); - while (get_timer(start) < timeout) { - if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { - ret = 0; - break; - } - - /* Try again after 10usec */ - udelay(10); - }; - - /* Needed as a fix for ST-Phy */ - eth_mdio_read(dev, addr, reg, &value); - - return ret; -} - -#if defined(CONFIG_DW_SEARCH_PHY) -static int find_phy(struct eth_device *dev) -{ - int phy_addr = 0; - u16 ctrl, oldctrl; - - do { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - oldctrl = ctrl & BMCR_ANENABLE; - - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - ctrl &= BMCR_ANENABLE; - - if (ctrl == oldctrl) { - phy_addr++; - } else { - ctrl ^= BMCR_ANENABLE; - eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl); - - return phy_addr; - } - } while (phy_addr < 32); - - return -1; -} +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; #endif -static int dw_reset_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - u16 ctrl; - ulong start; - int timeout = CONFIG_PHYRESET_TIMEOUT; - u32 phy_addr = priv->address; - - eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET); - - start = get_timer(0); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl); - if (!(ctrl & BMCR_RESET)) - break; - - /* Try again after 10usec */ - udelay(10); - }; - - if (get_timer(start) >= CONFIG_PHYRESET_TIMEOUT) + phydev = phy_find_by_mask(priv->bus, mask, priv->interface); + if (!phydev) return -1; -#ifdef CONFIG_PHY_RESET_DELAY - udelay(CONFIG_PHY_RESET_DELAY); -#endif - return 0; -} + phydev->supported &= PHY_GBIT_FEATURES; + phydev->advertising = phydev->supported; -/* - * Add weak default function for board specific PHY configuration - */ -int __weak designware_board_phy_init(struct eth_device *dev, int phy_addr, - int (*mii_write)(struct eth_device *, u8, u8, u16), - int dw_reset_phy(struct eth_device *)) -{ - return 0; -} + priv->phydev = phydev; + phy_config(phydev); -static int configure_phy(struct eth_device *dev) -{ - struct dw_eth_dev *priv = dev->priv; - int phy_addr; - u16 bmcr; -#if defined(CONFIG_DW_AUTONEG) - u16 bmsr; - u32 timeout; - ulong start; -#endif - -#if defined(CONFIG_DW_SEARCH_PHY) - phy_addr = find_phy(dev); - if (phy_addr >= 0) - priv->address = phy_addr; - else - return -1; -#else - phy_addr = priv->address; -#endif - - /* - * Some boards need board specific PHY initialization. This is - * after the main driver init code but before the auto negotiation - * is run. - */ - if (designware_board_phy_init(dev, phy_addr, - eth_mdio_write, dw_reset_phy) < 0) - return -1; - - if (dw_reset_phy(dev) < 0) - return -1; - -#if defined(CONFIG_DW_AUTONEG) - /* Set Auto-Neg Advertisement capabilities to 10/100 half/full */ - eth_mdio_write(dev, phy_addr, MII_ADVERTISE, 0x1E1); - - bmcr = BMCR_ANENABLE | BMCR_ANRESTART; -#else - bmcr = BMCR_SPEED100 | BMCR_FULLDPLX; - -#if defined(CONFIG_DW_SPEED10M) - bmcr &= ~BMCR_SPEED100; -#endif -#if defined(CONFIG_DW_DUPLEXHALF) - bmcr &= ~BMCR_FULLDPLX; -#endif -#endif - if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0) - return -1; - - /* Read the phy status register and populate priv structure */ -#if defined(CONFIG_DW_AUTONEG) - timeout = CONFIG_AUTONEG_TIMEOUT; - start = get_timer(0); - puts("Waiting for PHY auto negotiation to complete"); - while (get_timer(start) < timeout) { - eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr); - if (bmsr & BMSR_ANEGCOMPLETE) { - priv->phy_configured = 1; - break; - } - - /* Print dot all 1s to show progress */ - if ((get_timer(start) % 1000) == 0) - putc('.'); - - /* Try again after 1msec */ - udelay(1000); - }; - - if (!(bmsr & BMSR_ANEGCOMPLETE)) - puts(" TIMEOUT!\n"); - else - puts(" done\n"); -#else - priv->phy_configured = 1; -#endif - - priv->speed = miiphy_speed(dev->name, phy_addr); - priv->duplex = miiphy_duplex(dev->name, phy_addr); - - return 0; -} - -#if defined(CONFIG_MII) -static int dw_mii_read(const char *devname, u8 addr, u8 reg, u16 *val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_read(dev, addr, reg, val); - - return 0; -} - -static int dw_mii_write(const char *devname, u8 addr, u8 reg, u16 val) -{ - struct eth_device *dev; - - dev = eth_get_dev_by_name(devname); - if (dev) - eth_mdio_write(dev, addr, reg, val); - - return 0; + return 1; } -#endif -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) +int designware_initialize(ulong base_addr, u32 interface) { struct eth_device *dev; struct dw_eth_dev *priv; @@ -533,19 +374,14 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) memset(dev, 0, sizeof(struct eth_device)); memset(priv, 0, sizeof(struct dw_eth_dev)); - sprintf(dev->name, "mii%d", id); + sprintf(dev->name, "dwmac.%lx", base_addr); dev->iobase = (int)base_addr; dev->priv = priv; - eth_getenv_enetaddr_by_index("eth", id, &dev->enetaddr[0]); - priv->dev = dev; priv->mac_regs_p = (struct eth_mac_regs *)base_addr; priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + DW_DMA_BASE_OFFSET); - priv->address = phy_addr; - priv->phy_configured = 0; - priv->interface = interface; dev->init = dw_eth_init; dev->send = dw_eth_send; @@ -555,8 +391,10 @@ int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface) eth_register(dev); -#if defined(CONFIG_MII) - miiphy_register(dev->name, dw_mii_read, dw_mii_write); -#endif - return 1; + priv->interface = interface; + + dw_mdio_init(dev->name, priv->mac_regs_p); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return dw_phy_init(dev); } diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 5440c9215fb..afeaccec19a 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -16,8 +16,6 @@ #define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ) #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ) struct eth_mac_regs { u32 conf; /* 0x00 */ @@ -217,14 +215,9 @@ struct dmamacdescr { #endif struct dw_eth_dev { - u32 address; u32 interface; - u32 speed; - u32 duplex; u32 tx_currdescnum; u32 rx_currdescnum; - u32 phy_configured; - u32 link_printed; struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM]; struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM]; @@ -236,15 +229,8 @@ struct dw_eth_dev { struct eth_dma_regs *dma_regs_p; struct eth_device *dev; + struct phy_device *phydev; + struct mii_dev *bus; }; -/* Speed specific definitions */ -#define SPEED_10M 1 -#define SPEED_100M 2 -#define SPEED_1000M 3 - -/* Duplex mode specific definitions */ -#define HALF_DUPLEX 1 -#define FULL_DUPLEX 2 - #endif diff --git a/include/configs/bf609-ezkit.h b/include/configs/bf609-ezkit.h index 1a43e1b433e..12192ffb5d7 100644 --- a/include/configs/bf609-ezkit.h +++ b/include/configs/bf609-ezkit.h @@ -72,12 +72,13 @@ #define CONFIG_NET_MULTI #define CONFIG_HOSTNAME "bf609-ezkit" #define CONFIG_DESIGNWARE_ETH +#define CONFIG_PHY_ADDR 1 #define CONFIG_DW_PORTS 1 -#define CONFIG_DW_AUTONEG #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_MII +#define CONFIG_PHYLIB /* i2c Settings */ #define CONFIG_BFIN_TWI_I2C diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 23f7ad77b61..e090a376d03 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -17,11 +17,9 @@ /* Ethernet driver configuration */ #define CONFIG_MII #define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_SEARCH_PHY -#define CONFIG_DW0_PHY 1 #define CONFIG_NET_MULTI +#define CONFIG_PHYLIB #define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ -#define CONFIG_DW_AUTONEG #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* USBD driver configuration */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h index 7f4dc5801c2..28dddcc5b93 100644 --- a/include/configs/spear6xx_evb.h +++ b/include/configs/spear6xx_evb.h @@ -37,6 +37,9 @@ #define CONFIG_SYS_FSMC_NAND_8BIT #define CONFIG_SYS_NAND_BASE 0xD2000000 +/* Ethernet PHY configuration */ +#define CONFIG_PHY_NATSEMI + /* Environment Settings */ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY diff --git a/include/netdev.h b/include/netdev.h index 47fa80d6fc4..37056291946 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -36,7 +36,7 @@ int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); -int designware_initialize(u32 id, ulong base_addr, u32 phy_addr, u32 interface); +int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); -- cgit v1.2.3 From 50b0df814b0f75c08a3d45a017016a75af3edb5d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Wed, 22 Jan 2014 20:49:09 +0400 Subject: net/designware: make driver compatible with data cache Up until now this driver only worked with data cache disabled. To make it work with enabled data cache following changes were required: * Flush Tx/Rx buffer descriptors their modification * Invalidate Tx/Rx buffer descriptors before reading its values * Flush cache for data passed from CPU to GMAC * Invalidate cache for data passed from GMAC to CPU Cc: Joe Hershberger Cc: Vipin Kumar Cc: Stefan Roese Cc: Mischa Jonker Cc: Shiraz Hashim Cc: Albert ARIBAUD Cc: Amit Virdi Cc: Sonic Zhang Signed-off-by: Alexey Brodkin --- drivers/net/designware.c | 53 +++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 50 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 44c1e350ced..c45593bcc09 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -119,6 +119,11 @@ static void tx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Tx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->tx_mac_descrtable, + (unsigned int)priv->tx_mac_descrtable + + sizeof(priv->tx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); priv->tx_currdescnum = 0; } @@ -132,6 +137,15 @@ static void rx_descs_init(struct eth_device *dev) struct dmamacdescr *desc_p; u32 idx; + /* Before passing buffers to GMAC we need to make sure zeros + * written there right after "priv" structure allocation were + * flushed into RAM. + * Otherwise there's a chance to get some of them flushed in RAM when + * GMAC is already pushing data to RAM via DMA. This way incoming from + * GMAC data will be corrupted. */ + flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs + + RX_TOTAL_BUFSIZE); + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { desc_p = &desc_table_p[idx]; desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE]; @@ -147,6 +161,11 @@ static void rx_descs_init(struct eth_device *dev) /* Correcting the last pointer of the chain */ desc_p->dmamac_next = &desc_table_p[0]; + /* Flush all Rx buffer descriptors at once */ + flush_dcache_range((unsigned int)priv->rx_mac_descrtable, + (unsigned int)priv->rx_mac_descrtable + + sizeof(priv->rx_mac_descrtable)); + writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); priv->rx_currdescnum = 0; } @@ -261,6 +280,11 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) u32 desc_num = priv->tx_currdescnum; struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; + /* Invalidate only "status" field for the following check */ + invalidate_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Check if the descriptor is owned by CPU */ if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { printf("CPU not owner of tx frame\n"); @@ -269,6 +293,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) memcpy((void *)desc_p->dmamac_addr, packet, length); + /* Flush data to be sent */ + flush_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + length); + #if defined(CONFIG_DW_ALTDESCRIPTOR) desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \ @@ -284,6 +312,10 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; #endif + /* Flush modified buffer descriptor */ + flush_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + sizeof(struct dmamacdescr)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_TX_DESCR_NUM) desc_num = 0; @@ -299,18 +331,28 @@ static int dw_eth_send(struct eth_device *dev, void *packet, int length) static int dw_eth_recv(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; - u32 desc_num = priv->rx_currdescnum; + u32 status, desc_num = priv->rx_currdescnum; struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; - - u32 status = desc_p->txrx_status; int length = 0; + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range((unsigned long)desc_p, + (unsigned long)desc_p + + sizeof(struct dmamacdescr)); + + status = desc_p->txrx_status; + /* Check if the owner is the CPU */ if (!(status & DESC_RXSTS_OWNBYDMA)) { length = (status & DESC_RXSTS_FRMLENMSK) >> \ DESC_RXSTS_FRMLENSHFT; + /* Invalidate received data */ + invalidate_dcache_range((unsigned long)desc_p->dmamac_addr, + (unsigned long)desc_p->dmamac_addr + + length); + NetReceive(desc_p->dmamac_addr, length); /* @@ -319,6 +361,11 @@ static int dw_eth_recv(struct eth_device *dev) */ desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; + /* Flush only status field - others weren't changed */ + flush_dcache_range((unsigned long)&desc_p->txrx_status, + (unsigned long)&desc_p->txrx_status + + sizeof(desc_p->txrx_status)); + /* Test the wrap-around condition. */ if (++desc_num >= CONFIG_RX_DESCR_NUM) desc_num = 0; -- cgit v1.2.3 From def816a2ba87c2a3507536e8cb226f0f85bdae2c Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Thu, 30 Jan 2014 16:11:12 -0700 Subject: mmc: set rca to 1 for MMC cards U-Boot currently sets MMC cards' RCA register to 0. This value is reserved according to the specification. Use a value of 1 instead, just like the Linux kernel. Signed-off-by: Stephen Warren Acked-by: Jaehoon Chung Signed-off-by: Pantelis Antoniou --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c6a1c23fbf1..7efc2bedbe1 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -430,7 +430,7 @@ int mmc_complete_op_cond(struct mmc *mmc) mmc->ocr = cmd.response[0]; mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); - mmc->rca = 0; + mmc->rca = 1; return 0; } -- cgit v1.2.3 From d3e016cc28684cd32d826a9414a0e89ccf80861a Mon Sep 17 00:00:00 2001 From: Rajeshwari S Shinde Date: Wed, 5 Feb 2014 10:48:15 +0530 Subject: MMC: DWMMC: Correct the CLKDIV register value This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde Acked-by: Jaehoon Chung Signed-off-by: Pantelis Antoniou --- arch/arm/include/asm/arch-exynos/dwmmc.h | 4 ++++ drivers/mmc/dw_mmc.c | 2 +- drivers/mmc/exynos_dw_mmc.c | 17 +++++++++++++++-- include/dwmmc.h | 2 +- 4 files changed, 21 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h index 09d739dfca9..a7ca12c477e 100644 --- a/arch/arm/include/asm/arch-exynos/dwmmc.h +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -23,6 +23,10 @@ #define MPSCTRL_ENCRYPTION (0x1<<1) #define MPSCTRL_VALID (0x1<<0) +/* CLKSEL Register */ +#define DWMCI_DIVRATIO_BIT 24 +#define DWMCI_DIVRATIO_MASK 0x7 + #ifdef CONFIG_OF_CONTROL int exynos_dwmmc_init(const void *blob); #endif diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 4cec5aaa604..d45c15cfa4e 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -237,7 +237,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) * host->bus_hz should be set from user. */ if (host->get_mmc_clk) - sclk = host->get_mmc_clk(host->dev_index); + sclk = host->get_mmc_clk(host); else if (host->bus_hz) sclk = host->bus_hz; else { diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index b3e5c5e5e09..de8cdcc42b3 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -29,9 +29,22 @@ static void exynos_dwmci_clksel(struct dwmci_host *host) dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); } -unsigned int exynos_dwmci_get_clk(int dev_index) +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) { - return get_mmc_clk(dev_index); + unsigned long sclk; + int8_t clk_div; + + /* + * Since SDCLKIN is divided inside controller by the DIVRATIO + * value set in the CLKSEL register, we need to use the same output + * clock value to calculate the CLKDIV value. + * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1) + */ + clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT) + & DWMCI_DIVRATIO_MASK) + 1; + sclk = get_mmc_clk(host->dev_index); + + return sclk / clk_div; } static void exynos_dwmci_board_init(struct dwmci_host *host) diff --git a/include/dwmmc.h b/include/dwmmc.h index a02dd67c137..b64155851d6 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -142,7 +142,7 @@ struct dwmci_host { void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); - unsigned int (*get_mmc_clk)(int dev_index); + unsigned int (*get_mmc_clk)(struct dwmci_host *host); }; struct dwmci_idmac { -- cgit v1.2.3 From f9ec45d1d9d83db9a6539f78d51ff257373f3c4f Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Wed, 22 Jan 2014 09:17:09 +0100 Subject: mmc: Enabled quirk SDHCI_QUIRK_BROKEN_R1B As per the below commit "mmc: sdhci: add the quirk for broken r1b response" (sha1: 3a6383207be3f71b39004e64464a6e99290b16fa) need to add quirk SDHCI_QUIRK_BROKEN_R1B, when the response type is R1b. Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek Acked-by: Jagannadha Sutradharudu Teki Signed-off-by: Pantelis Antoniou --- drivers/mmc/zynq_sdhci.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 610bef5cbae..72a272f2ba0 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -23,7 +23,8 @@ int zynq_sdhci_init(u32 regbase) host->name = "zynq_sdhci"; host->ioaddr = (void *)regbase; - host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD; + host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD | + SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); host->host_caps = MMC_MODE_HC; -- cgit v1.2.3 From 792970b0a344d905848fb98564ed469786af11b7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:21 -0500 Subject: cmd_mmc.c: Add 'partconf' command to mmc Add a partconf sub-command to the mmc command to allow for setting the boot_ack, boot_partition and partition_access fields of PARTITION_CONFIG (formerly BOOT_CONFIG, EXT_CSD[179]). Part of this requires changing the check for 'part' from an strncmp to a strcmp, like the rest of the sub-commands. Cc: Andy Fleming Cc: Pantelis Antoniou Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 30 +++++++++++++++++++++++++++++- drivers/mmc/mmc.c | 21 +++++++++++++++++++++ include/mmc.h | 2 ++ 3 files changed, 52 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a322063cf6a..5842e85de9f 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -195,7 +195,7 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; else return 0; - } else if (strncmp(argv[1], "part", 4) == 0) { + } else if (strcmp(argv[1], "part") == 0) { block_dev_desc_t *mmc_dev; struct mmc *mmc; @@ -311,7 +311,33 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* acknowledge to be sent during boot operation */ return boot_part_access(mmc, 1, part_num, access); + } else if (strcmp(argv[1], "partconf") == 0) { + int dev; + struct mmc *mmc; + u8 ack, part_num, access; + + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + ack = simple_strtoul(argv[3], NULL, 10); + part_num = simple_strtoul(argv[4], NULL, 10); + access = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + if (IS_SD(mmc)) { + puts("PARTITION_CONFIG only exists on eMMC\n"); + return 1; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_part_conf(mmc, ack, part_num, access); } else if (strcmp(argv[1], "bootpart-resize") == 0) { int dev; struct mmc *mmc; @@ -451,6 +477,8 @@ U_BOOT_CMD( " - Enable boot_part for booting and disable access to boot_part\n" "mmc bootpart-resize \n" " - Change sizes of boot and RPMB partitions of specified device\n" + "mmc partconf dev boot_ack boot_partition partition_access\n" + " - Change the bits of the PARTITION_CONFIG field of the specified device\n" #endif "mmc setdsr - set DSR register value\n" ); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 7efc2bedbe1..907c4185ade 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1505,4 +1505,25 @@ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) } return 0; } + +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); + + if (err) + return err; + return 0; +} #endif diff --git a/include/mmc.h b/include/mmc.h index e1060b9ff27..7e026da4446 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -312,6 +312,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); /* Function to send commands to open/close the specified boot partition */ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the PARTITION_CONFIG field of EXT_CSD */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /** * Start device initialization and return immediately; it does not block on -- cgit v1.2.3 From 5a99b9de1a845bf254292ae4730633e6ca8a29c7 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:22 -0500 Subject: cmd_mmc.c: Add bootbus mmc sub-command Add a bootbus sub-command to the mmc command to allow for setting the boot_bus_width, reset_boot_bus_width and boot_mode fields of BOOT_BUS_WIDTH (EXT_CSD[177]). Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 29 +++++++++++++++++++++++++++++ drivers/mmc/mmc.c | 21 +++++++++++++++++++++ include/mmc.h | 5 +++++ 3 files changed, 55 insertions(+) (limited to 'drivers') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 5842e85de9f..a028149d906 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -338,6 +338,33 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* acknowledge to be sent during boot operation */ return mmc_set_part_conf(mmc, ack, part_num, access); + } else if (strcmp(argv[1], "bootbus") == 0) { + int dev; + struct mmc *mmc; + u8 width, reset, mode; + + if (argc == 6) { + dev = simple_strtoul(argv[2], NULL, 10); + width = simple_strtoul(argv[3], NULL, 10); + reset = simple_strtoul(argv[4], NULL, 10); + mode = simple_strtoul(argv[5], NULL, 10); + } else { + return CMD_RET_USAGE; + } + + mmc = find_mmc_device(dev); + if (!mmc) { + printf("no mmc device at slot %x\n", dev); + return 1; + } + + if (IS_SD(mmc)) { + puts("BOOT_BUS_WIDTH only exists on eMMC\n"); + return 1; + } + + /* acknowledge to be sent during boot operation */ + return mmc_set_boot_bus_width(mmc, width, reset, mode); } else if (strcmp(argv[1], "bootpart-resize") == 0) { int dev; struct mmc *mmc; @@ -475,6 +502,8 @@ U_BOOT_CMD( " - Enable boot_part for booting and enable R/W access of boot_part\n" "mmc close \n" " - Enable boot_part for booting and disable access to boot_part\n" + "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" + " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize \n" " - Change sizes of boot and RPMB partitions of specified device\n" "mmc partconf dev boot_ack boot_partition partition_access\n" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 907c4185ade..37719d26558 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1506,6 +1506,27 @@ int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) return 0; } +/* + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. + * + * Returns 0 on success. + */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); + + if (err) + return err; + return 0; +} + /* * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and diff --git a/include/mmc.h b/include/mmc.h index 7e026da4446..3594286d42c 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -187,6 +187,9 @@ #define EXT_CSD_BOOT_PART_NUM(x) (x << 3) #define EXT_CSD_PARTITION_ACCESS(x) (x << 0) +#define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3) +#define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2) +#define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x) #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) @@ -314,6 +317,8 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); +/* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /** * Start device initialization and return immediately; it does not block on -- cgit v1.2.3 From 614b2bf1c9bf80dbad24f5e5ce1d115bf24a831d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 5 Feb 2014 10:24:23 -0500 Subject: cmd_mmc.c: Drop open/close mmc sub-commands The open and close mmc sub-commands implement a hard-coded set of values specific to the SMDK5250 platform. Remove these commands as what they did can be done instead with a series of mmc dev / bootpart / bootbus commands instead now. Cc: Amar Cc: Minkyu Kang Acked-by: Jaehoon Chung Signed-off-by: Tom Rini Signed-off-by: Pantelis Antoniou --- common/cmd_mmc.c | 72 ------------------------------------------------------- drivers/mmc/mmc.c | 65 ------------------------------------------------- include/mmc.h | 2 -- 3 files changed, 139 deletions(-) (limited to 'drivers') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index a028149d906..2d519270602 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -131,36 +131,6 @@ U_BOOT_CMD( "- display info of the current MMC device" ); -#ifdef CONFIG_SUPPORT_EMMC_BOOT -static int boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - err = mmc_boot_part_access(mmc, ack, part_num, access); - - if ((err == 0) && (access != 0)) { - printf("\t\t\t!!!Notice!!!\n"); - - printf("!You must close EMMC boot Partition"); - printf("after all images are written\n"); - - printf("!EMMC boot partition has continuity"); - printf("at image writing time.\n"); - - printf("!So, do not close the boot partition"); - printf("before all images are written.\n"); - return 0; - } else if ((err == 0) && (access == 0)) - return 0; - else if ((err != 0) && (access != 0)) { - printf("EMMC boot partition-%d OPEN Failed.\n", part_num); - return 1; - } else { - printf("EMMC boot partition-%d CLOSE Failed.\n", part_num); - return 1; - } -} -#endif - static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { enum mmc_state state; @@ -273,44 +243,6 @@ static int do_mmcops(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; #ifdef CONFIG_SUPPORT_EMMC_BOOT - } else if ((strcmp(argv[1], "open") == 0) || - (strcmp(argv[1], "close") == 0)) { - int dev; - struct mmc *mmc; - u8 part_num, access = 0; - - if (argc == 4) { - dev = simple_strtoul(argv[2], NULL, 10); - part_num = simple_strtoul(argv[3], NULL, 10); - } else { - return CMD_RET_USAGE; - } - - mmc = find_mmc_device(dev); - if (!mmc) { - printf("no mmc device at slot %x\n", dev); - return 1; - } - - if (IS_SD(mmc)) { - printf("SD device cannot be opened/closed\n"); - return 1; - } - - if ((part_num <= 0) || (part_num > MMC_NUM_BOOT_PARTITION)) { - printf("Invalid boot partition number:\n"); - printf("Boot partition number cannot be <= 0\n"); - printf("EMMC44 supports only 2 boot partitions\n"); - return 1; - } - - if (strcmp(argv[1], "open") == 0) - access = part_num; /* enable R/W access to boot part*/ - else - access = 0; /* No access to boot partition */ - - /* acknowledge to be sent during boot operation */ - return boot_part_access(mmc, 1, part_num, access); } else if (strcmp(argv[1], "partconf") == 0) { int dev; struct mmc *mmc; @@ -498,10 +430,6 @@ U_BOOT_CMD( "mmc dev [dev] [part] - show or set current mmc device [partition]\n" "mmc list - lists available devices\n" #ifdef CONFIG_SUPPORT_EMMC_BOOT - "mmc open \n" - " - Enable boot_part for booting and enable R/W access of boot_part\n" - "mmc close \n" - " - Enable boot_part for booting and disable access to boot_part\n" "mmc bootbus dev boot_bus_width reset_boot_bus_width boot_mode\n" " - Set the BOOT_BUS_WIDTH field of the specified device\n" "mmc bootpart-resize \n" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 37719d26558..8ab0bc948f5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1441,71 +1441,6 @@ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, return 0; } -/* - * This function shall form and send the commands to open / close the - * boot partition specified by user. - * - * Input Parameters: - * ack: 0x0 - No boot acknowledge sent (default) - * 0x1 - Boot acknowledge sent during boot operation - * part_num: User selects boot data that will be sent to master - * 0x0 - Device not boot enabled (default) - * 0x1 - Boot partition 1 enabled for boot - * 0x2 - Boot partition 2 enabled for boot - * access: User selects partitions to access - * 0x0 : No access to boot partition (default) - * 0x1 : R/W boot partition 1 - * 0x2 : R/W boot partition 2 - * 0x3 : R/W Replay Protected Memory Block (RPMB) - * - * Returns 0 on success. - */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - struct mmc_cmd cmd; - - /* Boot ack enable, boot partition enable , boot partition access */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_PART_CONF << 16) | - ((EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - if (access) { - debug("mmc boot partition#%d open fail:Error1 = %d\n", - part_num, err); - } else { - debug("mmc boot partition#%d close fail:Error = %d\n", - part_num, err); - } - return err; - } - - if (access) { - /* 4bit transfer mode at booting time. */ - cmd.cmdidx = MMC_CMD_SWITCH; - cmd.resp_type = MMC_RSP_R1b; - - cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | - (EXT_CSD_BOOT_BUS_WIDTH << 16) | - ((1 << 0) << 8); - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc boot partition#%d open fail:Error2 = %d\n", - part_num, err); - return err; - } - } - return 0; -} - /* * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH diff --git a/include/mmc.h b/include/mmc.h index 3594286d42c..e95a2376d20 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -313,8 +313,6 @@ int mmc_set_dsr(struct mmc *mmc, u16 val); /* Function to change the size of boot partition and rpmb partitions */ int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, unsigned long rpmbsize); -/* Function to send commands to open/close the specified boot partition */ -int mmc_boot_part_access(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the PARTITION_CONFIG field of EXT_CSD */ int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access); /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */ -- cgit v1.2.3 From 22a240c32c1340183fce12867ae5f8736b92a638 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Fri, 13 Dec 2013 10:35:11 +0400 Subject: serial/serial_arc - add driver for ARC UART Driver for non-standard on-chip UART, instantiated in the ARC (Synopsys) FPGA Boards such as ARCAngel4/ML50x Signed-off-by: Alexey Brodkin Cc: Mischa Jonker Cc: Francois Bedard Cc: Tom Rini Cc: Wolfgang Denk Cc: Stefano Babic --- drivers/serial/Makefile | 1 + drivers/serial/serial.c | 2 + drivers/serial/serial_arc.c | 105 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/serial/serial_arc.c (limited to 'drivers') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 6b4cadefdbd..5eb46014495 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o +obj-$(CONFIG_ARC_SERIAL) += serial_arc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index df2b84aaafd..05cb3698219 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(arm_dcc_initialize); serial_initfunc(mxs_auart_initialize); +serial_initfunc(arc_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -253,6 +254,7 @@ void serial_initialize(void) sh_serial_initialize(); arm_dcc_initialize(); mxs_auart_initialize(); + arc_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c new file mode 100644 index 00000000000..e63d25d7949 --- /dev/null +++ b/drivers/serial/serial_arc.c @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct arc_serial_regs { + unsigned int id0; + unsigned int id1; + unsigned int id2; + unsigned int id3; + unsigned int data; + unsigned int status; + unsigned int baudl; + unsigned int baudh; +}; + +/* Bit definitions of STATUS register */ +#define UART_RXEMPTY (1 << 5) +#define UART_OVERFLOW_ERR (1 << 1) +#define UART_TXEMPTY (1 << 7) + +struct arc_serial_regs *regs; + +static void arc_serial_setbrg(void) +{ + int arc_console_baud; + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; + writel(arc_console_baud & 0xff, ®s->baudl); + writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); +} + +static int arc_serial_init(void) +{ + regs = (struct arc_serial_regs *)CONFIG_ARC_UART_BASE; + serial_setbrg(); + return 0; +} + +static void arc_serial_putc(const char c) +{ + if (c == '\n') + arc_serial_putc('\r'); + + while (!(readl(®s->status) & UART_TXEMPTY)) + ; + + writel(c, ®s->data); +} + +static int arc_serial_tstc(void) +{ + return !(readl(®s->status) & UART_RXEMPTY); +} + +static int arc_serial_getc(void) +{ + while (!arc_serial_tstc()) + ; + + /* Check for overflow errors */ + if (readl(®s->status) & UART_OVERFLOW_ERR) + return 0; + + return readl(®s->data) & 0xFF; +} + +static void arc_serial_puts(const char *s) +{ + while (*s) + arc_serial_putc(*s++); +} + +static struct serial_device arc_serial_drv = { + .name = "arc_serial", + .start = arc_serial_init, + .stop = NULL, + .setbrg = arc_serial_setbrg, + .putc = arc_serial_putc, + .puts = arc_serial_puts, + .getc = arc_serial_getc, + .tstc = arc_serial_tstc, +}; + +void arc_serial_initialize(void) +{ + serial_register(&arc_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &arc_serial_drv; +} -- cgit v1.2.3 From 18a6bcc139548f8018494ff60519948fa53e2141 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Thu, 16 Jan 2014 15:01:49 +0800 Subject: serial: opencores_yanu: Fix build error Fix build error due to missing include of serial.h and a trivial typo. Signed-off-by: Axel Lin Signed-off-by: Thomas Chou --- drivers/serial/opencores_yanu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 8de2eca2ac7..80e9ae53bc9 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -8,6 +8,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -154,7 +155,7 @@ static int oc_serial_tstc(void) ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); } -statoc int oc_serial_getc(void) +static int oc_serial_getc(void) { while (serial_tstc() == 0) WATCHDOG_RESET (); -- cgit v1.2.3 From 2d61e1bed2205b5ebce6b732693c30d01590f9fc Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Thu, 16 Jan 2014 15:03:52 +0800 Subject: serial: opencores_yanu: Avoid duplicate oc_serial_setbrg() implementation The implementation of oc_serial_setbrg() for CONFIG_SYS_NIOS_FIXEDBAUD and !CONFIG_SYS_NIOS_FIXEDBAUD are very similar. Add a baudrate variable and set it to either CONFIG_BAUDRATE or gd->baudrate. Then we can unify the code for both cases. Signed-off-by: Axel Lin Signed-off-by: Thomas Chou --- drivers/serial/opencores_yanu.c | 49 ++++++++--------------------------------- 1 file changed, 9 insertions(+), 40 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/opencores_yanu.c b/drivers/serial/opencores_yanu.c index 80e9ae53bc9..d4ed60c3030 100644 --- a/drivers/serial/opencores_yanu.c +++ b/drivers/serial/opencores_yanu.c @@ -18,62 +18,34 @@ DECLARE_GLOBAL_DATA_PTR; static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; -#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) - -/* Everything's already setup for fixed-baud PTF assignment*/ - static void oc_serial_setbrg(void) { int n, k; const unsigned max_uns = 0xFFFFFFFF; unsigned best_n, best_m, baud; + unsigned baudrate; - /* compute best N and M couple */ - best_n = YANU_MAX_PRESCALER_N; - for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { - if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - (unsigned)CONFIG_BAUDRATE) { - best_n = n; - break; - } - } - for (k = 0;; k++) { - if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) - break; - } - best_m = - ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / - ((unsigned)CONFIG_SYS_CLK_FREQ >> k); - - baud = best_m + best_n * YANU_BAUDE; - writel(baud, &uart->baud); - - return; -} - +#if defined(CONFIG_SYS_NIOS_FIXEDBAUD) + /* Everything's already setup for fixed-baud PTF assignment */ + baudrate = CONFIG_BAUDRATE; #else - -static void oc_serial_setbrg(void) -{ - int n, k; - const unsigned max_uns = 0xFFFFFFFF; - unsigned best_n, best_m, baud; - + baudrate = gd->baudrate; +#endif /* compute best N and M couple */ best_n = YANU_MAX_PRESCALER_N; for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= - gd->baudrate) { + baudrate) { best_n = n; break; } } for (k = 0;; k++) { - if (gd->baudrate <= (max_uns >> (15+n-k))) + if (baudrate <= (max_uns >> (15+n-k))) break; } best_m = - (gd->baudrate * (1 << (15 + n - k))) / + (baudrate * (1 << (15 + n - k))) / ((unsigned)CONFIG_SYS_CLK_FREQ >> k); baud = best_m + best_n * YANU_BAUDE; @@ -82,9 +54,6 @@ static void oc_serial_setbrg(void) return; } - -#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */ - static int oc_serial_init(void) { unsigned action,control; -- cgit v1.2.3 From 999c39a45f115a17f6b894e3a9cd894c598fb2e0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 22 Jan 2014 09:48:55 +0100 Subject: spi: xilinx: Move timeout calculation out of the loop Timeout calculation should be out of the data loop. This patch increase spi bandwidth for 30%. Signed-off-by: Michal Simek Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/xilinx_spi.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c index 5ac01846e44..56d99d17c7d 100644 --- a/drivers/spi/xilinx_spi.c +++ b/drivers/spi/xilinx_spi.c @@ -149,6 +149,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const unsigned char *txp = dout; unsigned char *rxp = din; unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */ + unsigned global_timeout; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, slave->bus, slave->cs, bitlen, bytes, flags); @@ -176,11 +177,12 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); - while (bytes--) { - unsigned timeout = /* at least 1usec or greater, leftover 1 */ - xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : + /* at least 1usec or greater, leftover 1 */ + global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 : (XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1; + while (bytes--) { + unsigned timeout = global_timeout; /* get Tx element from data out buffer and count up */ unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL; debug("%s: tx:%x ", __func__, d); -- cgit v1.2.3 From 5d584ccec106f8919ce39562e062d822770513b7 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 17 Feb 2014 17:33:17 +0100 Subject: spi: spi-mxc: implement clk control for ECSPI to fix SPI_MODE_3 SPI_MODE_3 requires clk high when inactive. The SCLK_CTL field of the config reg was not configured in case of CPOL. Fix configuration so that SPI_MODE_3 which uses CPOL configures the clk line to be high in inactive state. Signed-off-by: Markus Niebel Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/mxc_spi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index 95dd03f7b3f..f3f029d634a 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -115,7 +115,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, { u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); s32 reg_ctrl, reg_config; - u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, pre_div = 0, post_div = 0; + u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; + u32 pre_div = 0, post_div = 0; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; if (max_hz == 0) { @@ -164,8 +165,10 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, if (mode & SPI_CS_HIGH) ss_pol = 1; - if (mode & SPI_CPOL) + if (mode & SPI_CPOL) { sclkpol = 1; + sclkctl = 1; + } if (mode & SPI_CPHA) sclkpha = 1; @@ -180,6 +183,8 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, (ss_pol << (cs + MXC_CSPICON_SSPOL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) | (sclkpol << (cs + MXC_CSPICON_POL)); + reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) | + (sclkctl << (cs + MXC_CSPICON_CTL)); reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) | (sclkpha << (cs + MXC_CSPICON_PHA)); -- cgit v1.2.3 From 570533b820fb4cc2bbe34c44001cc4c371617e37 Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Sat, 21 Dec 2013 12:50:09 +0530 Subject: spi: ti_qspi: Add AM43xx specifics changes Add AM43xx specific changes. Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/ti_qspi.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 5a5b482769b..56662509120 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -11,6 +11,8 @@ #include #include #include +#include +#include /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 @@ -39,7 +41,8 @@ #define MM_SWITCH 0x01 #define MEM_CS 0x100 #define MEM_CS_UNSELECT 0xfffff0ff -#define MMAP_START_ADDR 0x5c000000 +#define MMAP_START_ADDR_DRA 0x5c000000 +#define MMAP_START_ADDR_AM43x 0x30000000 #define CORE_CTRL_IO 0x4a002558 #define QSPI_CMD_READ (0x3 << 0) @@ -99,7 +102,11 @@ static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave) struct spi_slave *slave = &qslave->slave; u32 memval = 0; - slave->memory_map = (void *)MMAP_START_ADDR; +#ifdef CONFIG_DRA7XX + slave->memory_map = (void *)MMAP_START_ADDR_DRA; +#else + slave->memory_map = (void *)MMAP_START_ADDR_AM43x; +#endif memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES | QSPI_SETUP0_NUM_D_BYTES_NO_BITS | @@ -165,6 +172,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, { struct ti_qspi_slave *qslave; +#ifdef CONFIG_AM43XX + gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio"); + gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1); +#endif + qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs); if (!qslave) { printf("SPI_error: Fail to allocate ti_qspi_slave\n"); @@ -229,7 +241,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, const uchar *txp = dout; uchar *rxp = din; uint status; - int timeout, val; + int timeout; + +#ifdef CONFIG_DRA7XX + int val; +#endif debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n", slave->bus, slave->cs, bitlen, words, flags); @@ -237,15 +253,19 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, /* Setup mmap flags */ if (flags & SPI_XFER_MMAP) { writel(MM_SWITCH, &qslave->base->memswitch); +#ifdef CONFIG_DRA7XX val = readl(CORE_CTRL_IO); val |= MEM_CS; writel(val, CORE_CTRL_IO); +#endif return 0; } else if (flags & SPI_XFER_MMAP_END) { writel(~MM_SWITCH, &qslave->base->memswitch); +#ifdef CONFIG_DRA7XX val = readl(CORE_CTRL_IO); val &= MEM_CS_UNSELECT; writel(val, CORE_CTRL_IO); +#endif return 0; } -- cgit v1.2.3 From bb7cd0ddf978b96c40a4889608c9b9ea16127afa Mon Sep 17 00:00:00 2001 From: Sourav Poddar Date: Sat, 21 Dec 2013 12:50:10 +0530 Subject: spi: ti_qspi: Add delay before xfer for am43xx Without this delay, write/read is failing. Looks like, the WIP always remain set and hence a timeout occurs leading to the error. Without this patch, device does not get probed also. Here is the log. U-Boot# U-Boot# U-Boot# U-Boot# sf probe 0 SF: Unsupported flash IDs: manuf ff, jedec ffff, ext_jedec ffff Failed to initialize SPI flash at 0:0 U-Boot# sf probe 0 While with this patch, log is U-Boot# sf probe 0 SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB, mapped at 30000000 U-Boot# sf erase 0 0x80000 SF: 524288 bytes @ 0x0 Erased: OK U-Boot# mw 81000000 0xdededede 0x40000 U-Boot# sf write 81000000 0 0x40000 SF: 262144 bytes @ 0x0 Written: OK U-Boot# sf read 82000000 0 0x40000 SF: 262144 bytes @ 0x0 Read: OK U-Boot# md 0x82000000 Signed-off-by: Sourav Poddar Reviewed-by: Jagannadha Sutradharudu Teki --- drivers/spi/ti_qspi.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers') diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 56662509120..dfa5d0ca216 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -285,6 +285,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd |= QSPI_3_PIN; qslave->cmd |= 0xfff; +/* FIXME: This delay is required for successfull + * completion of read/write/erase. Once its root + * caused, it will be remove from the driver. + */ +#ifdef CONFIG_AM43XX + udelay(100); +#endif while (words--) { if (txp) { debug("tx cmd %08x dc %08x data %02x\n", -- cgit v1.2.3 From bf83495040fcf273eba534f7c2c0cb2325d2240c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 19 Dec 2013 23:38:58 +0530 Subject: zynq: serial: Simplify serial driver initialization Define both serial uarts in the driver and return default uart based on board configuration. - Move baseaddresses to hardware.h - Define default baudrate and clock values Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/hardware.h | 2 ++ drivers/serial/serial_zynq.c | 34 ++++++++++++++++++------------- include/configs/zynq-common.h | 19 ++--------------- 3 files changed, 24 insertions(+), 31 deletions(-) (limited to 'drivers') diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 1fe044801cf..d0fba642839 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -7,6 +7,8 @@ #ifndef _ASM_ARCH_HARDWARE_H #define _ASM_ARCH_HARDWARE_H +#define ZYNQ_SERIAL_BASEADDR0 0xE0000000 +#define ZYNQ_SERIAL_BASEADDR1 0xE0001000 #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000 #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000 #define ZYNQ_SCU_BASEADDR 0xF8F00000 diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index ff28f3c8019..9a1ee00e9c3 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -10,6 +10,7 @@ #include #include #include +#include #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ @@ -33,13 +34,23 @@ struct uart_zynq { }; static struct uart_zynq *uart_zynq_ports[2] = { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 - [0] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR0, + [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, + [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +}; + +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE #endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 - [1] = (struct uart_zynq *)CONFIG_ZYNQ_SERIAL_BASEADDR1, +#if !defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) +# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE +#endif + +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0) +# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 +#endif +#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1) +# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 #endif -}; struct uart_zynq_params { u32 baudrate; @@ -47,14 +58,10 @@ struct uart_zynq_params { }; static struct uart_zynq_params uart_zynq_ports_param[2] = { -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE0) && defined(CONFIG_ZYNQ_SERIAL_CLOCK0) [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, -#endif -#if defined(CONFIG_ZYNQ_SERIAL_BAUDRATE1) && defined(CONFIG_ZYNQ_SERIAL_CLOCK1) [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, -#endif }; /* Set up the baud rate in gd struct */ @@ -186,20 +193,19 @@ struct serial_device uart_zynq_serial1_device = __weak struct serial_device *default_serial_console(void) { +#if defined(CONFIG_ZYNQ_SERIAL_UART0) if (uart_zynq_ports[0]) return &uart_zynq_serial0_device; +#endif +#if defined(CONFIG_ZYNQ_SERIAL_UART1) if (uart_zynq_ports[1]) return &uart_zynq_serial1_device; - +#endif return NULL; } void zynq_serial_initalize(void) { -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0 serial_register(&uart_zynq_serial0_device); -#endif -#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1 serial_register(&uart_zynq_serial1_device); -#endif } diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index bafa01b2e34..b5bf7acadf2 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -35,27 +35,12 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* Zynq Serial driver */ -#ifdef CONFIG_ZYNQ_SERIAL_UART0 -# define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0000000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 -#endif - -#ifdef CONFIG_ZYNQ_SERIAL_UART1 -# define CONFIG_ZYNQ_SERIAL_BASEADDR1 0xE0001000 -# define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE -# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 -#endif - -#if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1) -# define CONFIG_ZYNQ_SERIAL -#endif - /* DCC driver */ #if defined(CONFIG_ZYNQ_DCC) # define CONFIG_ARM_DCC # define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */ +#else +# define CONFIG_ZYNQ_SERIAL #endif /* Ethernet driver */ -- cgit v1.2.3 From 1cd46ed2d30a931a66400635f158b14861f2d3b4 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:39:00 -0800 Subject: net: zynq_gem: Move RCLK details out of driver The GEM driver should not need to know about Zynq specific details of RCLK related registers and bitfields in the SLCR. Move those details to the slcr driver. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 6 +++--- arch/arm/include/asm/arch-zynq/sys_proto.h | 2 +- drivers/net/zynq_gem.c | 7 ++----- 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index b4c11c324c0..6710d92c344 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -50,7 +50,7 @@ void zynq_slcr_cpu_reset(void) } /* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) +void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) { zynq_slcr_unlock(); @@ -63,12 +63,12 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk) /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ writel(clk, &slcr_base->gem1_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem1_rclk_ctrl); + writel(1, &slcr_base->gem1_rclk_ctrl); } else { /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ writel(clk, &slcr_base->gem0_clk_ctrl); /* Configure GEM_RCLK_CTRL */ - writel(rclk, &slcr_base->gem0_rclk_ctrl); + writel(1, &slcr_base->gem0_rclk_ctrl); } udelay(100000); out: diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index 8f925af8a41..a485d790a32 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -10,7 +10,7 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 rclk, u32 clk); +extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 381bca459e1..2eb9e7d1ef3 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -270,7 +270,7 @@ static int zynq_gem_setup_mac(struct eth_device *dev) static int zynq_gem_init(struct eth_device *dev, bd_t * bis) { - u32 i, rclk, clk = 0; + u32 i, clk = 0; struct phy_device *phydev; const u32 stat_size = (sizeof(struct zynq_gem_regs) - offsetof(struct zynq_gem_regs, stat)) / 4; @@ -348,17 +348,14 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); - rclk = (0 << 4) | (1 << 0); clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; case SPEED_100: clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); - rclk = 1 << 0; clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; case SPEED_10: - rclk = 1 << 0; /* FIXME untested */ clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); break; @@ -367,7 +364,7 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) zynq_slcr_gem_clk_setup(dev->iobase != - ZYNQ_GEM_BASEADDR0, rclk, clk); + ZYNQ_GEM_BASEADDR0, clk); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); -- cgit v1.2.3 From 97598fcf10eba577622f3387eaecd43dd710da0d Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:39:01 -0800 Subject: net: zynq_gem: Calculate clock dividers dynamically Remove hard coded clock divider setting and use the Zynq clock framework to dynamically calculate appropriate dividers at run time. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- arch/arm/cpu/armv7/zynq/slcr.c | 13 ++++++++----- arch/arm/include/asm/arch-zynq/sys_proto.h | 2 +- drivers/net/zynq_gem.c | 17 +++++++++++------ 3 files changed, 20 insertions(+), 12 deletions(-) (limited to 'drivers') diff --git a/arch/arm/cpu/armv7/zynq/slcr.c b/arch/arm/cpu/armv7/zynq/slcr.c index 6710d92c344..d7c18823322 100644 --- a/arch/arm/cpu/armv7/zynq/slcr.c +++ b/arch/arm/cpu/armv7/zynq/slcr.c @@ -8,6 +8,7 @@ #include #include #include +#include #define SLCR_LOCK_MAGIC 0x767B #define SLCR_UNLOCK_MAGIC 0xDF0D @@ -50,8 +51,10 @@ void zynq_slcr_cpu_reset(void) } /* Setup clk for network */ -void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) +void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate) { + int ret; + zynq_slcr_unlock(); if (gem_id > 1) { @@ -59,14 +62,14 @@ void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk) goto out; } + ret = zynq_clk_set_rate(gem0_clk + gem_id, clk_rate); + if (ret) + goto out; + if (gem_id) { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem1_clk_ctrl); /* Configure GEM_RCLK_CTRL */ writel(1, &slcr_base->gem1_rclk_ctrl); } else { - /* Set divisors for appropriate frequency in GEM_CLK_CTRL */ - writel(clk, &slcr_base->gem0_clk_ctrl); /* Configure GEM_RCLK_CTRL */ writel(1, &slcr_base->gem0_rclk_ctrl); } diff --git a/arch/arm/include/asm/arch-zynq/sys_proto.h b/arch/arm/include/asm/arch-zynq/sys_proto.h index a485d790a32..0a2ba058f26 100644 --- a/arch/arm/include/asm/arch-zynq/sys_proto.h +++ b/arch/arm/include/asm/arch-zynq/sys_proto.h @@ -10,7 +10,7 @@ extern void zynq_slcr_lock(void); extern void zynq_slcr_unlock(void); extern void zynq_slcr_cpu_reset(void); -extern void zynq_slcr_gem_clk_setup(u32 gem_id, u32 clk); +extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate); extern void zynq_slcr_devcfg_disable(void); extern void zynq_slcr_devcfg_enable(void); extern u32 zynq_slcr_get_boot_mode(void); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 2eb9e7d1ef3..6d4001b0173 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -90,6 +90,11 @@ #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000 +/* Clock frequencies for different speeds */ +#define ZYNQ_GEM_FREQUENCY_10 2500000UL +#define ZYNQ_GEM_FREQUENCY_100 25000000UL +#define ZYNQ_GEM_FREQUENCY_1000 125000000UL + /* Device registers */ struct zynq_gem_regs { u32 nwctrl; /* Network Control reg */ @@ -270,7 +275,8 @@ static int zynq_gem_setup_mac(struct eth_device *dev) static int zynq_gem_init(struct eth_device *dev, bd_t * bis) { - u32 i, clk = 0; + u32 i; + unsigned long clk_rate = 0; struct phy_device *phydev; const u32 stat_size = (sizeof(struct zynq_gem_regs) - offsetof(struct zynq_gem_regs, stat)) / 4; @@ -348,23 +354,22 @@ static int zynq_gem_init(struct eth_device *dev, bd_t * bis) case SPEED_1000: writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); - clk = (1 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000, ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100); - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_100; break; case SPEED_10: - /* FIXME untested */ - clk = (5 << 20) | (8 << 8) | (0 << 4) | (1 << 0); + clk_rate = ZYNQ_GEM_FREQUENCY_10; break; } /* Change the rclk and clk only not using EMIO interface */ if (!priv->emio) zynq_slcr_gem_clk_setup(dev->iobase != - ZYNQ_GEM_BASEADDR0, clk); + ZYNQ_GEM_BASEADDR0, clk_rate); setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); -- cgit v1.2.3 From 19605e2e038eb7266c74c4aba6a4d6c9f33db797 Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Thu, 21 Nov 2013 13:38:55 -0800 Subject: serial_zynq: Migrate to Zynq clock framework Remove hard coded frequencies and use Zynq's clock framework to obtain the UART clock frequency. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- drivers/serial/serial_zynq.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 9a1ee00e9c3..22c6bf099cf 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ @@ -45,23 +46,13 @@ static struct uart_zynq *uart_zynq_ports[2] = { # define CONFIG_ZYNQ_SERIAL_BAUDRATE1 CONFIG_BAUDRATE #endif -#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK0) -# define CONFIG_ZYNQ_SERIAL_CLOCK0 50000000 -#endif -#if !defined(CONFIG_ZYNQ_SERIAL_CLOCK1) -# define CONFIG_ZYNQ_SERIAL_CLOCK1 50000000 -#endif - struct uart_zynq_params { u32 baudrate; - u32 clock; }; static struct uart_zynq_params uart_zynq_ports_param[2] = { [0].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE0, - [0].clock = CONFIG_ZYNQ_SERIAL_CLOCK0, [1].baudrate = CONFIG_ZYNQ_SERIAL_BAUDRATE1, - [1].clock = CONFIG_ZYNQ_SERIAL_CLOCK1, }; /* Set up the baud rate in gd struct */ @@ -71,7 +62,7 @@ static void uart_zynq_serial_setbrg(const int port) unsigned int calc_bauderror, bdiv, bgen; unsigned long calc_baud = 0; unsigned long baud = uart_zynq_ports_param[port].baudrate; - unsigned long clock = uart_zynq_ports_param[port].clock; + unsigned long clock = get_uart_clk(port); struct uart_zynq *regs = uart_zynq_ports[port]; /* master clock -- cgit v1.2.3 From 9137d19bdd321b810275f2e967e3a39165a4e8de Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 30 Jan 2014 11:02:13 +0100 Subject: net, phy: atheros ar803x bug commit 626ee1e3 "phylib: update atheros ar803x phy" leads in failing ethernet on the pxm2 board. Calling genphy_config() instead of ar8021_config(), which seems for ar8021 phys not ar803x phys, make it working again. Signed-off-by: Heiko Schocher Cc: Shengzhou Liu Cc: Joe Hershberger --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 32c2ab9944e..994500b688b 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -52,7 +52,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8021_config, + .config = genphy_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; -- cgit v1.2.3 From 9e4140329ee9a787d0f96ac2829d618d47f7973f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 4 Feb 2014 17:24:24 +0900 Subject: kbuild: change out-of-tree build This commit changes the working directory where the build process occurs. Before this commit, build process occurred under the source tree for both in-tree and out-of-tree build. That's why we needed to add $(obj) prefix to all generated files in makefiles like follows: $(obj)u-boot.bin: $(obj)u-boot Here, $(obj) is empty for in-tree build, whereas it points to the output directory for out-of-tree build. And our old build system changes the current working directory with "make -C " syntax when descending into the sub-directories. On the other hand, Kbuild uses a different idea to handle out-of-tree build and directory descending. The build process of Kbuild always occurs under the output tree. When "O=dir/to/store/output/files" is given, the build system changes the current working directory to that directory and restarts the make. Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=" syntax for descending into sub-directories. (We can write it like "make $(obj)=" with a shorthand.) This means the current working directory is always the top of the output directory. Signed-off-by: Masahiro Yamada Tested-by: Gerhard Sittig --- MAKEALL | 6 +- Makefile | 569 ++++++++++++++------------ arch/arm/cpu/arm1136/config.mk | 2 +- arch/arm/cpu/arm926ejs/config.mk | 2 +- arch/arm/cpu/arm926ejs/davinci/config.mk | 2 +- arch/arm/cpu/armv7/am33xx/config.mk | 2 +- arch/arm/cpu/armv7/config.mk | 2 +- arch/arm/cpu/armv7/omap3/config.mk | 2 +- arch/arm/cpu/armv7/omap4/config.mk | 2 +- arch/arm/cpu/armv7/omap5/config.mk | 2 +- arch/arm/cpu/armv7/socfpga/config.mk | 2 +- arch/blackfin/config.mk | 10 +- arch/blackfin/cpu/Makefile | 8 +- arch/mips/cpu/mips32/config.mk | 2 +- arch/mips/cpu/mips64/config.mk | 2 +- arch/mips/cpu/xburst/config.mk | 2 +- arch/nds32/config.mk | 2 +- arch/powerpc/lib/Makefile | 4 +- arch/sandbox/cpu/Makefile | 4 +- arch/sparc/config.mk | 3 +- arch/x86/lib/Makefile | 2 +- board/ait/cam_enc_4xx/config.mk | 2 +- board/avionic-design/medcom-wide/Makefile | 2 +- board/avionic-design/plutux/Makefile | 2 +- board/avionic-design/tec-ng/Makefile | 2 +- board/avionic-design/tec/Makefile | 2 +- board/compal/paz00/Makefile | 2 +- board/compulab/trimslice/Makefile | 2 +- board/cray/L1/Makefile | 8 +- board/h2200/Makefile | 2 +- board/matrix_vision/mvblm7/Makefile | 4 +- board/matrix_vision/mvsmr/Makefile | 2 +- board/nvidia/common/Makefile | 2 +- board/pcs440ep/config.mk | 2 +- board/samsung/origen/Makefile | 2 +- common/Makefile | 9 +- config.mk | 42 +- doc/DocBook/Makefile | 6 +- drivers/bios_emulator/Makefile | 2 +- dts/Makefile | 6 +- examples/api/Makefile | 16 +- examples/standalone/Makefile | 14 +- fs/ubifs/Makefile | 2 +- lib/Makefile | 2 +- mkconfig | 2 +- nand_spl/board/amcc/acadia/Makefile | 30 +- nand_spl/board/amcc/bamboo/Makefile | 30 +- nand_spl/board/amcc/canyonlands/Makefile | 30 +- nand_spl/board/amcc/kilauea/Makefile | 28 +- nand_spl/board/amcc/sequoia/Makefile | 32 +- nand_spl/board/freescale/mpc8315erdb/Makefile | 30 +- nand_spl/board/freescale/mpc8536ds/Makefile | 42 +- nand_spl/board/freescale/mpc8569mds/Makefile | 42 +- nand_spl/board/freescale/mpc8572ds/Makefile | 42 +- nand_spl/board/freescale/p1023rds/Makefile | 42 +- nand_spl/board/freescale/p1_p2_rdb/Makefile | 42 +- nand_spl/board/sheldon/simpc8313/Makefile | 30 +- post/lib_powerpc/fpu/Makefile | 2 +- rules.mk | 19 +- scripts/Kbuild.include | 4 +- scripts/Makefile.build | 57 ++- scripts/Makefile.host.tmp | 18 +- spl/Makefile | 49 ++- tools/Makefile | 18 +- 64 files changed, 612 insertions(+), 744 deletions(-) (limited to 'drivers') diff --git a/MAKEALL b/MAKEALL index 54b0d893a6b..d7ad51dc440 100755 --- a/MAKEALL +++ b/MAKEALL @@ -674,8 +674,6 @@ build_target() { output_dir="${OUTPUT_PREFIX}" fi - export BUILD_DIR="${output_dir}" - target_arch=$(get_target_arch ${target}) eval cross_toolchain=\$CROSS_COMPILE_`echo $target_arch | tr '[:lower:]' '[:upper:]'` if [ "${cross_toolchain}" ] ; then @@ -686,6 +684,10 @@ build_target() { MAKE=make fi + if [ "${output_dir}" != "." ] ; then + MAKE="${MAKE} O=${output_dir}" + fi + ${MAKE} distclean >/dev/null ${MAKE} -s ${target}_config diff --git a/Makefile b/Makefile index b24b425cb94..1409c8bf398 100644 --- a/Makefile +++ b/Makefile @@ -14,8 +14,8 @@ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION) endif -TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h -VERSION_FILE = $(obj)include/generated/version_autogenerated.h +TIMESTAMP_FILE = include/generated/timestamp_autogenerated.h +VERSION_FILE = include/generated/version_autogenerated.h HOSTARCH := $(shell uname -m | \ sed -e s/i.86/x86/ \ @@ -43,32 +43,82 @@ else XECHO = : endif -######################################################################### -# -# U-boot build supports generating object files in a separate external -# directory. Two use cases are supported: -# -# 1) Add O= to the make command line -# 'make O=/tmp/build all' -# -# 2) Set environment variable BUILD_DIR to point to the desired location -# 'export BUILD_DIR=/tmp/build' -# 'make' -# -# The second approach can also be used with a MAKEALL script -# 'export BUILD_DIR=/tmp/build' -# './MAKEALL' +# kbuild supports saving output files in a separate directory. +# To locate output files in a separate directory two syntaxes are supported. +# In both cases the working directory must be the root of the kernel src. +# 1) O= +# Use "make O=dir/to/store/output/files/" # -# Command line 'O=' setting overrides BUILD_DIR environment variable. -# -# When none of the above methods is used the local build is performed and -# the object files are placed in the source directory. +# 2) Set KBUILD_OUTPUT +# Set the environment variable KBUILD_OUTPUT to point to the directory +# where the output files shall be placed. +# export KBUILD_OUTPUT=dir/to/store/output/files/ +# make # +# The O= assignment takes precedence over the KBUILD_OUTPUT environment +# variable. + + +# KBUILD_SRC is set on invocation of make in OBJ directory +# KBUILD_SRC is not intended to be used by the regular user (for now) +ifeq ($(KBUILD_SRC),) +# OK, Make called in directory where kernel src resides +# Do we want to locate output files in a separate directory? ifeq ("$(origin O)", "command line") -BUILD_DIR := $(O) + KBUILD_OUTPUT := $(O) +endif + +ifeq ("$(origin W)", "command line") + export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W) endif +# That's our default target when none is given on the command line +PHONY := _all +_all: + +# Cancel implicit rules on top Makefile +$(CURDIR)/Makefile Makefile: ; + +ifneq ($(KBUILD_OUTPUT),) +# Invoke a second make in the output directory, passing relevant variables +# check that the output directory actually exists +saved-output := $(KBUILD_OUTPUT) +KBUILD_OUTPUT := $(shell cd $(KBUILD_OUTPUT) && /bin/pwd) +$(if $(KBUILD_OUTPUT),, \ + $(error output directory "$(saved-output)" does not exist)) + +PHONY += $(MAKECMDGOALS) sub-make + +$(filter-out _all sub-make $(CURDIR)/Makefile, $(MAKECMDGOALS)) _all: sub-make + @: + +sub-make: FORCE + $(if $(KBUILD_VERBOSE:1=),@)$(MAKE) -C $(KBUILD_OUTPUT) \ + KBUILD_SRC=$(CURDIR) \ + KBUILD_EXTMOD="$(KBUILD_EXTMOD)" -f $(CURDIR)/Makefile \ + $(filter-out _all sub-make,$(MAKECMDGOALS)) + +# Leave processing to above invocation of make +skip-makefile := 1 +endif # ifneq ($(KBUILD_OUTPUT),) +endif # ifeq ($(KBUILD_SRC),) + +# We process the rest of the Makefile if this is the final invocation of make +ifeq ($(skip-makefile),) + +PHONY += all +_all: all + +srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR)) +objtree := $(CURDIR) +src := $(srctree) +obj := $(objtree) + +VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD)) + +export srctree objtree VPATH + # Call a source code checker (by default, "sparse") as part of the # C compilation. # @@ -87,41 +137,16 @@ ifndef CHECKSRC endif export CHECKSRC -ifneq ($(BUILD_DIR),) -saved-output := $(BUILD_DIR) - -# Attempt to create a output directory. -$(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) - -# Verify if it was successful. -BUILD_DIR := $(shell cd $(BUILD_DIR) && /bin/pwd) -$(if $(BUILD_DIR),,$(error output directory "$(saved-output)" does not exist)) -endif # ifneq ($(BUILD_DIR),) - -OBJTREE := $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR)) +OBJTREE := $(objtree) SPLTREE := $(OBJTREE)/spl TPLTREE := $(OBJTREE)/tpl -SRCTREE := $(CURDIR) -srctree := $(SRCTREE) +SRCTREE := $(srctree) TOPDIR := $(SRCTREE) -LNDIR := $(OBJTREE) -export TOPDIR SRCTREE srctree OBJTREE SPLTREE TPLTREE +export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE MKCONFIG := $(SRCTREE)/mkconfig export MKCONFIG -# $(obj) and (src) are defined in config.mk but here in main Makefile -# we also need them before config.mk is included which is the case for -# some targets like unconfig, clean, clobber, distclean, etc. -ifneq ($(OBJTREE),$(SRCTREE)) -obj := $(OBJTREE)/ -src := $(SRCTREE)/ -else -obj := -src := -endif -export obj src - # Make sure CDPATH settings don't interfere unexport CDPATH @@ -136,14 +161,14 @@ SUBDIRS = $(SUBDIR_TOOLS) .PHONY : $(SUBDIRS) $(VERSION_FILE) $(TIMESTAMP_FILE) -ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) +ifeq (include/config.mk,$(wildcard include/config.mk)) # Include autoconf.mk before config.mk so that the config options are available # to all top level build files. We need the dummy all: target to prevent the # dependency target in autoconf.mk.dep from being the default. all: -sinclude $(obj)include/autoconf.mk.dep -sinclude $(obj)include/autoconf.mk +sinclude include/autoconf.mk.dep +sinclude include/autoconf.mk SUBDIR_EXAMPLES-y := examples/standalone SUBDIR_EXAMPLES-$(CONFIG_API) += examples/api @@ -152,7 +177,7 @@ SUBDIRS += $(SUBDIR_EXAMPLES-y) endif # load ARCH, BOARD, and CPU configuration -include $(obj)include/config.mk +include include/config.mk export ARCH CPU BOARD VENDOR SOC # set default to nothing for native builds @@ -197,6 +222,9 @@ HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") endif +# Look for make include files relative to root of kernel src +MAKEFLAGS += --include-dir=$(srctree) + # We need some generic definitions (do not try to remake the file). $(srctree)/scripts/Kbuild.include: ; include $(srctree)/scripts/Kbuild.include @@ -287,7 +315,7 @@ endif export CONFIG_SYS_TEXT_BASE -LDFLAGS_u-boot += -T $(obj)u-boot.lds $(LDFLAGS_FINAL) +LDFLAGS_u-boot += -T u-boot.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SYS_TEXT_BASE),) LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE) endif @@ -350,9 +378,9 @@ head-y := $(CPUDIR)/start.o head-$(CONFIG_4xx) += arch/powerpc/cpu/ppc4xx/resetvec.o head-$(CONFIG_MPC85xx) += arch/powerpc/cpu/mpc85xx/resetvec.o -OBJS := $(addprefix $(obj),$(head-y)) +OBJS := $(head-y) -HAVE_VENDOR_COMMON_LIB = $(if $(wildcard board/$(VENDOR)/common/Makefile),y,n) +HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(srctree)/board/$(VENDOR)/common/Makefile),y,n) LIBS-y += lib/ LIBS-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/ @@ -412,7 +440,7 @@ LIBS-$(CONFIG_PPC) += arch/powerpc/cpu/ LIBS-y += board/$(BOARDDIR)/ LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) -LIBS := $(addprefix $(obj),$(sort $(LIBS-y))) +LIBS := $(sort $(LIBS-y)) .PHONY : $(LIBS) # Add GCC lib @@ -437,9 +465,6 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -__OBJS := $(subst $(obj),,$(OBJS)) -__LIBS := $(subst $(obj),,$(LIBS)) - ######################################################################### ######################################################################### @@ -464,66 +489,66 @@ ifneq ($(CONFIG_STATIC_RELA),) DO_STATIC_RELA = \ start=$$($(NM) $(1) | grep __rel_dyn_start | cut -f 1 -d ' '); \ end=$$($(NM) $(1) | grep __rel_dyn_end | cut -f 1 -d ' '); \ - $(obj)tools/relocate-rela $(2) $(3) $$start $$end + tools/relocate-rela $(2) $(3) $$start $$end else DO_STATIC_RELA = endif # Always append ALL so that arch config.mk's can add custom ones -ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map - -ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin -ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin -ALL-$(CONFIG_RAMBOOT_PBL) += $(obj)u-boot.pbl -ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin -ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.img -ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin -ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin +ALL-y += u-boot.srec u-boot.bin System.map + +ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin +ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin +ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl +ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img +ALL-$(CONFIG_TPL) += tpl/u-boot-tpl.bin +ALL-$(CONFIG_OF_SEPARATE) += u-boot.dtb u-boot-dtb.bin ifneq ($(CONFIG_SPL_TARGET),) -ALL-$(CONFIG_SPL) += $(obj)$(CONFIG_SPL_TARGET:"%"=%) +ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%) endif -ALL-$(CONFIG_REMAKE_ELF) += $(obj)u-boot.elf +ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf # enable combined SPL/u-boot/dtb rules for tegra ifneq ($(CONFIG_TEGRA),) ifeq ($(CONFIG_SPL),y) ifeq ($(CONFIG_OF_SEPARATE),y) -ALL-y += $(obj)u-boot-dtb-tegra.bin +ALL-y += u-boot-dtb-tegra.bin else -ALL-y += $(obj)u-boot-nodtb-tegra.bin +ALL-y += u-boot-nodtb-tegra.bin endif endif endif all: $(ALL-y) $(SUBDIR_EXAMPLES-y) -$(obj)u-boot.dtb: checkdtc $(obj)u-boot - $(MAKE) $(build) dts binary - mv $(obj)dts/dt.dtb $@ +u-boot.dtb: checkdtc u-boot + $(MAKE) $(build)=dts binary + mv dts/dt.dtb $@ -$(obj)u-boot-dtb.bin: $(obj)u-boot.bin $(obj)u-boot.dtb +u-boot-dtb.bin: u-boot.bin u-boot.dtb cat $^ >$@ -$(obj)u-boot.hex: $(obj)u-boot +u-boot.hex: u-boot $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -$(obj)u-boot.srec: $(obj)u-boot +u-boot.srec: u-boot $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -$(obj)u-boot.bin: $(obj)u-boot +u-boot.bin: u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE)) $(BOARD_SIZE_CHECK) -$(obj)u-boot.ldr: $(obj)u-boot +u-boot.ldr: u-boot $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) $(BOARD_SIZE_CHECK) -$(obj)u-boot.ldr.hex: $(obj)u-boot.ldr +u-boot.ldr.hex: u-boot.ldr $(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@ -I binary -$(obj)u-boot.ldr.srec: $(obj)u-boot.ldr +u-boot.ldr.srec: u-boot.ldr $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ -I binary # @@ -534,79 +559,78 @@ ifndef CONFIG_SYS_UBOOT_START CONFIG_SYS_UBOOT_START := 0 endif -$(obj)u-boot.img: $(obj)u-boot.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ +u-boot.img: u-boot.bin + tools/mkimage -A $(ARCH) -T firmware -C none \ -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \ -e $(CONFIG_SYS_UBOOT_START) \ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \ sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ -$(obj)u-boot.imx: $(obj)u-boot.bin depend - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx +u-boot.imx: u-boot.bin depend + $(MAKE) $(build)=arch/arm/imx-common $(objtree)/u-boot.imx -$(obj)u-boot.kwb: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ +u-boot.kwb: u-boot.bin + tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ -$(obj)u-boot.pbl: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \ +u-boot.pbl: u-boot.bin + tools/mkimage -n $(CONFIG_SYS_FSL_PBL_RCW) \ -R $(CONFIG_SYS_FSL_PBL_PBI) -T pblimage \ -d $< $@ -$(obj)u-boot.sha1: $(obj)u-boot.bin - $(obj)tools/ubsha1 $(obj)u-boot.bin +u-boot.sha1: u-boot.bin + tools/ubsha1 u-boot.bin -$(obj)u-boot.dis: $(obj)u-boot +u-boot.dis: u-boot $(OBJDUMP) -d $< > $@ # $@ is output, $(1) and $(2) are inputs, $(3) is padded intermediate, # $(4) is pad-to SPL_PAD_APPEND = \ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(4) -I binary -O binary \ - $(1) $(obj)$(3); \ - cat $(obj)$(3) $(2) > $@; \ - rm $(obj)$(3) + $(1) $(3); \ + cat $(3) $(2) > $@; \ + rm $(3) ifdef CONFIG_TPL -SPL_PAYLOAD := $(obj)tpl/u-boot-with-tpl.bin +SPL_PAYLOAD := tpl/u-boot-with-tpl.bin else -SPL_PAYLOAD := $(obj)u-boot.bin +SPL_PAYLOAD := u-boot.bin endif -$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(SPL_PAYLOAD) +u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) $(call SPL_PAD_APPEND,$<,$(SPL_PAYLOAD),spl/u-boot-spl-pad.bin,$(CONFIG_SPL_PAD_TO)) -$(obj)tpl/u-boot-with-tpl.bin: $(obj)tpl/u-boot-tpl.bin $(obj)u-boot.bin - $(call SPL_PAD_APPEND,$<,$(obj)u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO)) +tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin + $(call SPL_PAD_APPEND,$<,u-boot.bin,tpl/u-boot-tpl-pad.bin,$(CONFIG_TPL_PAD_TO)) -$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \ +u-boot-with-spl.imx: spl/u-boot-spl.bin u-boot.bin + $(MAKE) $(build)=arch/arm/imx-common \ $(OBJTREE)/u-boot-with-spl.imx -$(obj)u-boot-with-nand-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common \ +u-boot-with-nand-spl.imx: spl/u-boot-spl.bin u-boot.bin + $(MAKE) $(build)=arch/arm/imx-common \ $(OBJTREE)/u-boot-with-nand-spl.imx -$(obj)u-boot.ubl: $(obj)u-boot-with-spl.bin - $(obj)tools/mkimage -n $(UBL_CONFIG) -T ublimage \ - -e $(CONFIG_SYS_TEXT_BASE) -d $< $(obj)u-boot.ubl +u-boot.ubl: u-boot-with-spl.bin + tools/mkimage -n $(UBL_CONFIG) -T ublimage \ + -e $(CONFIG_SYS_TEXT_BASE) -d $< u-boot.ubl -$(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - $(obj)tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(CONFIG_AIS_CONFIG_FILE),"/dev/null") \ +u-boot.ais: spl/u-boot-spl.bin u-boot.img + tools/mkimage -s -n $(if $(CONFIG_AIS_CONFIG_FILE),$(srctree)/$(CONFIG_AIS_CONFIG_FILE:"%"=%),"/dev/null") \ -T aisimage \ -e $(CONFIG_SPL_TEXT_BASE) \ - -d $(obj)spl/u-boot-spl.bin \ - $(obj)spl/u-boot-spl.ais + -d spl/u-boot-spl.bin \ + spl/u-boot-spl.ais $(OBJCOPY) ${OBJCFLAGS} -I binary \ --pad-to=$(CONFIG_SPL_MAX_SIZE) -O binary \ - $(obj)spl/u-boot-spl.ais $(obj)spl/u-boot-spl-pad.ais - cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \ - $(obj)u-boot.ais + spl/u-boot-spl.ais spl/u-boot-spl-pad.ais + cat spl/u-boot-spl-pad.ais u-boot.img > u-boot.ais -$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin - $(MAKE) $(build) $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb +u-boot.sb: u-boot.bin spl/u-boot-spl.bin + $(MAKE) $(build)=$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. # Both images are created using mkimage (crc etc), so that the ROM @@ -614,124 +638,123 @@ $(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin # SPL image (with mkimage header) and not the binary. Otherwise the resulting image # which is loaded/copied by the ROM bootloader to SRAM doesn't fit. # The resulting image containing both U-Boot images is called u-boot.spr -$(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \ +u-boot.spr: u-boot.img spl/u-boot-spl.bin + tools/mkimage -A $(ARCH) -T firmware -C none \ -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n XLOADER \ - -d $(obj)spl/u-boot-spl.bin $@ + -d spl/u-boot-spl.bin $@ $(OBJCOPY) -I binary -O binary \ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff $@ - cat $(obj)u-boot.img >> $@ + cat u-boot.img >> $@ ifneq ($(CONFIG_TEGRA),) -$(obj)u-boot-nodtb-tegra.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin - $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary $(obj)spl/u-boot-spl $(obj)spl/u-boot-spl-pad.bin - cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@ - rm $(obj)spl/u-boot-spl-pad.bin +u-boot-nodtb-tegra.bin: spl/u-boot-spl.bin u-boot.bin + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_TEXT_BASE) -O binary spl/u-boot-spl spl/u-boot-spl-pad.bin + cat spl/u-boot-spl-pad.bin u-boot.bin > $@ + rm spl/u-boot-spl-pad.bin ifeq ($(CONFIG_OF_SEPARATE),y) -$(obj)u-boot-dtb-tegra.bin: $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb - cat $(obj)u-boot-nodtb-tegra.bin $(obj)u-boot.dtb > $@ +u-boot-dtb-tegra.bin: u-boot-nodtb-tegra.bin u-boot.dtb + cat u-boot-nodtb-tegra.bin u-boot.dtb > $@ endif endif -$(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@ +u-boot-img.bin: spl/u-boot-spl.bin u-boot.img + cat spl/u-boot-spl.bin u-boot.img > $@ # PPC4xx needs the SPL at the end of the image, since the reset vector # is located at 0xfffffffc. So we can't use the "u-boot-img.bin" target # and need to introduce a new build target with the full blown U-Boot # at the start padded up to the start of the SPL image. And then concat # the SPL image to the end. -$(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img +u-boot-img-spl-at-end.bin: spl/u-boot-spl.bin u-boot.img $(OBJCOPY) -I binary -O binary --pad-to=$(CONFIG_UBOOT_PAD_TO) \ - --gap-fill=0xff $(obj)u-boot.img $@ - cat $(obj)spl/u-boot-spl.bin >> $@ + --gap-fill=0xff u-boot.img $@ + cat spl/u-boot-spl.bin >> $@ # Create a new ELF from a raw binary file. This is useful for arm64 # where static relocation needs to be performed on the raw binary, # but certain simulators only accept an ELF file (but don't do the # relocation). # FIXME refactor dts/Makefile to share target/arch detection -$(obj)u-boot.elf: $(obj)u-boot.bin +u-boot.elf: u-boot.bin @$(OBJCOPY) -B aarch64 -I binary -O elf64-littleaarch64 \ - $< $(obj)u-boot-elf.o - @$(LD) $(obj)u-boot-elf.o -o $@ \ + $< u-boot-elf.o + @$(LD) u-boot-elf.o -o $@ \ --defsym=_start=$(CONFIG_SYS_TEXT_BASE) \ -Ttext=$(CONFIG_SYS_TEXT_BASE) ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ - cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ - -Wl,--start-group $(__LIBS) -Wl,--end-group \ + $(CC) $(SYMS) -T u-boot.lds \ + -Wl,--start-group $(LIBS) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot else GEN_UBOOT = \ - cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ - $(__OBJS) \ - --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ + $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ + $(OBJS) \ + --start-group $(LIBS) --end-group $(PLATFORM_LIBS) \ -Map u-boot.map -o u-boot endif -$(obj)u-boot: depend \ - $(SUBDIR_TOOLS) $(OBJS) $(LIBS) $(obj)u-boot.lds +u-boot: depend $(SUBDIR_TOOLS) $(OBJS) $(LIBS) u-boot.lds $(GEN_UBOOT) ifeq ($(CONFIG_KALLSYMS),y) - smap=`$(call SYSTEM_MAP,$(obj)u-boot) | \ + smap=`$(call SYSTEM_MAP,u-boot) | \ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \ - -c common/system_map.c -o $(obj)common/system_map.o - $(GEN_UBOOT) $(obj)common/system_map.o + -c $(srctree)/common/system_map.c -o common/system_map.o + $(GEN_UBOOT) common/system_map.o endif $(OBJS): @: $(LIBS): depend $(SUBDIR_TOOLS) - $(MAKE) $(build) $(dir $(subst $(obj),,$@)) + $(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) $(SUBDIRS): depend - $(MAKE) $(build) $@ all + $(MAKE) $(build)=$@ all -$(SUBDIR_EXAMPLES-y): $(obj)u-boot +$(SUBDIR_EXAMPLES-y): u-boot -$(obj)u-boot.lds: $(LDSCRIPT) depend +u-boot.lds: $(LDSCRIPT) depend $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend - $(MAKE) $(build) nand_spl/board/$(BOARDDIR) all + $(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all -$(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin +u-boot-nand.bin: nand_spl u-boot.bin + cat nand_spl/u-boot-spl-16k.bin u-boot.bin > u-boot-nand.bin -$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend - $(MAKE) -C spl all +spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend + $(MAKE) obj=spl -f $(srctree)/spl/Makefile all -$(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend - $(MAKE) -C spl all CONFIG_TPL_BUILD=y +tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend + $(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \ - $(obj)include/spl-autoconf.mk \ - $(obj)include/tpl-autoconf.mk \ - $(obj)include/autoconf.mk \ - $(obj)include/generated/generic-asm-offsets.h \ - $(obj)include/generated/asm-offsets.h + include/spl-autoconf.mk \ + include/tpl-autoconf.mk \ + include/autoconf.mk \ + include/generated/generic-asm-offsets.h \ + include/generated/asm-offsets.h TAG_SUBDIRS = $(SUBDIRS) -TAG_SUBDIRS += $(dir $(__LIBS)) +TAG_SUBDIRS += $(dir $(LIBS)) TAG_SUBDIRS += include FIND := find FINDFLAGS := -L checkstack: - $(CROSS_COMPILE)objdump -d $(obj)u-boot \ - `$(FIND) $(obj) -name u-boot-spl -print` | \ - perl $(src)scripts/checkstack.pl $(ARCH) + $(CROSS_COMPILE)objdump -d u-boot \ + `$(FIND) . -name u-boot-spl -print` | \ + perl $(src)/scripts/checkstack.pl $(ARCH) tags ctags: - ctags -w -o $(obj)ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ + ctags -w -o ctags `$(FIND) $(FINDFLAGS) $(TAG_SUBDIRS) \ -name '*.[chS]' -print` etags: @@ -746,7 +769,7 @@ SYSTEM_MAP = \ $(NM) $1 | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ LC_ALL=C sort -$(obj)System.map: $(obj)u-boot +System.map: u-boot @$(call SYSTEM_MAP,$<) > $@ checkthumb: @@ -778,76 +801,76 @@ checkdtc: # This target actually generates 2 files; autoconf.mk and autoconf.mk.dep. # the dep file is only include in this top level makefile to determine when # to regenerate the autoconf.mk file. -$(obj)include/autoconf.mk.dep: $(obj)include/config.h include/common.h +include/autoconf.mk.dep: include/config.h include/common.h @$(XECHO) Generating $@ ; \ : Generate the dependancies ; \ $(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \ - -MQ $(obj)include/autoconf.mk include/common.h > $@ || \ + -MQ include/autoconf.mk $(srctree)/include/common.h > $@ || \ rm $@ -$(obj)include/autoconf.mk: $(obj)include/config.h +include/autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ + $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp # Auto-generate the spl-autoconf.mk file (which is included by all makefiles for SPL) -$(obj)include/tpl-autoconf.mk: $(obj)include/config.h +include/tpl-autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\ - -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ + -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp -$(obj)include/spl-autoconf.mk: $(obj)include/config.h +include/spl-autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM include/common.h > $@.tmp && \ - sed -n -f tools/scripts/define2mk.sed $@.tmp > $@; \ + $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp -$(obj)include/generated/generic-asm-offsets.h: $(obj)lib/asm-offsets.s +include/generated/generic-asm-offsets.h: lib/asm-offsets.s @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)lib/asm-offsets.s $@ + $(srctree)/tools/scripts/make-asm-offsets lib/asm-offsets.s $@ -$(obj)lib/asm-offsets.s: $(obj)include/config.h $(src)lib/asm-offsets.c - @mkdir -p $(obj)lib +lib/asm-offsets.s: include/config.h $(srctree)/lib/asm-offsets.c + @mkdir -p lib $(CC) -DDO_DEPS_ONLY \ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)lib/asm-offsets.c -c -S + -o $@ $(srctree)/lib/asm-offsets.c -c -S -$(obj)include/generated/asm-offsets.h: $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s +include/generated/asm-offsets.h: $(CPUDIR)/$(SOC)/asm-offsets.s @$(XECHO) Generating $@ - tools/scripts/make-asm-offsets $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s $@ + $(srctree)/tools/scripts/make-asm-offsets $(CPUDIR)/$(SOC)/asm-offsets.s $@ -$(obj)$(CPUDIR)/$(SOC)/asm-offsets.s: $(obj)include/config.h - @mkdir -p $(obj)$(CPUDIR)/$(SOC) - if [ -f $(src)$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ +$(CPUDIR)/$(SOC)/asm-offsets.s: include/config.h + @mkdir -p $(CPUDIR)/$(SOC) + if [ -f $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ $(CC) -DDO_DEPS_ONLY \ $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ - -o $@ $(src)$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \ + -o $@ $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \ else \ touch $@; \ fi ######################################################################### else # !config.mk -all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ -$(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ +all u-boot.hex u-boot.srec u-boot.bin \ +u-boot.img u-boot.dis u-boot \ $(filter-out tools,$(SUBDIRS)) \ -depend dep tags ctags etags cscope $(obj)System.map: +depend dep tags ctags etags cscope System.map: @echo "System not configured - see README" >&2 @ exit 1 tools: $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) $(build) $@ all + $(MAKE) $(build)=$@ all endif # config.mk # ARM relocations should all be R_ARM_RELATIVE (32-bit) or # R_AARCH64_RELATIVE (64-bit). -checkarmreloc: $(obj)u-boot +checkarmreloc: u-boot @RELOC="`$(CROSS_COMPILE)readelf -r -W $< | cut -d ' ' -f 4 | \ grep R_A | sort -u`"; \ if test "$$RELOC" != "R_ARM_RELATIVE" -a \ @@ -877,15 +900,15 @@ $(TIMESTAMP_FILE): @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ easylogo env gdb: - $(MAKE) $(build) tools/$@ MTD_VERSION=${MTD_VERSION} + $(MAKE) $(build)=tools/$@ MTD_VERSION=${MTD_VERSION} gdbtools: gdb xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc - $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@ + $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) $(build)=doc/DocBook $@ tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) $(build) tools HOST_TOOLS_ALL=y + $(MAKE) $(build)=tools HOST_TOOLS_ALL=y .PHONY : CHANGELOG CHANGELOG: @@ -897,57 +920,52 @@ include/license.h: tools/bin2header COPYING ######################################################################### unconfig: - @rm -f $(obj)include/config.h $(obj)include/config.mk \ - $(obj)board/*/config.tmp $(obj)board/*/*/config.tmp \ - $(obj)include/autoconf.mk $(obj)include/autoconf.mk.dep \ - $(obj)include/spl-autoconf.mk \ - $(obj)include/tpl-autoconf.mk + @rm -f include/config.h include/config.mk \ + board/*/config.tmp board/*/*/config.tmp \ + include/autoconf.mk include/autoconf.mk.dep \ + include/spl-autoconf.mk \ + include/tpl-autoconf.mk %_config:: unconfig @$(MKCONFIG) -A $(@:_config=) -sinclude $(obj).boards.depend -$(obj).boards.depend: boards.cfg - @awk '(NF && $$1 !~ /^#/) { print $$7 ": " $$7 "_config; $$(MAKE)" }' $< > $@ - -######################################################################### ######################################################################### clean: - @rm -f $(obj)examples/standalone/atmel_df_pow2 \ - $(obj)examples/standalone/hello_world \ - $(obj)examples/standalone/interrupt \ - $(obj)examples/standalone/mem_to_mem_idma2intr \ - $(obj)examples/standalone/sched \ - $(addprefix $(obj)examples/standalone/, smc91111_eeprom smc911x_eeprom) \ - $(obj)examples/standalone/test_burst \ - $(obj)examples/standalone/timer - @rm -f $(addprefix $(obj)examples/api/, demo demo.bin) - @rm -f $(obj)tools/bmp_logo $(obj)tools/easylogo/easylogo \ - $(obj)tools/env/fw_printenv \ - $(obj)tools/envcrc \ - $(addprefix $(obj)tools/gdb/, gdbcont gdbsend) \ - $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ - $(obj)tools/dumpimage \ - $(addprefix $(obj)tools/, mkenvimage mkimage) \ - $(obj)tools/mpc86x_clk \ - $(addprefix $(obj)tools/, mk$(BOARD)spl mkexynosspl) \ - $(obj)tools/mxsboot \ - $(obj)tools/ncb $(obj)tools/ubsha1 \ - $(obj)tools/kernel-doc/docproc \ - $(obj)tools/proftool - @rm -f $(addprefix $(obj)board/cray/L1/, bootscript.c bootscript.image) \ - $(obj)board/matrix_vision/*/bootscript.img \ - $(obj)spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl \ - $(obj)u-boot.lds \ - $(addprefix $(obj)arch/blackfin/cpu/, init.lds init.elf) - @rm -f $(obj)include/bmp_logo.h - @rm -f $(obj)include/bmp_logo_data.h - @rm -f $(obj)lib/asm-offsets.s - @rm -f $(obj)include/generated/asm-offsets.h - @rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s + @rm -f examples/standalone/atmel_df_pow2 \ + examples/standalone/hello_world \ + examples/standalone/interrupt \ + examples/standalone/mem_to_mem_idma2intr \ + examples/standalone/sched \ + $(addprefix examples/standalone/, smc91111_eeprom smc911x_eeprom) \ + examples/standalone/test_burst \ + examples/standalone/timer + @rm -f $(addprefix examples/api/, demo demo.bin) + @rm -f tools/bmp_logo tools/easylogo/easylogo \ + tools/env/fw_printenv \ + tools/envcrc \ + $(addprefix tools/gdb/, gdbcont gdbsend) \ + tools/gen_eth_addr tools/img2srec \ + tools/dumpimage \ + $(addprefix tools/, mkenvimage mkimage) \ + tools/mpc86x_clk \ + $(addprefix tools/, mk$(BOARD)spl mkexynosspl) \ + tools/mxsboot \ + tools/ncb tools/ubsha1 \ + tools/kernel-doc/docproc \ + tools/proftool + @rm -f $(addprefix board/cray/L1/, bootscript.c bootscript.image) \ + board/matrix_vision/*/bootscript.img \ + spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl \ + u-boot.lds \ + $(addprefix arch/blackfin/cpu/, init.lds init.elf) + @rm -f include/bmp_logo.h + @rm -f include/bmp_logo_data.h + @rm -f lib/asm-offsets.s + @rm -f include/generated/asm-offsets.h + @rm -f $(CPUDIR)/$(SOC)/asm-offsets.s @rm -f $(TIMESTAMP_FILE) $(VERSION_FILE) - @$(MAKE) -s -C doc/DocBook/ cleandocs + @$(MAKE) -f $(srctree)/doc/DocBook/Makefile cleandocs @find $(OBJTREE) -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \ -o -name '*.o' -o -name '*.a' -o -name '*.exe' \ @@ -962,38 +980,38 @@ clobber: tidy @find $(OBJTREE) -type f \( -name '*.srec' \ -o -name '*.bin' -o -name u-boot.img \) \ -print0 | xargs -0 rm -f - @rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS \ - $(obj)cscope.* $(obj)*.*~ - @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL-y) - @rm -f $(obj)u-boot.kwb - @rm -f $(obj)u-boot.pbl - @rm -f $(obj)u-boot.imx - @rm -f $(obj)u-boot-with-spl.imx - @rm -f $(obj)u-boot-with-nand-spl.imx - @rm -f $(obj)u-boot.ubl - @rm -f $(obj)u-boot.ais - @rm -f $(obj)u-boot.dtb - @rm -f $(obj)u-boot.sb - @rm -f $(obj)u-boot.spr - @rm -f $(addprefix $(obj)nand_spl/, u-boot.lds u-boot.lst System.map) - @rm -f $(addprefix $(obj)nand_spl/, u-boot-nand_spl.lds u-boot-spl u-boot-spl.map) - @rm -f $(addprefix $(obj)spl/, u-boot-spl u-boot-spl.bin u-boot-spl.map) - @rm -f $(obj)spl/u-boot-spl.lds - @rm -f $(addprefix $(obj)tpl/, u-boot-tpl u-boot-tpl.bin u-boot-tpl.map) - @rm -f $(obj)tpl/u-boot-spl.lds - @rm -f $(obj)MLO MLO.byteswap - @rm -f $(obj)SPL - @rm -f $(obj)tools/xway-swap-bytes - @rm -fr $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm - @rm -fr $(obj)include/generated - @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f - @rm -f $(obj)dts/*.tmp - @rm -f $(addprefix $(obj)spl/, u-boot-spl.ais, u-boot-spl-pad.ais) + @rm -f $(OBJS) *.bak ctags etags TAGS \ + cscope.* *.*~ + @rm -f u-boot u-boot.map u-boot.hex $(ALL-y) + @rm -f u-boot.kwb + @rm -f u-boot.pbl + @rm -f u-boot.imx + @rm -f u-boot-with-spl.imx + @rm -f u-boot-with-nand-spl.imx + @rm -f u-boot.ubl + @rm -f u-boot.ais + @rm -f u-boot.dtb + @rm -f u-boot.sb + @rm -f u-boot.spr + @rm -f $(addprefix nand_spl/, u-boot.lds u-boot.lst System.map) + @rm -f $(addprefix nand_spl/, u-boot-nand_spl.lds u-boot-spl u-boot-spl.map) + @rm -f $(addprefix spl/, u-boot-spl u-boot-spl.bin u-boot-spl.map) + @rm -f spl/u-boot-spl.lds + @rm -f $(addprefix tpl/, u-boot-tpl u-boot-tpl.bin u-boot-tpl.map) + @rm -f tpl/u-boot-spl.lds + @rm -f MLO MLO.byteswap + @rm -f SPL + @rm -f tools/xway-swap-bytes + @rm -fr include/asm/proc include/asm/arch include/asm + @rm -fr include/generated + @[ ! -d nand_spl ] || find nand_spl -name "*" -type l -print | xargs rm -f + @rm -f dts/*.tmp + @rm -f $(addprefix spl/, u-boot-spl.ais, u-boot-spl-pad.ais) mrproper \ distclean: clobber unconfig ifneq ($(OBJTREE),$(SRCTREE)) - rm -rf $(obj)* + rm -rf * endif backup: @@ -1001,3 +1019,12 @@ backup: gtar --force-local -zcvf `LC_ALL=C date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F ######################################################################### + +endif # skip-makefile + +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index f74228cdba1..ab1fc4ad156 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -14,6 +14,6 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif else -ALL-y += $(obj)u-boot.imx +ALL-y += u-boot.imx endif endif diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index 4d9895f5d8f..f27ca15086f 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -13,6 +13,6 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif else -ALL-y += $(obj)u-boot.imx +ALL-y += u-boot.imx endif endif diff --git a/arch/arm/cpu/arm926ejs/davinci/config.mk b/arch/arm/cpu/arm926ejs/davinci/config.mk index d5c978b4467..69e9d5ab211 100644 --- a/arch/arm/cpu/arm926ejs/davinci/config.mk +++ b/arch/arm/cpu/arm926ejs/davinci/config.mk @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-$(CONFIG_SPL_FRAMEWORK) += $(obj)u-boot.ais +ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.ais endif diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 8e3668f781e..1c06fb40a4f 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -7,5 +7,5 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/MLO ALL-$(CONFIG_SPL_SPI_SUPPORT) += $(OBJTREE)/MLO.byteswap else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 38b7c401f85..d01f3d9f500 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -20,6 +20,6 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/SPL endif else -ALL-y += $(obj)u-boot.imx +ALL-y += u-boot.imx endif endif diff --git a/arch/arm/cpu/armv7/omap3/config.mk b/arch/arm/cpu/armv7/omap3/config.mk index 1d6a57c66c6..2a3d1c5c3a5 100644 --- a/arch/arm/cpu/armv7/omap3/config.mk +++ b/arch/arm/cpu/armv7/omap3/config.mk @@ -11,5 +11,5 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap4/config.mk b/arch/arm/cpu/armv7/omap4/config.mk index 1d6a57c66c6..2a3d1c5c3a5 100644 --- a/arch/arm/cpu/armv7/omap4/config.mk +++ b/arch/arm/cpu/armv7/omap4/config.mk @@ -11,5 +11,5 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk index 2673af96681..261b272234a 100644 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -9,5 +9,5 @@ ifdef CONFIG_SPL_BUILD ALL-y += $(OBJTREE)/MLO else -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk index d33ab7d62fd..3d18491577f 100644 --- a/arch/arm/cpu/armv7/socfpga/config.mk +++ b/arch/arm/cpu/armv7/socfpga/config.mk @@ -4,5 +4,5 @@ # SPDX-License-Identifier: GPL-2.0+ # ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.img +ALL-y += u-boot.img endif diff --git a/arch/blackfin/config.mk b/arch/blackfin/config.mk index 73fa79855f5..c752025aaf7 100644 --- a/arch/blackfin/config.mk +++ b/arch/blackfin/config.mk @@ -12,7 +12,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin ifeq ($(CONFIG_BFIN_CPU),) CONFIG_BFIN_CPU := \ $(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \ - $(src)include/configs/$(BOARD).h) + $(srctree)/include/configs/$(BOARD).h) else CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%)) endif @@ -28,10 +28,10 @@ PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU) ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) -ALL-y += $(obj)u-boot.ldr +ALL-y += u-boot.ldr endif ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y) -CREATE_LDR_ENV = $(obj)tools/envcrc --binary > $(obj)env-ldr.o +CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o HOSTCFLAGS_NOPED_ADSP := \ $(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) .*\' ; then \ echo "$< contains external references!" 1>&2 ; \ @@ -35,7 +35,7 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif -$(obj)init.lds: init.lds.S +$(obj)/init.lds: $(src)/init.lds.S $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ -$(obj)init.elf: $(obj)init.lds $(obj)init.o $(obj)initcode.o +$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o $(LD) $(LDFLAGS) -T $^ -o $@ diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 067f8715259..7ee7faae8f7 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -21,4 +21,4 @@ else PLATFORM_LDFLAGS += -m elf32ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk index d1a8b2c7aa3..02113a1f091 100644 --- a/arch/mips/cpu/mips64/config.mk +++ b/arch/mips/cpu/mips64/config.mk @@ -21,4 +21,4 @@ else PLATFORM_LDFLAGS += -m elf64ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T $(srctree)/$(src)/mips64.lds diff --git a/arch/mips/cpu/xburst/config.mk b/arch/mips/cpu/xburst/config.mk index d81da210170..00b0fd9c9c6 100644 --- a/arch/mips/cpu/xburst/config.mk +++ b/arch/mips/cpu/xburst/config.mk @@ -12,4 +12,4 @@ else PLATFORM_LDFLAGS += -m elf32ltsmip endif -CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T mips.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 -T $(srctree)/$(src)/mips.lds diff --git a/arch/nds32/config.mk b/arch/nds32/config.mk index e93e3a8c28d..550f8a440e6 100644 --- a/arch/nds32/config.mk +++ b/arch/nds32/config.mk @@ -10,7 +10,7 @@ CROSS_COMPILE ?= nds32le-linux- -CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T nds32.lds +CONFIG_STANDALONE_LOAD_ADDR = 0x300000 -T $(srctree)/$(src)/nds32.lds PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -mrelax PLATFORM_RELFLAGS += -gdwarf-2 diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index a706d3cc70f..ac780d4077f 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -54,11 +54,11 @@ ifndef CONFIG_SPL_BUILD # Workaround for local bus unaligned access problems # on MPC512x and MPC5200 ifdef CONFIG_MPC512X -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +$(obj)/ppcstring.o: AFLAGS += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif ifdef CONFIG_MPC5200 -$(obj)ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +$(obj)/ppcstring.o: AFLAGS += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif endif diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index b564294a847..c5f5426b05f 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,7 +10,7 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)os.o: CFLAGS := $(filter-out -nostdinc,\ +$(obj)/os.o: CFLAGS := $(filter-out -nostdinc,\ $(patsubst -I%,-idirafter%,$(CFLAGS))) -$(obj).depend.os: CPPFLAGS := $(filter-out -nostdinc,\ +$(obj)/.depend.os: CPPFLAGS := $(filter-out -nostdinc,\ $(patsubst -I%,-idirafter%,$(CPPFLAGS))) diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index e94e7cbab56..9bb37241d2e 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -7,6 +7,7 @@ CROSS_COMPILE ?= sparc-elf- -CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) -T sparc.lds +CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \ + -T $(srctree)/$(src)/sparc.lds PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 638f79069cc..a35d062792a 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -23,5 +23,5 @@ obj-$(CONFIG_CMD_ZBOOT) += zimage.o LIBGCC := $(notdir $(NORMAL_LIBGCC)) extra-y := $(LIBGCC) -$(obj)$(LIBGCC): $(NORMAL_LIBGCC) +$(obj)/$(LIBGCC): $(NORMAL_LIBGCC) $(OBJCOPY) $< $@ --prefix-symbols=__normal_ diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index d7e7894831d..c7cfacacba8 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -9,7 +9,7 @@ UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD -ALL-y += $(obj)u-boot.ubl +ALL-y += u-boot.ubl else # as SPL_TEXT_BASE is not page-aligned, we need for some # linkers the -n flag (Do not page align data), to prevent diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile index 87e19123b04..bcf7ccfe2ac 100644 --- a/board/avionic-design/medcom-wide/Makefile +++ b/board/avionic-design/medcom-wide/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile index 87e19123b04..bcf7ccfe2ac 100644 --- a/board/avionic-design/plutux/Makefile +++ b/board/avionic-design/plutux/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile index 79d86026261..a556b92e8ed 100644 --- a/board/avionic-design/tec-ng/Makefile +++ b/board/avionic-design/tec-ng/Makefile @@ -7,4 +7,4 @@ obj-y := ../common/tamonten-ng.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile index 87e19123b04..bcf7ccfe2ac 100644 --- a/board/avionic-design/tec/Makefile +++ b/board/avionic-design/tec/Makefile @@ -9,4 +9,4 @@ obj-y := ../common/tamonten.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile index b2d3b6b4b25..e6a0b299973 100644 --- a/board/compal/paz00/Makefile +++ b/board/compal/paz00/Makefile @@ -16,4 +16,4 @@ obj-y := paz00.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile index f3bd00dbf18..311eb92d7b9 100644 --- a/board/compulab/trimslice/Makefile +++ b/board/compulab/trimslice/Makefile @@ -7,4 +7,4 @@ obj-y := trimslice.o -include ../../nvidia/common/common.mk +include $(srctree)/board/nvidia/common/common.mk diff --git a/board/cray/L1/Makefile b/board/cray/L1/Makefile index 5f6c690b7c2..6aae9fa62f4 100644 --- a/board/cray/L1/Makefile +++ b/board/cray/L1/Makefile @@ -9,8 +9,8 @@ obj-y = L1.o flash.o obj-y += init.o obj-y += bootscript.o -$(obj)bootscript.c: $(obj)bootscript.image - od -t x1 -v -A x $^ | awk -f x2c.awk > $@ +$(obj)/bootscript.c: $(obj)/bootscript.image + od -t x1 -v -A x $^ | awk -f $(srctree)/$(src)/x2c.awk > $@ -$(obj)bootscript.image: $(src)bootscript.hush $(src)Makefile - -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $(src)bootscript.hush $@ +$(obj)/bootscript.image: $(src)/bootscript.hush + -$(OBJTREE)/tools/mkimage -A ppc -O linux -T script -C none -a 0 -e 0 -n bootscript -d $< $@ diff --git a/board/h2200/Makefile b/board/h2200/Makefile index d4fa15344cc..e516e916b41 100644 --- a/board/h2200/Makefile +++ b/board/h2200/Makefile @@ -10,5 +10,5 @@ obj-y := h2200.o extra-y := h2200-header.bin -$(obj)h2200-header.bin: $(obj)h2200-header.o +$(obj)/h2200-header.bin: $(obj)/h2200-header.o $(OBJCOPY) -O binary $< $@ diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile index 879d7946554..1bc1d61dcf6 100644 --- a/board/matrix_vision/mvblm7/Makefile +++ b/board/matrix_vision/mvblm7/Makefile @@ -8,5 +8,5 @@ obj-y := mvblm7.o pci.o fpga.o extra-y := bootscript.img -$(obj)bootscript.img: - @mkimage -T script -C none -n M7_script -d bootscript $@ +$(obj)/bootscript.img: $(src)/bootscript + @mkimage -T script -C none -n M7_script -d $< $@ diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile index b6a4f6754bf..9454259c172 100644 --- a/board/matrix_vision/mvsmr/Makefile +++ b/board/matrix_vision/mvsmr/Makefile @@ -12,5 +12,5 @@ obj-y := mvsmr.o fpga.o extra-y := bootscript.img -$(obj)bootscript.img: bootscript +$(obj)/bootscript.img: $(src)/bootscript @mkimage -T script -C none -n mvSMR_Script -d $< $@ diff --git a/board/nvidia/common/Makefile b/board/nvidia/common/Makefile index e3fcf2bdffc..e3b2651570d 100644 --- a/board/nvidia/common/Makefile +++ b/board/nvidia/common/Makefile @@ -1,4 +1,4 @@ # Copyright (c) 2011 The Chromium OS Authors. # SPDX-License-Identifier: GPL-2.0+ -include common.mk +include $(src)/common.mk diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 1e761284e4d..b90d5d0ec1f 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -10,7 +10,7 @@ # # Check the U-Boot Image with a SHA1 checksum -ALL-y += $(obj)u-boot.sha1 +ALL-y += u-boot.sha1 PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/samsung/origen/Makefile b/board/samsung/origen/Makefile index 31e88f44246..37acba71e01 100644 --- a/board/samsung/origen/Makefile +++ b/board/samsung/origen/Makefile @@ -13,7 +13,7 @@ always := $(hostprogs-y) # # TODO: # Fix the root cause in tools/mkorigenspl.c and delete the following work-around -$(obj)tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS)) +$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS)) else obj-y += origen.o endif diff --git a/common/Makefile b/common/Makefile index 2fe14ccc41b..2d758436284 100644 --- a/common/Makefile +++ b/common/Makefile @@ -238,11 +238,10 @@ obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o obj-y += memsize.o obj-y += stdio.o -$(obj)env_embedded.o: $(src)env_embedded.c +$(obj)/env_embedded.o: $(src)/env_embedded.c $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell $(obj)../tools/envcrc) \ - -c -o $@ $(src)env_embedded.c + -DENV_CRC=$(shell tools/envcrc) -c -o $@ $< # SEE README.arm-unaligned-accesses -$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +$(obj)/hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +$(obj)/fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) diff --git a/config.mk b/config.mk index ed1a51972f5..0fa316743ce 100644 --- a/config.mk +++ b/config.mk @@ -6,42 +6,6 @@ # ######################################################################### -ifeq ($(CURDIR),$(SRCTREE)) -dir := -else -dir := $(subst $(SRCTREE)/,,$(CURDIR)) -endif - -ifneq ($(OBJTREE),$(SRCTREE)) -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) -else -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) -endif -else -obj := $(if $(dir),$(OBJTREE)/$(dir)/,$(OBJTREE)/) -endif -src := $(if $(dir),$(SRCTREE)/$(dir)/,$(SRCTREE)/) - -$(shell mkdir -p $(obj)) -else -# Create object files for SPL in a separate directory -ifeq ($(CONFIG_SPL_BUILD),y) -ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(if $(dir),$(TPLTREE)/$(dir)/,$(TPLTREE)/) -else -obj := $(if $(dir),$(SPLTREE)/$(dir)/,$(SPLTREE)/) - -endif -$(shell mkdir -p $(obj)) -else -obj := -endif -src := -endif - # clean the slate ... PLATFORM_RELFLAGS = PLATFORM_CPPFLAGS = @@ -52,14 +16,14 @@ PLATFORM_LDFLAGS = # Load generated board configuration ifeq ($(CONFIG_TPL_BUILD),y) # Include TPL autoconf -sinclude $(OBJTREE)/include/tpl-autoconf.mk +sinclude include/tpl-autoconf.mk else ifeq ($(CONFIG_SPL_BUILD),y) # Include SPL autoconf -sinclude $(OBJTREE)/include/spl-autoconf.mk +sinclude include/spl-autoconf.mk else # Include normal autoconf -sinclude $(OBJTREE)/include/autoconf.mk +sinclude include/autoconf.mk endif endif sinclude $(OBJTREE)/include/config.mk diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index 29b79d7cd11..aa7c44b127c 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -6,8 +6,6 @@ # To add a new book the only step required is to add the book to the # list of DOCBOOKS. -include $(TOPDIR)/config.mk - DOCBOOKS := fs.xml linker_lists.xml stdio.xml ### @@ -122,7 +120,7 @@ quiet_cmd_db2pdf = PDF $@ index = index.html -main_idx = $(index) +main_idx = doc/DocBook/$(index) build_main_index = rm -rf $(main_idx); \ echo '

U-Boot Bootloader HTML Documentation

' >> $(main_idx) && \ echo '

U-Boot Version: $(U_BOOT_VERSION)

' >> $(main_idx) && \ @@ -151,7 +149,7 @@ quiet_cmd_db2man = MAN $@ @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) - $(Q)mkdir -p $(obj)man + $(Q)mkdir -p $(obj)/man $(call cmd_db2man) @touch $@ diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 52a2ceb4759..330f36f3bd2 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -8,7 +8,7 @@ obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -EXTRA_CFLAGS += -I. -I./include \ +EXTRA_CFLAGS += -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ -D__PPC__ -D__BIG_ENDIAN__ CFLAGS += $(EXTRA_CFLAGS) diff --git a/dts/Makefile b/dts/Makefile index 6c7198f65ff..d81f32d914d 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -26,7 +26,7 @@ DTC_FLAGS := -R 4 -p 0x1000 \ # Use a constant name for this so we can access it from C code. # objcopy doesn't seem to allow us to set the symbol name independently of # the filename. -DT_BIN := $(obj)dt.dtb +DT_BIN := $(obj)/dt.dtb $(DT_BIN): $(TOPDIR)/board/$(VENDOR)/dts/$(DEVICE_TREE).dts $(CPP) $(DTS_CPPFLAGS) $< -o $(DT_BIN).dts.tmp @@ -38,7 +38,7 @@ process_lds = \ # Run the compiler and get the link script from the linker GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1 -$(obj)dt.o: $(DT_BIN) +$(obj)/dt.o: $(DT_BIN) # We want the output format and arch. # We also hope to win a prize for ugliest Makefile / shell interaction # We look in the LDSCRIPT first. @@ -62,7 +62,7 @@ $(obj)dt.o: $(DT_BIN) \ cd $(dir ${DT_BIN}) && \ $(OBJCOPY) -I binary -O $${oformat} -B $${oarch} \ - $(notdir ${DT_BIN}) $@ + $(notdir ${DT_BIN}) $(notdir $@) rm $(DT_BIN) obj-$(CONFIG_OF_EMBED) := dt.o diff --git a/examples/api/Makefile b/examples/api/Makefile index ee3c487c132..db0bb34afeb 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -40,23 +40,23 @@ SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c)) SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S)) # Create a list of object files to be compiled -OBJS += $(addprefix $(obj),$(SOBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(COBJ_FILES-y)) -OBJS += $(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y))) -OBJS += $(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y))) +OBJS += $(addprefix $(obj)/,$(SOBJ_FILES-y)) +OBJS += $(addprefix $(obj)/,$(COBJ_FILES-y)) +OBJS += $(addprefix $(obj)/,$(notdir $(EXT_COBJ_FILES-y))) +OBJS += $(addprefix $(obj)/,$(notdir $(EXT_SOBJ_FILES-y))) ######################################################################### -$(obj)demo: $(OBJS) +$(obj)/demo: $(OBJS) $(LD) --gc-sections -Ttext $(LOAD_ADDR) -o $@ $^ $(PLATFORM_LIBS) -$(obj)demo.bin: $(obj)demo +$(obj)/demo.bin: $(obj)/demo $(OBJCOPY) -O binary $< $@ 2>/dev/null # Rule to build generic library C files -$(addprefix $(obj),$(notdir $(EXT_COBJ_FILES-y))): $(obj)%.o: $(SRCTREE)/lib/%.c +$(addprefix $(obj)/,$(notdir $(EXT_COBJ_FILES-y))): $(obj)/%.o: $(SRCTREE)/lib/%.c $(CC) -g $(CFLAGS) -c -o $@ $< # Rule to build architecture-specific library assembly files -$(addprefix $(obj),$(notdir $(EXT_SOBJ_FILES-y))): $(obj)%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S +$(addprefix $(obj)/,$(notdir $(EXT_SOBJ_FILES-y))): $(obj)/%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S $(CC) -g $(CFLAGS) -c -o $@ $< diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 1f8d70ce8a7..a6819f77929 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -31,7 +31,7 @@ clean-files := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra- COBJS := $(ELF:=.o) -LIB = $(obj)libstubs.o +LIB = $(obj)/libstubs.o LIBAOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o LIBAOBJS-$(CONFIG_8xx) += test_burst_lib.o @@ -39,11 +39,11 @@ LIBAOBJS := $(LIBAOBJS-y) LIBCOBJS = stubs.o -LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) +LIBOBJS = $(addprefix $(obj)/,$(LIBAOBJS) $(LIBCOBJS)) SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) -OBJS := $(addprefix $(obj),$(COBJS)) -ELF := $(addprefix $(obj),$(ELF)) +OBJS := $(addprefix $(obj)/,$(COBJS)) +ELF := $(addprefix $(obj)/,$(ELF)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) @@ -67,13 +67,13 @@ $(LIB): $(LIBOBJS) $(call cmd_link_o_target, $(LIBOBJS)) $(ELF): -$(obj)%: $(obj)%.o $(LIB) +$(obj)/%: $(obj)/%.o $(LIB) $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc -$(obj)%.srec: $(obj)% +$(obj)/%.srec: $(obj)/% $(OBJCOPY) -O srec $< $@ 2>/dev/null -$(obj)%.bin: $(obj)% +$(obj)/%.bin: $(obj)/% $(OBJCOPY) -O binary $< $@ 2>/dev/null diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 389b0e37e79..5682b16916a 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -15,4 +15,4 @@ obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o obj-y += log.o orphan.o recovery.o replay.o # SEE README.arm-unaligned-accesses -$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +$(obj)/super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) diff --git a/lib/Makefile b/lib/Makefile index 760340fbdef..43b13d09e2f 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -67,4 +67,4 @@ obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o # SEE README.arm-unaligned-accesses -$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +$(obj)/bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) diff --git a/mkconfig b/mkconfig index b96c81fbc2b..5f516f214a3 100755 --- a/mkconfig +++ b/mkconfig @@ -23,7 +23,7 @@ options="" if [ \( $# -eq 2 \) -a \( "$1" = "-A" \) ] ; then # Automatic mode - line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' boards.cfg` + line=`awk '($0 !~ /^#/ && $7 ~ /^'"$2"'$/) { print $1, $2, $3, $4, $5, $6, $7, $8 }' $srctree/boards.cfg` if [ -z "$line" ] ; then echo "make: *** No rule to make target \`$2_config'. Stop." >&2 exit 1 diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 3b00d496ea2..041213f3346 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -18,8 +18,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o cache.o COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -47,49 +47,41 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)cache.S: +$(obj)/cache.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ -$(obj)gpio.c: +$(obj)/gpio.c: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/gpio.c $@ -$(obj)ndfc.c: +$(obj)/ndfc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory -$(obj)memory.c: +$(obj)/memory.c: @rm -f $@ ln -s $(SRCTREE)/board/amcc/acadia/memory.c $@ -$(obj)pll.c: +$(obj)/pll.c: @rm -f $@ ln -s $(SRCTREE)/board/amcc/acadia/pll.c $@ # from nand_spl directory -$(obj)nand_boot.c: +$(obj)/nand_boot.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory -$(obj)nand_ecc.c: +$(obj)/nand_ecc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index 4063274de66..92b604e9f56 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -18,8 +18,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o init.o resetvec.o COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -41,43 +41,29 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)ndfc.c: +$(obj)/ndfc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory -$(obj)init.S: +$(obj)/init.S: @rm -f $@ ln -s $(SRCTREE)/board/amcc/bamboo/init.S $@ # from nand_spl directory -$(obj)nand_boot.c: +$(obj)/nand_boot.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory -$(obj)nand_ecc.c: +$(obj)/nand_ecc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)sdram.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/sdram.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index 13c8b3690da..9a730e95f54 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -23,8 +23,8 @@ COBJS += nand_boot.o COBJS += nand_ecc.o COBJS += ndfc.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -46,43 +46,29 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)ndfc.c: +$(obj)/ndfc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory -$(obj)init.S: +$(obj)/init.S: @rm -f $@ ln -s $(SRCTREE)/board/amcc/canyonlands/init.S $@ # from nand_spl directory -$(obj)nand_boot.c: +$(obj)/nand_boot.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory -$(obj)nand_ecc.c: +$(obj)/nand_ecc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)ddr2_fixed.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/ddr2_fixed.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 9d07147d400..1c5498cfa56 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -18,8 +18,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o cache.o COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -41,44 +41,36 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)44x_spd_ddr2.c: $(obj)ecc.h +$(obj)/44x_spd_ddr2.c: $(obj)/ecc.h @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c $@ -$(obj)cache.S: +$(obj)/cache.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/cache.S $@ -$(obj)ecc.h: +$(obj)/ecc.h: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/ecc.h $@ -$(obj)ndfc.c: +$(obj)/ndfc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from nand_spl directory -$(obj)nand_boot.c: +$(obj)/nand_boot.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/nand directory -$(obj)nand_ecc.c: +$(obj)/nand_ecc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 111bb0d3aa5..62131ab3996 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -18,8 +18,8 @@ CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o init.o resetvec.o COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -41,47 +41,39 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files # from cpu directory -$(obj)denali_data_eye.c: +$(obj)/denali_data_eye.c: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/denali_data_eye.c $@ -$(obj)ndfc.c: +$(obj)/ndfc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/ndfc.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/resetvec.S $@ -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/ppc4xx/start.S $@ # from board directory -$(obj)init.S: +$(obj)/init.S: @rm -f $@ ln -s $(SRCTREE)/board/amcc/sequoia/init.S $@ -$(obj)sdram.c: +$(obj)/sdram.c: @rm -f $@ - @rm -f $(obj)sdram.h + @rm -f $(obj)/sdram.h ln -s $(SRCTREE)/board/amcc/sequoia/sdram.c $@ - ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)sdram.h + ln -s $(SRCTREE)/board/amcc/sequoia/sdram.h $(obj)/sdram.h # from nand_spl directory -$(obj)nand_boot.c: +$(obj)/nand_boot.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot.c $@ # from drivers/mtd/nand directory -$(obj)nand_ecc.c: +$(obj)/nand_ecc.c: @rm -f $@ ln -s $(SRCTREE)/drivers/mtd/nand/nand_ecc.c $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index 78138237839..a2054ee1ab5 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -20,8 +20,8 @@ SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -42,37 +42,29 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)start.S: +$(obj)/start.S: ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)sdram.c: +$(obj)/sdram.c: ln -sf $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ -$(obj)$(BOARD).c: +$(obj)/$(BOARD).c: ln -sf $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ -$(obj)cache.c: +$(obj)/cache.c: ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)time.c: +$(obj)/time.c: ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $@ -$(obj)ticks.S: +$(obj)/ticks.S: ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index 5d9953b6f3d..f711cf30ba5 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -22,8 +22,8 @@ SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -45,64 +45,50 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index 5d9953b6f3d..f711cf30ba5 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -22,8 +22,8 @@ SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -45,64 +45,50 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index 5d9953b6f3d..f711cf30ba5 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -22,8 +22,8 @@ SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -45,64 +45,50 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 652590df8d1..21a6920e638 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -18,8 +18,8 @@ SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -41,64 +41,50 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -sf $(SRCTREE)/$(CPUDIR)/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ ln -sf $(SRCTREE)/$(CPUDIR)/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index 5d9953b6f3d..f711cf30ba5 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -22,8 +22,8 @@ SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -45,64 +45,50 @@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)cpu_init_early.c: +$(obj)/cpu_init_early.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@ -$(obj)fsl_law.c: +$(obj)/fsl_law.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc8xxx/law.c $@ -$(obj)law.c: +$(obj)/law.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -sf $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)resetvec.S: +$(obj)/resetvec.S: @rm -f $@ ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $@ -$(obj)fixed_ivor.S: +$(obj)/fixed_ivor.S: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S $@ -$(obj)start.S: $(obj)fixed_ivor.S +$(obj)/start.S: $(obj)/fixed_ivor.S @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $@ -$(obj)tlb.c: +$(obj)/tlb.c: @rm -f $@ ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $@ -$(obj)tlb_table.c: +$(obj)/tlb_table.c: @rm -f $@ ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $@ - -ifneq ($(OBJTREE), $(SRCTREE)) -$(obj)nand_boot.c: - @rm -f $@ - ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $@ -endif - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index 5e83abcb14c..ca45ecd3280 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -19,8 +19,8 @@ SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) @@ -41,46 +41,38 @@ $(nandobj)u-boot.lds: $(LDSCRIPT) # create symbolic links for common files -$(obj)start.S: +$(obj)/start.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/start.S $@ -$(obj)nand_boot_fsl_elbc.c: +$(obj)/nand_boot_fsl_elbc.c: @rm -f $@ ln -s $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c $@ -$(obj)sdram.c: +$(obj)/sdram.c: @rm -f $@ ln -s $(SRCTREE)/board/$(BOARDDIR)/sdram.c $@ -$(obj)$(BOARD).c: +$(obj)/$(BOARD).c: @rm -f $@ ln -s $(SRCTREE)/board/$(BOARDDIR)/$(BOARD).c $@ -$(obj)ns16550.c: +$(obj)/ns16550.c: @rm -f $@ ln -s $(SRCTREE)/drivers/serial/ns16550.c $@ -$(obj)spl_minimal.c: +$(obj)/spl_minimal.c: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@ -$(obj)cache.c: +$(obj)/cache.c: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/lib/cache.c $@ -$(obj)time.c: +$(obj)/time.c: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/lib/time.c $@ -$(obj)ticks.S: +$(obj)/ticks.S: @rm -f $@ ln -s $(SRCTREE)/arch/powerpc/lib/ticks.S $@ - -######################################################################### - -$(obj)%.o: $(obj)%.S - $(CC) $(AFLAGS) -c -o $@ $< - -$(obj)%.o: $(obj)%.c - $(CC) $(CFLAGS) -c -o $@ $< diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile index a7aa5bcb7ea..c720a26f61d 100644 --- a/post/lib_powerpc/fpu/Makefile +++ b/post/lib_powerpc/fpu/Makefile @@ -18,7 +18,7 @@ obj-y += darwin-ldouble.o CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//) CFLAGS += -mhard-float -fkeep-inline-functions -$(addprefix $(obj),$(obj-y)): $(obj)%.o: %.c +$(addprefix $(obj)/,$(obj-y)): $(obj)/%.o: $(src)/%.c $(CC) $(ALL_CFLAGS) -o $@.fp $< -c $(OBJCOPY) -R .gnu.attributes $@.fp $@ rm -f $@.fp diff --git a/rules.mk b/rules.mk index b36de4daa2b..e4fd3371df5 100644 --- a/rules.mk +++ b/rules.mk @@ -6,41 +6,42 @@ # ######################################################################### -_depend: $(obj).depend +_depend: $(obj)/.depend # Split the source files into two camps: those in the current directory, and # those somewhere else. For the first camp we want to support CPPFLAGS_ # and for the second we don't / can't. -PWD_SRCS := $(filter $(notdir $(SRCS)),$(SRCS)) -OTHER_SRCS := $(filter-out $(notdir $(SRCS)),$(SRCS)) +PWD_SRCS := $(foreach f,$(SRCS), $(if \ + $(filter $(if $(KBUILD_SRC),$(srctree)/)$(src)/$(notdir $f),$f), $f)) +OTHER_SRCS := $(filter-out $(PWD_SRCS),$(SRCS)) # This is a list of dependency files to generate -DEPS := $(basename $(patsubst %,$(obj).depend.%,$(PWD_SRCS))) +DEPS := $(basename $(addprefix $(obj)/.depend., $(notdir $(PWD_SRCS)))) # Join all the dependencies into a single file, in three parts # 1 .Concatenate all the generated depend files together # 2. Add in the deps from OTHER_SRCS which we couldn't process # 3. Add in the HOSTSRCS -$(obj).depend: $(src)Makefile $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \ +$(obj)/.depend: $(TOPDIR)/config.mk $(DEPS) $(OTHER_SRCS) \ $(HOSTSRCS) cat /dev/null $(DEPS) >$@ @for f in $(OTHER_SRCS); do \ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(CC) -M $(CPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ + $(CC) -M $(CPPFLAGS) -MQ $(obj)/$$g $$f >> $@ ; \ done @for f in $(HOSTSRCS); do \ g=`basename $$f | sed -e 's/\(.*\)\.[[:alnum:]_]/\1.o/'`; \ - $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)$$g $$f >> $@ ; \ + $(HOSTCC) -M $(HOSTCPPFLAGS) -MQ $(obj)/$$g $$f >> $@ ; \ done MAKE_DEPEND = $(CC) -M $(CPPFLAGS) $(EXTRA_CPPFLAGS_DEP) \ -MQ $(addsuffix .o,$(obj)$(basename $<)) $< >$@ -$(obj).depend.%: %.c +$(obj)/.depend.%: $(src)/%.c $(MAKE_DEPEND) -$(obj).depend.%: %.S +$(obj)/.depend.%: $(src)/%.S $(MAKE_DEPEND) ######################################################################### diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index ca5fd56ca25..6113c13d161 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -165,9 +165,7 @@ ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2)) # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= # Usage: # $(Q)$(MAKE) $(build)=dir -#build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj -# temporary -build := -f $(srctree)/scripts/Makefile.build -C +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj ### # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj= diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 7789efab82c..52a44ff3777 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -2,17 +2,28 @@ .PHONY: all all: +ifeq ($(CONFIG_TPL_BUILD),y) + src := $(patsubst tpl/%,%,$(obj)) +else + ifeq ($(CONFIG_SPL_BUILD),y) + src := $(patsubst spl/%,%,$(obj)) + else + src := $(obj) + endif +endif + include $(srctree)/scripts/Kbuild.include -include $(TOPDIR)/config.mk +include $(srctree)/config.mk # variable LIB is used in examples/standalone/Makefile -__LIB := $(obj)built-in.o -LIBGCC = $(obj)libgcc.o +__LIB := $(obj)/built-in.o +LIBGCC = $(obj)/libgcc.o SRCS := subdir-y := obj-dirs := -include Makefile +kbuild-dir := $(if $(filter /%,$(src)),$(src),$(srctree)/$(src)) +include $(kbuild-dir)/Makefile # Do not include host rules unless needed ifneq ($(hostprogs-y)$(hostprogs-m),) @@ -28,31 +39,37 @@ lib-y := $(sort $(lib-y)) subdir-y += $(patsubst %/,%,$(filter %/, $(obj-y))) obj-y := $(patsubst %/, %/built-in.o, $(obj-y)) subdir-obj-y := $(filter %/built-in.o, $(obj-y)) -subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y)) +subdir-obj-y := $(addprefix $(obj)/,$(subdir-obj-y)) + +SRCS += $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \ + $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S) -SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \ - $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S)) -OBJS := $(addprefix $(obj),$(obj-y)) +SRCS := $(addprefix $(if $(KBUILD_SRC),$(srctree)/$(src)/,$(src)/),$(SRCS)) +SRCS := $(wildcard $(SRCS)) + +OBJS := $(addprefix $(obj)/,$(obj-y)) # $(obj-dirs) is a list of directories that contain object files obj-dirs += $(dir $(OBJS)) +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) + # Create directories for object files if directory does not exist # Needed when obj-y := dir/file.o syntax is used _dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) -LGOBJS := $(addprefix $(obj),$(sort $(lib-y))) +LGOBJS := $(addprefix $(obj)/,$(sort $(lib-y))) -all: $(__LIB) $(addprefix $(obj),$(extra-y) $(always)) $(subdir-y) +all: $(__LIB) $(addprefix $(obj)/,$(extra-y) $(always)) $(subdir-y) -$(__LIB): $(obj).depend $(OBJS) +$(__LIB): $(obj)/.depend $(OBJS) $(call cmd_link_o_target, $(OBJS)) ifneq ($(strip $(lib-y)),) all: $(LIBGCC) -$(LIBGCC): $(obj).depend $(LGOBJS) +$(LIBGCC): $(obj)/.depend $(LGOBJS) $(call cmd_link_o_target, $(LGOBJS)) endif @@ -63,7 +80,7 @@ endif ifneq ($(subdir-y),) $(subdir-y): FORCE - $(MAKE) -C $@ -f $(TOPDIR)/scripts/Makefile.build + $(MAKE) $(build)=$(obj)/$@ endif ######################################################################### @@ -78,18 +95,18 @@ ALL_CFLAGS += $(EXTRA_CPPFLAGS) # See rules.mk EXTRA_CPPFLAGS_DEP = $(CPPFLAGS_$(BCURDIR)/$(addsuffix .o,$(basename $<))) \ $(CPPFLAGS_$(BCURDIR)) -$(obj)%.s: %.S +$(obj)/%.s: $(src)/%.S $(CPP) $(ALL_AFLAGS) -o $@ $< -$(obj)%.o: %.S +$(obj)/%.o: $(src)/%.S $(CC) $(ALL_AFLAGS) -o $@ $< -c -$(obj)%.o: %.c +$(obj)/%.o: $(src)/%.c ifneq ($(CHECKSRC),0) $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $< endif $(CC) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.i: %.c +$(obj)/%.i: $(src)/%.c $(CPP) $(ALL_CFLAGS) -o $@ $< -c -$(obj)%.s: %.c +$(obj)/%.s: $(src)/%.c $(CC) $(ALL_CFLAGS) -o $@ $< -c -S # If the list of objects to link is empty, just create an empty built-in.o @@ -99,11 +116,11 @@ cmd_link_o_target = $(if $(strip $1),\ ######################################################################### -# defines $(obj).depend target +# defines $(obj)/.depend target include $(TOPDIR)/rules.mk -sinclude $(obj).depend +sinclude $(obj)/.depend ######################################################################### diff --git a/scripts/Makefile.host.tmp b/scripts/Makefile.host.tmp index 4b57846f4a3..53fe9300be7 100644 --- a/scripts/Makefile.host.tmp +++ b/scripts/Makefile.host.tmp @@ -21,11 +21,11 @@ host-objdirs += $(foreach f,$(host-cmulti), \ host-objdirs := $(strip $(sort $(filter-out ./,$(host-objdirs)))) -__hostprogs := $(addprefix $(obj),$(__hostprogs)) -host-csingle := $(addprefix $(obj),$(host-csingle)) -host-cmulti := $(addprefix $(obj),$(host-cmulti)) -host-cobjs := $(addprefix $(obj),$(host-cobjs)) -host-objdirs := $(addprefix $(obj),$(host-objdirs)) +__hostprogs := $(addprefix $(obj)/,$(__hostprogs)) +host-csingle := $(addprefix $(obj)/,$(host-csingle)) +host-cmulti := $(addprefix $(obj)/,$(host-cmulti)) +host-cobjs := $(addprefix $(obj)/,$(host-cobjs)) +host-objdirs := $(addprefix $(obj)/,$(host-objdirs)) obj-dirs += $(host-objdirs) @@ -49,13 +49,13 @@ hostc_flags = $(__hostc_flags) ##### # Compile programs on the host -$(host-csingle): $(obj)%: %.c +$(host-csingle): $(obj)/%: $(src)/%.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOSTLDFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -$(host-cmulti): $(obj)%: $(host-cobjs) - $(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj),$($(@F)-objs)) $(HOSTLOADLIBES_$(@F)) +$(host-cmulti): $(obj)/%: $(host-cobjs) + $(HOSTCC) $(HOSTLDFLAGS) -o $@ $(addprefix $(obj)/,$($(@F)-objs)) $(HOSTLOADLIBES_$(@F)) -$(host-cobjs): $(obj)%.o: %.c +$(host-cobjs): $(obj)/%.o: $(src)/%.c $(HOSTCC) $(HOSTCFLAGS) $(HOST_EXTRACFLAGS) $(HOSTCFLAGS_$(@F)) $(HOSTCFLAGS_$(BCURDIR)) -o $@ $< -c targets += $(host-csingle) $(host-cmulti) $(host-cobjs) diff --git a/spl/Makefile b/spl/Makefile index 8d0e6c3b313..18606ac34c7 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -14,6 +14,11 @@ # Based on top-level Makefile. # +src := $(obj) + +# Create output directory if not already present +_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) + include $(srctree)/scripts/Kbuild.include CONFIG_SPL_BUILD := y @@ -37,14 +42,6 @@ endif include $(TOPDIR)/config.mk -# We want the final binaries in this directory -ifeq ($(CONFIG_TPL_BUILD),y) -obj := $(OBJTREE)/tpl/ -SPLTREE := $(TPLTREE) -else -obj := $(OBJTREE)/spl/ -endif - HAVE_VENDOR_COMMON_LIB = $(if $(wildcard $(SRCTREE)/board/$(VENDOR)/common/Makefile),y,n) ifdef CONFIG_SPL_START_S_PATH @@ -113,11 +110,13 @@ PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) endif -START := $(addprefix $(SPLTREE)/,$(head-y)) -LIBS := $(addprefix $(SPLTREE)/,$(sort $(LIBS-y))) +LIBS-y := $(sort $(LIBS-y)) + +__START := $(head-y) +__LIBS := $(LIBS-y) -__START := $(subst $(obj),,$(START)) -__LIBS := $(subst $(obj),,$(LIBS)) +START := $(addprefix $(obj)/,$(head-y)) +LIBS := $(addprefix $(obj)/,$(LIBS-y)) # Linker Script ifdef CONFIG_SPL_LDSCRIPT @@ -148,21 +147,21 @@ LDPPFLAGS += \ $(shell $(LD) --version | \ sed -ne 's/GNU ld version \([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p') -$(OBJTREE)/MLO: $(obj)u-boot-spl.bin +$(OBJTREE)/MLO: $(obj)/u-boot-spl.bin $(OBJTREE)/tools/mkimage -T omapimage \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ -$(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin +$(OBJTREE)/MLO.byteswap: $(obj)/u-boot-spl.bin $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ -$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend - $(MAKE) $(build) $(SRCTREE)/arch/arm/imx-common $@ +$(objtree)/SPL : $(obj)/u-boot-spl.bin depend + $(MAKE) $(build)=spl/arch/arm/imx-common $@ -ALL-y += $(obj)$(SPL_BIN).bin +ALL-y += $(obj)/$(SPL_BIN).bin ifdef CONFIG_SAMSUNG -ALL-y += $(obj)$(BOARD)-spl.bin +ALL-y += $(obj)/$(BOARD)-spl.bin endif all: $(ALL-y) @@ -173,16 +172,16 @@ VAR_SIZE_PARAM = --vs else VAR_SIZE_PARAM = endif -$(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin +$(obj)/$(BOARD)-spl.bin: $(obj)/u-boot-spl.bin $(if $(wildcard $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl),\ $(OBJTREE)/spl/board/samsung/$(BOARD)/tools/mk$(BOARD)spl,\ $(OBJTREE)/tools/mkexynosspl) $(VAR_SIZE_PARAM) $< $@ endif -$(obj)$(SPL_BIN).bin: $(obj)$(SPL_BIN) +$(obj)/$(SPL_BIN).bin: $(obj)/$(SPL_BIN) $(OBJCOPY) $(OBJCFLAGS) $(SPL_OBJCFLAGS) -O binary $< $@ -LDFLAGS_$(SPL_BIN) += -T $(obj)u-boot-spl.lds $(LDFLAGS_FINAL) +LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif @@ -192,19 +191,19 @@ GEN_UBOOT = \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map $(SPL_BIN).map -o $(SPL_BIN) -$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds +$(obj)/$(SPL_BIN): depend $(START) $(LIBS) $(obj)/u-boot-spl.lds $(GEN_UBOOT) $(START): @: $(LIBS): depend - $(MAKE) $(build) $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)) + $(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) -$(obj)u-boot-spl.lds: $(LDSCRIPT) depend +$(obj)/u-boot-spl.lds: $(LDSCRIPT) depend $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ -depend: $(obj).depend +depend: $(obj)/.depend .PHONY: depend # defines $(obj).depend target diff --git a/tools/Makefile b/tools/Makefile index 21341b7aff5..9b19dcb2645 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -142,8 +142,8 @@ HOSTCFLAGS_sha1.o := -pedantic always := $(hostprogs-y) # Generated LCD/video logo -LOGO_H = $(OBJTREE)/include/bmp_logo.h -LOGO_DATA_H = $(OBJTREE)/include/bmp_logo_data.h +LOGO_H = $(objtree)/include/bmp_logo.h +LOGO_DATA_H = $(objtree)/include/bmp_logo_data.h LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_H) LOGO-$(CONFIG_LCD_LOGO) += $(LOGO_DATA_H) LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_H) @@ -151,14 +151,14 @@ LOGO-$(CONFIG_VIDEO_LOGO) += $(LOGO_DATA_H) # Generic logo ifeq ($(LOGO_BMP),) -LOGO_BMP= logos/denx.bmp +LOGO_BMP= $(srctree)/$(src)/logos/denx.bmp # Use board logo and fallback to vendor ifneq ($(wildcard logos/$(BOARD).bmp),) -LOGO_BMP= logos/$(BOARD).bmp +LOGO_BMP= $(srctree)/$(src)/logos/$(BOARD).bmp else ifneq ($(wildcard logos/$(VENDOR).bmp),) -LOGO_BMP= logos/$(VENDOR).bmp +LOGO_BMP= $(srctree)/$(src)/logos/$(VENDOR).bmp endif endif @@ -187,8 +187,8 @@ all: $(LOGO-y) subdir-y := kernel-doc -$(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-info $(LOGO_BMP) > $@ +$(LOGO_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-info $(LOGO_BMP) > $@ -$(LOGO_DATA_H): $(obj)bmp_logo $(LOGO_BMP) - $(obj)./bmp_logo --gen-data $(LOGO_BMP) > $@ +$(LOGO_DATA_H): $(obj)/bmp_logo $(LOGO_BMP) + $(obj)/bmp_logo --gen-data $(LOGO_BMP) > $@ -- cgit v1.2.3 From 6825a95b0ba72c4e5667d02d8b31986e2e9abd5a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 4 Feb 2014 17:24:28 +0900 Subject: kbuild: use Linux Kernel build scripts Now we are ready to switch over to real Kbuild. This commit disables temporary scripts: scripts/{Makefile.build.tmp, Makefile.host.tmp} and enables real Kbuild scripts: scripts/{Makefile.build,Makefile.host,Makefile.lib}. This switch is triggered by the line in scripts/Kbuild.include -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj We need to adjust some build scripts for U-Boot. But smaller amount of modification is preferable. Additionally, we need to fix compiler flags which are locally added or removed. In Kbuild, it is not allowed to change CFLAGS locally. Instead, ccflags-y, asflags-y, cppflags-y, CFLAGS_$(basetarget).o, CFLAGS_REMOVE_$(basetarget).o are prepared for that purpose. Signed-off-by: Masahiro Yamada Tested-by: Gerhard Sittig --- Makefile | 239 +++++++++++++++++++++----- arch/arm/imx-common/Makefile | 2 +- arch/blackfin/cpu/Makefile | 5 +- arch/blackfin/lib/Makefile | 5 +- arch/m68k/cpu/mcf5227x/Makefile | 2 +- arch/m68k/cpu/mcf523x/Makefile | 2 +- arch/m68k/cpu/mcf52x2/Makefile | 2 +- arch/m68k/cpu/mcf532x/Makefile | 2 +- arch/m68k/cpu/mcf5445x/Makefile | 2 +- arch/m68k/cpu/mcf547x_8x/Makefile | 2 +- arch/powerpc/cpu/mpc8xx/Makefile | 2 +- arch/powerpc/lib/Makefile | 4 +- arch/sandbox/cpu/Makefile | 11 +- board/bct-brettl2/config.mk | 7 +- board/bf518f-ezbrd/config.mk | 7 +- board/bf526-ezbrd/config.mk | 7 +- board/bf527-ad7160-eval/config.mk | 7 +- board/bf527-ezkit/config.mk | 7 +- board/bf527-sdp/config.mk | 7 +- board/bf533-ezkit/config.mk | 7 +- board/bf533-stamp/config.mk | 7 +- board/bf537-stamp/config.mk | 7 +- board/bf538f-ezkit/config.mk | 7 +- board/bf548-ezkit/config.mk | 7 +- board/bf561-acvilon/config.mk | 7 +- board/bf561-ezkit/config.mk | 7 +- board/br4/config.mk | 7 +- board/cm-bf527/config.mk | 7 +- board/cm-bf533/config.mk | 7 +- board/cm-bf537e/config.mk | 7 +- board/cm-bf537u/config.mk | 7 +- board/cm-bf548/config.mk | 7 +- board/cm-bf561/config.mk | 7 +- board/ip04/config.mk | 7 +- board/matrix_vision/mvblx/Makefile | 2 +- board/pr1/config.mk | 7 +- board/sandburst/karef/Makefile | 2 +- board/sandburst/metrobox/Makefile | 2 +- board/st-ericsson/snowball/Makefile | 2 +- board/st-ericsson/u8500/Makefile | 2 +- board/tcm-bf518/config.mk | 7 +- board/tcm-bf537/config.mk | 7 +- common/Makefile | 10 +- config.mk | 13 +- disk/Makefile | 2 +- doc/DocBook/Makefile | 67 ++++---- drivers/bios_emulator/Makefile | 5 +- drivers/hwmon/Makefile | 2 +- drivers/net/npe/Makefile | 4 +- drivers/rtc/Makefile | 2 +- drivers/usb/musb-new/Makefile | 7 +- dts/Makefile | 2 +- examples/api/Makefile | 15 +- examples/standalone/Makefile | 22 ++- fs/ubifs/Makefile | 2 +- fs/yaffs2/Makefile | 9 +- lib/Makefile | 2 +- lib/lzma/Makefile | 2 +- nand_spl/board/amcc/acadia/Makefile | 9 +- nand_spl/board/amcc/bamboo/Makefile | 9 +- nand_spl/board/amcc/canyonlands/Makefile | 9 +- nand_spl/board/amcc/kilauea/Makefile | 9 +- nand_spl/board/amcc/sequoia/Makefile | 9 +- nand_spl/board/freescale/mpc8315erdb/Makefile | 9 +- nand_spl/board/freescale/mpc8536ds/Makefile | 9 +- nand_spl/board/freescale/mpc8569mds/Makefile | 9 +- nand_spl/board/freescale/mpc8572ds/Makefile | 9 +- nand_spl/board/freescale/p1023rds/Makefile | 9 +- nand_spl/board/freescale/p1_p2_rdb/Makefile | 9 +- nand_spl/board/sheldon/simpc8313/Makefile | 9 +- net/Makefile | 2 +- post/lib_powerpc/fpu/Makefile | 29 ++-- scripts/Kbuild.include | 2 +- scripts/Makefile.build | 22 ++- scripts/Makefile.lib | 14 +- spl/Makefile | 27 +-- tools/Makefile | 23 +-- 77 files changed, 526 insertions(+), 325 deletions(-) (limited to 'drivers') diff --git a/Makefile b/Makefile index 1409c8bf398..4f00f08d314 100644 --- a/Makefile +++ b/Makefile @@ -43,6 +43,78 @@ else XECHO = : endif +# *DOCUMENTATION* +# To see a list of typical targets execute "make help" +# More info can be located in ./README +# Comments in this file are targeted only to the developer, do not +# expect to learn how to build the kernel reading this file. + +# Do not: +# o use make's built-in rules and variables +# (this increases performance and avoids hard-to-debug behaviour); +# o print "Entering directory ..."; +MAKEFLAGS += -rR --no-print-directory + +# Avoid funny character set dependencies +unexport LC_ALL +LC_COLLATE=C +LC_NUMERIC=C +export LC_COLLATE LC_NUMERIC + +# We are using a recursive build, so we need to do a little thinking +# to get the ordering right. +# +# Most importantly: sub-Makefiles should only ever modify files in +# their own directory. If in some directory we have a dependency on +# a file in another dir (which doesn't happen often, but it's often +# unavoidable when linking the built-in.o targets which finally +# turn into vmlinux), we will call a sub make in that other dir, and +# after that we are sure that everything which is in that other dir +# is now up to date. +# +# The only cases where we need to modify files which have global +# effects are thus separated out and done before the recursive +# descending is started. They are now explicitly listed as the +# prepare rule. + +# To put more focus on warnings, be less verbose as default +# Use 'make V=1' to see the full commands + +ifeq ("$(origin V)", "command line") + KBUILD_VERBOSE = $(V) +endif +ifndef KBUILD_VERBOSE + KBUILD_VERBOSE = 0 +endif + +# Call a source code checker (by default, "sparse") as part of the +# C compilation. +# +# Use 'make C=1' to enable checking of only re-compiled files. +# Use 'make C=2' to enable checking of *all* source files, regardless +# of whether they are re-compiled or not. +# +# See the file "Documentation/sparse.txt" for more details, including +# where to get the "sparse" utility. + +ifeq ("$(origin C)", "command line") + KBUILD_CHECKSRC = $(C) +endif +ifndef KBUILD_CHECKSRC + KBUILD_CHECKSRC = 0 +endif + +# Use make M=dir to specify directory of external module to build +# Old syntax make ... SUBDIRS=$PWD is still supported +# Setting the environment variable KBUILD_EXTMOD take precedence +ifdef SUBDIRS + KBUILD_EXTMOD ?= $(SUBDIRS) +endif + +ifeq ("$(origin M)", "command line") + KBUILD_EXTMOD := $(M) +endif + # kbuild supports saving output files in a separate directory. # To locate output files in a separate directory two syntaxes are supported. # In both cases the working directory must be the root of the kernel src. @@ -107,8 +179,14 @@ endif # ifeq ($(KBUILD_SRC),) # We process the rest of the Makefile if this is the final invocation of make ifeq ($(skip-makefile),) +# If building an external module we do not care about the all: rule +# but instead _all depend on modules PHONY += all +ifeq ($(KBUILD_EXTMOD),) _all: all +else +_all: modules +endif srctree := $(if $(KBUILD_SRC),$(KBUILD_SRC),$(CURDIR)) objtree := $(CURDIR) @@ -119,24 +197,6 @@ VPATH := $(srctree)$(if $(KBUILD_EXTMOD),:$(KBUILD_EXTMOD)) export srctree objtree VPATH -# Call a source code checker (by default, "sparse") as part of the -# C compilation. -# -# Use 'make C=1' to enable checking of re-compiled files. -# -# See the linux kernel file "Documentation/sparse.txt" for more details, -# including where to get the "sparse" utility. - -ifdef C -ifeq ("$(origin C)", "command line") -CHECKSRC := $(C) -endif -endif -ifndef CHECKSRC - CHECKSRC = 0 -endif -export CHECKSRC - OBJTREE := $(objtree) SPLTREE := $(OBJTREE)/spl TPLTREE := $(OBJTREE)/tpl @@ -222,6 +282,78 @@ HOSTCFLAGS += $(call os_x_before, 10, 4, "-traditional-cpp") HOSTLDFLAGS += $(call os_x_before, 10, 5, "-multiply_defined suppress") endif +# Decide whether to build built-in, modular, or both. +# Normally, just do built-in. + +KBUILD_MODULES := +KBUILD_BUILTIN := 1 + +# If we have only "make modules", don't compile built-in objects. +# When we're building modules with modversions, we need to consider +# the built-in objects during the descend as well, in order to +# make sure the checksums are up to date before we record them. + +ifeq ($(MAKECMDGOALS),modules) + KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1) +endif + +# If we have "make modules", compile modules +# in addition to whatever we do anyway. +# Just "make" or "make all" shall build modules as well + +# U-Boot does not need modules +#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),) +# KBUILD_MODULES := 1 +#endif + +#ifeq ($(MAKECMDGOALS),) +# KBUILD_MODULES := 1 +#endif + +export KBUILD_MODULES KBUILD_BUILTIN +export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD + +# Beautify output +# --------------------------------------------------------------------------- +# +# Normally, we echo the whole command before executing it. By making +# that echo $($(quiet)$(cmd)), we now have the possibility to set +# $(quiet) to choose other forms of output instead, e.g. +# +# quiet_cmd_cc_o_c = Compiling $(RELDIR)/$@ +# cmd_cc_o_c = $(CC) $(c_flags) -c -o $@ $< +# +# If $(quiet) is empty, the whole command will be printed. +# If it is set to "quiet_", only the short version will be printed. +# If it is set to "silent_", nothing will be printed at all, since +# the variable $(silent_cmd_cc_o_c) doesn't exist. +# +# A simple variant is to prefix commands with $(Q) - that's useful +# for commands that shall be hidden in non-verbose mode. +# +# $(Q)ln $@ :< +# +# If KBUILD_VERBOSE equals 0 then the above command will be hidden. +# If KBUILD_VERBOSE equals 1 then the above command is displayed. + +ifeq ($(KBUILD_VERBOSE),1) + quiet = + Q = +else + quiet=quiet_ + Q = @ +endif + +# If the user is running make -s (silent mode), suppress echoing of +# commands + +ifneq ($(filter s% -s%,$(MAKEFLAGS)),) + quiet=silent_ +endif + +export quiet Q KBUILD_VERBOSE + + # Look for make include files relative to root of kernel src MAKEFLAGS += --include-dir=$(srctree) @@ -278,6 +410,31 @@ export DTC CHECK CHECKFLAGS export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE export KBUILD_CFLAGS KBUILD_AFLAGS +# When compiling out-of-tree modules, put MODVERDIR in the module +# tree rather than in the kernel tree. The kernel tree might +# even be read-only. +export MODVERDIR := $(if $(KBUILD_EXTMOD),$(firstword $(KBUILD_EXTMOD))/).tmp_versions + +# Files to ignore in find ... statements + +RCS_FIND_IGNORE := \( -name SCCS -o -name BitKeeper -o -name .svn -o -name CVS \ + -o -name .pc -o -name .hg -o -name .git \) -prune -o +export RCS_TAR_IGNORE := --exclude SCCS --exclude BitKeeper --exclude .svn \ + --exclude CVS --exclude .pc --exclude .hg --exclude .git + +# =========================================================================== +# Rules shared between *config targets and build targets + +# Basic helpers built in scripts/ +PHONY += scripts_basic +scripts_basic: + $(Q)$(MAKE) $(build)=scripts/basic + $(Q)rm -f .tmp_quiet_recordmcount + +# To avoid any implicit rule to kick in, define an empty command. +scripts/basic/%: scripts_basic ; + + KBUILD_CFLAGS += -Os #-fomit-frame-pointer ifdef BUILD_TAG @@ -333,6 +490,10 @@ endif endif endif +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS) +c_flags := $(KBUILD_CFLAGS) $(cpp_flags) + # If board code explicitly specified LDSCRIPT or CONFIG_SYS_LDSCRIPT, use # that (or fail if absent). Otherwise, search for a linker script in a # standard location. @@ -446,12 +607,12 @@ LIBS := $(sort $(LIBS-y)) # Add GCC lib ifdef USE_PRIVATE_LIBGCC ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/libgcc.o +PLATFORM_LIBGCC = $(OBJTREE)/arch/$(ARCH)/lib/lib.a else PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc endif else -PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(c_flags) -print-libgcc-file-name`) -lgcc endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS @@ -701,7 +862,7 @@ u-boot: depend $(SUBDIR_TOOLS) $(OBJS) $(LIBS) u-boot.lds ifeq ($(CONFIG_KALLSYMS),y) smap=`$(call SYSTEM_MAP,u-boot) | \ awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\\\000"}'` ; \ - $(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" \ + $(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \ -c $(srctree)/common/system_map.c -o common/system_map.o $(GEN_UBOOT) common/system_map.o endif @@ -709,27 +870,27 @@ endif $(OBJS): @: -$(LIBS): depend $(SUBDIR_TOOLS) - $(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) +$(LIBS): depend $(SUBDIR_TOOLS) scripts_basic + $(Q)$(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) -$(SUBDIRS): depend - $(MAKE) $(build)=$@ all +$(SUBDIRS): depend scripts_basic + $(Q)$(MAKE) $(build)=$@ $(SUBDIR_EXAMPLES-y): u-boot u-boot.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@ -nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend +nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend scripts_basic $(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all u-boot-nand.bin: nand_spl u-boot.bin cat nand_spl/u-boot-spl-16k.bin u-boot.bin > u-boot-nand.bin -spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend +spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend scripts_basic $(MAKE) obj=spl -f $(srctree)/spl/Makefile all -tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend +tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend scripts_basic $(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y # Explicitly make _depend in subdirs containing multiple targets to prevent @@ -804,14 +965,14 @@ checkdtc: include/autoconf.mk.dep: include/config.h include/common.h @$(XECHO) Generating $@ ; \ : Generate the dependancies ; \ - $(CC) -x c -DDO_DEPS_ONLY -M $(CFLAGS) $(CPPFLAGS) \ + $(CC) -x c -DDO_DEPS_ONLY -M $(c_flags) \ -MQ include/autoconf.mk $(srctree)/include/common.h > $@ || \ rm $@ include/autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp @@ -819,7 +980,7 @@ include/autoconf.mk: include/config.h include/tpl-autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\ + $(CPP) $(c_flags) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\ -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp @@ -827,7 +988,7 @@ include/tpl-autoconf.mk: include/config.h include/spl-autoconf.mk: include/config.h @$(XECHO) Generating $@ ; \ : Extract the config macros ; \ - $(CPP) $(CFLAGS) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ + $(CPP) $(c_flags) -DCONFIG_SPL_BUILD -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && \ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp > $@; \ rm $@.tmp @@ -838,7 +999,7 @@ include/generated/generic-asm-offsets.h: lib/asm-offsets.s lib/asm-offsets.s: include/config.h $(srctree)/lib/asm-offsets.c @mkdir -p lib $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + $(c_flags) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ -o $@ $(srctree)/lib/asm-offsets.c -c -S include/generated/asm-offsets.h: $(CPUDIR)/$(SOC)/asm-offsets.s @@ -849,7 +1010,7 @@ $(CPUDIR)/$(SOC)/asm-offsets.s: include/config.h @mkdir -p $(CPUDIR)/$(SOC) if [ -f $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c ];then \ $(CC) -DDO_DEPS_ONLY \ - $(CFLAGS) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ + $(c_flags) $(CFLAGS_$(BCURDIR)/$(@F)) $(CFLAGS_$(BCURDIR)) \ -o $@ $(srctree)/$(CPUDIR)/$(SOC)/asm-offsets.c -c -S; \ else \ touch $@; \ @@ -900,15 +1061,15 @@ $(TIMESTAMP_FILE): @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ easylogo env gdb: - $(MAKE) $(build)=tools/$@ MTD_VERSION=${MTD_VERSION} + $(Q)$(MAKE) $(build)=tools/$@ MTD_VERSION=${MTD_VERSION} gdbtools: gdb xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc - $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) $(build)=doc/DocBook $@ + $(Q)$(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) $(build)=doc/DocBook $@ tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE) - $(MAKE) $(build)=tools HOST_TOOLS_ALL=y + $(Q)$(MAKE) $(build)=tools HOST_TOOLS_ALL=y .PHONY : CHANGELOG CHANGELOG: @@ -968,7 +1129,7 @@ clean: @$(MAKE) -f $(srctree)/doc/DocBook/Makefile cleandocs @find $(OBJTREE) -type f \ \( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \ - -o -name '*.o' -o -name '*.a' -o -name '*.exe' \ + -o -name '*.o' -o -name '*.a' -o -name '*.exe' -o -name '*.cmd' \ -o -name '*.cfgtmp' \) -print \ | xargs rm -f diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile index ee5c872f51e..9dda59df04b 100644 --- a/arch/arm/imx-common/Makefile +++ b/arch/arm/imx-common/Makefile @@ -25,7 +25,7 @@ obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/% mkdir -p $(dir $@) - $(CC) -E -x c $< $(CPPFLAGS) -o $@ + $(CPP) $(cpp_flags) -x c -o $@ $< $(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp $(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \ diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile index 369dc74e947..dd4d2d13e0e 100644 --- a/arch/blackfin/cpu/Makefile +++ b/arch/blackfin/cpu/Makefile @@ -25,7 +25,7 @@ extra-y += check_initcode # make sure our initcode (which goes into LDR) does not # have relocs or external references -$(obj)/initcode.o: CFLAGS += -fno-function-sections -fno-data-sections +CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $< $(obj)/check_initcode: $(obj)/initcode.o ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) @@ -35,7 +35,6 @@ ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS) fi endif -$(obj)/init.lds: $(src)/init.lds.S - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P $^ -o $@ +CPPFLAGS_init.lds := -ansi $(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o $(LD) $(LDFLAGS) -T $^ -o $@ diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile index a5c552f38a6..4ba7bf69493 100644 --- a/arch/blackfin/lib/Makefile +++ b/arch/blackfin/lib/Makefile @@ -9,7 +9,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -DBFIN_BOARD_NAME='"$(BOARD)"' +# Unnecessary. +# Use CONFIG_SYS_BOARD instead of BFIN_BOARD_NAME +# and delete this. +ccflags-y += -DBFIN_BOARD_NAME='"$(BOARD)"' obj-y += ins.o obj-y += memcmp.o diff --git a/arch/m68k/cpu/mcf5227x/Makefile b/arch/m68k/cpu/mcf5227x/Makefile index a47fd56739d..e0c5db60f4e 100644 --- a/arch/m68k/cpu/mcf5227x/Makefile +++ b/arch/m68k/cpu/mcf5227x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf523x/Makefile b/arch/m68k/cpu/mcf523x/Makefile index a47fd56739d..e0c5db60f4e 100644 --- a/arch/m68k/cpu/mcf523x/Makefile +++ b/arch/m68k/cpu/mcf523x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf52x2/Makefile b/arch/m68k/cpu/mcf52x2/Makefile index d9bf9008ecc..b92fd864c4d 100644 --- a/arch/m68k/cpu/mcf52x2/Makefile +++ b/arch/m68k/cpu/mcf52x2/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = interrupts.o cpu.o speed.o cpu_init.o diff --git a/arch/m68k/cpu/mcf532x/Makefile b/arch/m68k/cpu/mcf532x/Makefile index 97aa3f16a9f..9c53c50c487 100644 --- a/arch/m68k/cpu/mcf532x/Makefile +++ b/arch/m68k/cpu/mcf532x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y := start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o diff --git a/arch/m68k/cpu/mcf5445x/Makefile b/arch/m68k/cpu/mcf5445x/Makefile index b506719c8f0..9be91ed1572 100644 --- a/arch/m68k/cpu/mcf5445x/Makefile +++ b/arch/m68k/cpu/mcf5445x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o interrupts.o pci.o diff --git a/arch/m68k/cpu/mcf547x_8x/Makefile b/arch/m68k/cpu/mcf547x_8x/Makefile index 0fa50bfccd8..4f82099b6b2 100644 --- a/arch/m68k/cpu/mcf547x_8x/Makefile +++ b/arch/m68k/cpu/mcf547x_8x/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y = start.o obj-y = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index d40bdab1e14..f83fd5ecf4d 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DET_DEBUG +# ccflags-y += -DET_DEBUG extra-y += start.o extra-y += traps.o diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index ac780d4077f..e6d8be51cae 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -54,11 +54,11 @@ ifndef CONFIG_SPL_BUILD # Workaround for local bus unaligned access problems # on MPC512x and MPC5200 ifdef CONFIG_MPC512X -$(obj)/ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif ifdef CONFIG_MPC5200 -$(obj)/ppcstring.o: AFLAGS += -Dmemcpy=__memcpy +AFLAGS_ppcstring.o += -Dmemcpy=__memcpy obj-y += memcpy_mpc5200.o endif endif diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index c5f5426b05f..63dededf70f 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -10,7 +10,10 @@ obj-y := cpu.o os.o start.o state.o # os.c is build in the system environment, so needs standard includes -$(obj)/os.o: CFLAGS := $(filter-out -nostdinc,\ - $(patsubst -I%,-idirafter%,$(CFLAGS))) -$(obj)/.depend.os: CPPFLAGS := $(filter-out -nostdinc,\ - $(patsubst -I%,-idirafter%,$(CPPFLAGS))) +# CFLAGS_REMOVE_os.o cannot be used to drop header include path +quiet_cmd_cc_os.o = CC $(quiet_modtag) $@ +cmd_cc_os.o = $(CC) $(filter-out -nostdinc, \ + $(patsubst -I%,-idirafter%,$(c_flags))) -c -o $@ $< + +$(obj)/os.o: $(src)/os.c FORCE + $(call if_changed_dep,cc_os.o) diff --git a/board/bct-brettl2/config.mk b/board/bct-brettl2/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/bct-brettl2/config.mk +++ b/board/bct-brettl2/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/bf518f-ezbrd/config.mk b/board/bf518f-ezbrd/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/bf518f-ezbrd/config.mk +++ b/board/bf518f-ezbrd/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/bf526-ezbrd/config.mk b/board/bf526-ezbrd/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/bf526-ezbrd/config.mk +++ b/board/bf526-ezbrd/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/bf527-ad7160-eval/config.mk +++ b/board/bf527-ad7160-eval/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/bf527-ezkit/config.mk b/board/bf527-ezkit/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/bf527-ezkit/config.mk +++ b/board/bf527-ezkit/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/bf527-sdp/config.mk b/board/bf527-sdp/config.mk index 5f327a990e1..af299f5f1e1 100644 --- a/board/bf527-sdp/config.mk +++ b/board/bf527-sdp/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 6 diff --git a/board/bf533-ezkit/config.mk b/board/bf533-ezkit/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/bf533-ezkit/config.mk +++ b/board/bf533-ezkit/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf533-stamp/config.mk b/board/bf533-stamp/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/bf533-stamp/config.mk +++ b/board/bf533-stamp/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf537-stamp/config.mk b/board/bf537-stamp/config.mk index ae2ea0b7476..bc0e7476e50 100644 --- a/board/bf537-stamp/config.mk +++ b/board/bf537-stamp/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf538f-ezkit/config.mk b/board/bf538f-ezkit/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/bf538f-ezkit/config.mk +++ b/board/bf538f-ezkit/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/bf548-ezkit/config.mk b/board/bf548-ezkit/config.mk index ad3a7293dfe..8d2c60f308c 100644 --- a/board/bf548-ezkit/config.mk +++ b/board/bf548-ezkit/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 diff --git a/board/bf561-acvilon/config.mk b/board/bf561-acvilon/config.mk index c33aef9d283..ce947155722 100644 --- a/board/bf561-acvilon/config.mk +++ b/board/bf561-acvilon/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/bf561-ezkit/config.mk b/board/bf561-ezkit/config.mk index c33aef9d283..ce947155722 100644 --- a/board/bf561-ezkit/config.mk +++ b/board/bf561-ezkit/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/br4/config.mk b/board/br4/config.mk index 5c18d5c9e46..2436ec07f43 100644 --- a/board/br4/config.mk +++ b/board/br4/config.mk @@ -9,6 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/cm-bf527/config.mk b/board/cm-bf527/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/cm-bf527/config.mk +++ b/board/cm-bf527/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/cm-bf533/config.mk b/board/cm-bf533/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/cm-bf533/config.mk +++ b/board/cm-bf533/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537e/config.mk b/board/cm-bf537e/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/cm-bf537e/config.mk +++ b/board/cm-bf537e/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/cm-bf537u/config.mk +++ b/board/cm-bf537u/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/cm-bf548/config.mk b/board/cm-bf548/config.mk index c005afb881f..289c8a488e0 100644 --- a/board/cm-bf548/config.mk +++ b/board/cm-bf548/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --dma 6 diff --git a/board/cm-bf561/config.mk b/board/cm-bf561/config.mk index c33aef9d283..ce947155722 100644 --- a/board/cm-bf561/config.mk +++ b/board/cm-bf561/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 diff --git a/board/ip04/config.mk b/board/ip04/config.mk index ae2ea0b7476..bc0e7476e50 100644 --- a/board/ip04/config.mk +++ b/board/ip04/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/board/matrix_vision/mvblx/Makefile b/board/matrix_vision/mvblx/Makefile index c6c09339562..c056ebaf781 100644 --- a/board/matrix_vision/mvblx/Makefile +++ b/board/matrix_vision/mvblx/Makefile @@ -8,4 +8,4 @@ obj-y += mvblx.o fpga.o obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o -CFLAGS += -Werror +ccflags-y += -Werror diff --git a/board/pr1/config.mk b/board/pr1/config.mk index 5c18d5c9e46..2436ec07f43 100644 --- a/board/pr1/config.mk +++ b/board/pr1/config.mk @@ -9,6 +9,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile index f890008be22..d5a9b34f1d2 100644 --- a/board/sandburst/karef/Makefile +++ b/board/sandburst/karef/Makefile @@ -13,7 +13,7 @@ BUILDUSER := $(shell whoami) FORCEBUILD := $(shell rm -f karef.o) -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +ccflags-y += -DBUILDUSER='"$(BUILDUSER)"' # TBS: end debugging obj-y = karef.o ../common/flash.o ../common/sb_common.o diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile index 37d91a51a3a..8121cce514d 100644 --- a/board/sandburst/metrobox/Makefile +++ b/board/sandburst/metrobox/Makefile @@ -12,7 +12,7 @@ BUILDUSER := $(shell whoami) FORCEBUILD := $(shell rm -f metrobox.o) -CFLAGS += -DBUILDUSER='"$(BUILDUSER)"' +ccflags-y += -DBUILDUSER='"$(BUILDUSER)"' # TBS: end debugging obj-y = metrobox.o ../common/flash.o ../common/sb_common.o diff --git a/board/st-ericsson/snowball/Makefile b/board/st-ericsson/snowball/Makefile index 6867a70b7cf..f0605e2bcd3 100644 --- a/board/st-ericsson/snowball/Makefile +++ b/board/st-ericsson/snowball/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D__RELEASE -D__STN_8500 +ccflags-y += -D__RELEASE -D__STN_8500 obj-y := snowball.o diff --git a/board/st-ericsson/u8500/Makefile b/board/st-ericsson/u8500/Makefile index b9dfbe93595..d6c4280475a 100644 --- a/board/st-ericsson/u8500/Makefile +++ b/board/st-ericsson/u8500/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D__RELEASE -D__STN_8500 +ccflags-y += -D__RELEASE -D__STN_8500 obj-y := u8500_href.o gpio.o diff --git a/board/tcm-bf518/config.mk b/board/tcm-bf518/config.mk index f1ef9bf682d..0d3df2dbd90 100644 --- a/board/tcm-bf518/config.mk +++ b/board/tcm-bf518/config.mk @@ -7,6 +7,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif diff --git a/board/tcm-bf537/config.mk b/board/tcm-bf537/config.mk index 973d3575593..97eaafef2e2 100644 --- a/board/tcm-bf537/config.mk +++ b/board/tcm-bf537/config.mk @@ -7,9 +7,10 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS_lib += -O2 -CFLAGS_lib/lzma += -O2 -CFLAGS_lib/zlib += -O2 +# FIX ME +ifneq ($(filter lib lib/lzma lib/zlib, $(obj)),) +ccflags-y := -O2 +endif # Set some default LDR flags based on boot mode. LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8 diff --git a/common/Makefile b/common/Makefile index 2d758436284..3b2ff9bb529 100644 --- a/common/Makefile +++ b/common/Makefile @@ -238,10 +238,6 @@ obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o obj-y += memsize.o obj-y += stdio.o -$(obj)/env_embedded.o: $(src)/env_embedded.c - $(CC) $(AFLAGS) -Wa,--no-warn \ - -DENV_CRC=$(shell tools/envcrc) -c -o $@ $< - -# SEE README.arm-unaligned-accesses -$(obj)/hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) -$(obj)/fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) +CFLAGS_hush.o := $(PLATFORM_NO_UNALIGNED) +CFLAGS_fdt_support.o := $(PLATFORM_NO_UNALIGNED) diff --git a/config.mk b/config.mk index 0fa316743ce..1336ef871c0 100644 --- a/config.mk +++ b/config.mk @@ -58,19 +58,10 @@ RELFLAGS= $(PLATFORM_RELFLAGS) OBJCFLAGS += --gap-fill=0xff -CPPFLAGS = $(KBUILD_CPPFLAGS) $(RELFLAGS) -CPPFLAGS += $(UBOOTINCLUDE) -CPPFLAGS += $(NOSTDINC_FLAGS) -pipe $(PLATFORM_CPPFLAGS) - -CFLAGS := $(KBUILD_CFLAGS) $(CPPFLAGS) +CPPFLAGS = $(RELFLAGS) +CPPFLAGS += -pipe $(PLATFORM_CPPFLAGS) BCURDIR = $(subst $(SRCTREE)/,,$(CURDIR:$(obj)%=%)) -AFLAGS := $(KBUILD_AFLAGS) $(CPPFLAGS) - LDFLAGS += $(PLATFORM_LDFLAGS) LDFLAGS_FINAL += -Bstatic - -######################################################################### - -export PLATFORM_CPPFLAGS PLATFORM_RELFLAGS CPPFLAGS CFLAGS AFLAGS diff --git a/disk/Makefile b/disk/Makefile index 48abec8328e..6970cecc71a 100644 --- a/disk/Makefile +++ b/disk/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DET_DEBUG -DDEBUG +#ccflags-y += -DET_DEBUG -DDEBUG obj-$(CONFIG_PARTITIONS) += part.o obj-$(CONFIG_MAC_PARTITION) += part_mac.o diff --git a/doc/DocBook/Makefile b/doc/DocBook/Makefile index aa7c44b127c..75e59c2b0df 100644 --- a/doc/DocBook/Makefile +++ b/doc/DocBook/Makefile @@ -24,9 +24,9 @@ PS_METHOD = $(prefer-db2x) ### # The targets that may be used. -PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs +PHONY += xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs -BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS)) +BOOKS := $(addprefix $(obj)/,$(DOCBOOKS)) xmldocs: $(BOOKS) sgmldocs: xmldocs @@ -51,10 +51,10 @@ installmandocs: mandocs ### #External programs used -KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc -DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc +KERNELDOC = $(srctree)/tools/kernel-doc/kernel-doc +DOCPROC = $(objtree)/tools/kernel-doc/docproc -XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl +XMLTOFLAGS = -m $(srctree)/doc/DocBook/stylesheet.xsl XMLTOFLAGS += --skip-validation ### @@ -64,28 +64,36 @@ XMLTOFLAGS += --skip-validation # appropriate parameters. # The following rules are used to generate the .xml documentation # required to generate the final targets. (ps, pdf, html). -%.xml: %.tmpl - $(DOCPROC) doc $< >$@ - -ifeq ($@, "cleandocs") -sinclude $(obj).depend -$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS)) - rm -f $(obj).depend ; \ - touch $(obj).depend ; \ - for file in $^ ; do \ - xmlfile=`echo "$${file}" | \ - sed "s/tmpl$$/xml/"` ; \ - echo -n "$${xmlfile}: ">> $(obj).depend ; \ - $(DOCPROC) depend $$file >> $(obj).depend ; \ - echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \ - $(obj).depend ; \ - done +quiet_cmd_docproc = DOCPROC $@ + cmd_docproc = SRCTREE=$(srctree)/ $(DOCPROC) doc $< >$@ +define rule_docproc + set -e; \ + $(if $($(quiet)cmd_$(1)),echo ' $($(quiet)cmd_$(1))';) \ + $(cmd_$(1)); \ + ( \ + echo 'cmd_$@ := $(cmd_$(1))'; \ + echo $@: `SRCTREE=$(srctree) $(DOCPROC) depend $<`; \ + ) > $(dir $@).$(notdir $@).cmd +endef + +%.xml: %.tmpl FORCE + $(call if_changed_rule,docproc) + +### +#Read in all saved dependency files +cmd_files := $(wildcard $(foreach f,$(BOOKS),$(dir $(f)).$(notdir $(f)).cmd)) + +ifneq ($(cmd_files),) + include $(cmd_files) endif ### # Changes in kernel-doc force a rebuild of all documentation $(BOOKS): $(KERNELDOC) +# Tell kbuild to always build the programs +always := $(hostprogs-y) + notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \ exit 1 db2xtemplate = db2TYPE -o $(dir $@) $< @@ -111,12 +119,12 @@ endif quiet_cmd_db2ps = PS $@ cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template)) %.ps : %.xml - $(call cmd_db2ps) + $(call cmd,db2ps) quiet_cmd_db2pdf = PDF $@ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template)) %.pdf : %.xml - $(call cmd_db2pdf) + $(call cmd,db2pdf) index = index.html @@ -132,16 +140,16 @@ build_main_index = rm -rf $(main_idx); \ quiet_cmd_db2html = HTML $@ cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \ echo ' \ - $(patsubst %.html,%,$(notdir $@))

' > $@ + $(patsubst %.html,%,$(notdir $@))

' > $@ %.html: %.xml @(which xmlto > /dev/null 2>&1) || \ (echo "*** You need to install xmlto ***"; \ exit 1) @rm -rf $@ $(patsubst %.html,%,$@) - $(call cmd_db2html) + $(call cmd,db2html) @if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \ - cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi + cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi quiet_cmd_db2man = MAN $@ cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi @@ -150,7 +158,7 @@ quiet_cmd_db2man = MAN $@ (echo "*** You need to install xmlto ***"; \ exit 1) $(Q)mkdir -p $(obj)/man - $(call cmd_db2man) + $(call cmd,db2man) @touch $@ ### @@ -162,7 +170,7 @@ quiet_cmd_fig2eps = FIG2EPS $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2eps) + $(call cmd,fig2eps) quiet_cmd_fig2png = FIG2PNG $@ cmd_fig2png = fig2dev -Lpng $< $@ @@ -171,7 +179,7 @@ quiet_cmd_fig2png = FIG2PNG $@ @(which fig2dev > /dev/null 2>&1) || \ (echo "*** You need to install transfig ***"; \ exit 1) - $(call cmd_fig2png) + $(call cmd,fig2png) ### # Rule to convert a .c file to inline XML documentation @@ -217,7 +225,6 @@ clean-files := $(DOCBOOKS) \ clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man cleandocs: - @rm -f $(obj).depend @$(Q)rm -f $(call objectify, $(clean-files)) @$(Q)rm -rf $(call objectify, $(clean-dirs)) diff --git a/drivers/bios_emulator/Makefile b/drivers/bios_emulator/Makefile index 330f36f3bd2..e56356ee867 100644 --- a/drivers/bios_emulator/Makefile +++ b/drivers/bios_emulator/Makefile @@ -8,8 +8,5 @@ obj-y = atibios.o biosemu.o besys.o bios.o \ $(X86DIR)/sys.o \ $(X86DIR)/debug.o -EXTRA_CFLAGS += -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ +ccflags-y := -I$(srctree)/$(src) -I$(srctree)/$(src)/include \ -D__PPC__ -D__BIG_ENDIAN__ - -CFLAGS += $(EXTRA_CFLAGS) -CPPFLAGS += $(EXTRA_CFLAGS) diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index a78a7242534..25b8e8a2d79 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -8,7 +8,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_DTT_ADM1021) += adm1021.o obj-$(CONFIG_DTT_ADT7460) += adt7460.o diff --git a/drivers/net/npe/Makefile b/drivers/net/npe/Makefile index 07792552167..ff554cf1523 100644 --- a/drivers/net/npe/Makefile +++ b/drivers/net/npe/Makefile @@ -5,9 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -LOCAL_CFLAGS += -I$(TOPDIR)/drivers/net/npe/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux -CFLAGS += $(LOCAL_CFLAGS) -CPPFLAGS += $(LOCAL_CFLAGS) # needed for depend +ccflags-y += -I$(src)/include -DCONFIG_IXP425_COMPONENT_ETHDB -D__linux obj-y := npe.o \ miiphy.o \ diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index d5a2725c971..003d322d23a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -#CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_RTC_AT91SAM9_RTT) += at91sam9_rtt.o obj-$(CONFIG_RTC_BFIN) += bfin_rtc.o diff --git a/drivers/usb/musb-new/Makefile b/drivers/usb/musb-new/Makefile index ba72348b76a..3facf0fc105 100644 --- a/drivers/usb/musb-new/Makefile +++ b/drivers/usb/musb-new/Makefile @@ -9,7 +9,6 @@ obj-$(CONFIG_USB_MUSB_DSPS) += musb_dsps.o obj-$(CONFIG_USB_MUSB_AM35X) += am35x.o obj-$(CONFIG_USB_MUSB_OMAP2PLUS) += omap2430.o -CFLAGS_NO_WARN := $(call cc-option,-Wno-unused-variable) \ - $(call cc-option,-Wno-unused-but-set-variable) \ - $(call cc-option,-Wno-unused-label) -CFLAGS += $(CFLAGS_NO_WARN) +ccflags-y := $(call cc-option,-Wno-unused-variable) \ + $(call cc-option,-Wno-unused-but-set-variable) \ + $(call cc-option,-Wno-unused-label) diff --git a/dts/Makefile b/dts/Makefile index d81f32d914d..cc6ecf66eb5 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -36,7 +36,7 @@ process_lds = \ $(1) | sed -r -n 's/^OUTPUT_$(2)[ ("]*([^")]*).*/\1/p' # Run the compiler and get the link script from the linker -GET_LDS = $(CC) $(CFLAGS) $(LDFLAGS) -Wl,--verbose 2>&1 +GET_LDS = $(CC) $(c_flags) $(ld_flags) -Wl,--verbose 2>&1 $(obj)/dt.o: $(DT_BIN) # We want the output format and arch. diff --git a/examples/api/Makefile b/examples/api/Makefile index db0bb34afeb..8b798860745 100644 --- a/examples/api/Makefile +++ b/examples/api/Makefile @@ -5,7 +5,7 @@ # ifdef FTRACE -CFLAGS += -finstrument-functions -DFTRACE +ccflags-y += -finstrument-functions -DFTRACE endif ifeq ($(ARCH),powerpc) @@ -33,12 +33,6 @@ EXT_COBJ_FILES-y += lib/time.o EXT_COBJ_FILES-y += lib/vsprintf.o EXT_SOBJ_FILES-$(CONFIG_PPC) += arch/powerpc/lib/ppcstring.o -# Create a list of source files so their dependencies can be auto-generated -SRCS += $(addprefix $(SRCTREE)/,$(EXT_COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/,$(EXT_SOBJ_FILES-y:.o=.S)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(COBJ_FILES-y:.o=.c)) -SRCS += $(addprefix $(SRCTREE)/examples/api/,$(SOBJ_FILES-y:.o=.S)) - # Create a list of object files to be compiled OBJS += $(addprefix $(obj)/,$(SOBJ_FILES-y)) OBJS += $(addprefix $(obj)/,$(COBJ_FILES-y)) @@ -54,9 +48,10 @@ $(obj)/demo.bin: $(obj)/demo $(OBJCOPY) -O binary $< $@ 2>/dev/null # Rule to build generic library C files -$(addprefix $(obj)/,$(notdir $(EXT_COBJ_FILES-y))): $(obj)/%.o: $(SRCTREE)/lib/%.c - $(CC) -g $(CFLAGS) -c -o $@ $< +$(addprefix $(obj)/,$(notdir $(EXT_COBJ_FILES-y))): $(obj)/%.o: $(SRCTREE)/lib/%.c FORCE + $(call cmd,force_checksrc) + $(call if_changed_rule,cc_o_c) # Rule to build architecture-specific library assembly files $(addprefix $(obj)/,$(notdir $(EXT_SOBJ_FILES-y))): $(obj)/%.o: $(SRCTREE)/arch/$(ARCH)/lib/%.S - $(CC) -g $(CFLAGS) -c -o $@ $< + $(call if_changed_dep,as_o_S) diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index a6819f77929..90e173b83ee 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -6,7 +6,7 @@ # ifdef FTRACE -CFLAGS += -finstrument-functions -DFTRACE +ccflags-y += -finstrument-functions -DFTRACE endif extra-y := hello_world @@ -39,10 +39,11 @@ LIBAOBJS := $(LIBAOBJS-y) LIBCOBJS = stubs.o +.SECONDARY: $(call objectify,$(COBJS)) +targets += $(patsubst $(obj)/%,%,$(LIB)) $(COBJS) $(LIBAOBJS) $(LIBCOBJS) + LIBOBJS = $(addprefix $(obj)/,$(LIBAOBJS) $(LIBCOBJS)) -SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) -OBJS := $(addprefix $(obj)/,$(COBJS)) ELF := $(addprefix $(obj)/,$(ELF)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) @@ -52,19 +53,22 @@ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) # also causes the entry point of the standalone application to be # inconsistent. ifeq ($(ARCH),powerpc) -AFLAGS := $(filter-out $(RELFLAGS),$(AFLAGS)) -CFLAGS := $(filter-out $(RELFLAGS),$(CFLAGS)) -CPPFLAGS := $(filter-out $(RELFLAGS),$(CPPFLAGS)) +# FIX ME +CPPFLAGS := $(filter-out $(RELFLAGS), $(CPPFLAGS)) endif # We don't want gcc reordering functions if possible. This ensures that an # application's entry point will be the first function in the application's # source file. -CFLAGS += $(call cc-option,-fno-toplevel-reorder) +ccflags-y += $(call cc-option,-fno-toplevel-reorder) ######################################################################### -$(LIB): $(LIBOBJS) - $(call cmd_link_o_target, $(LIBOBJS)) + +quiet_cmd_link_lib = LD $@ + cmd_link_lib = $(LD) $(ld_flags) -r -o $@ $(filter $(LIBOBJS), $^) + +$(LIB): $(LIBOBJS) FORCE + $(call if_changed,link_lib) $(ELF): $(obj)/%: $(obj)/%.o $(LIB) diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile index 5682b16916a..6b1a9a5b005 100644 --- a/fs/ubifs/Makefile +++ b/fs/ubifs/Makefile @@ -15,4 +15,4 @@ obj-y += tnc.o tnc_misc.o debug.o crc16.o budget.o obj-y += log.o orphan.o recovery.o replay.o # SEE README.arm-unaligned-accesses -$(obj)/super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +CFLAGS_super.o := $(PLATFORM_NO_UNALIGNED) diff --git a/fs/yaffs2/Makefile b/fs/yaffs2/Makefile index d811287ddbf..45ff7458c60 100644 --- a/fs/yaffs2/Makefile +++ b/fs/yaffs2/Makefile @@ -24,9 +24,6 @@ obj-y := \ yaffs_summary.o yaffs_tagscompat.o yaffs_verify.o yaffs_yaffs1.o \ yaffs_yaffs2.o yaffs_mtdif.o yaffs_mtdif2.o -YCFLAGS = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM -YCFLAGS += -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE -YCFLAGS += -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES - -CFLAGS += $(YCFLAGS) -CPPFLAGS += $(YCFLAGS) +ccflags-y = -DCONFIG_YAFFS_DIRECT -DCONFIG_YAFFS_SHORT_NAMES_IN_RAM \ + -DCONFIG_YAFFS_YAFFS2 -DNO_Y_INLINE \ + -DCONFIG_YAFFS_PROVIDE_DEFS -DCONFIG_YAFFSFS_PROVIDE_VALUES diff --git a/lib/Makefile b/lib/Makefile index 43b13d09e2f..8c483c99a3a 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -67,4 +67,4 @@ obj-$(CONFIG_BOOTP_RANDOM_DELAY) += rand.o obj-$(CONFIG_CMD_LINK_LOCAL) += rand.o # SEE README.arm-unaligned-accesses -$(obj)/bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED) +CFLAGS_bzlib.o := $(PLATFORM_NO_UNALIGNED) diff --git a/lib/lzma/Makefile b/lib/lzma/Makefile index f8eda06c9f5..b6c80671b90 100644 --- a/lib/lzma/Makefile +++ b/lib/lzma/Makefile @@ -8,6 +8,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -CFLAGS += -D_LZMA_PROB32 +ccflags-y += -D_LZMA_PROB32 obj-y += LzmaDec.o LzmaTools.o diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 041213f3346..d256abf9e18 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -12,17 +12,18 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o cache.o COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ $(nandobj)System.map @@ -42,7 +43,7 @@ $(nandobj)System.map: $(nandobj)u-boot-spl sort > $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/amcc/bamboo/Makefile b/nand_spl/board/amcc/bamboo/Makefile index 92b604e9f56..4f36d6c882f 100644 --- a/nand_spl/board/amcc/bamboo/Makefile +++ b/nand_spl/board/amcc/bamboo/Makefile @@ -12,17 +12,18 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o init.o resetvec.o COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -36,7 +37,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/amcc/canyonlands/Makefile b/nand_spl/board/amcc/canyonlands/Makefile index 9a730e95f54..5c9c8e83eda 100644 --- a/nand_spl/board/amcc/canyonlands/Makefile +++ b/nand_spl/board/amcc/canyonlands/Makefile @@ -12,8 +12,8 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS := start.o SOBJS += init.o @@ -23,11 +23,12 @@ COBJS += nand_boot.o COBJS += nand_ecc.o COBJS += ndfc.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -41,7 +42,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/amcc/kilauea/Makefile b/nand_spl/board/amcc/kilauea/Makefile index 1c5498cfa56..cfe308222b3 100644 --- a/nand_spl/board/amcc/kilauea/Makefile +++ b/nand_spl/board/amcc/kilauea/Makefile @@ -12,17 +12,18 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o cache.o COBJS = 44x_spd_ddr2.o nand_boot.o nand_ecc.o ndfc.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -36,7 +37,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/amcc/sequoia/Makefile b/nand_spl/board/amcc/sequoia/Makefile index 62131ab3996..de02886b291 100644 --- a/nand_spl/board/amcc/sequoia/Makefile +++ b/nand_spl/board/amcc/sequoia/Makefile @@ -12,17 +12,18 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \ $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o init.o resetvec.o COBJS = denali_data_eye.o nand_boot.o nand_ecc.o ndfc.o sdram.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -36,7 +37,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8315erdb/Makefile b/nand_spl/board/freescale/mpc8315erdb/Makefile index a2054ee1ab5..a68567427e5 100644 --- a/nand_spl/board/freescale/mpc8315erdb/Makefile +++ b/nand_spl/board/freescale/mpc8315erdb/Makefile @@ -13,18 +13,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -38,7 +39,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8536ds/Makefile b/nand_spl/board/freescale/mpc8536ds/Makefile index f711cf30ba5..f0beaedf1a5 100644 --- a/nand_spl/board/freescale/mpc8536ds/Makefile +++ b/nand_spl/board/freescale/mpc8536ds/Makefile @@ -15,18 +15,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -40,7 +41,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8569mds/Makefile b/nand_spl/board/freescale/mpc8569mds/Makefile index f711cf30ba5..f0beaedf1a5 100644 --- a/nand_spl/board/freescale/mpc8569mds/Makefile +++ b/nand_spl/board/freescale/mpc8569mds/Makefile @@ -15,18 +15,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -40,7 +41,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/mpc8572ds/Makefile b/nand_spl/board/freescale/mpc8572ds/Makefile index f711cf30ba5..f0beaedf1a5 100644 --- a/nand_spl/board/freescale/mpc8572ds/Makefile +++ b/nand_spl/board/freescale/mpc8572ds/Makefile @@ -15,18 +15,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -40,7 +41,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/p1023rds/Makefile b/nand_spl/board/freescale/p1023rds/Makefile index 21a6920e638..3918ac585bb 100644 --- a/nand_spl/board/freescale/p1023rds/Makefile +++ b/nand_spl/board/freescale/p1023rds/Makefile @@ -11,18 +11,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -36,7 +37,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/freescale/p1_p2_rdb/Makefile b/nand_spl/board/freescale/p1_p2_rdb/Makefile index f711cf30ba5..f0beaedf1a5 100644 --- a/nand_spl/board/freescale/p1_p2_rdb/Makefile +++ b/nand_spl/board/freescale/p1_p2_rdb/Makefile @@ -15,18 +15,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \ nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -40,7 +41,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \ -ansi -D__ASSEMBLY__ -P - <$< >$@ # create symbolic links for common files diff --git a/nand_spl/board/sheldon/simpc8313/Makefile b/nand_spl/board/sheldon/simpc8313/Makefile index ca45ecd3280..35b1f974db2 100644 --- a/nand_spl/board/sheldon/simpc8313/Makefile +++ b/nand_spl/board/sheldon/simpc8313/Makefile @@ -12,18 +12,19 @@ nandobj := $(OBJTREE)/nand_spl/ LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \ $(LDFLAGS) $(LDFLAGS_FINAL) -AFLAGS += -DCONFIG_NAND_SPL -CFLAGS += -DCONFIG_NAND_SPL +asflags-y += -DCONFIG_NAND_SPL +ccflags-y += -DCONFIG_NAND_SPL SOBJS = start.o ticks.o COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \ time.o cache.o -SRCS := $(addprefix $(obj)/,$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS)) __OBJS := $(SOBJS) $(COBJS) LNDIR := $(nandobj)board/$(BOARDDIR) +targets += $(__OBJS) + all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin $(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl @@ -37,7 +38,7 @@ $(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds -Map $(nandobj)u-boot-spl.map -o $@ $(nandobj)u-boot.lds: $(LDSCRIPT) - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ + $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@ # create symbolic links for common files diff --git a/net/Makefile b/net/Makefile index 31aadc2ffc1..942595021da 100644 --- a/net/Makefile +++ b/net/Makefile @@ -5,7 +5,7 @@ # SPDX-License-Identifier: GPL-2.0+ # -# CFLAGS += -DDEBUG +#ccflags-y += -DDEBUG obj-$(CONFIG_CMD_NET) += arp.o obj-$(CONFIG_CMD_NET) += bootp.o diff --git a/post/lib_powerpc/fpu/Makefile b/post/lib_powerpc/fpu/Makefile index c720a26f61d..556a833f6df 100644 --- a/post/lib_powerpc/fpu/Makefile +++ b/post/lib_powerpc/fpu/Makefile @@ -5,20 +5,19 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += 20001122-1.o -obj-y += 20010114-2.o -obj-y += 20010226-1.o -obj-y += 980619-1.o -obj-y += acc1.o -obj-y += compare-fp-1.o -obj-y += fpu.o -obj-y += mul-subnormal-single-1.o -obj-y += darwin-ldouble.o +objs-before-objcopy := 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o \ + acc1.o compare-fp-1.o fpu.o mul-subnormal-single-1.o darwin-ldouble.o +targets += $(objs-before-objcopy) -CFLAGS := $(shell echo $(CFLAGS) | sed s/-msoft-float//) -CFLAGS += -mhard-float -fkeep-inline-functions +# remove -msoft-float flag +$(foreach m, $(objs-before-objcopy), $(eval CFLAGS_REMOVE_$m := -msoft-float)) +ccflags-y := -mhard-float -fkeep-inline-functions -$(addprefix $(obj)/,$(obj-y)): $(obj)/%.o: $(src)/%.c - $(CC) $(ALL_CFLAGS) -o $@.fp $< -c - $(OBJCOPY) -R .gnu.attributes $@.fp $@ - rm -f $@.fp +# Do not delete intermidiate files (*.o) +.SECONDARY: $(call objectify, $(objs-before-objcopy)) + +obj-y := $(objs-before-objcopy:.o=_.o) + +OBJCOPYFLAGS := -R .gnu.attributes +$(obj)/%_.o: $(obj)/%.o + $(call if_changed,objcopy) diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include index 30a5551a4dc..6113c13d161 100644 --- a/scripts/Kbuild.include +++ b/scripts/Kbuild.include @@ -165,7 +165,7 @@ ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2)) # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.build obj= # Usage: # $(Q)$(MAKE) $(build)=dir -build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build.tmp obj +build := -f $(if $(KBUILD_SRC),$(srctree)/)scripts/Makefile.build obj ### # Shorthand for $(Q)$(MAKE) -f scripts/Makefile.modbuiltin obj= diff --git a/scripts/Makefile.build b/scripts/Makefile.build index d5d859c8072..2a87984a317 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -2,7 +2,16 @@ # Building # ========================================================================== -src := $(obj) +# Modified for U-Boot +ifeq ($(CONFIG_TPL_BUILD),y) + src := $(patsubst tpl/%,%,$(obj)) +else + ifeq ($(CONFIG_SPL_BUILD),y) + src := $(patsubst spl/%,%,$(obj)) + else + src := $(obj) + endif +endif PHONY := __build __build: @@ -35,6 +44,11 @@ subdir-ccflags-y := include scripts/Kbuild.include +# Added for U-Boot +# We must include config.mk after Kbuild.include +# so that some config.mk can use cc-option. +include config.mk + # For backward compatibility check that these variables do not change save-cflags := $(CFLAGS) @@ -115,14 +129,16 @@ ifneq ($(hostprogs-y)$(hostprogs-m),) include scripts/Makefile.host endif -ifneq ($(KBUILD_SRC),) +# Uncommented for U-Boot +# We need to create output dicrectory for SPL and TPL even for in-tree build +#ifneq ($(KBUILD_SRC),) # Create output directory if not already present _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) # Create directories for object files if directory does not exist # Needed when obj-y := dir/file.o syntax is used _dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d))) -endif +#endif ifndef obj $(warning kbuild: Makefile.build is included improperly) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 49392ecbef1..d4b5cb5d0ea 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -101,12 +101,13 @@ basename_flags = -D"KBUILD_BASENAME=KBUILD_STR($(call name-fix,$(basetarget)))" modname_flags = $(if $(filter 1,$(words $(modname))),\ -D"KBUILD_MODNAME=KBUILD_STR($(call name-fix,$(modname)))") -orig_c_flags = $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \ +# U-Boot also uses $(CPPFLAGS) +orig_c_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_CFLAGS) $(KBUILD_SUBDIR_CCFLAGS) \ $(ccflags-y) $(CFLAGS_$(basetarget).o) _c_flags = $(filter-out $(CFLAGS_REMOVE_$(basetarget).o), $(orig_c_flags)) -_a_flags = $(KBUILD_CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \ +_a_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(KBUILD_AFLAGS) $(KBUILD_SUBDIR_ASFLAGS) \ $(asflags-y) $(AFLAGS_$(basetarget).o) -_cpp_flags = $(KBUILD_CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F)) +_cpp_flags = $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(cppflags-y) $(CPPFLAGS_$(@F)) # # Enable gcov profiling flags for a file, directory or for all files depending @@ -137,14 +138,15 @@ __a_flags = $(call flags,_a_flags) __cpp_flags = $(call flags,_cpp_flags) endif -c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ +# Modified for U-Boot: LINUXINCLUDE -> UBOOTINCLUDE +c_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ $(__c_flags) $(modkern_cflags) \ -D"KBUILD_STR(s)=\#s" $(basename_flags) $(modname_flags) -a_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ +a_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ $(__a_flags) $(modkern_aflags) -cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(LINUXINCLUDE) \ +cpp_flags = -Wp,-MD,$(depfile) $(NOSTDINC_FLAGS) $(UBOOTINCLUDE) \ $(__cpp_flags) ld_flags = $(LDFLAGS) $(ldflags-y) diff --git a/spl/Makefile b/spl/Makefile index 18606ac34c7..6b985d1e4ac 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -106,8 +106,7 @@ LIBS-y := $(patsubst %/, %/built-in.o, $(LIBS-y)) # Add GCC lib ifeq ("$(USE_PRIVATE_LIBGCC)", "yes") -PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o -PLATFORM_LIBS := $(filter-out %/libgcc.o, $(filter-out -lgcc, $(PLATFORM_LIBS))) $(PLATFORM_LIBGCC) +PLATFORM_LIBS := $(SPLTREE)/arch/$(ARCH)/lib/lib.a endif LIBS-y := $(sort $(LIBS-y)) @@ -155,7 +154,7 @@ $(OBJTREE)/MLO.byteswap: $(obj)/u-boot-spl.bin $(OBJTREE)/tools/mkimage -T omapimage -n byteswap \ -a $(CONFIG_SPL_TEXT_BASE) -d $< $@ -$(objtree)/SPL : $(obj)/u-boot-spl.bin depend +$(objtree)/SPL : $(obj)/u-boot-spl.bin $(MAKE) $(build)=spl/arch/arm/imx-common $@ ALL-y += $(obj)/$(SPL_BIN).bin @@ -191,20 +190,24 @@ GEN_UBOOT = \ --start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \ -Map $(SPL_BIN).map -o $(SPL_BIN) -$(obj)/$(SPL_BIN): depend $(START) $(LIBS) $(obj)/u-boot-spl.lds +$(obj)/$(SPL_BIN): $(START) $(LIBS) $(obj)/u-boot-spl.lds $(GEN_UBOOT) $(START): @: -$(LIBS): depend - $(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) +$(LIBS): + $(Q)$(MAKE) $(build)=$(patsubst %/,%,$(dir $@)) -$(obj)/u-boot-spl.lds: $(LDSCRIPT) depend - $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ +# FIX ME +cpp_flags := $(KBUILD_CPPFLAGS) $(CPPFLAGS) $(UBOOTINCLUDE) $(NOSTDINC_FLAGS) -depend: $(obj)/.depend -.PHONY: depend +$(obj)/u-boot-spl.lds: $(LDSCRIPT) FORCE + $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@ -# defines $(obj).depend target -include $(SRCTREE)/rules.mk +PHONY += FORCE +FORCE: + +# Declare the contents of the .PHONY variable as phony. We keep that +# information in a variable so we can use it in if_changed and friends. +.PHONY: $(PHONY) diff --git a/tools/Makefile b/tools/Makefile index 9b19dcb2645..70a3fc2155a 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -40,19 +40,19 @@ hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX) hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) -HOSTCFLAGS_bmp_logo$(SFX) := -pedantic +HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) envcrc$(SFX)-objs := crc32.o env_embedded.o envcrc.o sha1.o hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) -HOSTCFLAGS_gen_eth_addr$(SFX) := -pedantic +HOSTCFLAGS_gen_eth_addr$(SFX).o := -pedantic hostprogs-$(CONFIG_CMD_LOADS) += img2srec$(SFX) -HOSTCFLAGS_img2srec$(SFX) := -pedantic +HOSTCFLAGS_img2srec$(SFX).o := -pedantic hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) -HOSTCFLAGS_xway-swap-bytes$(SFX) := -pedantic +HOSTCFLAGS_xway-swap-bytes$(SFX).o := -pedantic hostprogs-y += mkenvimage$(SFX) mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o @@ -97,7 +97,7 @@ HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register # the mxsimage support within tools/mxsimage.c . -HOSTCFLAGS += -DCONFIG_MXS +HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS endif ifdef CONFIG_FIT_SIGNATURE @@ -111,11 +111,11 @@ endif hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX) hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX) -HOSTCFLAGS_mkexynosspl$(SFX) := -pedantic +HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic hostprogs-$(CONFIG_MX23) += mxsboot$(SFX) hostprogs-$(CONFIG_MX28) += mxsboot$(SFX) -HOSTCFLAGS_mxsboot$(SFX) := -pedantic +HOSTCFLAGS_mxsboot$(SFX).o := -pedantic hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX) hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) @@ -137,7 +137,7 @@ HOSTCFLAGS_sha1.o := -pedantic # Don't build by default #hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX) -#HOSTCFLAGS_mpc86x_clk$(SFX) := -pedantic +#HOSTCFLAGS_mpc86x_clk$(SFX).o := -pedantic always := $(hostprogs-y) @@ -164,11 +164,6 @@ endif endif # !LOGO_BMP -# now $(obj) is defined -HOSTSRCS += $(addprefix $(SRCTREE)/,$(EXT_OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/tools/,$(OBJ_FILES-y:.o=.c)) -HOSTSRCS += $(addprefix $(SRCTREE)/lib/libfdt/,$(LIBFDT_OBJ_FILES-y:.o=.c)) - # # Use native tools and options # Define __KERNEL_STRICT_NAMES to prevent typedef overlaps @@ -183,7 +178,7 @@ HOST_EXTRACFLAGS += -include $(SRCTREE)/include/libfdt_env.h \ -D__KERNEL_STRICT_NAMES \ -D_GNU_SOURCE -all: $(LOGO-y) +__build: $(LOGO-y) subdir-y := kernel-doc -- cgit v1.2.3 From 9e901071550dd533cc291fb5d19b0841993f6fe7 Mon Sep 17 00:00:00 2001 From: Michael Burr Date: Wed, 22 Jan 2014 09:46:07 +0100 Subject: i2c: zynq: Support for 0-length register address Fixed bug with alen == 0 in 'i2c_write', 'i2c_read' Further minor corrections: - Write 'address' register before 'data' register. - Write 'transfer_size' register before 'address' register. Signed-off-by: Michael Burr Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index 70a9aeafd53..11ef0f8d4f9 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -189,20 +189,22 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, * Temporarily disable restart (by clearing hold) * It doesn't seem to work. */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW | - ZYNQ_I2C_CONTROL_HOLD); + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); writel(0xFF, &zynq_i2c->interrupt_status); - while (alen--) - writel(addr >> (8*alen), &zynq_i2c->data); - writel(dev, &zynq_i2c->address); + if (alen) { + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); + writel(dev, &zynq_i2c->address); + while (alen--) + writel(addr >> (8 * alen), &zynq_i2c->data); - /* Wait for the address to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; + /* Wait for the address to be sent */ + if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); } - debug("Device acked address\n"); setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); @@ -247,17 +249,19 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, ZYNQ_I2C_CONTROL_HOLD); clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); writel(0xFF, &zynq_i2c->interrupt_status); - while (alen--) - writel(addr >> (8*alen), &zynq_i2c->data); - /* Start the tranfer */ writel(dev, &zynq_i2c->address); - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { - /* Release the bus */ - clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); - return -ETIMEDOUT; + if (alen) { + while (alen--) + writel(addr >> (8 * alen), &zynq_i2c->data); + /* Start the tranfer */ + if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + /* Release the bus */ + clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); + return -ETIMEDOUT; + } + debug("Device acked address\n"); } - debug("Device acked address\n"); while (length--) { writel(*(cur_data++), &zynq_i2c->data); if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { -- cgit v1.2.3 From 18948632a92f83cfad125edc6ff4a162a7d90a05 Mon Sep 17 00:00:00 2001 From: Michael Burr Date: Wed, 22 Jan 2014 09:46:08 +0100 Subject: i2c: zynq: Add support for the second i2c controller Initialize the second i2c controller. Signed-off-by: Michael Burr Signed-off-by: Michal Simek --- drivers/i2c/zynq_i2c.c | 44 ++++++++++++++++++++++++++----------------- include/configs/zynq-common.h | 6 +++--- 2 files changed, 30 insertions(+), 20 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/zynq_i2c.c b/drivers/i2c/zynq_i2c.c index 11ef0f8d4f9..f1f65131a2a 100644 --- a/drivers/i2c/zynq_i2c.c +++ b/drivers/i2c/zynq_i2c.c @@ -64,19 +64,21 @@ struct zynq_i2c_registers { #define ZYNQ_I2C_FIFO_DEPTH 16 #define ZYNQ_I2C_TRANSFERT_SIZE_MAX 255 /* Controller transfer limit */ -#if defined(CONFIG_ZYNQ_I2C0) -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR0 -#else -# define ZYNQ_I2C_BASE ZYNQ_I2C_BASEADDR1 -#endif - -static struct zynq_i2c_registers *zynq_i2c = - (struct zynq_i2c_registers *)ZYNQ_I2C_BASE; +static struct zynq_i2c_registers *i2c_select(struct i2c_adapter *adap) +{ + return adap->hwadapnr ? + /* Zynq PS I2C1 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR1 : + /* Zynq PS I2C0 */ + (struct zynq_i2c_registers *)ZYNQ_I2C_BASEADDR0; +} /* I2C init called by cmd_i2c when doing 'i2c reset'. */ static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, int slaveadd) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */ writel((16 << ZYNQ_I2C_CONTROL_DIV_B_SHIFT) | (2 << ZYNQ_I2C_CONTROL_DIV_A_SHIFT), &zynq_i2c->control); @@ -87,7 +89,7 @@ static void zynq_i2c_init(struct i2c_adapter *adap, int requested_speed, } #ifdef DEBUG -static void zynq_i2c_debug_status(void) +static void zynq_i2c_debug_status(struct zynq_i2c_registers *zynq_i2c) { int int_status; int status; @@ -129,7 +131,7 @@ static void zynq_i2c_debug_status(void) #endif /* Wait for an interrupt */ -static u32 zynq_i2c_wait(u32 mask) +static u32 zynq_i2c_wait(struct zynq_i2c_registers *zynq_i2c, u32 mask) { int timeout, int_status; @@ -140,7 +142,7 @@ static u32 zynq_i2c_wait(u32 mask) break; } #ifdef DEBUG - zynq_i2c_debug_status(); + zynq_i2c_debug_status(zynq_i2c)); #endif /* Clear interrupt status flags */ writel(int_status & mask, &zynq_i2c->interrupt_status); @@ -154,6 +156,8 @@ static u32 zynq_i2c_wait(u32 mask) */ static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) { + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); + /* Attempt to read a byte */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | ZYNQ_I2C_CONTROL_RW); @@ -162,7 +166,7 @@ static int zynq_i2c_probe(struct i2c_adapter *adap, u8 dev) writel(dev, &zynq_i2c->address); writel(1, &zynq_i2c->transfer_size); - return (zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + return (zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_NACK) & ZYNQ_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT; } @@ -177,6 +181,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, u32 status; u32 i = 0; u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Check the hardware can handle the requested bytes */ if ((length < 0) || (length > ZYNQ_I2C_TRANSFERT_SIZE_MAX)) @@ -198,7 +203,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, writel(addr >> (8 * alen), &zynq_i2c->data); /* Wait for the address to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); return -ETIMEDOUT; @@ -214,7 +219,7 @@ static int zynq_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, /* Wait for data */ do { - status = zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP | + status = zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP | ZYNQ_I2C_INTERRUPT_DATA); if (!status) { /* Release the bus */ @@ -243,6 +248,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, int alen, u8 *data, int length) { u8 *cur_data = data; + struct zynq_i2c_registers *zynq_i2c = i2c_select(adap); /* Write the register address */ setbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_CLR_FIFO | @@ -254,7 +260,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, while (alen--) writel(addr >> (8 * alen), &zynq_i2c->data); /* Start the tranfer */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); return -ETIMEDOUT; @@ -265,7 +271,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, while (length--) { writel(*(cur_data++), &zynq_i2c->data); if (readl(&zynq_i2c->transfer_size) == ZYNQ_I2C_FIFO_DEPTH) { - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) { + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) { /* Release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); @@ -277,7 +283,7 @@ static int zynq_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, /* All done... release the bus */ clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); /* Wait for the address and data to be sent */ - if (!zynq_i2c_wait(ZYNQ_I2C_INTERRUPT_COMP)) + if (!zynq_i2c_wait(zynq_i2c, ZYNQ_I2C_INTERRUPT_COMP)) return -ETIMEDOUT; return 0; } @@ -295,3 +301,7 @@ U_BOOT_I2C_ADAP_COMPLETE(zynq_0, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, zynq_i2c_write, zynq_i2c_set_bus_speed, CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, 0) +U_BOOT_I2C_ADAP_COMPLETE(zynq_1, zynq_i2c_init, zynq_i2c_probe, zynq_i2c_read, + zynq_i2c_write, zynq_i2c_set_bus_speed, + CONFIG_SYS_I2C_ZYNQ_SPEED, CONFIG_SYS_I2C_ZYNQ_SLAVE, + 1) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9b6db043b57..787d32d2b80 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -104,13 +104,13 @@ # define CONFIG_DOS_PARTITION #endif +#define CONFIG_SYS_I2C_ZYNQ /* I2C */ -#if defined(CONFIG_ZYNQ_I2C0) || defined(CONFIG_ZYNQ_I2C1) +#if defined(CONFIG_SYS_I2C_ZYNQ) # define CONFIG_CMD_I2C # define CONFIG_SYS_I2C -# define CONFIG_SYS_I2C_ZYNQ # define CONFIG_SYS_I2C_ZYNQ_SPEED 100000 -# define CONFIG_SYS_I2C_ZYNQ_SLAVE 1 +# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0 #endif /* EEPROM */ -- cgit v1.2.3 From bb0fad0ea095944c76dc94fcd13b91699413f79f Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 28 Jan 2014 13:53:33 +0800 Subject: blackfin: the sclk MHz in i2c driver should be divided by 1000 other than 1024 Signed-off-by: Sonic Zhang --- drivers/i2c/bfin-twi_i2c.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index b3a04d32074..5c372809c91 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -274,7 +274,7 @@ unsigned int i2c_get_bus_speed(void) */ void i2c_init(int speed, int slaveaddr) { - uint8_t prescale = ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F; + uint8_t prescale = ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ twi->control = prescale; -- cgit v1.2.3 From d6a320d5bb3050eeb9a586481145d3a75ef24db8 Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 28 Jan 2014 13:53:34 +0800 Subject: blackfin: add spi and i2c specific get clock functions Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/blackfin_local.h | 7 ------- arch/blackfin/include/asm/clock.h | 11 +++++++++++ drivers/i2c/bfin-twi_i2c.c | 3 ++- drivers/spi/bfin_spi.c | 7 ++++--- drivers/spi/bfin_spi6xx.c | 7 ++++--- 5 files changed, 21 insertions(+), 14 deletions(-) (limited to 'drivers') diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 4d6eeab0ec1..868c82ea7db 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -42,13 +42,6 @@ # include -extern u_long get_vco(void); -extern u_long get_cclk(void); -extern u_long get_sclk(void); -extern u_long get_sclk0(void); -extern u_long get_sclk1(void); -extern u_long get_dclk(void); - # define bfin_revid() (bfin_read_CHIPID() >> 28) extern int bfin_os_log_check(void); diff --git a/arch/blackfin/include/asm/clock.h b/arch/blackfin/include/asm/clock.h index fc84fe43f12..59d3faa29df 100644 --- a/arch/blackfin/include/asm/clock.h +++ b/arch/blackfin/include/asm/clock.h @@ -68,10 +68,21 @@ static inline uint32_t early_get_uart_clk(void) return uclk; } +extern u_long get_vco(void); +extern u_long get_cclk(void); +extern u_long get_sclk(void); + #ifdef CGU_DIV +extern u_long get_sclk0(void); +extern u_long get_sclk1(void); +extern u_long get_dclk(void); # define get_uart_clk get_sclk0 +# define get_i2c_clk get_sclk0 +# define get_spi_clk get_sclk0 #else # define get_uart_clk get_sclk +# define get_i2c_clk get_sclk +# define get_spi_clk get_sclk #endif #endif diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/bfin-twi_i2c.c index 5c372809c91..cfab064dfad 100644 --- a/drivers/i2c/bfin-twi_i2c.c +++ b/drivers/i2c/bfin-twi_i2c.c @@ -10,6 +10,7 @@ #include #include +#include #include /* Every register is 32bit aligned, but only 16bits in size */ @@ -274,7 +275,7 @@ unsigned int i2c_get_bus_speed(void) */ void i2c_init(int speed, int slaveaddr) { - uint8_t prescale = ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F; + uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ twi->control = prescale; diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c index aa89d89a32a..71a31d0127f 100644 --- a/drivers/spi/bfin_spi.c +++ b/drivers/spi/bfin_spi.c @@ -13,6 +13,7 @@ #include #include +#include #include #include #include @@ -140,12 +141,12 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 baud; - sclk = get_sclk(); + clk = get_spi_clk(); /* baud should be rounded up */ - baud = DIV_ROUND_UP(sclk, 2 * hz); + baud = DIV_ROUND_UP(clk, 2 * hz); if (baud < 2) baud = 2; else if (baud > (u16)-1) diff --git a/drivers/spi/bfin_spi6xx.c b/drivers/spi/bfin_spi6xx.c index 07b833d3a3d..eba01d16f50 100644 --- a/drivers/spi/bfin_spi6xx.c +++ b/drivers/spi/bfin_spi6xx.c @@ -22,6 +22,7 @@ #include #include +#include #include #include #include @@ -135,11 +136,11 @@ static const unsigned short cs_pins[][7] = { void spi_set_speed(struct spi_slave *slave, uint hz) { struct bfin_spi_slave *bss = to_bfin_spi_slave(slave); - ulong sclk; + ulong clk; u32 clock; - sclk = get_sclk1(); - clock = sclk / hz; + clk = get_spi_clk(); + clock = clk / hz; if (clock) clock--; bss->clock = clock; -- cgit v1.2.3 From 86bdd70a09be7868df19983af27f3c18e96c610f Mon Sep 17 00:00:00 2001 From: Sonic Zhang Date: Tue, 28 Jan 2014 13:53:35 +0800 Subject: blackfin: rename bfin-twi_i2c driver to adi_i2c The ADI twi peripheral is not binding to Blackfin processor only. Change to a generic name. Signed-off-by: Sonic Zhang --- arch/blackfin/include/asm/twi.h | 15 ++ drivers/i2c/adi_i2c.c | 378 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 393 insertions(+) create mode 100644 arch/blackfin/include/asm/twi.h create mode 100644 drivers/i2c/adi_i2c.c (limited to 'drivers') diff --git a/arch/blackfin/include/asm/twi.h b/arch/blackfin/include/asm/twi.h new file mode 100644 index 00000000000..922cdbd892e --- /dev/null +++ b/arch/blackfin/include/asm/twi.h @@ -0,0 +1,15 @@ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#ifndef __ARCH_TWI_H +#define __ARCH_TWI_H + +#include +#include + +#endif diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c new file mode 100644 index 00000000000..743aa251a12 --- /dev/null +++ b/drivers/i2c/adi_i2c.c @@ -0,0 +1,378 @@ +/* + * i2c.c - driver for Blackfin on-chip TWI/I2C + * + * Copyright (c) 2006-2010 Analog Devices Inc. + * + * Licensed under the GPL-2 or later. + */ + +#include +#include + +#include +#include + +/* Every register is 32bit aligned, but only 16bits in size */ +#define ureg(name) u16 name; u16 __pad_##name; +struct twi_regs { + ureg(clkdiv); + ureg(control); + ureg(slave_ctl); + ureg(slave_stat); + ureg(slave_addr); + ureg(master_ctl); + ureg(master_stat); + ureg(master_addr); + ureg(int_stat); + ureg(int_mask); + ureg(fifo_ctl); + ureg(fifo_stat); + char __pad[0x50]; + ureg(xmt_data8); + ureg(xmt_data16); + ureg(rcv_data8); + ureg(rcv_data16); +}; +#undef ureg + +/* U-Boot I2C framework allows only one active device at a time. */ +#ifdef TWI_CLKDIV +#define TWI0_CLKDIV TWI_CLKDIV +#endif +static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; + +#ifdef DEBUG +# define dmemset(s, c, n) memset(s, c, n) +#else +# define dmemset(s, c, n) +#endif +#define debugi(fmt, args...) \ + debug( \ + "MSTAT:0x%03x FSTAT:0x%x ISTAT:0x%02x\t%-20s:%-3i: " fmt "\n", \ + twi->master_stat, twi->fifo_stat, twi->int_stat, \ + __func__, __LINE__, ## args) + +#ifdef CONFIG_TWICLK_KHZ +# error do not define CONFIG_TWICLK_KHZ ... use CONFIG_SYS_I2C_SPEED +#endif + +/* + * The way speed is changed into duty often results in integer truncation + * with 50% duty, so we'll force rounding up to the next duty by adding 1 + * to the max. In practice this will get us a speed of something like + * 385 KHz. The other limit is easy to handle as it is only 8 bits. + */ +#define I2C_SPEED_MAX 400000 +#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed)) +#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1) +#define I2C_DUTY_MIN 0xff /* 8 bit limited */ +#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED) +/* Note: duty is inverse of speed, so the comparisons below are correct */ +#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN +# error "The Blackfin I2C hardware can only operate 20KHz - 400KHz" +#endif + +/* All transfers are described by this data structure */ +struct i2c_msg { + u8 flags; +#define I2C_M_COMBO 0x4 +#define I2C_M_STOP 0x2 +#define I2C_M_READ 0x1 + int len; /* msg length */ + u8 *buf; /* pointer to msg data */ + int alen; /* addr length */ + u8 *abuf; /* addr buffer */ +}; + +/* Allow msec timeout per ~byte transfer */ +#define I2C_TIMEOUT 10 + +/** + * wait_for_completion - manage the actual i2c transfer + * @msg: the i2c msg + */ +static int wait_for_completion(struct i2c_msg *msg) +{ + uint16_t int_stat; + ulong timebase = get_timer(0); + + do { + int_stat = twi->int_stat; + + if (int_stat & XMTSERV) { + debugi("processing XMTSERV"); + twi->int_stat = XMTSERV; + SSYNC(); + if (msg->alen) { + twi->xmt_data8 = *(msg->abuf++); + --msg->alen; + } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { + twi->xmt_data8 = *(msg->buf++); + --msg->len; + } else { + twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; + SSYNC(); + } + } + if (int_stat & RCVSERV) { + debugi("processing RCVSERV"); + twi->int_stat = RCVSERV; + SSYNC(); + if (msg->len) { + *(msg->buf++) = twi->rcv_data8; + --msg->len; + } else if (msg->flags & I2C_M_STOP) { + twi->master_ctl |= STOP; + SSYNC(); + } + } + if (int_stat & MERR) { + debugi("processing MERR"); + twi->int_stat = MERR; + SSYNC(); + return msg->len; + } + if (int_stat & MCOMP) { + debugi("processing MCOMP"); + twi->int_stat = MCOMP; + SSYNC(); + if (msg->flags & I2C_M_COMBO && msg->len) { + twi->master_ctl = (twi->master_ctl & ~RSTART) | + (min(msg->len, 0xff) << 6) | MEN | MDIR; + SSYNC(); + } else + break; + } + + /* If we were able to do something, reset timeout */ + if (int_stat) + timebase = get_timer(0); + + } while (get_timer(timebase) < I2C_TIMEOUT); + + return msg->len; +} + +/** + * i2c_transfer - setup an i2c transfer + * @return: 0 if things worked, non-0 if things failed + * + * Here we just get the i2c stuff all prepped and ready, and then tail off + * into wait_for_completion() for all the bits to go. + */ +static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags) +{ + uchar addr_buffer[] = { + (addr >> 0), + (addr >> 8), + (addr >> 16), + }; + struct i2c_msg msg = { + .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), + .buf = buffer, + .len = len, + .abuf = addr_buffer, + .alen = alen, + }; + int ret; + + dmemset(buffer, 0xff, len); + debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ", + chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); + + /* wait for things to settle */ + while (twi->master_stat & BUSBUSY) + if (ctrlc()) + return 1; + + /* Set Transmit device address */ + twi->master_addr = chip; + + /* Clear the FIFO before starting things */ + twi->fifo_ctl = XMTFLUSH | RCVFLUSH; + SSYNC(); + twi->fifo_ctl = 0; + SSYNC(); + + /* prime the pump */ + if (msg.alen) { + len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; + debugi("first byte=0x%02x", *msg.abuf); + twi->xmt_data8 = *(msg.abuf++); + --msg.alen; + } else if (!(msg.flags & I2C_M_READ) && msg.len) { + debugi("first byte=0x%02x", *msg.buf); + twi->xmt_data8 = *(msg.buf++); + --msg.len; + } + + /* clear int stat */ + twi->master_stat = -1; + twi->int_stat = -1; + twi->int_mask = 0; + SSYNC(); + + /* Master enable */ + twi->master_ctl = + (twi->master_ctl & FAST) | + (min(len, 0xff) << 6) | MEN | + ((msg.flags & I2C_M_READ) ? MDIR : 0); + SSYNC(); + debugi("CTL=0x%04x", twi->master_ctl); + + /* process the rest */ + ret = wait_for_completion(&msg); + debugi("ret=%d", ret); + + if (ret) { + twi->master_ctl &= ~MEN; + twi->control &= ~TWI_ENA; + SSYNC(); + twi->control |= TWI_ENA; + SSYNC(); + } + + return ret; +} + +/** + * i2c_set_bus_speed - set i2c bus speed + * @speed: bus speed (in HZ) + */ +int i2c_set_bus_speed(unsigned int speed) +{ + u16 clkdiv = I2C_SPEED_TO_DUTY(speed); + + /* Set TWI interface clock */ + if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) + return -1; + twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); + + /* Don't turn it on */ + twi->master_ctl = (speed > 100000 ? FAST : 0); + + return 0; +} + +/** + * i2c_get_bus_speed - get i2c bus speed + * @speed: bus speed (in HZ) + */ +unsigned int i2c_get_bus_speed(void) +{ + /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ + return 5000000 / (twi->clkdiv & 0xff); +} + +/** + * i2c_init - initialize the i2c bus + * @speed: bus speed (in HZ) + * @slaveaddr: address of device in slave mode (0 - not slave) + * + * Slave mode isn't actually implemented. It'll stay that way until + * we get a real request for it. + */ +void i2c_init(int speed, int slaveaddr) +{ + uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; + + /* Set TWI internal clock as 10MHz */ + twi->control = prescale; + + /* Set TWI interface clock as specified */ + i2c_set_bus_speed(speed); + + /* Enable it */ + twi->control = TWI_ENA | prescale; + SSYNC(); + + debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); + +#if CONFIG_SYS_I2C_SLAVE +# error I2C slave support not tested/supported + /* If they want us as a slave, do it */ + if (slaveaddr) { + twi->slave_addr = slaveaddr; + twi->slave_ctl = SEN; + } +#endif +} + +/** + * i2c_probe - test if a chip exists at a given i2c address + * @chip: i2c chip addr to search for + * @return: 0 if found, non-0 if not found + */ +int i2c_probe(uchar chip) +{ + u8 byte; + return i2c_read(chip, 0, 0, &byte, 1); +} + +/** + * i2c_read - read data from an i2c device + * @chip: i2c chip addr + * @addr: memory (register) address in the chip + * @alen: byte size of address + * @buffer: buffer to store data read from chip + * @len: how many bytes to read + * @return: 0 on success, non-0 on failure + */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); +} + +/** + * i2c_write - write data to an i2c device + * @chip: i2c chip addr + * @addr: memory (register) address in the chip + * @alen: byte size of address + * @buffer: buffer holding data to write to chip + * @len: how many bytes to write + * @return: 0 on success, non-0 on failure + */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + return i2c_transfer(chip, addr, alen, buffer, len, 0); +} + +/** + * i2c_set_bus_num - change active I2C bus + * @bus: bus index, zero based + * @returns: 0 on success, non-0 on failure + */ +int i2c_set_bus_num(unsigned int bus) +{ + switch (bus) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case 0: twi = (void *)TWI0_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case 1: twi = (void *)TWI1_CLKDIV; return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case 2: twi = (void *)TWI2_CLKDIV; return 0; +#endif + default: return -1; + } +} + +/** + * i2c_get_bus_num - returns index of active I2C bus + */ +unsigned int i2c_get_bus_num(void) +{ + switch ((unsigned long)twi) { +#if CONFIG_SYS_MAX_I2C_BUS > 0 + case TWI0_CLKDIV: return 0; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 1 + case TWI1_CLKDIV: return 1; +#endif +#if CONFIG_SYS_MAX_I2C_BUS > 2 + case TWI2_CLKDIV: return 2; +#endif + default: return -1; + } +} -- cgit v1.2.3 From 16c550274c2590ea20d32de9480365048e271aad Mon Sep 17 00:00:00 2001 From: Scott Jiang Date: Tue, 28 Jan 2014 13:53:36 +0800 Subject: blackfin: make i2c driver blackfin independant The ADI twi peripheral is not binding to Blackfin processor only. Access i2c registers by standard io functions. Fix coding style. Signed-off-by: Scott Jiang Signed-off-by: Sonic Zhang --- drivers/i2c/adi_i2c.c | 151 ++++++++++++++++++++++++++------------------------ 1 file changed, 80 insertions(+), 71 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c index 743aa251a12..675f4171ced 100644 --- a/drivers/i2c/adi_i2c.c +++ b/drivers/i2c/adi_i2c.c @@ -1,7 +1,7 @@ /* - * i2c.c - driver for Blackfin on-chip TWI/I2C + * i2c.c - driver for ADI TWI/I2C * - * Copyright (c) 2006-2010 Analog Devices Inc. + * Copyright (c) 2006-2013 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -11,6 +11,7 @@ #include #include +#include /* Every register is 32bit aligned, but only 16bits in size */ #define ureg(name) u16 name; u16 __pad_##name; @@ -39,7 +40,7 @@ struct twi_regs { #ifdef TWI_CLKDIV #define TWI0_CLKDIV TWI_CLKDIV #endif -static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV; +static struct twi_regs *twi = (void *)TWI0_CLKDIV; #ifdef DEBUG # define dmemset(s, c, n) memset(s, c, n) @@ -93,53 +94,54 @@ struct i2c_msg { */ static int wait_for_completion(struct i2c_msg *msg) { - uint16_t int_stat; + u16 int_stat, ctl; ulong timebase = get_timer(0); do { - int_stat = twi->int_stat; + int_stat = readw(&twi->int_stat); if (int_stat & XMTSERV) { debugi("processing XMTSERV"); - twi->int_stat = XMTSERV; - SSYNC(); + writew(XMTSERV, &twi->int_stat); if (msg->alen) { - twi->xmt_data8 = *(msg->abuf++); + writew(*(msg->abuf++), &twi->xmt_data8); --msg->alen; } else if (!(msg->flags & I2C_M_COMBO) && msg->len) { - twi->xmt_data8 = *(msg->buf++); + writew(*(msg->buf++), &twi->xmt_data8); --msg->len; } else { - twi->master_ctl |= (msg->flags & I2C_M_COMBO) ? RSTART | MDIR : STOP; - SSYNC(); + ctl = readw(&twi->master_ctl); + if (msg->flags & I2C_M_COMBO) + writew(ctl | RSTART | MDIR, + &twi->master_ctl); + else + writew(ctl | STOP, &twi->master_ctl); } } if (int_stat & RCVSERV) { debugi("processing RCVSERV"); - twi->int_stat = RCVSERV; - SSYNC(); + writew(RCVSERV, &twi->int_stat); if (msg->len) { - *(msg->buf++) = twi->rcv_data8; + *(msg->buf++) = readw(&twi->rcv_data8); --msg->len; } else if (msg->flags & I2C_M_STOP) { - twi->master_ctl |= STOP; - SSYNC(); + ctl = readw(&twi->master_ctl); + writew(ctl | STOP, &twi->master_ctl); } } if (int_stat & MERR) { debugi("processing MERR"); - twi->int_stat = MERR; - SSYNC(); + writew(MERR, &twi->int_stat); return msg->len; } if (int_stat & MCOMP) { debugi("processing MCOMP"); - twi->int_stat = MCOMP; - SSYNC(); + writew(MCOMP, &twi->int_stat); if (msg->flags & I2C_M_COMBO && msg->len) { - twi->master_ctl = (twi->master_ctl & ~RSTART) | + ctl = readw(&twi->master_ctl); + ctl = (ctl & ~RSTART) | (min(msg->len, 0xff) << 6) | MEN | MDIR; - SSYNC(); + writew(ctl, &twi->master_ctl); } else break; } @@ -160,8 +162,11 @@ static int wait_for_completion(struct i2c_msg *msg) * Here we just get the i2c stuff all prepped and ready, and then tail off * into wait_for_completion() for all the bits to go. */ -static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, u8 flags) +static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, + int len, u8 flags) { + int ret; + u16 ctl; uchar addr_buffer[] = { (addr >> 0), (addr >> 8), @@ -174,62 +179,59 @@ static int i2c_transfer(uchar chip, uint addr, int alen, uchar *buffer, int len, .abuf = addr_buffer, .alen = alen, }; - int ret; dmemset(buffer, 0xff, len); - debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i flags=0x%02x[%s] ", - chip, addr, alen, buffer[0], len, flags, (flags & I2C_M_READ ? "rd" : "wr")); + debugi("chip=0x%x addr=0x%02x alen=%i buf[0]=0x%02x len=%i ", + chip, addr, alen, buffer[0], len); + debugi("flags=0x%02x[%s] ", flags, + (flags & I2C_M_READ ? "rd" : "wr")); /* wait for things to settle */ - while (twi->master_stat & BUSBUSY) + while (readw(&twi->master_stat) & BUSBUSY) if (ctrlc()) return 1; /* Set Transmit device address */ - twi->master_addr = chip; + writew(chip, &twi->master_addr); /* Clear the FIFO before starting things */ - twi->fifo_ctl = XMTFLUSH | RCVFLUSH; - SSYNC(); - twi->fifo_ctl = 0; - SSYNC(); + writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl); + writew(0, &twi->fifo_ctl); /* prime the pump */ if (msg.alen) { len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len; debugi("first byte=0x%02x", *msg.abuf); - twi->xmt_data8 = *(msg.abuf++); + writew(*(msg.abuf++), &twi->xmt_data8); --msg.alen; } else if (!(msg.flags & I2C_M_READ) && msg.len) { debugi("first byte=0x%02x", *msg.buf); - twi->xmt_data8 = *(msg.buf++); + writew(*(msg.buf++), &twi->xmt_data8); --msg.len; } /* clear int stat */ - twi->master_stat = -1; - twi->int_stat = -1; - twi->int_mask = 0; - SSYNC(); + writew(-1, &twi->master_stat); + writew(-1, &twi->int_stat); + writew(0, &twi->int_mask); /* Master enable */ - twi->master_ctl = - (twi->master_ctl & FAST) | - (min(len, 0xff) << 6) | MEN | - ((msg.flags & I2C_M_READ) ? MDIR : 0); - SSYNC(); - debugi("CTL=0x%04x", twi->master_ctl); + ctl = readw(&twi->master_ctl); + ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN | + ((msg.flags & I2C_M_READ) ? MDIR : 0); + writew(ctl, &twi->master_ctl); /* process the rest */ ret = wait_for_completion(&msg); debugi("ret=%d", ret); if (ret) { - twi->master_ctl &= ~MEN; - twi->control &= ~TWI_ENA; - SSYNC(); - twi->control |= TWI_ENA; - SSYNC(); + ctl = readw(&twi->master_ctl) & ~MEN; + writew(ctl, &twi->master_ctl); + ctl = readw(&twi->control) & ~TWI_ENA; + writew(ctl, &twi->control); + ctl = readw(&twi->control) | TWI_ENA; + writew(ctl, &twi->control); } return ret; @@ -246,10 +248,11 @@ int i2c_set_bus_speed(unsigned int speed) /* Set TWI interface clock */ if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN) return -1; - twi->clkdiv = (clkdiv << 8) | (clkdiv & 0xff); + clkdiv = (clkdiv << 8) | (clkdiv & 0xff); + writew(clkdiv, &twi->clkdiv); /* Don't turn it on */ - twi->master_ctl = (speed > 100000 ? FAST : 0); + writew(speed > 100000 ? FAST : 0, &twi->master_ctl); return 0; } @@ -260,8 +263,9 @@ int i2c_set_bus_speed(unsigned int speed) */ unsigned int i2c_get_bus_speed(void) { + u16 clkdiv = readw(&twi->clkdiv) & 0xff; /* 10 MHz / (2 * CLKDIV) -> 5 MHz / CLKDIV */ - return 5000000 / (twi->clkdiv & 0xff); + return 5000000 / clkdiv; } /** @@ -274,27 +278,22 @@ unsigned int i2c_get_bus_speed(void) */ void i2c_init(int speed, int slaveaddr) { - uint8_t prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; + u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F; /* Set TWI internal clock as 10MHz */ - twi->control = prescale; + writew(prescale, &twi->control); /* Set TWI interface clock as specified */ i2c_set_bus_speed(speed); /* Enable it */ - twi->control = TWI_ENA | prescale; - SSYNC(); + writew(TWI_ENA | prescale, &twi->control); - debugi("CONTROL:0x%04x CLKDIV:0x%04x", twi->control, twi->clkdiv); + debugi("CONTROL:0x%04x CLKDIV:0x%04x", readw(&twi->control), + readw(&twi->clkdiv)); #if CONFIG_SYS_I2C_SLAVE # error I2C slave support not tested/supported - /* If they want us as a slave, do it */ - if (slaveaddr) { - twi->slave_addr = slaveaddr; - twi->slave_ctl = SEN; - } #endif } @@ -320,7 +319,8 @@ int i2c_probe(uchar chip) */ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - return i2c_transfer(chip, addr, alen, buffer, len, (alen ? I2C_M_COMBO : I2C_M_READ)); + return i2c_transfer(chip, addr, alen, buffer, + len, (alen ? I2C_M_COMBO : I2C_M_READ)); } /** @@ -346,15 +346,21 @@ int i2c_set_bus_num(unsigned int bus) { switch (bus) { #if CONFIG_SYS_MAX_I2C_BUS > 0 - case 0: twi = (void *)TWI0_CLKDIV; return 0; + case 0: + twi = (void *)TWI0_CLKDIV; + return 0; #endif #if CONFIG_SYS_MAX_I2C_BUS > 1 - case 1: twi = (void *)TWI1_CLKDIV; return 0; + case 1: + twi = (void *)TWI1_CLKDIV; + return 0; #endif #if CONFIG_SYS_MAX_I2C_BUS > 2 - case 2: twi = (void *)TWI2_CLKDIV; return 0; + case 2: + twi = (void *)TWI2_CLKDIV; + return 0; #endif - default: return -1; + default: return -1; } } @@ -365,14 +371,17 @@ unsigned int i2c_get_bus_num(void) { switch ((unsigned long)twi) { #if CONFIG_SYS_MAX_I2C_BUS > 0 - case TWI0_CLKDIV: return 0; + case TWI0_CLKDIV: + return 0; #endif #if CONFIG_SYS_MAX_I2C_BUS > 1 - case TWI1_CLKDIV: return 1; + case TWI1_CLKDIV: + return 1; #endif #if CONFIG_SYS_MAX_I2C_BUS > 2 - case TWI2_CLKDIV: return 2; + case TWI2_CLKDIV: + return 2; #endif - default: return -1; + default: return -1; } } -- cgit v1.2.3 From 9e50c406c8eede1105bd8ad1c1b74e0ef64af233 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Sat, 25 Jan 2014 07:27:13 +0100 Subject: i2c, bootcount: add support for bootcounter on i2c devices add support for bootcounter on an i2c device. And add a README for all bootcounter options. Signed-off-by: Heiko Schocher --- README | 20 ++++++++++++++++++ drivers/bootcount/Makefile | 1 + drivers/bootcount/bootcount_i2c.c | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) create mode 100644 drivers/bootcount/bootcount_i2c.c (limited to 'drivers') diff --git a/README b/README index bfd89b0bfb0..f14364b5a56 100644 --- a/README +++ b/README @@ -2855,6 +2855,26 @@ CBFS (Coreboot Filesystem) support The signing part is build into mkimage regardless of this option. +- bootcount support: + CONFIG_BOOTCOUNT_LIMIT + + This enables the bootcounter support, see: + http://www.denx.de/wiki/DULG/UBootBootCountLimit + + CONFIG_AT91SAM9XE + enable special bootcounter support on at91sam9xe based boards. + CONFIG_BLACKFIN + enable special bootcounter support on blackfin based boards. + CONFIG_SOC_DA8XX + enable special bootcounter support on da850 based boards. + CONFIG_BOOTCOUNT_RAM + enable support for the bootcounter in RAM + CONFIG_BOOTCOUNT_I2C + enable support for the bootcounter on an i2c (like RTC) device. + CONFIG_SYS_I2C_RTC_ADDR = i2c chip address + CONFIG_SYS_BOOTCOUNT_ADDR = i2c addr which is used for + the bootcounter. + CONFIG_BOOTCOUNT_ALEN = address len - Show boot progress: CONFIG_SHOW_BOOT_PROGRESS diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index bed6971aa55..6f1c419c7a7 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o obj-$(CONFIG_BOOTCOUNT_ENV) += bootcount_env.o +obj-$(CONFIG_BOOTCOUNT_I2C) += bootcount_i2c.o diff --git a/drivers/bootcount/bootcount_i2c.c b/drivers/bootcount/bootcount_i2c.c new file mode 100644 index 00000000000..e27b168c55c --- /dev/null +++ b/drivers/bootcount/bootcount_i2c.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2013 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define BC_MAGIC 0xbc + +void bootcount_store(ulong a) +{ + unsigned char buf[3]; + int ret; + + buf[0] = BC_MAGIC; + buf[1] = (a & 0xff); + ret = i2c_write(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) + puts("Error writing bootcount\n"); +} + +ulong bootcount_load(void) +{ + unsigned char buf[3]; + int ret; + + ret = i2c_read(CONFIG_SYS_I2C_RTC_ADDR, CONFIG_SYS_BOOTCOUNT_ADDR, + CONFIG_BOOTCOUNT_ALEN, buf, 2); + if (ret != 0) { + puts("Error loading bootcount\n"); + return 0; + } + if (buf[0] == BC_MAGIC) + return buf[1]; + + bootcount_store(0); + + return 0; +} -- cgit v1.2.3 From 070cbaf821e07531db6e55946932f4172dd72045 Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Tue, 4 Feb 2014 11:56:23 -0600 Subject: designware_i2c: Enhance DesignWare I2C driver address support Enhance the DesignWare I2C driver to support address length more than 1 byte. This enhancement is required as some I2C slave device such as EEPROM chip might have 16 bit address byte. Signed-off-by: Chin Liang See Acked-by: Alexey Brodkin Cc: Tom Rini cc: Armando Visconti Cc: Stefan Roese Cc: Albert ARIBAUD Cc: Heiko Schocher --- drivers/i2c/designware_i2c.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 9ed929521a8..deea4f83caf 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -197,35 +197,18 @@ static int i2c_wait_for_bb(void) return 0; } -/* check parameters for i2c_read and i2c_write */ -static int check_params(uint addr, int alen, uchar *buffer, int len) -{ - if (buffer == NULL) { - printf("Buffer is invalid\n"); - return 1; - } - - if (alen > 1) { - printf("addr len %d not supported\n", alen); - return 1; - } - - if (addr + len > 256) { - printf("address out of range\n"); - return 1; - } - - return 0; -} - -static int i2c_xfer_init(uchar chip, uint addr) +static int i2c_xfer_init(uchar chip, uint addr, int alen) { if (i2c_wait_for_bb()) return 1; i2c_setaddress(chip); - writel(addr, &i2c_regs_p->ic_cmd_data); - + while (alen) { + alen--; + /* high byte address going out first */ + writel((addr >> (alen * 8)) & 0xff, + &i2c_regs_p->ic_cmd_data); + } return 0; } @@ -285,10 +268,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_rx = get_timer(0); @@ -345,10 +325,7 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) addr); #endif - if (check_params(addr, alen, buffer, len)) - return 1; - - if (i2c_xfer_init(chip, addr)) + if (i2c_xfer_init(chip, addr, alen)) return 1; start_time_tx = get_timer(0); -- cgit v1.2.3 From d22643e7e819a94a32652cfb041c24d4fd99a7ec Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 6 Feb 2014 02:59:34 +0100 Subject: i2c: i2c-mxs: Wait for I2C to empty queue Make sure the I2C write queue is empty before leaving the mxs_i2c_write(). If we start and I2C write and only wait for ACK, the MXS I2C IP block may enter next operation while still processing the write aftermath internally. This will in turn disrupt one or more subsequent transfer(s). A testcase for this issue is as such. This testcase is also interesting because the first I2C_WRITE which becomes disruptive happens in the 'i2c read' command. The 'i2c read' command first uses I2C_WRITE to send I2C address of the chip and then uses I2C_READ to read data from the chip. After this command completes, the 'i2c probe' will use sequence of I2C_WRITE commands to probe the I2C bus. The problem is that the first I2C_WRITE disrupted the I2C IP block operation and this sideeffect propagates all the way to this next I2C_WRITE used by the 'i2c probe' call. The result is the 'i2c probe' receives an ACK on I2C address 0x00, even if this ACK was owned by the previous I2C_WRITE operation. Note that the 'i2c read' command must read from a valid I2C chip address. Wrong: > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 00 50 51 With this patch > i2c probe Valid chip addresses: 50 51 > i2c read 0x50 0x0.2 0x10 0x42000000 > i2c probe Valid chip addresses: 50 51 Signed-off-by: Marek Vasut Cc: Heiko Schocher Cc: Fabio Estevam --- drivers/i2c/mxs_i2c.c | 39 ++++++++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/mxs_i2c.c b/drivers/i2c/mxs_i2c.c index a298c95e144..de3b19402b4 100644 --- a/drivers/i2c/mxs_i2c.c +++ b/drivers/i2c/mxs_i2c.c @@ -64,16 +64,17 @@ static void mxs_i2c_setup_read(uint8_t chip, int len) writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); } -static void mxs_i2c_write(uchar chip, uint addr, int alen, +static int mxs_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int blen, int stop) { struct mxs_i2c_regs *i2c_regs = (struct mxs_i2c_regs *)MXS_I2C0_BASE; - uint32_t data; + uint32_t data, tmp; int i, remain, off; + int timeout = MXS_I2C_MAX_TIMEOUT; if ((alen > 4) || (alen == 0)) { debug("MXS I2C: Invalid address length\n"); - return; + return -EINVAL; } if (stop) @@ -106,6 +107,19 @@ static void mxs_i2c_write(uchar chip, uint addr, int alen, writel(data >> remain, &i2c_regs->hw_i2c_data); writel(I2C_QUEUECTRL_QUEUE_RUN, &i2c_regs->hw_i2c_queuectrl_set); + + while (--timeout) { + tmp = readl(&i2c_regs->hw_i2c_queuestat); + if (tmp & I2C_QUEUESTAT_WR_QUEUE_EMPTY) + break; + } + + if (!timeout) { + debug("MXS I2C: Failed transmitting data!\n"); + return -EINVAL; + } + + return 0; } static int mxs_i2c_wait_for_ack(void) @@ -154,7 +168,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int ret; int i; - mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + ret = mxs_i2c_write(chip, addr, alen, NULL, 0, 0); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) { debug("MXS I2C: Failed writing address\n"); @@ -193,7 +212,12 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { int ret; - mxs_i2c_write(chip, addr, alen, buffer, len, 1); + ret = mxs_i2c_write(chip, addr, alen, buffer, len, 1); + if (ret) { + debug("MXS I2C: Failed writing address\n"); + return ret; + } + ret = mxs_i2c_wait_for_ack(); if (ret) debug("MXS I2C: Failed writing address\n"); @@ -204,8 +228,9 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) int i2c_probe(uchar chip) { int ret; - mxs_i2c_write(chip, 0, 1, NULL, 0, 1); - ret = mxs_i2c_wait_for_ack(); + ret = mxs_i2c_write(chip, 0, 1, NULL, 0, 1); + if (!ret) + ret = mxs_i2c_wait_for_ack(); mxs_i2c_reset(); return ret; } -- cgit v1.2.3 From d5243359e1afc957acd373dbbde1cf6c70ee5485 Mon Sep 17 00:00:00 2001 From: Hannes Petermaier Date: Mon, 3 Feb 2014 21:22:18 +0100 Subject: OMAP24xx I2C: Add support for set-speed Adds support for set-speed on the OMAP24xx I2C Adapter. Changes to omap24_i2c_write(...) for polling ARDY Bit from IRQ-Status. Otherwise on a subsequent call the transfer of last byte from the predecessor is aborted and therefore lost. For exmaple when i2c_write(...) is followed by a i2c_setspeed(...) (which has to deactivate and activate master for changing psc,...). Minor cosmetical changes. Signed-off-by: Hannes Petermaier Cc: Heiko Schocher --- drivers/i2c/omap24xx_i2c.c | 147 ++++++++++++++++++++++++++++++--------------- include/i2c.h | 1 + 2 files changed, 98 insertions(+), 50 deletions(-) (limited to 'drivers') diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index c7840049b11..a39b5917ecd 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -32,6 +32,10 @@ * - Status functions now read irqstatus_raw as per TRM guidelines * (except for OMAP243X and OMAP34XX). * - Driver now supports up to I2C5 (OMAP5). + * + * Copyright (c) 2014 Hannes Petermaier , B&R + * - Added support for set_speed + * */ #include @@ -53,43 +57,66 @@ static int wait_for_bb(struct i2c_adapter *adap); static struct i2c *omap24_get_base(struct i2c_adapter *adap); static u16 wait_for_event(struct i2c_adapter *adap); static void flush_fifo(struct i2c_adapter *adap); - -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) { - struct i2c *i2c_base = omap24_get_base(adap); - int psc, fsscll, fssclh; - int hsscll = 0, hssclh = 0; - u32 scll, sclh; - int timeout = I2C_TIMEOUT; + unsigned int sampleclk, prescaler; + int fsscll, fssclh; - /* Only handle standard, fast and high speeds */ - if ((speed != OMAP_I2C_STANDARD) && - (speed != OMAP_I2C_FAST_MODE) && - (speed != OMAP_I2C_HIGH_SPEED)) { - printf("Error : I2C unsupported speed %d\n", speed); - return; - } + speed <<= 1; + prescaler = 0; + /* + * some divisors may cause a precission loss, but shouldn't + * be a big thing, because i2c_clk is then allready very slow. + */ + while (prescaler <= 0xFF) { + sampleclk = I2C_IP_CLK / (prescaler+1); - psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; - psc -= 1; - if (psc < I2C_PSC_MIN) { - printf("Error : I2C unsupported prescalar %d\n", psc); - return; + fsscll = sampleclk / speed; + fssclh = fsscll; + fsscll -= I2C_FASTSPEED_SCLL_TRIM; + fssclh -= I2C_FASTSPEED_SCLH_TRIM; + + if (((fsscll > 0) && (fssclh > 0)) && + ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) && + (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) { + if (pscl) + *pscl = fsscll; + if (psch) + *psch = fssclh; + + return prescaler; + } + prescaler++; } + return -1; +} +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int psc, fsscll = 0, fssclh = 0; + int hsscll = 0, hssclh = 0; + u32 scll = 0, sclh = 0; - if (speed == OMAP_I2C_HIGH_SPEED) { + if (speed >= OMAP_I2C_HIGH_SPEED) { /* High speed */ + psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; + psc -= 1; + if (psc < I2C_PSC_MIN) { + printf("Error : I2C unsupported prescaler %d\n", psc); + return -1; + } /* For first phase of HS mode */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / - (2 * OMAP_I2C_FAST_MODE); + fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); + + fssclh = fsscll; fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing first phase clock\n"); - return; + return -1; } /* For second phase of HS mode */ @@ -100,7 +127,7 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) if (((fsscll < 0) || (fssclh < 0)) || ((fsscll > 255) || (fssclh > 255))) { puts("Error : I2C initializing second phase clock\n"); - return; + return -1; } scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; @@ -108,20 +135,29 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) } else { /* Standard and fast speed */ - fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); - - fsscll -= I2C_FASTSPEED_SCLL_TRIM; - fssclh -= I2C_FASTSPEED_SCLH_TRIM; - if (((fsscll < 0) || (fssclh < 0)) || - ((fsscll > 255) || (fssclh > 255))) { + psc = omap24_i2c_findpsc(&scll, &sclh, speed); + if (0 > psc) { puts("Error : I2C initializing clock\n"); - return; + return -1; } - - scll = (unsigned int)fsscll; - sclh = (unsigned int)fssclh; } + adap->speed = speed; + adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + writew(0, &i2c_base->con); + writew(psc, &i2c_base->psc); + writew(scll, &i2c_base->scll); + writew(sclh, &i2c_base->sclh); + writew(I2C_CON_EN, &i2c_base->con); + writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ + + return 0; +} +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int timeout = I2C_TIMEOUT; + if (readw(&i2c_base->con) & I2C_CON_EN) { writew(0, &i2c_base->con); udelay(50000); @@ -139,14 +175,14 @@ static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) udelay(1000); } - writew(0, &i2c_base->con); - writew(psc, &i2c_base->psc); - writew(scll, &i2c_base->scll); - writew(sclh, &i2c_base->sclh); + if (0 != omap24_i2c_setspeed(adap, speed)) { + printf("ERROR: failed to setup I2C bus-speed!\n"); + return; + } /* own address */ writew(slaveadd, &i2c_base->oa); - writew(I2C_CON_EN, &i2c_base->con); + #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* * Have to enable interrupts for OMAP2/3, these IPs don't have @@ -165,7 +201,8 @@ static void flush_fifo(struct i2c_adapter *adap) struct i2c *i2c_base = omap24_get_base(adap); u16 stat; - /* note: if you try and read data when its not there or ready + /* + * note: if you try and read data when its not there or ready * you get a bus error */ while (1) { @@ -220,8 +257,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { - res = 0; /* Device found */ - udelay(I2C_WAIT); /* Required by AM335X in SPL */ + res = 0; /* Device found */ + udelay(adap->waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -307,7 +344,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", status); @@ -351,7 +388,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto rd_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; goto rd_exit; } @@ -379,6 +416,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int i; u16 status; int i2c_error = 0; + int timeout = I2C_TIMEOUT; if (alen < 0) { puts("I2C write: addr len < 0\n"); @@ -428,7 +466,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, adap->hwadapnr, status); goto wr_exit; } - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", status); @@ -448,7 +486,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, /* Address phase is over, now write data */ for (i = 0; i < len; i++) { status = wait_for_event(adap); - if (status == 0 || status & I2C_STAT_NACK) { + if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", status); @@ -464,6 +502,15 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, goto wr_exit; } } + /* + * poll ARDY bit for making sure that last byte really has been + * transferred on the bus. + */ + do { + status = wait_for_event(adap); + } while (!(status & I2C_STAT_ARDY) && timeout--); + if (timeout <= 0) + printf("i2c_write: timed out writig last byte!\n"); wr_exit: flush_fifo(adap); @@ -490,7 +537,7 @@ static int wait_for_bb(struct i2c_adapter *adap) I2C_STAT_BB) && timeout--) { #endif writew(stat, &i2c_base->stat); - udelay(I2C_WAIT); + udelay(adap->waitdelay); } if (timeout <= 0) { @@ -513,7 +560,7 @@ static u16 wait_for_event(struct i2c_adapter *adap) int timeout = I2C_TIMEOUT; do { - udelay(I2C_WAIT); + udelay(adap->waitdelay); #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) status = readw(&i2c_base->stat); #else @@ -580,12 +627,12 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) #endif U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE, 0) U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, - omap24_i2c_read, omap24_i2c_write, NULL, + omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, CONFIG_SYS_OMAP24_I2C_SPEED1, CONFIG_SYS_OMAP24_I2C_SLAVE1, 1) diff --git a/include/i2c.h b/include/i2c.h index f93a18366e0..1b4078ed62f 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -68,6 +68,7 @@ struct i2c_adapter { uint (*set_bus_speed)(struct i2c_adapter *adap, uint speed); int speed; + int waitdelay; int slaveaddr; int init_done; int hwadapnr; -- cgit v1.2.3 From 3d93f6959b0e91a8ee6845363e18b2d4375a0a53 Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Mon, 10 Feb 2014 12:20:12 +0400 Subject: designware_i2c: remove inclusion of As soon as all boards have their CONFIG_SYS_I2C_BASE defined in configuration files instead of "asm/arch/hardware.h" it's safe to remove the inclusion in question and make driver platform-independent. Cc: Tom Rini Cc: Heiko Schocher Cc: Stefan Roese Cc: Vipin Kumar Cc: Armando Visconti Signed-off-by: Alexey Brodkin --- drivers/i2c/designware_i2c.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers') diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index deea4f83caf..c891ebd39e2 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -7,7 +7,6 @@ #include #include -#include #include "designware_i2c.h" #ifdef CONFIG_I2C_MULTI_BUS -- cgit v1.2.3 From 17eb1d8f5717ec42fe5a5872f1bf413aedf3614c Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Thu, 20 Feb 2014 10:29:18 +0100 Subject: dfu: mmc: fs: Fix format accepted by ext4write command The commit: "EXT4: Fix number base handling of "ext4write" command" SHA1: f7740f7712b8638f08b83a7e5d00bc1d6bb086a9 Cleaned up the ext4write command format. This commit shall be regarded as a follow up, since the DFU subsystem is using those commands for its normal operation. Signed-off-by: Lukasz Majewski --- drivers/dfu/dfu_mmc.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) (limited to 'drivers') diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index f942758696e..0816f46bad8 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -73,16 +73,12 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); break; case DFU_FS_EXT4: sprintf(cmd_buf, "ext4%s mmc %d:%d 0x%x /%s", op == DFU_OP_READ ? "load" : "write", dfu->data.mmc.dev, dfu->data.mmc.part, (unsigned int) buf, dfu->name); - if (op == DFU_OP_WRITE) - sprintf(cmd_buf + strlen(cmd_buf), " %ld", *len); break; default: printf("%s: Layout (%s) not (yet) supported!\n", __func__, @@ -90,6 +86,9 @@ static int mmc_file_op(enum dfu_op op, struct dfu_entity *dfu, return -1; } + if (op == DFU_OP_WRITE) + sprintf(cmd_buf + strlen(cmd_buf), " %lx", *len); + debug("%s: %s 0x%p\n", __func__, cmd_buf, cmd_buf); ret = run_command(cmd_buf, 0); -- cgit v1.2.3 From 130fbeb1c51f19a2b81c4e27d23da735b5b235d4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 20 Feb 2014 10:14:10 -0500 Subject: blackfin: Add to numerous drivers With d6a320d we moved some clock externs out of blackfin_local.h and into clock.h but now need to include in more drivers to avoid warnings. Cc: Sonic Zhang Signed-off-by: Tom Rini --- arch/blackfin/lib/board.c | 1 + board/cm-bf548/video.c | 1 + common/cmd_otp.c | 1 + drivers/block/pata_bfin.c | 1 + drivers/mmc/bfin_sdh.c | 1 + drivers/net/bfin_mac.c | 1 + drivers/usb/musb/blackfin_usb.c | 1 + 7 files changed, 7 insertions(+) (limited to 'drivers') diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index facbc7a563f..62342014a47 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -23,6 +23,7 @@ #include #include +#include #include #ifdef CONFIG_CMD_NAND diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c index a43413e976f..c35d2850708 100644 --- a/board/cm-bf548/video.c +++ b/board/cm-bf548/video.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/common/cmd_otp.c b/common/cmd_otp.c index 6f933355176..67808aa377e 100644 --- a/common/cmd_otp.c +++ b/common/cmd_otp.c @@ -18,6 +18,7 @@ #include #include +#include #include static const char *otp_strerror(uint32_t err) diff --git a/drivers/block/pata_bfin.c b/drivers/block/pata_bfin.c index 27ecaf4f9ed..b7fd1cd6344 100644 --- a/drivers/block/pata_bfin.c +++ b/drivers/block/pata_bfin.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 26311741f5f..bd9b641135a 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 42e208cfb60..0c2d2ef1a96 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -16,6 +16,7 @@ #include #include +#include #include #include #include diff --git a/drivers/usb/musb/blackfin_usb.c b/drivers/usb/musb/blackfin_usb.c index 35268ba58ef..65fff887d3e 100644 --- a/drivers/usb/musb/blackfin_usb.c +++ b/drivers/usb/musb/blackfin_usb.c @@ -11,6 +11,7 @@ #include #include +#include #include #include "musb_core.h" -- cgit v1.2.3 From 1d568c7666e81fa920de38a3c83895764ea8cf0f Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Sat, 8 Feb 2014 10:10:01 +0400 Subject: serial/serial_arc: add work-around of ISS bug Explanation is in in-lined comment. Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Noam Camus Cc: Tom Rini --- drivers/serial/serial_arc.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers') diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index e63d25d7949..55d07691fcf 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -39,7 +39,23 @@ static void arc_serial_setbrg(void) arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; writel(arc_console_baud & 0xff, ®s->baudl); + +#ifdef CONFIG_ARC + /* + * UART ISS(Instruction Set simulator) emulation has a subtle bug: + * A existing value of Baudh = 0 is used as a indication to startup + * it's internal state machine. + * Thus if baudh is set to 0, 2 times, it chokes. + * This happens with BAUD=115200 and the formaula above + * Until that is fixed, when running on ISS, we will set baudh to !0 + */ + if (gd->arch.running_on_hw) + writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); + else + writel(1, ®s->baudh); +#else writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); +#endif } static int arc_serial_init(void) -- cgit v1.2.3 From 94b5400e76f6a5100e2af88de274b0a6881bf94d Mon Sep 17 00:00:00 2001 From: Alexey Brodkin Date: Sat, 8 Feb 2014 10:10:02 +0400 Subject: serial/serial_arc: switch from {read|write}l to {read|write}b accessors This is required for proper functionality on big-endian targets. Memory-mapped registres of ARC UART are not 32-bit words but 8-bit bytes so on little-endian target either acessor (_l or _b) works fine. On big-endian only _b accessors works as expected. Signed-off-by: Alexey Brodkin Cc: Vineet Gupta Cc: Noam Camus Cc: Tom Rini --- drivers/serial/serial_arc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index 55d07691fcf..b21b12ba442 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -38,7 +38,7 @@ static void arc_serial_setbrg(void) gd->baudrate = CONFIG_BAUDRATE; arc_console_baud = gd->cpu_clk / (gd->baudrate * 4) - 1; - writel(arc_console_baud & 0xff, ®s->baudl); + writeb(arc_console_baud & 0xff, ®s->baudl); #ifdef CONFIG_ARC /* @@ -50,11 +50,11 @@ static void arc_serial_setbrg(void) * Until that is fixed, when running on ISS, we will set baudh to !0 */ if (gd->arch.running_on_hw) - writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); else - writel(1, ®s->baudh); + writeb(1, ®s->baudh); #else - writel((arc_console_baud & 0xff00) >> 8, ®s->baudh); + writeb((arc_console_baud & 0xff00) >> 8, ®s->baudh); #endif } @@ -70,15 +70,15 @@ static void arc_serial_putc(const char c) if (c == '\n') arc_serial_putc('\r'); - while (!(readl(®s->status) & UART_TXEMPTY)) + while (!(readb(®s->status) & UART_TXEMPTY)) ; - writel(c, ®s->data); + writeb(c, ®s->data); } static int arc_serial_tstc(void) { - return !(readl(®s->status) & UART_RXEMPTY); + return !(readb(®s->status) & UART_RXEMPTY); } static int arc_serial_getc(void) @@ -87,10 +87,10 @@ static int arc_serial_getc(void) ; /* Check for overflow errors */ - if (readl(®s->status) & UART_OVERFLOW_ERR) + if (readb(®s->status) & UART_OVERFLOW_ERR) return 0; - return readl(®s->data) & 0xFF; + return readb(®s->data) & 0xFF; } static void arc_serial_puts(const char *s) -- cgit v1.2.3 From 1cb8393a1363bdc15946ef5b0b20bd10717daa74 Mon Sep 17 00:00:00 2001 From: Axel Lin Date: Sat, 8 Feb 2014 15:04:58 +0800 Subject: serial: arc: Convert to use default_serial_puts Use default_serial_puts() instead of duplicating the implementation. Signed-off-by: Axel Lin --- drivers/serial/serial_arc.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers') diff --git a/drivers/serial/serial_arc.c b/drivers/serial/serial_arc.c index b21b12ba442..2ddbf32a507 100644 --- a/drivers/serial/serial_arc.c +++ b/drivers/serial/serial_arc.c @@ -93,19 +93,13 @@ static int arc_serial_getc(void) return readb(®s->data) & 0xFF; } -static void arc_serial_puts(const char *s) -{ - while (*s) - arc_serial_putc(*s++); -} - static struct serial_device arc_serial_drv = { .name = "arc_serial", .start = arc_serial_init, .stop = NULL, .setbrg = arc_serial_setbrg, .putc = arc_serial_putc, - .puts = arc_serial_puts, + .puts = default_serial_puts, .getc = arc_serial_getc, .tstc = arc_serial_tstc, }; -- cgit v1.2.3 From 4e5b1bd0dff216b00d7ce9a5201dfe173805a06c Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:42 -0800 Subject: driver/ddr: Change Freescale ARM DDR driver to support both big and little endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun --- README | 6 +++ drivers/ddr/fsl/arm_ddr_gen3.c | 103 +++++++++++++++++++++-------------------- drivers/ddr/fsl/ctrl_regs.c | 4 +- drivers/ddr/fsl/util.c | 12 ++--- include/fsl_ddr.h | 9 ++++ 5 files changed, 75 insertions(+), 59 deletions(-) (limited to 'drivers') diff --git a/README b/README index 6668631bccc..413d6828292 100644 --- a/README +++ b/README @@ -486,6 +486,12 @@ The following options need to be configured: PBI commands can be used to configure SoC before it starts the execution. Please refer doc/README.pblimage for more details + CONFIG_SYS_FSL_DDR_BE + Defines the DDR controller register space as Big Endian + + CONFIG_SYS_FSL_DDR_LE + Defines the DDR controller register space as Little Endian + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index bf113908fd4..d4ed9aec2ae 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -11,6 +11,7 @@ #include #include #include +#include #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL @@ -63,54 +64,54 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, goto step2; if (regs->ddr_eor) - out_be32(&ddr->eor, regs->ddr_eor); + ddr_out32(&ddr->eor, regs->ddr_eor); for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { if (i == 0) { - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs0_config, regs->cs[i].config); - out_be32(&ddr->cs0_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs0_config, regs->cs[i].config); + ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2); } else if (i == 1) { - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs1_config, regs->cs[i].config); - out_be32(&ddr->cs1_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs1_config, regs->cs[i].config); + ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2); } else if (i == 2) { - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs2_config, regs->cs[i].config); - out_be32(&ddr->cs2_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs2_config, regs->cs[i].config); + ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2); } else if (i == 3) { - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); - out_be32(&ddr->cs3_config, regs->cs[i].config); - out_be32(&ddr->cs3_config_2, regs->cs[i].config_2); + ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds); + ddr_out32(&ddr->cs3_config, regs->cs[i].config); + ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2); } } - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); - out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); - out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); - out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); - out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); - out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); - out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); - out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); - out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); - out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); + ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3); + ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); + ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); + ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); + ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); + ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); + ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4); + ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5); + ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6); + ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7); + ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8); + ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); + ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); + ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); + ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + + ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); + ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); + ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); + ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU /* * Skip these two registers if running on emulator @@ -118,23 +119,23 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, */ if (regs->ddr_wrlvl_cntl_2) - out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); + ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); if (regs->ddr_wrlvl_cntl_3) - out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); + ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); #endif - out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); - out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); - out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); - out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); - out_be32(&ddr->err_disable, regs->err_disable); - out_be32(&ddr->err_int_en, regs->err_int_en); + ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); + ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); + ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); + ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + ddr_out32(&ddr->err_disable, regs->err_disable); + ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { if (regs->debug[i]) { debug("Write to debug_%d as %08x\n", i + 1, regs->debug[i]); - out_be32(&ddr->debug[i], regs->debug[i]); + ddr_out32(&ddr->debug[i], regs->debug[i]); } } @@ -155,7 +156,7 @@ step2: /* Set, but do not enable the memory */ temp_sdram_cfg = regs->ddr_sdram_cfg; temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN); - out_be32(&ddr->sdram_cfg, temp_sdram_cfg); + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg); /* * 500 painful micro-seconds must elapse between @@ -167,8 +168,8 @@ step2: asm volatile("dsb sy;isb"); /* Let the controller go */ - temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; - out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; + ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("dsb sy;isb"); total_gb_size_per_controller = 0; @@ -202,7 +203,7 @@ step2: debug("Need to wait up to %d * 10ms\n", timeout); /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */ - while ((in_be32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && + while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) && (timeout >= 0)) { udelay(10000); /* throttle polling rate */ timeout--; diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 6bf22cfbd6f..5acbc737ba0 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -25,8 +25,8 @@ static u32 fsl_ddr_get_version(void) u32 ver_major_minor_errata; ddr = (void *)_DDR_ADDR; - ver_major_minor_errata = (in_be32(&ddr->ip_rev1) & 0xFFFF) << 8; - ver_major_minor_errata |= (in_be32(&ddr->ip_rev2) & 0xFF00) >> 8; + ver_major_minor_errata = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8; + ver_major_minor_errata |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8; return ver_major_minor_errata; } diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 0658261d8da..450a4887126 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -146,21 +146,21 @@ void board_add_ram_info(int use_default) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); #endif #if (CONFIG_NUM_DDR_CONTROLLERS > 1) - uint32_t cs0_config = in_be32(&ddr->cs0_config); + uint32_t cs0_config = ddr_in32(&ddr->cs0_config); #endif - uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg); + uint32_t sdram_cfg = ddr_in32(&ddr->sdram_cfg); int cas_lat; #if CONFIG_NUM_DDR_CONTROLLERS >= 2 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif #if CONFIG_NUM_DDR_CONTROLLERS >= 3 if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) { ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; - sdram_cfg = in_be32(&ddr->sdram_cfg); + sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif puts(" (DDR"); @@ -188,8 +188,8 @@ void board_add_ram_info(int use_default) puts(", 64-bit"); /* Calculate CAS latency based on timing cfg values */ - cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; - if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1) + cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1; + if ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 1) cas_lat += (8 << 1); printf(", CL=%d", cas_lat >> 1); if (cas_lat & 0x1) diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index e03f9db5f2e..72c0b2e94ed 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -14,6 +14,14 @@ #include +#ifdef CONFIG_SYS_FSL_DDR_LE +#define ddr_in32(a) in_le32(a) +#define ddr_out32(a, v) out_le32(a, v) +#else +#define ddr_in32(a) in_be32(a) +#define ddr_out32(a, v) out_be32(a, v) +#endif + #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names @@ -93,6 +101,7 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); +void board_add_ram_info(int use_default); /* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, -- cgit v1.2.3 From 6b9e309a8a7f0f33252288f0ed8794a83a488301 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:43 -0800 Subject: Driver/ddr: Add support of different DDR base address DDR base address has been the same from the view of core and DDR controllers. This has changed for Freescale ARM-based SoCs. Controllers setup DDR memory in a contiguous space and cores view it at separated locations. Signed-off-by: York Sun --- README | 5 +++++ drivers/ddr/fsl/main.c | 16 ++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/README b/README index 413d6828292..355e8988236 100644 --- a/README +++ b/README @@ -492,6 +492,11 @@ The following options need to be configured: CONFIG_SYS_FSL_DDR_LE Defines the DDR controller register space as Little Endian + CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + Physical address from the view of DDR controllers. It is the + same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But + it could be different for ARM SoCs. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index d0cd58925c3..dee50a0789b 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -17,6 +17,18 @@ #include #include +/* + * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for + * all Power SoCs. But it could be different for ARM SoCs. For example, + * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of + * 0x00_8000_0000 ~ 0x00_ffff_ffff + * 0x80_8000_0000 ~ 0xff_ffff_ffff + */ +#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#endif + #ifdef CONFIG_PPC #include @@ -255,7 +267,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]); } - current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE; + current_mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; total_mem = 0; if (pinfo->memctl_opts[0].memctl_interleaving) { rank_density = pinfo->dimm_params[0][0].rank_density >> @@ -536,7 +548,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } total_mem = 1 + (((unsigned long long)max_end << 24ULL) | - 0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE; + 0xFFFFFFULL) - CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; } return total_mem; -- cgit v1.2.3 From 6b1e1254f326940e5b65c7029f71b964bdf28fd4 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 10 Feb 2014 13:59:44 -0800 Subject: driver/ddr: Add 256 byte interleaving support Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun --- README | 5 +++++ drivers/ddr/fsl/ctrl_regs.c | 1 + drivers/ddr/fsl/main.c | 1 + drivers/ddr/fsl/options.c | 17 +++++++++++++++-- drivers/ddr/fsl/util.c | 3 +++ include/fsl_ddr_sdram.h | 1 + 6 files changed, 26 insertions(+), 2 deletions(-) (limited to 'drivers') diff --git a/README b/README index 355e8988236..f51f17ec693 100644 --- a/README +++ b/README @@ -497,6 +497,11 @@ The following options need to be configured: same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. + CONFIG_SYS_FSL_DDR_INTLV_256B + DDR controller interleaving on 256-byte. This is a special + interleaving mode, handled by Dickens for Freescale layerscape + SoCs with ARM core. + - Intel Monahans options: CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 5acbc737ba0..0882932b070 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -145,6 +145,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr, if (!popts->memctl_interleaving) break; switch (popts->memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index dee50a0789b..d62ca63c770 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -291,6 +291,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo, for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { if (pinfo->memctl_opts[i].memctl_interleaving) { switch (pinfo->memctl_opts[i].memctl_interleaving_mode) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 4aafcceaf59..b0cf046fdcd 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -818,21 +818,33 @@ unsigned int populate_memctl_options(int all_dimms_registered, * If memory controller interleaving is enabled, then the data * bus widths must be programmed identically for all memory controllers. * - * XXX: Attempt to set all controllers to the same chip select + * Attempt to set all controllers to the same chip select * interleaving mode. It will do a best effort to get the * requested ranks interleaved together such that the result * should be a subset of the requested configuration. + * + * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving + * with 256 Byte is enabled. */ #if (CONFIG_NUM_DDR_CONTROLLERS > 1) if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf)) +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + ; +#else goto done; - +#endif if (pdimm[0].n_ranks == 0) { printf("There is no rank on CS0 for controller %d.\n", ctrl_num); popts->memctl_interleaving = 0; goto done; } popts->memctl_interleaving = 1; +#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B + popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING; + popts->memctl_interleaving = 1; + debug("256 Byte interleaving\n"); + goto done; +#endif /* * test null first. if CONFIG_HWCONFIG is not defined * hwconfig_arg_cmp returns non-zero @@ -1085,6 +1097,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo) "Memory controller interleaving disabled.\n"); } else { switch (check_intlv) { + case FSL_DDR_256B_INTERLEAVING: case FSL_DDR_CACHE_LINE_INTERLEAVING: case FSL_DDR_PAGE_INTERLEAVING: case FSL_DDR_BANK_INTERLEAVING: diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 450a4887126..ad53658fc92 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -228,6 +228,9 @@ void board_add_ram_info(int use_default) puts(" DDR Controller Interleaving Mode: "); switch ((cs0_config >> 24) & 0xf) { + case FSL_DDR_256B_INTERLEAVING: + puts("256B"); + break; case FSL_DDR_CACHE_LINE_INTERLEAVING: puts("cache line"); break; diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 16cccc77083..2a36431146d 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_PAGE_INTERLEAVING 0x1 #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +#define FSL_DDR_256B_INTERLEAVING 0x8 #define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA #define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC #define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD -- cgit v1.2.3 From ee456337c6820721a7e5f7819830179fcafa9fc2 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 5 Feb 2014 13:09:56 +0530 Subject: SMC91111: Fix compilation warnings This patch fixes the following warning messages coming out of 'drivers/net/smc91111.h' when compiled for 'vexpress_aemv8a': warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Currently this issue seems to surface when SMSC is compiled for 64-bit ARMv8 platforms, so the change is protected under CONFIG_ARM64, so that it doesn't break other existing platforms. In addition this patch tries to fix some checkpatch errors and warnings (others related to camel-casing and volatile usage will be addressed by a later patch). This fix has been tested on both ARMv8 foundation model v1 and v2. Signed-off-by: Bhupesh Sharma --- drivers/net/smc91111.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'drivers') diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 9deee9bd2a0..d9135cb57df 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -248,17 +248,26 @@ struct smc91111_priv{ #define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN #define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) +#elif CONFIG_ARM64 +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r))))) #else -#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r)))) #endif #define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) #ifdef CONFIG_ADNPESC1 #define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} +#define SMC_outw(a, d, r) \ + ({ (*((volatile word*)((a)->iobase+((r)))) = d); \ + SSYNC(); \ + }) +#elif CONFIG_ARM64 +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+((dword)(r)))) = d) #else -#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) +#define SMC_outw(a, d, r) \ + (*((volatile word*)((a)->iobase+(r))) = d) #endif #define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ word __w = SMC_inw((a),(r)&~1); \ -- cgit v1.2.3 From 24e5219754111b52b2f59cd48d96f934f9bbf02b Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Tue, 11 Feb 2014 11:06:35 -0800 Subject: gpio: kona: Add Kona gpio driver Add support for the Kona GPIO controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Markus Mayer Reviewed-by: Tim Kryger --- drivers/gpio/Makefile | 1 + drivers/gpio/kona_gpio.c | 141 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) create mode 100644 drivers/gpio/kona_gpio.c (limited to 'drivers') diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b903c45c524..ed2c0c735b0 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MARVELL_MFP) += mvmfp.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c new file mode 100644 index 00000000000..65117438c57 --- /dev/null +++ b/drivers/gpio/kona_gpio.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define GPIO_BASE (void *)GPIO2_BASE_ADDR + +#define GPIO_PASSWD 0x00a5a501 +#define GPIO_PER_BANK 32 +#define GPIO_MAX_BANK_NUM 8 + +#define GPIO_BANK(gpio) ((gpio) >> 5) +#define GPIO_BITMASK(gpio) \ + (1UL << ((gpio) & (GPIO_PER_BANK - 1))) + +#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) +#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) +#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) +#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) +#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) +#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) +#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) +#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) +#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) + +#define GPIO_GPPWR_OFFSET 0x00000520 + +#define GPIO_GPCTR0_DBR_SHIFT 5 +#define GPIO_GPCTR0_DBR_MASK 0x000001e0 + +#define GPIO_GPCTR0_ITR_SHIFT 3 +#define GPIO_GPCTR0_ITR_MASK 0x00000018 +#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 +#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 +#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 + +#define GPIO_GPCTR0_IOTR_MASK 0x00000001 +#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 +#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 + +int gpio_request(unsigned gpio, const char *label) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_free(unsigned gpio) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + u32 val; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_INPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* read the GPIO bank status */ + off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? + GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); + val = readl(GPIO_BASE + off); + + /* return the specified bit status */ + return !!(val & bitmask); +} + +void gpio_set_value(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* this function only applies to output pin */ + if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { + printf("%s: Cannot set an input pin %d\n", __func__, gpio); + return; + } + + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); +} -- cgit v1.2.3 From 4bded3a367b5f0e4025b6460bf8e5101b2f2faac Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Tue, 11 Feb 2014 11:06:36 -0800 Subject: i2c: kona: Add Kona I2C driver Add support for the Kona I2C controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Tim Kryger --- drivers/i2c/Makefile | 1 + drivers/i2c/kona_i2c.c | 730 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 731 insertions(+) create mode 100644 drivers/i2c/kona_i2c.c (limited to 'drivers') diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index fa3a875705b..36d5e5f1a2e 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o +obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c new file mode 100644 index 00000000000..0b1715abf0d --- /dev/null +++ b/drivers/i2c/kona_i2c.c @@ -0,0 +1,730 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware register offsets and field defintions */ +#define CS_OFFSET 0x00000020 +#define CS_ACK_SHIFT 3 +#define CS_ACK_MASK 0x00000008 +#define CS_ACK_CMD_GEN_START 0x00000000 +#define CS_ACK_CMD_GEN_RESTART 0x00000001 +#define CS_CMD_SHIFT 1 +#define CS_CMD_CMD_NO_ACTION 0x00000000 +#define CS_CMD_CMD_START_RESTART 0x00000001 +#define CS_CMD_CMD_STOP 0x00000002 +#define CS_EN_SHIFT 0 +#define CS_EN_CMD_ENABLE_BSC 0x00000001 + +#define TIM_OFFSET 0x00000024 +#define TIM_PRESCALE_SHIFT 6 +#define TIM_P_SHIFT 3 +#define TIM_NO_DIV_SHIFT 2 +#define TIM_DIV_SHIFT 0 + +#define DAT_OFFSET 0x00000028 + +#define TOUT_OFFSET 0x0000002c + +#define TXFCR_OFFSET 0x0000003c +#define TXFCR_FIFO_FLUSH_MASK 0x00000080 +#define TXFCR_FIFO_EN_MASK 0x00000040 + +#define IER_OFFSET 0x00000044 +#define IER_READ_COMPLETE_INT_MASK 0x00000010 +#define IER_I2C_INT_EN_MASK 0x00000008 +#define IER_FIFO_INT_EN_MASK 0x00000002 +#define IER_NOACK_EN_MASK 0x00000001 + +#define ISR_OFFSET 0x00000048 +#define ISR_RESERVED_MASK 0xffffff60 +#define ISR_CMDBUSY_MASK 0x00000080 +#define ISR_READ_COMPLETE_MASK 0x00000010 +#define ISR_SES_DONE_MASK 0x00000008 +#define ISR_ERR_MASK 0x00000004 +#define ISR_TXFIFOEMPTY_MASK 0x00000002 +#define ISR_NOACK_MASK 0x00000001 + +#define CLKEN_OFFSET 0x0000004c +#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 +#define CLKEN_M_SHIFT 4 +#define CLKEN_N_SHIFT 1 +#define CLKEN_CLKEN_MASK 0x00000001 + +#define FIFO_STATUS_OFFSET 0x00000054 +#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 +#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 + +#define HSTIM_OFFSET 0x00000058 +#define HSTIM_HS_MODE_MASK 0x00008000 +#define HSTIM_HS_HOLD_SHIFT 10 +#define HSTIM_HS_HIGH_PHASE_SHIFT 5 +#define HSTIM_HS_SETUP_SHIFT 0 + +#define PADCTL_OFFSET 0x0000005c +#define PADCTL_PAD_OUT_EN_MASK 0x00000004 + +#define RXFCR_OFFSET 0x00000068 +#define RXFCR_NACK_EN_SHIFT 7 +#define RXFCR_READ_COUNT_SHIFT 0 +#define RXFIFORDOUT_OFFSET 0x0000006c + +/* Locally used constants */ +#define MAX_RX_FIFO_SIZE 64U /* bytes */ +#define MAX_TX_FIFO_SIZE 64U /* bytes */ + +#define I2C_TIMEOUT 100000 /* usecs */ + +#define WAIT_INT_CHK 100 /* usecs */ +#if I2C_TIMEOUT % WAIT_INT_CHK +#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK +#endif + +/* Operations that can be commanded to the controller */ +enum bcm_kona_cmd_t { + BCM_CMD_NOACTION = 0, + BCM_CMD_START, + BCM_CMD_RESTART, + BCM_CMD_STOP, +}; + +enum bus_speed_index { + BCM_SPD_100K = 0, + BCM_SPD_400K, + BCM_SPD_1MHZ, +}; + +/* Internal divider settings for standard mode, fast mode and fast mode plus */ +struct bus_speed_cfg { + uint8_t time_m; /* Number of cycles for setup time */ + uint8_t time_n; /* Number of cycles for hold time */ + uint8_t prescale; /* Prescale divider */ + uint8_t time_p; /* Timing coefficient */ + uint8_t no_div; /* Disable clock divider */ + uint8_t time_div; /* Post-prescale divider */ +}; + +static const struct bus_speed_cfg std_cfg_table[] = { + [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, + [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, + [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, +}; + +struct bcm_kona_i2c_dev { + void *base; + uint speed; + const struct bus_speed_cfg *std_cfg; +}; + +/* Keep these two defines in sync */ +#define DEF_SPD 100000 +#define DEF_SPD_ENUM BCM_SPD_100K + +#define DEF_DEVICE(num) \ +{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]} + +static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_DEVICE(0), +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_DEVICE(1), +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_DEVICE(2), +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_DEVICE(3), +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_DEVICE(4), +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_DEVICE(5), +#endif +}; + +#define I2C_M_TEN 0x0010 /* ten bit address */ +#define I2C_M_RD 0x0001 /* read data */ +#define I2C_M_NOSTART 0x4000 /* no restart between msgs */ + +struct i2c_msg { + uint16_t addr; + uint16_t flags; + uint16_t len; + uint8_t *buf; +}; + +static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + debug("%s, %d\n", __func__, cmd); + + switch (cmd) { + case BCM_CMD_NOACTION: + writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_START: + writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_RESTART: + writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | + (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + case BCM_CMD_STOP: + writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | + (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), + dev->base + CS_OFFSET); + break; + + default: + printf("Unknown command %d\n", cmd); + } +} + +static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, + dev->base + CLKEN_OFFSET); +} + +/* Wait until at least one of the mask bit(s) are set */ +static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev, + unsigned long time_left, + uint32_t mask) +{ + uint32_t status; + + while (time_left) { + status = readl(dev->base + ISR_OFFSET); + + if ((status & ~ISR_RESERVED_MASK) == 0) { + debug("Bogus I2C interrupt 0x%x\n", status); + continue; + } + + /* Must flush the TX FIFO when NAK detected */ + if (status & ISR_NOACK_MASK) + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); + + if (status & mask) { + /* We are done since one of the mask bits are set */ + return time_left; + } + udelay(WAIT_INT_CHK); + time_left -= WAIT_INT_CHK; + } + return 0; +} + +/* Send command to I2C bus */ +static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, + enum bcm_kona_cmd_t cmd) +{ + int rc = 0; + unsigned long time_left = I2C_TIMEOUT; + + /* Send the command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); + + /* Wait for transaction to finish or timeout */ + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + printf("controller timed out\n"); + rc = -ETIMEDOUT; + } + + /* Clear command */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + return rc; +} + +/* Read a single RX FIFO worth of data from the i2c bus */ +static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len, + unsigned int last_byte_nak) +{ + unsigned long time_left = I2C_TIMEOUT; + + /* Start the RX FIFO */ + writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | + (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET); + + /* Wait for FIFO read to complete */ + time_left = + wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK); + + if (!time_left) { + printf("RX FIFO time out\n"); + return -EREMOTEIO; + } + + /* Read data from FIFO */ + for (; len > 0; len--, buf++) + *buf = readl(dev->base + RXFIFORDOUT_OFFSET); + + return 0; +} + +/* Read any amount of data using the RX FIFO from the i2c bus */ +static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; + unsigned int last_byte_nak = 0; + unsigned int bytes_read = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_read < msg->len) { + if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { + last_byte_nak = 1; /* NAK last byte of transfer */ + bytes_to_read = msg->len - bytes_read; + } + + rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, + last_byte_nak); + if (rc < 0) + return -EREMOTEIO; + + bytes_read += bytes_to_read; + tmp_buf += bytes_to_read; + } + + return 0; +} + +/* Write a single byte of data to the i2c bus */ +static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, + unsigned int nak_expected) +{ + unsigned long time_left = I2C_TIMEOUT; + unsigned int nak_received; + + /* Clear pending session done interrupt */ + writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); + + /* Send one byte of data */ + writel(data, dev->base + DAT_OFFSET); + + time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK); + + if (!time_left) { + debug("controller timed out\n"); + return -ETIMEDOUT; + } + + nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; + + if (nak_received ^ nak_expected) { + debug("unexpected NAK/ACK\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write a single TX FIFO worth of data to the i2c bus */ +static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, + uint8_t *buf, unsigned int len) +{ + int k; + unsigned long time_left = I2C_TIMEOUT; + unsigned int fifo_status; + + /* Write data into FIFO */ + for (k = 0; k < len; k++) + writel(buf[k], (dev->base + DAT_OFFSET)); + + /* Wait for FIFO to empty */ + do { + time_left = + wait_for_int_timeout(dev, time_left, + (IER_FIFO_INT_EN_MASK | + IER_NOACK_EN_MASK)); + fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); + } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); + + /* Check if there was a NAK */ + if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { + printf("unexpected NAK\n"); + return -EREMOTEIO; + } + + /* Check if a timeout occured */ + if (!time_left) { + printf("completion timed out\n"); + return -EREMOTEIO; + } + + return 0; +} + +/* Write any amount of data using TX FIFO to the i2c bus */ +static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; + unsigned int bytes_written = 0; + int rc; + + uint8_t *tmp_buf = msg->buf; + + while (bytes_written < msg->len) { + if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) + bytes_to_write = msg->len - bytes_written; + + rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, + bytes_to_write); + if (rc < 0) + return -EREMOTEIO; + + bytes_written += bytes_to_write; + tmp_buf += bytes_to_write; + } + + return 0; +} + +/* Send i2c address */ +static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, + struct i2c_msg *msg) +{ + unsigned char addr; + + if (msg->flags & I2C_M_TEN) { + /* First byte is 11110XX0 where XX is upper 2 bits */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7); + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + /* Second byte is the remaining 8 bits */ + addr = msg->addr & 0xff; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + + if (msg->flags & I2C_M_RD) { + /* For read, send restart command */ + if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) + return -EREMOTEIO; + + /* Then re-send the first byte with the read bit set */ + addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01; + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + } else { + addr = msg->addr << 1; + + if (msg->flags & I2C_M_RD) + addr |= 1; + + if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) + return -EREMOTEIO; + } + + return 0; +} + +static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, + dev->base + CLKEN_OFFSET); +} + +static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) +{ + writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, + dev->base + HSTIM_OFFSET); + + writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | + (dev->std_cfg->time_p << TIM_P_SHIFT) | + (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | + (dev->std_cfg->time_div << TIM_DIV_SHIFT), + dev->base + TIM_OFFSET); + + writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | + (dev->std_cfg->time_n << CLKEN_N_SHIFT) | + CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET); +} + +/* Master transfer function */ +static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, + struct i2c_msg msgs[], int num) +{ + struct i2c_msg *pmsg; + int rc = 0; + int i; + + /* Enable pad output */ + writel(0, dev->base + PADCTL_OFFSET); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Send start command */ + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); + if (rc < 0) { + printf("Start command failed rc = %d\n", rc); + goto xfer_disable_pad; + } + + /* Loop through all messages */ + for (i = 0; i < num; i++) { + pmsg = &msgs[i]; + + /* Send restart for subsequent messages */ + if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { + rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); + if (rc < 0) { + printf("restart cmd failed rc = %d\n", rc); + goto xfer_send_stop; + } + } + + /* Send slave address */ + if (!(pmsg->flags & I2C_M_NOSTART)) { + rc = bcm_kona_i2c_do_addr(dev, pmsg); + if (rc < 0) { + debug("NAK from addr %2.2x msg#%d rc = %d\n", + pmsg->addr, i, rc); + goto xfer_send_stop; + } + } + + /* Perform data transfer */ + if (pmsg->flags & I2C_M_RD) { + rc = bcm_kona_i2c_read_fifo(dev, pmsg); + if (rc < 0) { + printf("read failure\n"); + goto xfer_send_stop; + } + } else { + rc = bcm_kona_i2c_write_fifo(dev, pmsg); + if (rc < 0) { + printf("write failure"); + goto xfer_send_stop; + } + } + } + + rc = num; + +xfer_send_stop: + /* Send a STOP command */ + bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); + +xfer_disable_pad: + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); + + /* Stop internal clock */ + bcm_kona_i2c_disable_clock(dev); + + return rc; +} + +static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev, + uint speed) +{ + switch (speed) { + case 100000: + dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; + break; + case 400000: + dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; + break; + case 1000000: + dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; + break; + default: + printf("%d hz bus speed not supported\n", speed); + return -EINVAL; + } + dev->speed = speed; + return 0; +} + +static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev) +{ + /* Parse bus speed */ + bcm_kona_i2c_assign_bus_speed(dev, dev->speed); + + /* Enable internal clocks */ + bcm_kona_i2c_enable_clock(dev); + + /* Configure internal dividers */ + bcm_kona_i2c_config_timing(dev); + + /* Disable timeout */ + writel(0, dev->base + TOUT_OFFSET); + + /* Enable autosense */ + bcm_kona_i2c_enable_autosense(dev); + + /* Enable TX FIFO */ + writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, + dev->base + TXFCR_OFFSET); + + /* Mask all interrupts */ + writel(0, dev->base + IER_OFFSET); + + /* Clear all pending interrupts */ + writel(ISR_CMDBUSY_MASK | + ISR_READ_COMPLETE_MASK | + ISR_SES_DONE_MASK | + ISR_ERR_MASK | + ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET); + + /* Enable the controller but leave it idle */ + bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); + + /* Disable pad output */ + writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); +} + +/* + * uboot layer + */ +struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap) +{ + return &g_i2c_devs[adap->hwadapnr]; +} + +static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + if (clk_bsc_enable(dev->base)) + return; + + bcm_kona_i2c_init(dev); +} + +static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + /* msg[0] writes the addr, msg[1] reads the data */ + struct i2c_msg msg[2]; + unsigned char msgbuf0[64]; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */ + + msg[1].addr = chip; + msg[1].flags = I2C_M_RD; + /* msg[1].buf dest ptr increments each read */ + + msgbuf0[0] = (unsigned char)addr; + msg[1].buf = buffer; + msg[1].len = len; + if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) { + /* Sending 2 i2c messages */ + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C read: I/O error\n"); + return -EIO; + } + return 0; +} + +static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c_msg msg[0]; + unsigned char msgbuf0[64]; + unsigned int i; + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + + msg[0].addr = chip; + msg[0].flags = 0; + msg[0].len = 2; /* addr byte plus data */ + msg[0].buf = msgbuf0; + + for (i = 0; i < len; i++) { + msgbuf0[0] = addr++; + msgbuf0[1] = buffer[i]; + if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) { + kona_i2c_init(adap, adap->speed, adap->slaveaddr); + debug("I2C write: I/O error\n"); + return -EIO; + } + } + return 0; +} + +static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + uchar tmp; + + /* + * read addr 0x0 of the given chip. + */ + return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1); +} + +static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) +{ + struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); + return bcm_kona_i2c_assign_bus_speed(dev, speed); +} + +/* + * Register kona i2c adapters. Keep the order below so + * that the bus number matches the adapter number. + */ +#define DEF_ADAPTER(num) \ +U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \ + kona_i2c_read, kona_i2c_write, \ + kona_i2c_set_bus_speed, DEF_SPD, 0x00, num) + +#ifdef CONFIG_SYS_I2C_BASE0 + DEF_ADAPTER(0) +#endif +#ifdef CONFIG_SYS_I2C_BASE1 + DEF_ADAPTER(1) +#endif +#ifdef CONFIG_SYS_I2C_BASE2 + DEF_ADAPTER(2) +#endif +#ifdef CONFIG_SYS_I2C_BASE3 + DEF_ADAPTER(3) +#endif +#ifdef CONFIG_SYS_I2C_BASE4 + DEF_ADAPTER(4) +#endif +#ifdef CONFIG_SYS_I2C_BASE5 + DEF_ADAPTER(5) +#endif -- cgit v1.2.3 From 7a9d0ad009dfde35d1c377c1c1203ccf2478c773 Mon Sep 17 00:00:00 2001 From: Darwin Rambo Date: Tue, 11 Feb 2014 11:06:37 -0800 Subject: mmc: kona: Add Kona mmc driver Add support for the Kona SDHCI found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Tim Kryger --- drivers/mmc/Makefile | 1 + drivers/mmc/kona_sdhci.c | 134 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 135 insertions(+) create mode 100644 drivers/mmc/kona_sdhci.c (limited to 'drivers') diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e793ed994e4..931922bc4a7 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o obj-$(CONFIG_SDHCI) += sdhci.o obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o +obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o obj-$(CONFIG_SH_MMCIF) += sh_mmcif.o obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o diff --git a/drivers/mmc/kona_sdhci.c b/drivers/mmc/kona_sdhci.c new file mode 100644 index 00000000000..77e42c8afe8 --- /dev/null +++ b/drivers/mmc/kona_sdhci.c @@ -0,0 +1,134 @@ +/* + * Copyright 2013 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define SDHCI_CORECTRL_OFFSET 0x00008000 +#define SDHCI_CORECTRL_EN 0x01 +#define SDHCI_CORECTRL_RESET 0x02 + +#define SDHCI_CORESTAT_OFFSET 0x00008004 +#define SDHCI_CORESTAT_CD_SW 0x01 + +#define SDHCI_COREIMR_OFFSET 0x00008008 +#define SDHCI_COREIMR_IP 0x01 + +static int init_kona_mmc_core(struct sdhci_host *host) +{ + unsigned int mask; + unsigned int timeout; + + if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) { + printf("%s: sd host controller reset error\n", __func__); + return 1; + } + + /* For kona a hardware reset before anything else. */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + do { + if (timeout == 0) { + printf("%s: reset timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } while (0 == + (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & + SDHCI_CORECTRL_RESET)); + + /* Clear the reset bit. */ + mask = mask & ~SDHCI_CORECTRL_RESET; + sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET); + + /* Enable AHB clock */ + mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); + sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET); + + /* Enable interrupts */ + sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET); + + /* Make sure Card is detected in controller */ + mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); + sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET); + + /* Wait max 100 ms */ + timeout = 1000; + while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { + if (timeout == 0) { + printf("%s: CARD DETECT timeout error\n", __func__); + return 1; + } + timeout--; + udelay(100); + } + return 0; +} + +int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks) +{ + int ret = 0; + u32 max_clk; + void *reg_base; + struct sdhci_host *host = NULL; + + host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host)); + if (!host) { + printf("%s: sdhci host malloc fail!\n", __func__); + return -ENOMEM; + } + switch (dev_index) { + case 0: + reg_base = (void *)CONFIG_SYS_SDIO_BASE0; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, + &max_clk); + break; + case 1: + reg_base = (void *)CONFIG_SYS_SDIO_BASE1; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, + &max_clk); + break; + case 2: + reg_base = (void *)CONFIG_SYS_SDIO_BASE2; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, + &max_clk); + break; + case 3: + reg_base = (void *)CONFIG_SYS_SDIO_BASE3; + ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, + &max_clk); + break; + default: + printf("%s: sdio dev index %d not supported\n", + __func__, dev_index); + ret = -EINVAL; + } + if (ret) + return ret; + + host->name = "kona-sdhci"; + host->ioaddr = reg_base; + host->quirks = quirks; + host->host_caps = MMC_MODE_HC; + + if (init_kona_mmc_core(host)) + return -EINVAL; + + if (quirks & SDHCI_QUIRK_REG32_RW) + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; + else + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + + add_sdhci(host, max_clk, min_clk); + return ret; +} -- cgit v1.2.3 From eae745379d4c6453d8f8888a8003a1c1ebcfbbd3 Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Mon, 24 Feb 2014 13:33:08 +0100 Subject: power: fix: Do not execute pmic command when not all necessary parameters are passed Lack of this check resulted in a data abort when CPU tried to execute the following command (without further mandatory input): 'pmic MAX77686_PMIC'. Only the 'pmic list' command requires one passed parameter. Other require at least two valid parameters for correct operation. Signed-off-by: Lukasz Majewski --- drivers/power/power_core.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers') diff --git a/drivers/power/power_core.c b/drivers/power/power_core.c index 29ccc831af2..fe1f3160218 100644 --- a/drivers/power/power_core.c +++ b/drivers/power/power_core.c @@ -140,6 +140,9 @@ int do_pmic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return CMD_RET_SUCCESS; } + if (argc < 3) + return CMD_RET_USAGE; + name = argv[1]; cmd = argv[2]; -- cgit v1.2.3 From e0d809647fb1aa01999de9a2e59349d28d48cfee Mon Sep 17 00:00:00 2001 From: Zhao Qiang Date: Mon, 23 Dec 2013 15:51:33 +0800 Subject: ar8031/8033/phy:enable autonegotiation for ar8031/8033 Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before while "if (phydev->supported & SUPPORTED_Autoneg)" now. So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033 to enable autonegotiation. Signed-off-by: Zhao Qiang Reviewed-by: York Sun --- drivers/net/phy/atheros.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers') diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 32c2ab9944e..0f437e8ffd4 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -13,6 +13,7 @@ static int ar8021_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + phydev->supported = phydev->drv->features; return 0; } -- cgit v1.2.3 From 91d7746df89f858548fe535137b4b185a6a76d59 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Mon, 17 Feb 2014 16:58:36 +0530 Subject: fsl/usb: Limit phy_type comparison to first four characters Use first four characters for phy_type comparison. Strcmp() should not be used to check the phy_type string which maybe parsed by hwconfig_subarg(). Hwconfig_subarg() returns part of hwconfig string starting from phy_type value till the end of the string. Since phy_type could be either "utmi" or "ulpi", strncmp() should be used so that a comparison of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed. Signed-off-by: Shaohui Xie Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 45e5d6a5bde..1ca7cf5d9b7 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -86,7 +86,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, #endif } - if (!strcmp(phy_type, "utmi")) { + if (!strncmp(phy_type, "utmi", 4)) { #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); setbits_be32(&ehci->control, UTMI_PHY_EN); -- cgit v1.2.3 From 9c653aad169ffdc9e18482970df9de1a29773034 Mon Sep 17 00:00:00 2001 From: Mugunthan V N Date: Tue, 18 Feb 2014 07:31:52 -0500 Subject: drivers: net: cpsw: add support to have phy address from cpsw platform data Some platforms like AM437x have different EVMs with different phy addresses, so this patch adds support for passing phy address via cpsw plaform data. Also renamed phy_id to phy_addr so better understanding of the code. Reviewed-by: Felipe Balbi Signed-off-by: Mugunthan V N [trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335 pengwyn boards] Signed-off-by: Tom Rini --- board/BuR/common/common.c | 4 ++-- board/compulab/cm_t335/cm_t335.c | 2 +- board/isee/igep0033/board.c | 2 +- board/phytec/pcm051/board.c | 4 ++-- board/siemens/dxr2/board.c | 2 +- board/siemens/pxm2/board.c | 4 ++-- board/siemens/rut/board.c | 4 ++-- board/silica/pengwyn/board.c | 4 ++-- board/ti/am335x/board.c | 4 ++-- board/ti/dra7xx/evm.c | 4 ++-- board/ti/ti814x/evm.c | 4 ++-- drivers/net/cpsw.c | 4 ++-- include/configs/am335x_evm.h | 1 - include/configs/am335x_igep0033.h | 1 - include/configs/bur_am335x_common.h | 1 - include/configs/cm_t335.h | 1 - include/configs/dra7xx_evm.h | 1 - include/configs/dxr2.h | 1 - include/configs/pcm051.h | 1 - include/configs/pengwyn.h | 1 - include/configs/pxm2.h | 1 - include/configs/rut.h | 1 - include/configs/ti814x_evm.h | 1 - include/cpsw.h | 2 +- 24 files changed, 22 insertions(+), 33 deletions(-) (limited to 'drivers') diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 6d187eaab20..04f3f1f4b23 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -141,12 +141,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 01019e8eb2f..9583149bed6 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -47,7 +47,7 @@ static void cpsw_control(int enabled) static struct cpsw_slave_data cpsw_slave = { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }; diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c index 089a835e0c6..9f8fcf2c1cf 100644 --- a/board/isee/igep0033/board.c +++ b/board/isee/igep0033/board.c @@ -116,7 +116,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c index 7e5e07ff232..1071662ea9e 100644 --- a/board/phytec/pcm051/board.c +++ b/board/phytec/pcm051/board.c @@ -176,13 +176,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RGMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RGMII, }, }; diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c index 6c316faa8f1..9b8f538312e 100644 --- a/board/siemens/dxr2/board.c +++ b/board/siemens/dxr2/board.c @@ -198,7 +198,7 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_MII, }, }; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index ef3d6cc158d..98083d52cd9 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -181,13 +181,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 25ab54d9a2a..e0ada3f6a5f 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -143,13 +143,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; diff --git a/board/silica/pengwyn/board.c b/board/silica/pengwyn/board.c index a553129d29d..ee88b6f3990 100644 --- a/board/silica/pengwyn/board.c +++ b/board/silica/pengwyn/board.c @@ -141,13 +141,13 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_MII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_MII, }, }; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 57217688d63..862f966e7cf 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -544,12 +544,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 0, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 1, }, }; diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index bed828584bf..7990e7990d4 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -149,12 +149,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, - .phy_id = 0, + .phy_addr = 2, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, - .phy_id = 1, + .phy_addr = 3, }, }; diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c index 140ad7103ad..54b3dfb82c5 100644 --- a/board/ti/ti814x/evm.c +++ b/board/ti/ti814x/evm.c @@ -132,12 +132,12 @@ static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x50, .sliver_reg_ofs = 0x700, - .phy_id = 1, + .phy_addr = 1, }, { .slave_reg_ofs = 0x90, .sliver_reg_ofs = 0x740, - .phy_id = 0, + .phy_addr = 0, }, }; diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 50167aab63a..dd6c26a7fb3 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -656,7 +656,7 @@ static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) cpsw_ale_add_mcast(priv, NetBcastAddr, 1 << slave_port); - priv->phy_mask |= 1 << slave->data->phy_id; + priv->phy_mask |= 1 << slave->data->phy_addr; } static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) @@ -948,7 +948,7 @@ static int cpsw_phy_init(struct eth_device *dev, struct cpsw_slave *slave) SUPPORTED_1000baseT_Full); phydev = phy_connect(priv->bus, - CONFIG_PHY_ADDR, + slave->data->phy_addr, dev, slave->data->phy_if); diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 59a8f36d169..23c056c82cb 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -398,7 +398,6 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 115d1b37c9e..e72ee05ec8c 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -181,7 +181,6 @@ #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_NET_MULTI #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC /* NAND support */ diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h index 1f57bd2744f..7bbe5964ae8 100644 --- a/include/configs/bur_am335x_common.h +++ b/include/configs/bur_am335x_common.h @@ -51,7 +51,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_SPL_ETH_SUPPORT #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_NATSEMI #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT /* used for a fetching MAC-Address */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h index 56e9a8e0e82..26b615b8c50 100644 --- a/include/configs/cm_t335.h +++ b/include/configs/cm_t335.h @@ -114,7 +114,6 @@ /* Network. */ #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS /* NAND support */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index c67cf60c0c6..291c538a346 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -62,7 +62,6 @@ #define CONFIG_MII /* Required in net/eth.c */ #define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 2 /* SPI */ #undef CONFIG_OMAP3_SPI diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h index 1e42f5c23c9..e95d74c04c7 100644 --- a/include/configs/dxr2.h +++ b/include/configs/dxr2.h @@ -49,7 +49,6 @@ #undef CONFIG_MII #undef CONFIG_PHY_GIGE -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #define CONFIG_FACTORYSET diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h index 6f41ee77183..9af3efd4b1a 100644 --- a/include/configs/pcm051.h +++ b/include/configs/pcm051.h @@ -297,7 +297,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_SMSC #endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h index 5a555567d02..fc25966e0f2 100644 --- a/include/configs/pengwyn.h +++ b/include/configs/pengwyn.h @@ -196,7 +196,6 @@ /* Network */ #define CONFIG_CMD_MII #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_RESET 1 #define CONFIG_PHY_NATSEMI diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h index 7722f7be2e7..6276d43395e 100644 --- a/include/configs/pxm2.h +++ b/include/configs/pxm2.h @@ -44,7 +44,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 0 #define CONFIG_PHY_ATHEROS #define CONFIG_FACTORYSET diff --git a/include/configs/rut.h b/include/configs/rut.h index d4519f946c3..6bddededaeb 100644 --- a/include/configs/rut.h +++ b/include/configs/rut.h @@ -41,7 +41,6 @@ #undef CONFIG_SPL_NET_VCI_STRING #undef CONFIG_SPL_ETH_SUPPORT -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_NATSEMI #define CONFIG_FACTORYSET diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h index ba16b1c14b5..b51400c4640 100644 --- a/include/configs/ti814x_evm.h +++ b/include/configs/ti814x_evm.h @@ -233,7 +233,6 @@ #define CONFIG_NET_MULTI #define CONFIG_PHY_GIGE #define CONFIG_PHYLIB -#define CONFIG_PHY_ADDR 1 #define CONFIG_PHY_ET1011C #define CONFIG_PHY_ET1011C_TX_CLK_FIX diff --git a/include/cpsw.h b/include/cpsw.h index 743cb96e7e9..a73843d2f75 100644 --- a/include/cpsw.h +++ b/include/cpsw.h @@ -19,7 +19,7 @@ struct cpsw_slave_data { u32 slave_reg_ofs; u32 sliver_reg_ofs; - int phy_id; + int phy_addr; int phy_if; }; -- cgit v1.2.3