From 7108dd24439375dafa3fcfab9415e930b0abb4b3 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 28 Nov 2022 01:02:27 -0600 Subject: video: sunxi: dw-hdmi: Use DM for clock gates and resets This abstracts away the CCU register layout, which is necessary for supporting new SoCs like H6 with a reorganized CCU. One of the resets is referenced from the PHY node instead of the controller node, so it will have to wait until the PHY code is factored out to a separate driver. Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/video/sunxi/sunxi_dw_hdmi.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) (limited to 'drivers') diff --git a/drivers/video/sunxi/sunxi_dw_hdmi.c b/drivers/video/sunxi/sunxi_dw_hdmi.c index 4f5d0989286..ef18d1f281f 100644 --- a/drivers/video/sunxi/sunxi_dw_hdmi.c +++ b/drivers/video/sunxi/sunxi_dw_hdmi.c @@ -5,12 +5,14 @@ * (C) Copyright 2017 Jernej Skrabec */ +#include #include #include #include #include #include #include +#include #include #include #include @@ -20,6 +22,8 @@ struct sunxi_dw_hdmi_priv { struct dw_hdmi hdmi; + struct reset_ctl_bulk resets; + struct clk_bulk clocks; }; struct sunxi_hdmi_phy { @@ -336,14 +340,16 @@ static int sunxi_dw_hdmi_probe(struct udevice *dev) clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK, CCM_HDMI_CTRL_PLL3); - /* Set ahb gating to pass */ - setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); + /* This reset is referenced from the PHY devicetree node. */ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); - setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); - setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE); - /* Clock on */ - setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); + ret = reset_deassert_bulk(&priv->resets); + if (ret) + return ret; + + ret = clk_enable_bulk(&priv->clocks); + if (ret) + return ret; sunxi_dw_hdmi_phy_init(&priv->hdmi); @@ -362,6 +368,7 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) { struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev); struct dw_hdmi *hdmi = &priv->hdmi; + int ret; hdmi->ioaddr = (ulong)dev_read_addr(dev); hdmi->i2c_clk_high = 0xd8; @@ -369,6 +376,14 @@ static int sunxi_dw_hdmi_of_to_plat(struct udevice *dev) hdmi->reg_io_width = 1; hdmi->phy_set = sunxi_dw_hdmi_phy_cfg; + ret = reset_get_bulk(dev, &priv->resets); + if (ret) + return ret; + + ret = clk_get_bulk(dev, &priv->clocks); + if (ret) + return ret; + return 0; } -- cgit v1.2.3