From 7b14cc991ba85d2b035479177cc1391ed729abd3 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Thu, 8 Aug 2019 09:59:05 +0000 Subject: imx8mq: Update the ddrc QoS setting for B1 chip Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping Reviewed-by: Ye Li Tested-by: Robby Cai --- drivers/ddr/imx/imx8m/lpddr4_init.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'drivers') diff --git a/drivers/ddr/imx/imx8m/lpddr4_init.c b/drivers/ddr/imx/imx8m/lpddr4_init.c index a4bc1de8eb6..0f46ca02b6c 100644 --- a/drivers/ddr/imx/imx8m/lpddr4_init.c +++ b/drivers/ddr/imx/imx8m/lpddr4_init.c @@ -54,7 +54,10 @@ void ddr_init(struct dram_timing_info *dram_timing) reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */ debug("DDRINFO: cfg clk\n"); - dram_pll_init(MHZ(750)); + if (is_imx8mq()) + dram_pll_init(MHZ(800)); + else + dram_pll_init(MHZ(750)); /* * release [0]ddr1_preset_n, [1]ddr1_core_reset_n, -- cgit v1.2.3