From a6c86decbb27e3d1e64af222d3179a88d0ea0a0d Mon Sep 17 00:00:00 2001
From: Vivek Gautam
Date: Sat, 14 Sep 2013 14:02:50 +0530
Subject: config: arm: exynos5250: Define CONFIG_SYS_CACHELINE_SIZE

XHCI stack driver needs this to align buffers to
CacheLine boundary. So define the same to be '64'

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Cc: Julius Werner <jwerner@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dan Murphy <dmurphy@ti.com>
Cc: Marek Vasut <marex@denx.de>
---
 include/configs/exynos5250-dt.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include')

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 8c21909d634..c9c19a75f33 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -37,6 +37,8 @@
 /* Keep L2 Cache Disabled */
 #define CONFIG_SYS_DCACHE_OFF
 
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /* Enable ACE acceleration for SHA1 and SHA256 */
 #define CONFIG_EXYNOS_ACE_SHA
 #define CONFIG_SHA_HW_ACCEL
-- 
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