From 3db93b8bedd32e914b38976141b3fdf4ea3ff738 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 31 Oct 2007 20:51:10 +0100 Subject: ppc4xx: Enable CPU POST test for 4xx with dcache enabled Now with caches enabled (i- and d-cache) on 44x, we need a chance to disable the cache for the CPU POST tests, since these tests consist of self modifying code. This is done via the new change_tlb() function. Signed-off-by: Stefan Roese --- post/lib_ppc/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'post') diff --git a/post/lib_ppc/cpu.c b/post/lib_ppc/cpu.c index 1f2ded2bf26..4ab6d2dc002 100644 --- a/post/lib_ppc/cpu.c +++ b/post/lib_ppc/cpu.c @@ -36,6 +36,7 @@ #include #include +#include #if CONFIG_POST & CFG_POST_CPU @@ -59,6 +60,8 @@ extern int cpu_post_test_multi (void); extern int cpu_post_test_string (void); extern int cpu_post_test_complex (void); +DECLARE_GLOBAL_DATA_PTR; + ulong cpu_post_makecr (long v) { ulong cr = 0; @@ -81,6 +84,10 @@ int cpu_post_test (int flags) WATCHDOG_RESET(); if (ic) icache_disable (); +#ifdef CONFIG_4xx_DCACHE + /* disable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE); +#endif if (ret == 0) ret = cpu_post_test_cmp (); @@ -129,6 +136,10 @@ int cpu_post_test (int flags) if (ic) icache_enable (); +#ifdef CONFIG_4xx_DCACHE + /* enable cache */ + change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0); +#endif WATCHDOG_RESET(); -- cgit v1.2.3