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/*
* (C) Copyright 2014
* Paul Kocialkowski <contact@paulk.fr>
*
* Based on the OMAP3 Pandora code:
* (C) Copyright 2008
* Grazvydas Ignotas <notasas@gmail.com>
*
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <twl4030.h>
#include <lp8720.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include "sniper.h"
DECLARE_GLOBAL_DATA_PTR;
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"Sniper",
"MMC",
};
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
#if defined(CONFIG_SPL_BUILD)
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
timings->mr = MICRON_V_MR_165;
/*
timings->mcfg = (0x02584019|(2<<6));
timings->ctrla = 0x92E1C4C6;
timings->ctrlb = 0x0002121C;
timings->rfr_ctrl = 0x0005e601;
timings->mr = 0x00000032;
*/
}
#endif
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_SNIPER();
}
#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
int ret;
ret = omap_mmc_init(0, 0, 0, -1, -1);
if (ret)
return ret;
ret = omap_mmc_init(1, 0, 0, SNIPER_GPIO_MICROSD_DET_N, -1);
if (ret)
return ret;
return 0;
}
#endif
#if defined(CONFIG_GENERIC_MMC)
void board_mmc_power_init(void)
{
/*
* In order to boot from MMC1 (microsd card), the LP8720 LDO1 (3.0V_MMC)
* regulator has to be enabled. The LP8720 is accessed through I2C3.
*
* Enabling TWL4030 VAUX2 (3.0V_MOTION) and TWL4030 VDAC
* (1.8V_MOTION_VIO) is required to power the sensors that are slaves
* on I2C3. When not powered, these sensors cause I2C3 SCK to stay low.
*/
i2c_set_bus_num(0);
/* TWL4030 VAUX2 (3.0V_MOTION) to 2.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED,
TWL4030_PM_RECEIVER_VAUX2_VSEL_28,
TWL4030_PM_RECEIVER_VAUX2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
/* TWL4030 VDAC (1.8V_MOTION_VIO) to 1.8V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
TWL4030_PM_RECEIVER_VDAC_VSEL_18,
TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
mdelay(100); /* ramp-up delay from Linux code */
i2c_set_bus_num(2);
lp8720_init(SNIPER_GPIO_CAM_SUBPM_EN, LP8720_CHIP_IDSEL_GND);
/* LP8720 LDO1 (3.0V_MMC) to 3.0V */
lp8720_ldo_voltage(LP8720_LDO1_SETTINGS, LP8720_LDO1235_V_30,
LP8720_DELAY_0);
lp8720_ldo_enable(LP8720_LDO1_EN);
i2c_set_bus_num(0);
/* TWL4030 VMMC2 to 3.2V */
twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED,
TWL4030_PM_RECEIVER_VMMC2_VSEL_32,
TWL4030_PM_RECEIVER_VMMC2_DEV_GRP,
TWL4030_PM_RECEIVER_DEV_GRP_P1);
mdelay(100); /* ramp-up delay from Linux code */
}
#endif
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