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authorDave Liu2009-03-14 12:48:19 +0800
committerKumar Gala2009-03-30 13:33:50 -0500
commit6a8197836702991468cead5ead073f589e2623ad (patch)
treeda8979bf71471ade2083ad1a352a32f74a7234c4
parent540dcf1cb86961e11aa92c47671f27762c581d8c (diff)
fsl-ddr: Fix two bugs in the ddr infrastructure
1. wr_lat UM said the total write latency for DDR2 is equal to WR_LAT + ADD_LAT, the write latency is CL + ADD_LAT - 1. so, the WR_LAT = CL - 1; 2. rd_to_pre we missed to add the ADD_LAT for DDR2 case. Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com>
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 292980d0b07..4c1498c8c6e 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -302,12 +302,15 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
*/
wr_lat = 0;
#elif defined(CONFIG_FSL_DDR2)
- wr_lat = cas_latency + additive_latency - 1;
+ wr_lat = cas_latency - 1;
#else
#error "Fix WR_LAT for DDR3"
#endif
rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
+#if defined(CONFIG_FSL_DDR2)
+ rd_to_pre += additive_latency;
+#endif
wr_data_delay = popts->write_data_delay;
cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);