diff options
| author | Neil Armstrong | 2017-11-27 10:16:17 +0100 |
|---|---|---|
| committer | Tom Rini | 2017-12-04 09:59:03 -0500 |
| commit | 9a41746f84b51890eace24e90067b4a1f2bd51d5 (patch) | |
| tree | a618c2985b15175d2cf0345c5291a0cf17f1ae52 | |
| parent | 6915b1033105b23ebc725be772bec00838830667 (diff) | |
board: odroid-c2: use common ethernet init function
Switch Odroid-C2 Ethernet init to the common Ethernet init function.
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| -rw-r--r-- | board/amlogic/odroid-c2/odroid-c2.c | 11 |
1 files changed, 2 insertions, 9 deletions
diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/odroid-c2/odroid-c2.c index a5ea8dc5af2..d68d0f13444 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/odroid-c2/odroid-c2.c @@ -9,7 +9,7 @@ #include <asm/io.h> #include <asm/arch/gxbb.h> #include <asm/arch/sm.h> -#include <phy.h> +#include <asm/arch/eth.h> #define EFUSE_SN_OFFSET 20 #define EFUSE_SN_SIZE 16 @@ -27,17 +27,10 @@ int misc_init_r(void) char serial[EFUSE_SN_SIZE]; ssize_t len; - /* Set RGMII mode */ - setbits_le32(GXBB_ETH_REG_0, GXBB_ETH_REG_0_PHY_INTF | - GXBB_ETH_REG_0_TX_PHASE(1) | - GXBB_ETH_REG_0_TX_RATIO(4) | - GXBB_ETH_REG_0_PHY_CLK_EN | - GXBB_ETH_REG_0_CLK_EN); + meson_gx_eth_init(PHY_INTERFACE_MODE_RGMII, 0); /* Enable power and clock gate */ setbits_le32(GXBB_GCLK_MPEG_0, GXBB_GCLK_MPEG_0_I2C); - setbits_le32(GXBB_GCLK_MPEG_1, GXBB_GCLK_MPEG_1_ETH); - clrbits_le32(GXBB_MEM_PD_REG_0, GXBB_MEM_PD_REG_0_ETH_MASK); /* Reset PHY on GPIOZ_14 */ clrbits_le32(GXBB_GPIO_EN(3), BIT(14)); |