diff options
| author | Stefan Roese | 2009-09-09 16:25:29 +0200 |
|---|---|---|
| committer | Stefan Roese | 2009-09-11 10:35:58 +0200 |
| commit | d1c3b27525b664e8c4db6bb173eed51bfc8220de (patch) | |
| tree | c00f3d0bcfbd5fcc1954cc9cefdbc4c9c41f41ea | |
| parent | e7963772eb78a6aa1fa65063d64eab3a8626daac (diff) | |
ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:
- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines
Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.
Signed-off-by: Stefan Roese <sr@denx.de>
128 files changed, 2088 insertions, 2399 deletions
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 8d79be2cedc..0db619952eb 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -57,7 +57,7 @@ int board_early_init_f(void) #if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR_PINSTP, reg); + mfsdr(SDR0_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif @@ -65,18 +65,18 @@ int board_early_init_f(void) acadia_gpio_init(); /* Configure 405EZ for NAND usage */ - mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); - mfsdr(sdrultra0, reg); + mtsdr(SDR0_NAND0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); + mfsdr(SDR0_ULTRA0, reg); reg &= ~SDR_ULTRA0_CSN_MASK; reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) | SDR_ULTRA0_NDGPIOBP | SDR_ULTRA0_EBCRDYEN | SDR_ULTRA0_NFSRSTEN; - mtsdr(sdrultra0, reg); + mtsdr(SDR0_ULTRA0, reg); /* USB Host core needs this bit set */ - mfsdr(sdrultra1, reg); - mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE); + mfsdr(SDR0_ULTRA1, reg); + mtsdr(SDR0_ULTRA1, reg | SDR_ULTRA1_LEDNENABLE); mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 3e5c80ea429..8c2addcb945 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -65,7 +65,7 @@ phys_size_t initdram(int board_type) u32 reg; /* don't reinit PLL when booting via I2C bootstrap option */ - mfsdr(SDR_PINSTP, reg); + mfsdr(SDR0_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); #endif @@ -81,25 +81,25 @@ phys_size_t initdram(int board_type) gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG); /* 2. EBC in Async mode */ - mtebc(pb1ap, 0x078F1EC0); - mtebc(pb2ap, 0x078F1EC0); - mtebc(pb1cr, 0x000BC000); - mtebc(pb2cr, 0x020BC000); + mtebc(PB1AP, 0x078F1EC0); + mtebc(PB2AP, 0x078F1EC0); + mtebc(PB1CR, 0x000BC000); + mtebc(PB2CR, 0x020BC000); /* 3. Set CRAM in Sync mode */ cram_bcr_write(0x7012); /* CRAM burst setting */ /* 4. EBC in Sync mode */ - mtebc(pb1ap, 0x9C0201C0); - mtebc(pb2ap, 0x9C0201C0); + mtebc(PB1AP, 0x9C0201C0); + mtebc(PB2AP, 0x9C0201C0); /* Set GPIO pins back to alternate function */ gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG); /* Config EBC to use RDY */ - mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + mfsdr(SDR0_ULTRA0, val); + mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN); /* Wait a short while, since for NAND booting this is too fast */ for (i=0; i<200000; i++) diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index 9dcce35c89b..b63813c7be4 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -51,11 +51,11 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033c); - mtcpr(cprplld, 0x0c010200); - mtcpr(cprprimad, 0x04060c0c); - mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x0000033c); + mtcpr(CPR0_PLLD, 0x0c010200); + mtcpr(CPC0_PRIMAD, 0x04060c0c); + mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_266_160_80) @@ -83,13 +83,13 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x20000238); - mtcpr(cprplld, 0x03010400); - mtcpr(cprprimad, 0x03050a0a); - mtcpr(cprperc0, 0x00000000); - mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0x07323200); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x20000238); + mtcpr(CPR0_PLLD, 0x03010400); + mtcpr(CPC0_PRIMAD, 0x03050a0a); + mtcpr(CPC0_PERC0, 0x00000000); + mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0x07323200); + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_333_166_83) @@ -117,12 +117,12 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x0000033C); - mtcpr(cprplld, 0x0a010000); - mtcpr(cprprimad, 0x02040808); - mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xA6A60300); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x0000033C); + mtcpr(CPR0_PLLD, 0x0a010000); + mtcpr(CPC0_PRIMAD, 0x02040808); + mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0xA6A60300); + mtcpr(CPR0_CLKUP, 0x40000000); } #elif defined(PLLMR0_100_100_12) @@ -143,12 +143,12 @@ void board_pll_init_f(void) */ /* Initialize PLL */ - mtcpr(cprpllc, 0x000003BC); - mtcpr(cprplld, 0x06060600); - mtcpr(cprprimad, 0x02020004); - mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(cprperd1, 0xC8C81600); - mtcpr(cprclkupd, 0x40000000); + mtcpr(CPR0_PLLC, 0x000003BC); + mtcpr(CPR0_PLLD, 0x06060600); + mtcpr(CPC0_PRIMAD, 0x02020004); + mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPC0_PERD1, 0xC8C81600); + mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU_<speed>_405EZ */ @@ -167,12 +167,12 @@ unsigned long get_tbclk(void) /* * Read PLL Mode registers */ - mfcpr(cprplld, cpr_plld); + mfcpr(CPR0_PLLD, cpr_plld); /* * Read CPR_PRIMAD register */ - mfcpr(cprprimad, cpr_primad); + mfcpr(CPC0_PRIMAD, cpr_primad); /* * Determine CPU clock frequency diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index febc61a0869..2ffd720d5c4 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -487,35 +487,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } @@ -695,8 +695,8 @@ void ext_bus_cntlr_init(void) | +-------------------------------------------------------------------------*/ /* NVRAM - FPGA */ - mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA); - mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5); + mtebc(PB5AP, EBC0_BNAP_NVRAM_FPGA); + mtebc(PB5CR, EBC0_BNCR_NVRAM_FPGA_CS5); /*-------------------------------------------------------------------------+ | @@ -749,7 +749,7 @@ void ext_bus_cntlr_init(void) case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN: /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -822,7 +822,7 @@ void ext_bus_cntlr_init(void) /* Default Strap Settings 5-7 */ /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */ /* Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, sdr0_sdstp1); + mfsdr(SDR0_SDSTP1, sdr0_sdstp1); boot_selection = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK; @@ -1013,8 +1013,8 @@ void ext_bus_cntlr_init(void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN | + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, EBC0_CFG_EBTC_DRIVEN | EBC0_CFG_PTD_ENABLED | EBC0_CFG_RTC_2048PERCLK | EBC0_CFG_EMPL_LOW | @@ -1029,20 +1029,20 @@ void ext_bus_cntlr_init(void) | Initialize EBC Bank 0-4 +-------------------------------------------------------------------------*/ /* EBC Bank0 */ - mtebc(pb0ap, ebc0_cs0_bnap_value); - mtebc(pb0cr, ebc0_cs0_bncr_value); + mtebc(PB0AP, ebc0_cs0_bnap_value); + mtebc(PB0CR, ebc0_cs0_bncr_value); /* EBC Bank1 */ - mtebc(pb1ap, ebc0_cs1_bnap_value); - mtebc(pb1cr, ebc0_cs1_bncr_value); + mtebc(PB1AP, ebc0_cs1_bnap_value); + mtebc(PB1CR, ebc0_cs1_bncr_value); /* EBC Bank2 */ - mtebc(pb2ap, ebc0_cs2_bnap_value); - mtebc(pb2cr, ebc0_cs2_bncr_value); + mtebc(PB2AP, ebc0_cs2_bnap_value); + mtebc(PB2CR, ebc0_cs2_bncr_value); /* EBC Bank3 */ - mtebc(pb3ap, ebc0_cs3_bnap_value); - mtebc(pb3cr, ebc0_cs3_bncr_value); + mtebc(PB3AP, ebc0_cs3_bnap_value); + mtebc(PB3CR, ebc0_cs3_bncr_value); /* EBC Bank4 */ - mtebc(pb4ap, ebc0_cs4_bnap_value); - mtebc(pb4cr, ebc0_cs4_bncr_value); + mtebc(PB4AP, ebc0_cs4_bnap_value); + mtebc(PB4CR, ebc0_cs4_bncr_value); return; } @@ -1939,10 +1939,10 @@ void configure_ppc440ep_pins(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL; sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE; - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); usb2_device_selection_in_fpga(); } @@ -1950,19 +1950,19 @@ void configure_ppc440ep_pins(void) /* USB1.1 Device Selection */ if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* USB1.1 Host Selection */ if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED) { - mfsdr(sdr_usb0, sdr0_usb0); + mfsdr(SDR0_USB0, sdr0_usb0); sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK; sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE; - mtsdr(sdr_usb0, sdr0_usb0); + mtsdr(SDR0_USB0, sdr0_usb0); } /* NAND Flash Selection */ @@ -1971,14 +1971,14 @@ void configure_ppc440ep_pins(void) update_ndfc_ios(gpio_tab); #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)) - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | SDR0_CUST0_CHIPSELGAT_EN1 | SDR0_CUST0_CHIPSELGAT_EN2); #else - mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL | + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_NDFC_SEL | SDR0_CUST0_NDFC_ENABLE | SDR0_CUST0_NDFC_BW_8_BIT | SDR0_CUST0_NDFC_ARE_MASK | @@ -1991,16 +1991,16 @@ void configure_ppc440ep_pins(void) else { /* Set Mux on EMAC */ - mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL); + mtsdr(SDR0_CUST0, SDR0_CUST0_MUX_EMAC_SEL); } /* MII Selection */ if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII); } @@ -2009,9 +2009,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII); } @@ -2020,9 +2020,9 @@ void configure_ppc440ep_pins(void) if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED) { update_zii_ios(gpio_tab); - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII); } @@ -2071,13 +2071,13 @@ void configure_ppc440ep_pins(void) /* Packet Reject Function Enable */ if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED) { - mfsdr(sdr_mfr, sdr0_mfr); + mfsdr(SDR0_MFR, sdr0_mfr); sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;; - mtsdr(sdr_mfr, sdr0_mfr); + mtsdr(SDR0_MFR, sdr0_mfr); } /* Perform effective access to hardware */ - mtsdr(sdr_pfc1, sdr0_pfc1); + mtsdr(SDR0_PFC1, sdr0_pfc1); set_chip_gpio_configuration(GPIO0, gpio_tab); set_chip_gpio_configuration(GPIO1, gpio_tab); diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index 001348ac5c9..7bf877de895 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -94,7 +94,7 @@ unsigned long flash_init(void) * Boot Settings in IIC EEprom address 0xA8 or 0xA4 * Read Serial Device Strap Register1 in PPC440EP */ - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; diff --git a/board/amcc/bubinga/bubinga.c b/board/amcc/bubinga/bubinga.c index 74a2a1c2144..d0aebec2cd4 100644 --- a/board/amcc/bubinga/bubinga.c +++ b/board/amcc/bubinga/bubinga.c @@ -41,9 +41,9 @@ int board_early_init_f(void) * and enable the internal PCI arbiter if selected */ if (in_8((void *)FPGA_REG1) & FPGA_REG1_PCI_INT_ARB) - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); else - mtdcr(cpc0_pci, CPC0_PCI_HOST_CFG_EN); + mtdcr(CPC0_PCI, CPC0_PCI_HOST_CFG_EN); return 0; } diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c index a10babbf739..baf89d5483f 100644 --- a/board/amcc/bubinga/flash.c +++ b/board/amcc/bubinga/flash.c @@ -106,25 +106,25 @@ unsigned long flash_init(void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 710a0af8252..3a03f307310 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -475,9 +475,9 @@ int board_early_init_r (void) /* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */ #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + mtebc(PB3CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #else - mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000); #endif /* Remove TLB entry of boot EBC mapping */ diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index ad09e62077c..2439b03a9f7 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -41,30 +41,30 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ - mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */ - mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ - mtebc(pb7ap, 0x01015280); /* FPGA registers */ - mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ + mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ + mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ + mtebc(PB7AP, 0x01015280); /* FPGA registers */ + mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ /* read FPGA_REG0 and set the bus controller */ status = *fpga_base; if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { - mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ - mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ + mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ + mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ + mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ } else { - mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */ - mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ + mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ + mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ /* set CS2 if FLASH_ONBD_N == 0 */ if (!(status & FLASH_ONBD_N)) { - mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */ - mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ + mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ + mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ } } @@ -186,7 +186,7 @@ int pci_pre_init(struct pci_controller *hose) * The ebony board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if ((strap & 0x00100000) == 0) { printf("PCI: CPC0_STRP1[PAE] not set.\n"); return 0; diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index e078ba4f9cf..1a45056daa0 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -220,9 +220,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); @@ -280,7 +280,7 @@ int pci_pre_init(struct pci_controller * hose ) * The katmai board is always configured as the host & requires the * PCI arbiter to be enabled. *-------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 7d02d904e09..71ad89fa6c3 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -42,12 +42,12 @@ int board_early_init_f(void) { u32 mfr; - mtebc( pb0ap, 0x03800000 ); /* set chip selects */ - mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ - mtebc( pb1ap, 0x03800000 ); - mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ - mtebc( pb2ap, 0x03800000 ); - mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ + mtebc( PB0AP, 0x03800000 ); /* set chip selects */ + mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ + mtebc( PB1AP, 0x03800000 ); + mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ + mtebc( PB2AP, 0x03800000 ); + mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */ mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */ @@ -67,9 +67,9 @@ int board_early_init_f(void) mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0xffffffff ); - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); return 0; } @@ -147,7 +147,7 @@ int pci_pre_init( struct pci_controller *hose ) * The luan board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index fe4540849da..5e32e8a7844 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -54,7 +54,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -63,14 +63,14 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /* read FPGA base register FPGA_REG0 */ @@ -95,53 +95,53 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)| + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)| cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)| + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | 4 MB FLASH. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| + mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)| + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)| cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| + mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)| EBC_BXAP_BCE_DISABLE| EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED| EBC_BXAP_BEM_WRITEONLY| EBC_BXAP_PEN_DISABLED); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)| + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)| EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------- @@ -189,9 +189,9 @@ int board_early_init_f (void) mtdcr (uic0pr, 0xfc000000); /* */ mtdcr (uic0tr, 0x00000000); /* */ mtdcr (uic0vr, 0x00000001); /* */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ECS_MASK; -/* mtsdr(sdr_mfr, mfr); */ +/* mtsdr(SDR0_MFR, mfr); */ fpga_init(); return 0; @@ -297,7 +297,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; @@ -379,8 +379,8 @@ void fpga_init(void) unsigned long sdr0_cust0; unsigned long pvr; - mfsdr (sdr_pfc0, sdr0_pfc0); - mfsdr (sdr_pfc1, sdr0_pfc1); + mfsdr (SDR0_PFC0, sdr0_pfc0); + mfsdr (SDR0_PFC1, sdr0_pfc1); group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1); pvr = get_pvr (); @@ -390,8 +390,8 @@ void fpga_init(void) sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); } else { sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE; switch (group) @@ -403,8 +403,8 @@ void fpga_init(void) out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_ENABLE); sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); break; case 3: case 4: @@ -412,8 +412,8 @@ void fpga_init(void) case 6: /* CPU trace B - Over EBMI */ sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE; - mtsdr (sdr_pfc0, sdr0_pfc0); - mtsdr (sdr_pfc1, sdr0_pfc1); + mtsdr (SDR0_PFC0, sdr0_pfc0); + mtsdr (SDR0_PFC1, sdr0_pfc1); out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) | FPGA_REG2_EXT_INTFACE_DISABLE); break; @@ -421,8 +421,8 @@ void fpga_init(void) } /* Initialize the ethernet specific functions in the fpga */ - mfsdr(sdr_pfc1, sdr0_pfc1); - mfsdr(sdr_cust0, sdr0_cust0); + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_CUST0, sdr0_cust0); if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) && ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) || (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI))) diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index 37a0c310fed..49078ebee2f 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -220,7 +220,7 @@ static void early_init_EBC(void) * default value : * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 */ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | @@ -237,8 +237,8 @@ static void early_init_EBC(void) * since some board registers values may be needed to determine the * boot type */ - mtebc(pb1ap, EBC_BXAP_FPGA); - mtebc(pb1cr, EBC_BXCR_FPGA_CS3); + mtebc(PB1AP, EBC_BXAP_FPGA); + mtebc(PB1CR, EBC_BXCR_FPGA_CS3); } @@ -399,12 +399,12 @@ static void early_reinit_EBC(int computed_boot_device) break; } - mtebc(pb0ap, ebc0_cs0_bxap_value); - mtebc(pb0cr, ebc0_cs0_bxcr_value); - mtebc(pb1ap, ebc0_cs1_bxap_value); - mtebc(pb1cr, ebc0_cs1_bxcr_value); - mtebc(pb2ap, ebc0_cs2_bxap_value); - mtebc(pb2cr, ebc0_cs2_bxcr_value); + mtebc(PB0AP, ebc0_cs0_bxap_value); + mtebc(PB0CR, ebc0_cs0_bxcr_value); + mtebc(PB1AP, ebc0_cs1_bxap_value); + mtebc(PB1CR, ebc0_cs1_bxcr_value); + mtebc(PB2AP, ebc0_cs2_bxap_value); + mtebc(PB2CR, ebc0_cs2_bxcr_value); } static void early_init_UIC(void) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 246ad948439..5913455ba15 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -46,8 +46,8 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. @@ -107,8 +107,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); @@ -144,19 +144,19 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(EBC0_CFGADDR, PB3CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - pbcr = mfdcr(ebccfgd); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb3cr); + mtdcr(EBC0_CFGADDR, PB3CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -309,8 +309,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); return 0; } @@ -370,35 +370,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #ifdef CONFIG_PCI_PNP hose->fixup_irq = sequoia_pci_fixup_irq; diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index d8806ac32dd..4e5796ee828 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -48,14 +48,14 @@ int board_early_init_f(void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */ + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); /* * Configure CPC0_PCI to enable PerWE as output * and enable the internal PCI arbiter */ - mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN); return 0; } diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index 2a78a22e65e..e4e441b319d 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -33,60 +33,60 @@ void show_reset_reg(void) /* read clock regsiter */ printf("===== Display reset and initialize register Start =========\n"); - mfcpr(clk_pllc,reg); + mfcpr(CPR0_PLLC,reg); printf("cpr_pllc = %#010lx\n",reg); - mfcpr(clk_plld,reg); + mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); - mfcpr(clk_primad,reg); + mfcpr(CPR0_PRIMAD,reg); printf("cpr_primad = %#010lx\n",reg); - mfcpr(clk_primbd,reg); + mfcpr(CPR0_PRIMBD,reg); printf("cpr_primbd = %#010lx\n",reg); - mfcpr(clk_opbd,reg); + mfcpr(CPR0_OPBD,reg); printf("cpr_opbd = %#010lx\n",reg); - mfcpr(clk_perd,reg); + mfcpr(CPR0_PERD,reg); printf("cpr_perd = %#010lx\n",reg); - mfcpr(clk_mald,reg); + mfcpr(CPR0_MALD,reg); printf("cpr_mald = %#010lx\n",reg); /* read sdr register */ - mfsdr(sdr_ebc,reg); - printf("sdr_ebc = %#010lx\n",reg); + mfsdr(SDR0_EBC,reg); + printf("SDR0_EBC = %#010lx\n",reg); - mfsdr(sdr_cp440,reg); - printf("sdr_cp440 = %#010lx\n",reg); + mfsdr(SDR0_CP440,reg); + printf("SDR0_CP440 = %#010lx\n",reg); - mfsdr(sdr_xcr,reg); - printf("sdr_xcr = %#010lx\n",reg); + mfsdr(SDR0_XCR,reg); + printf("SDR0_XCR = %#010lx\n",reg); - mfsdr(sdr_xpllc,reg); - printf("sdr_xpllc = %#010lx\n",reg); + mfsdr(SDR0_XPLLC,reg); + printf("SDR0_XPLLC = %#010lx\n",reg); - mfsdr(sdr_xplld,reg); - printf("sdr_xplld = %#010lx\n",reg); + mfsdr(SDR0_XPLLD,reg); + printf("SDR0_XPLLD = %#010lx\n",reg); - mfsdr(sdr_pfc0,reg); - printf("sdr_pfc0 = %#010lx\n",reg); + mfsdr(SDR0_PFC0,reg); + printf("SDR0_PFC0 = %#010lx\n",reg); - mfsdr(sdr_pfc1,reg); - printf("sdr_pfc1 = %#010lx\n",reg); + mfsdr(SDR0_PFC1,reg); + printf("SDR0_PFC1 = %#010lx\n",reg); - mfsdr(sdr_cust0,reg); - printf("sdr_cust0 = %#010lx\n",reg); + mfsdr(SDR0_CUST0,reg); + printf("SDR0_CUST0 = %#010lx\n",reg); - mfsdr(sdr_cust1,reg); - printf("sdr_cust1 = %#010lx\n",reg); + mfsdr(SDR0_CUST1,reg); + printf("SDR0_CUST1 = %#010lx\n",reg); - mfsdr(sdr_uart0,reg); - printf("sdr_uart0 = %#010lx\n",reg); + mfsdr(SDR0_UART0,reg); + printf("SDR0_UART0 = %#010lx\n",reg); - mfsdr(sdr_uart1,reg); - printf("sdr_uart1 = %#010lx\n",reg); + mfsdr(SDR0_UART1,reg); + printf("SDR0_UART1 = %#010lx\n",reg); printf("===== Display reset and initialize register End =========\n"); } @@ -96,14 +96,14 @@ void show_xbridge_info(void) unsigned long reg; printf("PCI-X chip control registers\n"); - mfsdr(sdr_xcr, reg); - printf("sdr_xcr = %#010lx\n", reg); + mfsdr(SDR0_XCR, reg); + printf("SDR0_XCR = %#010lx\n", reg); - mfsdr(sdr_xpllc, reg); - printf("sdr_xpllc = %#010lx\n", reg); + mfsdr(SDR0_XPLLC, reg); + printf("SDR0_XPLLC = %#010lx\n", reg); - mfsdr(sdr_xplld, reg); - printf("sdr_xplld = %#010lx\n", reg); + mfsdr(SDR0_XPLLD, reg); + printf("SDR0_XPLLD = %#010lx\n", reg); printf("PCI-X Bridge Configure registers\n"); printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 53ce88c6cdf..086778a6523 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -47,7 +47,7 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT | @@ -56,66 +56,66 @@ int board_early_init_f (void) /*-------------------------------------------------------------------------+ | 64MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | + mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | FPGA. Initialize bank 1 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | + mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | LCM. Initialize bank 2 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT); /*-------------------------------------------------------------------------+ | TMP. Initialize bank 3 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | + mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) | EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) | EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*-------------------------------------------------------------------------+ | Connector 4~7. Initialize bank 3~ 7 with default values. +-------------------------------------------------------------------------*/ - mtebc(pb4ap,0); - mtebc(pb4cr,0); - mtebc(pb5ap,0); - mtebc(pb5cr,0); - mtebc(pb6ap,0); - mtebc(pb6cr,0); - mtebc(pb7ap,0); - mtebc(pb7cr,0); + mtebc(PB4AP,0); + mtebc(PB4CR,0); + mtebc(PB5AP,0); + mtebc(PB5CR,0); + mtebc(PB6AP,0); + mtebc(PB6CR,0); + mtebc(PB7AP,0); + mtebc(PB7CR,0); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -164,13 +164,13 @@ int board_early_init_f (void) mtdcr (uic0vr, 0x00000001); /* */ /* Enable two GPIO 10~11 and TraceA signal */ - mfsdr(sdr_pfc0,reg); + mfsdr(SDR0_PFC0,reg); reg |= 0x00300000; - mtsdr(sdr_pfc0,reg); + mtsdr(SDR0_PFC0,reg); - mfsdr(sdr_pfc1,reg); + mfsdr(SDR0_PFC1,reg); reg |= 0x00100000; - mtsdr(sdr_pfc1,reg); + mtsdr(SDR0_PFC1,reg); /* Set GPIO 10 and 11 as output */ GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718); @@ -230,7 +230,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c index d363564d550..3dc6aabe17b 100644 --- a/board/amcc/walnut/flash.c +++ b/board/amcc/walnut/flash.c @@ -102,27 +102,27 @@ unsigned long flash_init(void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]); diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 3982896cb32..2a654fa895b 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -40,9 +40,9 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * Setup the GPIO pins @@ -101,10 +101,10 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ /*clear tmrclk divisor */ *(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00; @@ -129,8 +129,8 @@ int misc_init_r (void) int size_val = 0; /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -158,8 +158,8 @@ int misc_init_r (void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -353,35 +353,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index eda49eb1746..33b97a50407 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -981,7 +981,7 @@ unsigned long flash_init(void) * Boot Settings in IIC EEprom address 0xA8 or 0xA0 * Read Serial Device Strap Register1 in PPC440SPe */ - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK; ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK; diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 06c7d625a49..245004cee87 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -167,7 +167,7 @@ int board_early_init_f (void) | 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | +-------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_16PERCLK | EBC_CFG_ATC_PREVIOUS | @@ -188,8 +188,8 @@ int board_early_init_f (void) | boot type | +-------------------------------------------------------------------*/ - mtebc(pb1ap, EBC_BXAP_FPGA); - mtebc(pb1cr, EBC_BXCR_FPGA_CS1); + mtebc(PB1AP, EBC_BXAP_FPGA); + mtebc(PB1CR, EBC_BXCR_FPGA_CS1); /*-------------------------------------------------------------------+ | @@ -334,10 +334,10 @@ int board_early_init_f (void) break; } - mtebc(pb0ap, ebc0_cs0_bxap_value); - mtebc(pb0cr, ebc0_cs0_bxcr_value); - mtebc(pb2ap, ebc0_cs2_bxap_value); - mtebc(pb2cr, ebc0_cs2_bxcr_value); + mtebc(PB0AP, ebc0_cs0_bxap_value); + mtebc(PB0CR, ebc0_cs0_bxcr_value); + mtebc(PB2AP, ebc0_cs2_bxap_value); + mtebc(PB2CR, ebc0_cs2_bxcr_value); /*--------------------------------------------------------------------+ | Interrupt controller setup for the AMCC 440SPe Evaluation board. @@ -530,9 +530,9 @@ int board_early_init_f (void) mtdcr (uic0sr, 0x00000000); /* clear all interrupts */ mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */ - mfsdr(sdr_mfr, mfr); + mfsdr(SDR0_MFR, mfr); mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ - mtsdr(sdr_mfr, mfr); + mtsdr(SDR0_MFR, mfr); fpga_init(); @@ -608,7 +608,7 @@ int pci_pre_init(struct pci_controller * hose ) * The yucca board is always configured as the host & requires the * PCI arbiter to be enabled. *-------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 8a06ecc6650..5d1c4170dd1 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -198,8 +198,8 @@ static void init_sdram (void) unsigned long tmp; /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00062001); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, 0x00062001); /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ /* To set the appropriate timings, we need to know the SDRAM speed. */ @@ -212,26 +212,26 @@ static void init_sdram (void) /* divisor = ((mfdcr(strap)>> 28) & 0x3); */ /* write SDRAM timing for 100MHz. */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x0086400D); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, 0x0086400D); /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x05F00000); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, 0x05F00000); udelay (200); /* sdram controller.*/ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x90800000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x90800000); udelay (200); /* initially, disable ECC on all banks */ udelay (200); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGDATA, tmp); return; } @@ -282,18 +282,18 @@ int testdram (void) } printf ("Enable ECC.."); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); for (p = (unsigned long) 0; ((unsigned long) p < L1_MEMSIZE); *p++ = 0L) ; udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); printf ("enabled.\n"); return (0); diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index d700ea76cf3..e8dbb93e112 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -87,17 +87,17 @@ ext_bus_cntlr_init: /* Peripheral Bank 0 (Flash) initialization */ /*---------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x9B01 ori r4,r4,0x5480 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr @@ -125,16 +125,16 @@ ext_bus_cntlr_init: /* all reserved bits=0 */ /*---------------------------------------------------------------------- */ /*---------------------------------------------------------------------- */ - addi r4,0,pb1ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0185 /* hiword */ ori r4,r4,0x4380 /* loword */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 11596d2b7e9..cb24cd4ffeb 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -95,7 +95,7 @@ int board_early_init_f(void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtebc (epcr, 0xa8400000); /* EBC always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ return 0; /* success */ } @@ -135,29 +135,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/csb272/init.S b/board/csb272/init.S index 1cfef376a69..15b26f8bf86 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -38,17 +38,17 @@ #define WDCR_EBC(reg,val) \ addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #define WDCR_SDRAM(reg,val) \ addi r4,0,reg;\ - mtdcr memcfga,r4;\ + mtdcr SDRAM0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /****************************************************************************** * Function: ext_bus_cntlr_init @@ -106,51 +106,51 @@ ext_bus_cntlr_init: * SETUP CPC0_CR0 *******************************************************************/ LI32(r4, 0x007000c0) - mtdcr cntrl0, r4 + mtdcr CPC0_CR0, r4 /******************************************************************** * Setup CPC0_CR1: Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) + WDCR_EBC(EBC0_CFG, 0xd84c0000) /******************************************************************** * Memory Bank 0 (Intel 28F128J3 Flash) initialization *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x02869200)*/ - WDCR_EBC(pb0ap, 0x07869200) - WDCR_EBC(pb0cr, 0xfe0bc000) + /*WDCR_EBC(PB1AP, 0x02869200)*/ + WDCR_EBC(PB1AP, 0x07869200) + WDCR_EBC(PB0CR, 0xfe0bc000) /******************************************************************** * Memory Bank 1 (Holtek HT6542B PS/2) initialization *******************************************************************/ - WDCR_EBC(pb1ap, 0x1f869200) - WDCR_EBC(pb1cr, 0xf0818000) + WDCR_EBC(PB1AP, 0x1f869200) + WDCR_EBC(PB1CR, 0xf0818000) /******************************************************************** * Memory Bank 2 (Epson S1D13506) initialization *******************************************************************/ - WDCR_EBC(pb2ap, 0x05860300) - WDCR_EBC(pb2cr, 0xf045a000) + WDCR_EBC(PB2AP, 0x05860300) + WDCR_EBC(PB2CR, 0xf045a000) /******************************************************************** * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization *******************************************************************/ - WDCR_EBC(pb3ap, 0x0387d200) - WDCR_EBC(pb3cr, 0xf021c000) + WDCR_EBC(PB3AP, 0x0387d200) + WDCR_EBC(PB3CR, 0xf021c000) /******************************************************************** * Memory Bank 4-7 (Unused) initialization *******************************************************************/ - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) + WDCR_EBC(PB4AP, 0) + WDCR_EBC(PB4CR, 0) + WDCR_EBC(PB5AP, 0) + WDCR_EBC(PB5CR, 0) + WDCR_EBC(PB6AP, 0) + WDCR_EBC(PB6CR, 0) + WDCR_EBC(PB7AP, 0) + WDCR_EBC(PB7CR, 0) /* We are all done */ mtlr r0 /* Restore link register */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index 9dc130efc17..fa0fa193e82 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -63,7 +63,7 @@ int board_early_init_f(void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtebc (epcr, 0xa8400000); /* EBC always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* EBC always driven */ return 0; /* success */ } @@ -103,29 +103,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/csb472/init.S b/board/csb472/init.S index 2cf8afc4994..105cb71bec0 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -38,17 +38,17 @@ #define WDCR_EBC(reg,val) \ addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #define WDCR_SDRAM(reg,val) \ addi r4,0,reg;\ - mtdcr memcfga,r4;\ + mtdcr SDRAM0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /****************************************************************************** * Function: ext_bus_cntlr_init @@ -106,47 +106,47 @@ ext_bus_cntlr_init: * SETUP CPC0_CR0 *******************************************************************/ LI32(r4, 0x00c01030) - mtdcr cntrl0, r4 + mtdcr CPC0_CR0, r4 /******************************************************************** * Setup CPC0_CR1: Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - WDCR_EBC(epcr, 0xd84c0000) + WDCR_EBC(EBC0_CFG, 0xd84c0000) /******************************************************************** * Memory Bank 0 (Intel 28F640J3 Flash) initialization *******************************************************************/ - /*WDCR_EBC(pb0ap, 0x03055200)*/ - /*WDCR_EBC(pb0ap, 0x04055200)*/ - WDCR_EBC(pb0ap, 0x08055200) - WDCR_EBC(pb0cr, 0xff87a000) + /*WDCR_EBC(PB1AP, 0x03055200)*/ + /*WDCR_EBC(PB1AP, 0x04055200)*/ + WDCR_EBC(PB1AP, 0x08055200) + WDCR_EBC(PB0CR, 0xff87a000) /******************************************************************** * Memory Bank 3 (Xilinx XC95144 CPLD) initialization *******************************************************************/ - /*WDCR_EBC(pb3ap, 0x07869200)*/ - WDCR_EBC(pb3ap, 0x04055200) - WDCR_EBC(pb3cr, 0xf081c000) + /*WDCR_EBC(PB3AP, 0x07869200)*/ + WDCR_EBC(PB3AP, 0x04055200) + WDCR_EBC(PB3CR, 0xf081c000) /******************************************************************** * Memory Bank 1,2,4-7 (Unused) initialization *******************************************************************/ - WDCR_EBC(pb1ap, 0) - WDCR_EBC(pb1cr, 0) - WDCR_EBC(pb2ap, 0) - WDCR_EBC(pb2cr, 0) - WDCR_EBC(pb4ap, 0) - WDCR_EBC(pb4cr, 0) - WDCR_EBC(pb5ap, 0) - WDCR_EBC(pb5cr, 0) - WDCR_EBC(pb6ap, 0) - WDCR_EBC(pb6cr, 0) - WDCR_EBC(pb7ap, 0) - WDCR_EBC(pb7cr, 0) + WDCR_EBC(PB1AP, 0) + WDCR_EBC(PB1CR, 0) + WDCR_EBC(PB2AP, 0) + WDCR_EBC(PB2CR, 0) + WDCR_EBC(PB4AP, 0) + WDCR_EBC(PB4CR, 0) + WDCR_EBC(PB5AP, 0) + WDCR_EBC(PB5CR, 0) + WDCR_EBC(PB6AP, 0) + WDCR_EBC(PB6CR, 0) + WDCR_EBC(PB7AP, 0) + WDCR_EBC(PB7CR, 0) /* We are all done */ mtlr r0 /* Restore link register */ diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c index a6aa6554b95..56751e15995 100644 --- a/board/dave/PPChameleonEVB/PPChameleonEVB.c +++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c @@ -65,9 +65,9 @@ int board_early_init_f (void) * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ #if 1 /* test-only */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ #else - mtebc (epcr, 0x28400000); /* ebc in high-z */ + mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */ #endif return 0; } @@ -101,7 +101,7 @@ int misc_init_r (void) int status; int index; int i; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c index e5a0d3d17e2..237c807b4ff 100644 --- a/board/dave/PPChameleonEVB/flash.c +++ b/board/dave/PPChameleonEVB/flash.c @@ -75,9 +75,9 @@ unsigned long flash_init (void) debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base = -size; switch (size) { case 1 << 20: @@ -97,7 +97,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__); /* Monitor protection ON by default */ diff --git a/board/eric/eric.c b/board/eric/eric.c index 600b9d7a7ce..bc2a907f6b9 100644 --- a/board/eric/eric.c +++ b/board/eric/eric.c @@ -70,7 +70,7 @@ int board_early_init_f (void) mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ + mtdcr (CPC0_CR0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */ out32 (PPC405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */ out32 (PPC405GP_GPIO0_TCR, 0x7E400000); diff --git a/board/eric/flash.c b/board/eric/flash.c index 7e57513aebf..fded41271f1 100644 --- a/board/eric/flash.c +++ b/board/eric/flash.c @@ -105,24 +105,24 @@ unsigned long flash_init (void) if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/eric/init.S b/board/eric/init.S index 4820dd08c7f..16ab11eae25 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -76,129 +76,129 @@ ext_bus_cntlr_init: /* Memory Bank 0 (Flash) initialization (from openbios) */ /*----------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS0_AP@h ori r4,r4,CS0_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS0_CR@h ori r4,r4,CS0_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 1 (NVRAM/RTC) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb1ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS1_AP@h ori r4,r4,CS1_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS1_CR@h ori r4,r4,CS1_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 2 (A/D converter) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb2ap - mtdcr ebccfga,r4 + addi r4,0,PB2AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS2_AP@h ori r4,r4,CS2_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS2_CR@h ori r4,r4,CS2_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 3 (Ethernet PHY Reset) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb3ap - mtdcr ebccfga,r4 + addi r4,0,PB3AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS3_AP@h ori r4,r4,CS3_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS3_CR@h ori r4,r4,CS3_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb4ap - mtdcr ebccfga,r4 + addi r4,0,PB4AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS4_AP@h ori r4,r4,CS4_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS4_CR@h ori r4,r4,CS4_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb5ap - mtdcr ebccfga,r4 + addi r4,0,PB5AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS5_AP@h ori r4,r4,CS5_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS5_CR@h ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 6 (CPU LED0) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb6ap - mtdcr ebccfga,r4 + addi r4,0,PB6AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS6_AP@h ori r4,r4,CS6_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS6_CR@h ori r4,r4,CS5_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- */ /* Memory Bank 7 (CPU LED1) initialization */ /*----------------------------------------------------------------------- */ - addi r4,0,pb7ap - mtdcr ebccfga,r4 + addi r4,0,PB7AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS7_AP@h ori r4,r4,CS7_AP@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,CS7_CR@h ori r4,r4,CS7_CR@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* addis r4,r0,FPGA_BRDC@h */ /* ori r4,r4,FPGA_BRDC@l */ @@ -229,40 +229,40 @@ sdram_init: /*------------------------------------------------------------------- */ addi r4,0,mem_mb0cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB0CF@h ori r4,r4,MB0CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb1cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB1CF@h ori r4,r4,MB1CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB2CF for bank 2. off */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb2cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB2CF@h ori r4,r4,MB2CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set MB3CF for bank 3. off */ /*------------------------------------------------------------------- */ addi r4,0,mem_mb3cf - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,MB3CF@h ori r4,r4,MB3CF@l - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */ @@ -276,7 +276,7 @@ sdram_init: /* maybe 133Mhz. */ /*------------------------------------------------------------------- */ - mfdcr r5,strap /* determine FBK divider */ + mfdcr r5,CPC0_PSR /* determine FBK divider */ /* via STRAP reg to calc PLB speed. */ /* SDRAM speed is the same as the PLB */ /* speed. */ @@ -306,15 +306,15 @@ sdram_init: /* Set SDTR1 */ /*------------------------------------------------------------------- */ addi r4,0,mem_sdtr1 - mtdcr memcfga,r4 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r6 /*------------------------------------------------------------------- */ /* Set RTR */ /*------------------------------------------------------------------- */ addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r7 /*------------------------------------------------------------------- */ /* Delay to ensure 200usec have elapsed since reset. Assume worst */ @@ -333,10 +333,10 @@ sdram_init: /* read/prefetch. */ /*------------------------------------------------------------------- */ addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x8080 /* set DC_EN=1 */ ori r4,r4,0x0000 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*------------------------------------------------------------------- */ /* Delay to ensure 10msec have elapsed since reset. This is */ diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 5a021552dd3..46622a29fd4 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -92,7 +92,7 @@ int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -100,8 +100,8 @@ int board_revision(void) */ /* Setup GPIO pins (CS2/GPIO11, CS3/GPIO12 and CS4/GPIO13 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03800000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03800000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000); @@ -113,7 +113,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x001c0000: @@ -166,7 +166,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * New boards have a single 32MB flash connected to CS0 @@ -174,12 +174,12 @@ int board_early_init_f (void) */ if (board_revision() >= 8) { /* disable CS1 */ - mtebc(pb1ap, 0); - mtebc(pb1cr, 0); + mtebc(PB1AP, 0); + mtebc(PB1CR, 0); /* resize CS0 to 32MB */ - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP_HWREV8); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR_HWREV8); } return 0; @@ -209,7 +209,7 @@ int misc_init_r(void) int status; int index; int i; - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; char *str; uchar *logo_addr; ulong logo_size; @@ -219,8 +219,8 @@ int misc_init_r(void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { @@ -265,7 +265,7 @@ int misc_init_r(void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c index 074fe08b1c1..8da08facffc 100644 --- a/board/esd/ash405/ash405.c +++ b/board/esd/ash405/ash405.c @@ -77,7 +77,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/ash405/flash.c +++ b/board/esd/ash405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/canbt/canbt.c b/board/esd/canbt/canbt.c index 2fe6b7bf046..418d3e237ed 100644 --- a/board/esd/canbt/canbt.c +++ b/board/esd/canbt/canbt.c @@ -52,16 +52,16 @@ const unsigned char fpgadata[] = { int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; int index, len, i; int status; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr (cntrl0) & 0xf0001fff; - cntrl0Reg |= 0x0070f000; - mtdcr (cntrl0, cntrl0Reg); + CPC0_CR0Reg = mfdcr (CPC0_CR0) & 0xf0001fff; + CPC0_CR0Reg |= 0x0070f000; + mtdcr (CPC0_CR0, CPC0_CR0Reg); #ifdef FPGA_DEBUG /* set up serial port with default baudrate */ diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/canbt/flash.c +++ b/board/esd/canbt/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c index 01b12232b19..7a92401893d 100644 --- a/board/esd/cms700/cms700.c +++ b/board/esd/cms700/cms700.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c index cd57ed4598c..00c7024a852 100644 --- a/board/esd/cpci2dp/cpci2dp.c +++ b/board/esd/cpci2dp/cpci2dp.c @@ -31,13 +31,13 @@ DECLARE_GLOBAL_DATA_PTR; int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup GPIO pins */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5)); @@ -72,7 +72,7 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -81,8 +81,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index a677c623f78..4c9ed2fa585 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -214,7 +214,7 @@ int ctermm2(void) int cpci405_host(void) { - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return -1; /* yes, board is cpci405 host */ else return 0; /* no, board is cpci405 adapter */ @@ -222,14 +222,14 @@ int cpci405_host(void) int cpci405_version(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ @@ -238,7 +238,7 @@ int cpci405_version(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00180000: @@ -261,7 +261,7 @@ int cpci405_version(void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -283,8 +283,8 @@ int misc_init_r (void) /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, @@ -330,7 +330,7 @@ int misc_init_r (void) } /* restore gpio/cs settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); puts("FPGA: "); @@ -400,8 +400,8 @@ int misc_init_r (void) /* * Select cts (and not dsr) on uart1 */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return 0; } diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index d535924f86f..4fcf174d15b 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -91,13 +91,13 @@ unsigned long flash_init (void) size_b1 = 1 << 20; } base_b1 = -size_b1; - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); pbcr = (pbcr & 0x0001ffff) | base_b1 | (calc_size(size_b1) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b1=%x base_b1=%x pb1cr = %x\n", + printf("size_b1=%x base_b1=%x PB1CR = %x\n", size_b1, base_b1, pbcr); /* test-only */ #endif } @@ -108,13 +108,13 @@ unsigned long flash_init (void) size_b0 = 1 << 20; } base_b0 = base_b1 - size_b0; - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); pbcr = (pbcr & 0x0001ffff) | base_b0 | (calc_size(size_b0) << 17); - mtdcr (ebccfgd, pbcr); + mtdcr (EBC0_CFGDATA, pbcr); #if 0 /* test-only */ - printf("size_b0=%x base_b0=%x pb0cr = %x\n", + printf("size_b0=%x base_b0=%x PB0CR = %x\n", size_b0, base_b0, pbcr); /* test-only */ #endif } diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index 56c822ec97f..224dde4ee0b 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -64,13 +64,13 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr(EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c index e52d37bc217..fc0d091bca9 100644 --- a/board/esd/dp405/dp405.c +++ b/board/esd/dp405/dp405.c @@ -54,7 +54,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO13 (CS4) pin diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/dp405/flash.c +++ b/board/esd/dp405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index 8e9ac28b181..28a50c7b0e7 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -135,7 +135,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 100 us */ - mtebc (epcr, 0xb8400000); + mtebc (EBC0_CFG, 0xb8400000); return 0; } @@ -143,13 +143,13 @@ int board_early_init_f (void) int misc_init_r (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * Setup UART1 handshaking: use CTS instead of DSR */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00001000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00001000); return (0); } diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c index 240aa09f5b4..c62c6a9b030 100644 --- a/board/esd/du405/flash.c +++ b/board/esd/du405/flash.c @@ -67,25 +67,25 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 0ec519b8db6..376de983548 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -45,8 +45,8 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -145,8 +145,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* setup NAND FLASH */ mfsdr(SDR0_CUST0, sdr0_cust0); @@ -176,12 +176,12 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -265,8 +265,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); /* * release IO-RST# @@ -380,35 +380,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c index 5ae4c75861e..b72b716ddf2 100644 --- a/board/esd/hh405/hh405.c +++ b/board/esd/hh405/hh405.c @@ -374,7 +374,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c index 03e5ad7dd16..acb23dad1f5 100644 --- a/board/esd/hub405/hub405.c +++ b/board/esd/hub405/hub405.c @@ -97,7 +97,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index e763a895ea4..eda7c5713c3 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -68,9 +68,9 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; switch (size_b1) { case 1 << 20: @@ -90,14 +90,14 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; switch (size_b1) { case 1 << 20: @@ -117,8 +117,8 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]); diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c index 35bfa95f269..709bcdd9802 100644 --- a/board/esd/ocrtc/ocrtc.c +++ b/board/esd/ocrtc/ocrtc.c @@ -57,7 +57,7 @@ int board_early_init_f (void) * EBC Configuration Register: clear EBTC -> high-Z ebc signals between * transfers, set device-paced timeout to 256 cycles */ - mtebc (epcr, 0x20400000); + mtebc (EBC0_CFG, 0x20400000); return 0; } diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 90584838008..67a7bb5d867 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index 56184caa8f4..04bc569ead1 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -67,7 +67,7 @@ const unsigned char fpgadata[] = int board_revision(void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* @@ -77,8 +77,8 @@ int board_revision(void) /* * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x03000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200); udelay(1000); /* wait some time before reading input */ @@ -87,7 +87,7 @@ int board_revision(void) /* * Restore GPIO settings */ - mtdcr(cntrl0, cntrl0Reg); + mtdcr(CPC0_CR0, CPC0_CR0Reg); switch (value) { case 0x00100200: @@ -133,7 +133,7 @@ unsigned long fpga_init_state(void) int board_early_init_f (void) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; /* * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board) @@ -166,18 +166,18 @@ int board_early_init_f (void) /* * Setup GPIO pins (IRQ4/GPIO21 as GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg | 0x00008000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000); /* * Setup GPIO pins (CS6+CS7 as GPIO) */ - mtdcr(cntrl0, cntrl0Reg | 0x00300000); + mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000); /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } @@ -282,11 +282,11 @@ int misc_init_r (void) #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -#define plb0_acr 0x87 +#define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ - mtdcr(plb0_acr, 0x98000000); + mtdcr(PLB0_ACR, 0x98000000); free(dst); return (0); @@ -313,14 +313,14 @@ int checkboard (void) printf(" (Rev 1.%ld", gd->board_type); if (gd->board_type >= 2) { - unsigned long cntrl0Reg; + unsigned long CPC0_CR0Reg; unsigned long value; /* * Setup GPIO pins (Trace/GPIO1 to GPIO) */ - cntrl0Reg = mfdcr(cntrl0); - mtdcr(cntrl0, cntrl0Reg & ~0x08000000); + CPC0_CR0Reg = mfdcr(CPC0_CR0); + mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000); udelay(1000); /* wait some time before reading input */ diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index e41545a9369..a3c1cec6ef4 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -90,7 +90,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to * 512 ebc-clks -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 192a642aea0..5ff87e7a250 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -60,12 +60,12 @@ int board_early_init_f (void) * EBC Configuration Register: * set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); + mtebc (EBC0_CFG, 0xa8400000); /* * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_FPGA_INIT | CONFIG_SYS_FPGA_DONE | CONFIG_SYS_XEREADY | CONFIG_SYS_NONMONARCH | @@ -73,7 +73,7 @@ int board_early_init_f (void) if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | + mtdcr(CPC0_CR0, mfdcr(CPC0_CR0) | ((CONFIG_SYS_INTA_FAKE | CONFIG_SYS_SELF_RST) << 5)); } diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index f68e1b5e86b..419311aec83 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -127,7 +127,7 @@ int board_early_init_f(void) * - set ready timeout to 512 ebc-clks -> ca. 15 us * - EBC lines are always driven */ - mtebc(epcr, 0xa8400000); + mtebc(EBC0_CFG, 0xa8400000); return 0; } diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index f22a1c28888..119cbf26273 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -64,7 +64,7 @@ struct serial_device *default_serial_console(void) * Use default console on P4 when strapping jumper * is installed (bootstrap option != 'H'). */ - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); if (((val & 0xf0000000) >> 29) != 7) return &serial1_device; @@ -100,8 +100,8 @@ int board_early_init_f(void) u32 reg; /* general EBC configuration (disable EBC timeouts) */ - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xf8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xf8400000); /* * Setup the GPIO pins @@ -134,13 +134,13 @@ int board_early_init_f(void) out_be32((void *)GPIO1_ISR3H, 0x00000000); /* patch PLB:PCI divider for 66MHz PCI */ - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); if (pci_is_66mhz() && (reg != 0x02000000)) { - mtcpr(clk_spcid, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ + mtcpr(CPR0_SPCID, 0x02000000); /* 133MHZ : 2 for 66MHz PCI */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg |= CPR0_ICFG_RLI_MASK; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); mtspr(SPRN_DBCR0, 0x20000000); /* do chip reset */ } @@ -240,19 +240,19 @@ int misc_init_r(void) gd->bd->bi_flashoffset = 0; #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - pbcr = mfdcr(ebccfgd); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) - mtdcr(ebccfga, pb2cr); + mtdcr(EBC0_CFGADDR, PB2CR); #else - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); #endif - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -424,8 +424,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); #ifdef CONFIG_FPGA pmc440_init_fpga(); @@ -507,35 +507,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #ifdef CONFIG_PCI_PNP hose->fixup_irq = pmc440_pci_fixup_irq; diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/voh405/flash.c +++ b/board/esd/voh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c index 91275507e0f..7477f56b2b1 100644 --- a/board/esd/voh405/voh405.c +++ b/board/esd/voh405/voh405.c @@ -99,7 +99,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index a481acaea14..de9c7b974cf 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -56,7 +56,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * Reset CPLD via GPIO12 (CS3) pin diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c index 274ada9fe5c..a53122b2171 100644 --- a/board/esd/wuh405/flash.c +++ b/board/esd/wuh405/flash.c @@ -65,9 +65,9 @@ unsigned long flash_init (void) flash_get_offsets (-size_b0, &flash_info[0]); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b0 = -size_b0; switch (size_b0) { case 1 << 20: @@ -87,7 +87,7 @@ unsigned long flash_init (void) break; } pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ (void)flash_protect(FLAG_PROTECT_SET, diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c index e330fff16c9..e86f1d0abc6 100644 --- a/board/esd/wuh405/wuh405.c +++ b/board/esd/wuh405/wuh405.c @@ -75,7 +75,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/exbitgen/exbitgen.c b/board/exbitgen/exbitgen.c index dc07d3df063..0f8412776b6 100644 --- a/board/exbitgen/exbitgen.c +++ b/board/exbitgen/exbitgen.c @@ -94,29 +94,29 @@ phys_size_t initdram (int board_type) tot_size = 0; - mtdcr (memcfga, mem_mb0cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb1cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb2cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; } - mtdcr (memcfga, mem_mb3cf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + tmp = mfdcr (SDRAM0_CFGDATA); if (tmp & 0x00000001) { bank_size = 0x00400000 << ((tmp >> 17) & 0x7); tot_size += bank_size; diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index cb548746182..c2dae560f5f 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -109,10 +109,10 @@ #define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr ebccfga,r4;\ + mtdcr EBC0_CFGADDR,r4;\ addis r4,0,val@h;\ ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*--------------------------------------------------------------------- * Function: ext_bus_cntlr_init @@ -164,22 +164,22 @@ ext_bus_cntlr_init: * Memory Bank 0 (Boot Flash) initialization *--------------------------------------------------------------- */ - WDCR_EBC(pb0ap, FLASH_32bit_AP) - WDCR_EBC(pb0cr, 0xffe38000) -/*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ + WDCR_EBC(PB1AP, FLASH_32bit_AP) + WDCR_EBC(PB0CR, 0xffe38000) +/*pnc WDCR_EBC(PB0CR, FLASH_32bit_CR) */ /*--------------------------------------------------------------- * Memory Bank 5 (CPLD) initialization *--------------------------------------------------------------- */ - WDCR_EBC(pb5ap, 0x01010040) -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ - WDCR_EBC(pb5cr, 0x10038000) + WDCR_EBC(PB5AP, 0x01010040) +/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ + WDCR_EBC(PB5CR, 0x10038000) /*--------------------------------------------------------------- */ /* Memory Bank 6 (not used) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb6cr, 0x00000000) + WDCR_EBC(PB6CR, 0x00000000) /* Read HW ID to determine whether old H2 board or new generic CPU board */ addis r3, 0, HW_ID_ADDR@h @@ -196,24 +196,24 @@ setup_genieboard: /*--------------------------------------------------------------- */ /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ /*--------------------------------------------------------------- */ -/* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ -/* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ +/* WDCR_EBC(PB1AP, 0x7b015480) /###* T.B.M. */ +/* WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB1AP, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ -/* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ - WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ +/* WDCR_EBC(PB1CR, 0x20098000) /###* 16 MB */ + WDCR_EBC(PB1CR, 0x200B8000) /* 32 MB */ /*--------------------------------------------------------------- */ /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x01010000) /* */ - WDCR_EBC(pb4cr, 0x1021c000) /* */ + WDCR_EBC(PB4AP, 0x01010000) /* */ + WDCR_EBC(PB4CR, 0x1021c000) /* */ /*--------------------------------------------------------------- */ /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ - WDCR_EBC(pb7cr, 0X4001A000) + WDCR_EBC(PB7AP, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ + WDCR_EBC(PB7CR, 0X4001A000) bl setup_continue @@ -222,36 +222,36 @@ setup_h2evalboard: /*--------------------------------------------------------------- */ /* Memory Bank 1 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1cr, 0x20058000) + WDCR_EBC(PB1AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB1AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB1CR, 0x20058000) /*--------------------------------------------------------------- */ /* Memory Bank 2 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb2cr, 0x20458000) + WDCR_EBC(PB2AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB2AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB2CR, 0x20458000) /*--------------------------------------------------------------- */ /* Memory Bank 3 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb3cr, 0x20858000) + WDCR_EBC(PB3AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB3AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB3CR, 0x20858000) /*--------------------------------------------------------------- */ /* Memory Bank 4 (Application Flash) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ -/*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb4cr, 0x20C58000) + WDCR_EBC(PB4AP, 0x7b015480) /* T.B.M. */ +/*3010 WDCR_EBC(PB4AP, 0x7F8FFE80) /###* T.B.M. */ + WDCR_EBC(PB4CR, 0x20C58000) /*--------------------------------------------------------------- */ /* Memory Bank 7 (Heathrow chip) initialization */ /*--------------------------------------------------------------- */ - WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ - WDCR_EBC(pb7cr, 0X4001A000) + WDCR_EBC(PB7AP, 0x02000280) /* No Ready, 4 wait states */ + WDCR_EBC(PB7CR, 0X4001A000) setup_continue: @@ -294,7 +294,7 @@ sdram_init: /* Read PLL feedback divider and calculate clock period of local bus in */ /* granularity of 10 ps. Save clock period in r30 */ /*-------------------------------------------------------------- */ - mfdcr r4, pllmd + mfdcr r4, CPC0_PLLMR addi r9, 0, 25 srw r4, r4, r9 andi. r4, r4, 0x07 @@ -383,8 +383,8 @@ sdram_init: /* Set SDTR1 */ /*----------------------------------------------------------- */ addi r5,0,mem_sdtr1 - mtdcr memcfga,r5 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGADDR,r5 + mtdcr SDRAM0_CFGDATA,r4 /*----------------------------------------------------------- */ /* */ @@ -414,8 +414,8 @@ sdram_init: /* Set SDRAM bank 0 register and adjust r6 for next bank */ /*------------------------------------------------------ */ addi r7,0,mem_mb0cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ @@ -425,16 +425,16 @@ sdram_init: bne b1skip addi r7,0,mem_mb1cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ /* Set SDRAM bank 2 register and adjust r6 for next bank */ /*------------------------------------------------------ */ b1skip: addi r7,0,mem_mb2cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 add r6, r6, r15 /* add bank size to base address for next bank */ @@ -444,8 +444,8 @@ b1skip: addi r7,0,mem_mb2cf bne b3skip addi r7,0,mem_mb3cf - mtdcr memcfga,r7 - mtdcr memcfgd,r6 + mtdcr SDRAM0_CFGADDR,r7 + mtdcr SDRAM0_CFGDATA,r6 b3skip: /*----------------------------------------------------------- */ @@ -457,8 +457,8 @@ b3skip: bl rtr_2 rtr_1: addis r7, 0, 0x03F8 rtr_2: addi r4,0,mem_rtr - mtdcr memcfga,r4 - mtdcr memcfgd,r7 + mtdcr SDRAM0_CFGADDR,r4 + mtdcr SDRAM0_CFGDATA,r7 /*----------------------------------------------------------- */ /* Delay to ensure 200usec have elapsed since reset. Assume worst */ @@ -477,10 +477,10 @@ rtr_2: addi r4,0,mem_rtr /* read/prefetch. */ /*----------------------------------------------------------- */ addi r4,0,mem_mcopt1 - mtdcr memcfga,r4 + mtdcr SDRAM0_CFGADDR,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ ori r4,r4,0x0000 - mtdcr memcfgd,r4 + mtdcr SDRAM0_CFGDATA,r4 /*----------------------------------------------------------- */ @@ -980,9 +980,9 @@ fc07: /* For CPLD */ /* 0 + 00000 + 010 + 000 + 00 + 01 + 00 + 00 + 000 + 0 + 0 + 1 + 0 + 00000 */ -/* WDCR_EBC(pb5ap, 0x01010040) */ -/*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ -/* WDCR_EBC(pb5cr, 0X10018000) */ +/* WDCR_EBC(PB5AP, 0x01010040) */ +/*jsa recommendation: WDCR_EBC(PB5AP, 0x00010040) */ +/* WDCR_EBC(PB5CR, 0X10018000) */ /* Access parms */ /* 100 3 8 0 0 0 */ /* 0x100 + 001 + 11 + 00 + 0 0000 0000 0000 = 0x10038000 */ @@ -1003,9 +1003,9 @@ fc07: /* Usage: read/write */ /* Width: 32 bit */ -/* Walnut fpga pb7ap */ +/* Walnut fpga PB7AP */ /* 0 1 8 1 5 2 8 0 */ /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ -/* Walnut fpga pb7cr */ +/* Walnut fpga PB7CR */ /* 0xF0318000 */ /* */ diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c index f6f47197cdf..ae258e1f263 100644 --- a/board/g2000/g2000.c +++ b/board/g2000/g2000.c @@ -58,7 +58,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); /* ebc always driven */ + mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */ #endif return 0; @@ -114,7 +114,7 @@ int checkboard (void) long int init_sdram_static_settings(void) { -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL ); mtsdram0( mem_rtr , MEM_RTR_INIT_VAL ); @@ -154,15 +154,15 @@ int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong ap, cr; printf("\nEBC registers for PPC405GP:\n"); - mfebc(pb0ap, ap); mfebc(pb0cr, cr); + mfebc(PB0AP, ap); mfebc(PB0CR, cr); printf("0: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb1ap, ap); mfebc(pb1cr, cr); + mfebc(PB1AP, ap); mfebc(PB1CR, cr); printf("1: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb2ap, ap); mfebc(pb2cr, cr); + mfebc(PB2AP, ap); mfebc(PB2CR, cr); printf("2: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb3ap, ap); mfebc(pb3cr, cr); + mfebc(PB3AP, ap); mfebc(PB3CR, cr); printf("3: AP=%08lx CP=%08lx\n", ap, cr); - mfebc(pb4ap, ap); mfebc(pb4cr, cr); + mfebc(PB4AP, ap); mfebc(PB4CR, cr); printf("4: AP=%08lx CP=%08lx\n", ap, cr); printf("\n"); diff --git a/board/gdsys/compactcenter/compactcenter.c b/board/gdsys/compactcenter/compactcenter.c index f448ef93727..8a5ea300d7a 100644 --- a/board/gdsys/compactcenter/compactcenter.c +++ b/board/gdsys/compactcenter/compactcenter.c @@ -215,7 +215,7 @@ int board_early_init_r(void) EBC_BXCR_BS_128MB : EBC_BXCR_BS_64MB; /* Remap the NOR FLASH to 0xcn00.0000 ... 0xcfff.ffff */ - mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L + mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | bxcr_bw | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index 4ec1cdbc3e2..5246bc8c4fb 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -48,7 +48,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to 512 ebc-clks * -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ /* * setup io-latches diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index a661057438e..27c159bec62 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -42,8 +42,8 @@ int board_early_init_f(void) /* * Setup the external bus controller/chip selects */ - mfebc(xbcfg, reg); - mtebc(xbcfg, reg | 0x04000000); /* Set ATC */ + mfebc(EBC0_CFG, reg); + mtebc(EBC0_CFG, reg | 0x04000000); /* Set ATC */ /* * Setup the GPIO pins @@ -102,10 +102,10 @@ int board_early_init_f(void) /* * Setup other serial configuration */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00003e00); /* Pin function */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins */ return 0; } @@ -117,7 +117,7 @@ int misc_init_r(void) uint sz; /* Re-do sizing to get full correct info */ - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); if (gd->bd->bi_flashsize > 0x08000000) panic("Max. flash banksize is 128 MB!\n"); @@ -127,7 +127,7 @@ int misc_init_r(void) sz <<= 1; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -178,35 +178,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); /* enable 66 MHz ext. Clock */ out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x00008000); diff --git a/board/gdsys/neo/neo.c b/board/gdsys/neo/neo.c index 817ce17ff16..628ce3dc90b 100644 --- a/board/gdsys/neo/neo.c +++ b/board/gdsys/neo/neo.c @@ -43,7 +43,7 @@ int board_early_init_f(void) * EBC Configuration Register: set ready timeout to 512 ebc-clks * -> ca. 15 us */ - mtebc(epcr, 0xa8400000); /* ebc always driven */ + mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */ return 0; } diff --git a/board/jse/init.S b/board/jse/init.S index 7b932b25f0b..92f43f4fc7d 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -52,8 +52,6 @@ #include <asm/cache.h> #include <asm/mmu.h> -#define cpc0_cr0 0xB1 - .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ @@ -84,16 +82,16 @@ ext_bus_cntlr_init: /* Memory Bank 0 (Flash) initialization */ /*----------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x9B01 ori r4,r4,0x5480 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 blr diff --git a/board/jse/jse.c b/board/jse/jse.c index 6a6b9dd74b3..6dc9a01af8f 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -62,12 +62,12 @@ int board_early_init_f (void) /* EBC0_B1AP: BME=1, TWT=2, CSN=0, OEN=1, WBN=0, WBF=1, TH=0, RE=0, SOR=0, BEM=0, PEN=0 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, 0x01011000); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, 0x01011000); /* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */ - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000); /* Enable the /PerWE output as /PerWE, instead of /PCIINT. */ /* CPC0_CR1 |= PCIPW */ diff --git a/board/jse/sdram.c b/board/jse/sdram.c index a1f526de6ff..bb6f85eee51 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -35,60 +35,60 @@ phys_size_t initdram (int board_type) /* Configure the SDRAMS */ /* disable memory controller */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x00000000); udelay (500); /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besra); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besra); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */ - mtdcr (memcfga, mem_besrb); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_besrb); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Clear SDRAM0_ECCCFG (disable ECC) */ - mtdcr (memcfga, mem_ecccf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */ - mtdcr (memcfga, mem_eccerr); - mtdcr (memcfgd, 0xffffffff); + mtdcr (SDRAM0_CFGADDR, mem_eccerr); + mtdcr (SDRAM0_CFGDATA, 0xffffffff); /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2 */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, 0x010a4016); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, 0x010a4016); /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, 0x00084001); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, 0x00084001); /* Memory Bank 1 Config == BA=0x04000000, SZ=64M, AM=3, BE=1 */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, 0x04084001); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, 0x04084001); /* Memory Bank 2 Config == BE=0 */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* Memory Bank 3 Config == BE=0 */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, 0x00000000); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, 0x00000000); /* refresh timer = 0x400 */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, 0x04000000); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, 0x04000000); /* Power management idle timer set to the default. */ - mtdcr (memcfga, mem_pmit); - mtdcr (memcfgd, 0x07c00000); + mtdcr (SDRAM0_CFGADDR, mem_pmit); + mtdcr (SDRAM0_CFGDATA, 0x07c00000); udelay (500); /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) */ - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, 0x80e00000); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, 0x80e00000); return SDRAM_LEN; } @@ -108,28 +108,28 @@ int testdram (void) #ifdef DEBUG printf ("SDRAM Controller Registers --\n"); - mtdcr (memcfga, mem_mcopt1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_CFG : 0x%08x\n", val); - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_STATUS: 0x%08x\n", val); - mtdcr (memcfga, mem_mb0cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B0CR : 0x%08x\n", val); - mtdcr (memcfga, mem_mb1cf); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_B1CR : 0x%08x\n", val); - mtdcr (memcfga, mem_sdtr1); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_TR : 0x%08x\n", val); - mtdcr (memcfga, mem_rtr); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + val = mfdcr (SDRAM0_CFGDATA); printf (" SDRAM0_RTR : 0x%08x\n", val); #endif @@ -137,8 +137,8 @@ int testdram (void) bit. Really, there should already have been plenty of time, given it was started long ago. But, best to check. */ for (idx = 0; idx < 1000000; idx += 1) { - mtdcr (memcfga, 0x24); - val = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, 0x24); + val = mfdcr (SDRAM0_CFGDATA); if (val & 0x80000000) break; } diff --git a/board/korat/korat.c b/board/korat/korat.c index 8328ba326db..3d4d149f6c6 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -81,8 +81,8 @@ int board_early_init_f(void) korat_buzzer(0); #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the interrupt controller polarities, triggers, etc. @@ -157,8 +157,8 @@ int board_early_init_f(void) mtsdr(SDR0_PFC1, sdr0_pfc1); /* PCI arbiter enabled */ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); return 0; } @@ -359,12 +359,12 @@ int misc_init_r(void) gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size; gd->bd->bi_flashoffset = 0; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(flash1_size) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* * Re-check to get correct base address @@ -378,12 +378,12 @@ int misc_init_r(void) gd->bd->bi_flashoffset = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR; - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, pbcr); /* Monitor protection ON by default */ #if defined(CONFIG_KORAT_PERMANENT) @@ -552,8 +552,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); set_serial_number(); set_mac_addresses(); @@ -620,35 +620,35 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); #if defined(CONFIG_PCI_PNP) hose->fixup_irq = korat_pci_fixup_irq; diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 9b76e7663cc..a9c2a6f441a 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -38,8 +38,8 @@ int board_early_init_f(void) u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(plb0_acr, 0xDE000000); - mtdcr(plb1_acr, 0xDE000000); + mtdcr(PLB0_ACR, 0xDE000000); + mtdcr(PLB1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -90,9 +90,9 @@ int board_early_init_f(void) /* PCI arbiter disabled */ /* PCI Host Configuration disbaled */ - mfsdr(sdr_pci0, reg); + mfsdr(SDR0_PCI0, reg); reg = 0; - mtsdr(sdr_pci0, 0x00000000 | reg); + mtsdr(SDR0_PCI0, 0x00000000 | reg); gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1); @@ -157,7 +157,7 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -185,7 +185,7 @@ int misc_init_r(void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* * Re-check to get correct base address @@ -249,8 +249,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; - mtdcr(plb4_acr, reg); + reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; + mtdcr(PLB4_ACR, reg); /* * Init matrix keyboard @@ -296,35 +296,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 355608cd3bd..682f0e76dd8 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -97,7 +97,7 @@ int get_boot_mode(void) { unsigned long pbcr; int res = 0; - pbcr = mfdcr (strap); + pbcr = mfdcr (CPC0_PSR); if ((pbcr & PSR_ROM_WIDTH_MASK) == 0) /* boot via MPS or MPS mapping */ res = BOOT_MPS; @@ -123,29 +123,29 @@ void setup_cs_reloc(void) /* first findout on which cs the flash is */ if(mode & BOOT_MPS) { /* map flash high on CS1 and MPS on CS0 */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB0AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, MPS_CR); /* we use the default values (max values) for the flash * because its real size is not yet known */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR_B); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, FLASH_CR_B); } else { /* map flash high on CS0 and MPS on CS1 */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, MPS_CR); /* we use the default values (max values) for the flash * because its real size is not yet known */ - mtdcr (ebccfga, pb0ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, FLASH_CR_B); + mtdcr (EBC0_CFGADDR, PB0AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, FLASH_CR_B); } } @@ -217,34 +217,34 @@ unsigned long flash_init (void) } if(mode & BOOT_MPS) { /* flash is on CS1 */ - mtdcr(ebccfga, pb1cr); - flashcr = mfdcr (ebccfgd); + mtdcr(EBC0_CFGADDR, PB1CR); + flashcr = mfdcr (EBC0_CFGDATA); /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb1cr); - mtdcr(ebccfgd, flashcr); + mtdcr(EBC0_CFGADDR, PB1CR); + mtdcr(EBC0_CFGDATA, flashcr); } else { /* flash is on CS0 */ - mtdcr(ebccfga, pb0cr); - flashcr = mfdcr (ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + flashcr = mfdcr (EBC0_CFGDATA); /* we map the flash high in every case */ flashcr&=0x0001FFFF; /* mask out address bits */ flashcr|= ((0-flash_info[0].size) & 0xFFF00000); /* start addr */ flashcr|= (i << 17); /* size addr */ - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, flashcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, flashcr); } #if 0 /* enable this (PIP405/MIP405 only) if you want to test if the relocation has be done ok. This will disable both Chipselects */ - mtdcr (ebccfga, pb0cr); - mtdcr (ebccfgd, 0L); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, 0L); + mtdcr (EBC0_CFGADDR, PB0CR); + mtdcr (EBC0_CFGDATA, 0L); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, 0L); printf("CS0 & CS1 switched off for test\n"); #endif /* patch version_string */ diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index 19d92205112..f3d94c3fc1b 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -55,7 +55,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ + mfdcr r3,CPC0_PSR /* get strapping reg */ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ bnelr /* jump back if PCI boot */ @@ -84,9 +84,9 @@ ext_bus_cntlr_init: /*----------------------------------------------------------------------- * decide boot up mode *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA andi. r0, r4, 0x2000 /* mask out irrelevant bits */ beq 0f /* jump if 8 bit bus width */ @@ -96,18 +96,18 @@ ext_bus_cntlr_init: * Memory Bank 0 (16 Bit Flash) initialization *---------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(FLASH_AP_B)@h ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(FLASH_CR_B)@h ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 b 1f 0: @@ -117,66 +117,66 @@ ext_bus_cntlr_init: * Memory Bank 0 Multi Purpose Socket initialization *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(MPS_AP_B)@h ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(MPS_CR_B)@h ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 1: /*----------------------------------------------------------------------- * Memory Bank 2-3-4-5-6 (not used) initialization *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 nop /* pass2 DCR errata #8 */ blr diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 1738f543885..d8279e81c98 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -256,16 +256,16 @@ int init_sdram (void) gd->baudrate = 9600; serial_init (); /* set up the pld */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, PLD_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, PLD_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, PLD_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, PLD_CR); /* THIS IS OBSOLETE */ /* set up the board rev reg*/ - mtdcr (ebccfga, pb5ap); - mtdcr (ebccfgd, BOARD_AP); - mtdcr (ebccfga, pb5cr); - mtdcr (ebccfgd, BOARD_CR); + mtdcr (EBC0_CFGADDR, PB5AP); + mtdcr (EBC0_CFGDATA, BOARD_AP); + mtdcr (EBC0_CFGADDR, PB5CR); + mtdcr (EBC0_CFGDATA, BOARD_CR); #ifdef SDRAM_DEBUG /* get all informations from PLD */ serial_puts ("\nPLD Part 0x"); @@ -289,30 +289,30 @@ int init_sdram (void) SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n"); #endif /* set-up the chipselect machine */ - mtdcr (ebccfga, pb0cr); /* get cs0 config reg */ - tmp = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */ + tmp = mfdcr (EBC0_CFGDATA); if ((tmp & 0x00002000) == 0) { /* MPS Boot, set up the flash */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, FLASH_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, FLASH_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, FLASH_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, FLASH_CR); } else { /* Flash boot, set up the MPS */ - mtdcr (ebccfga, pb1ap); - mtdcr (ebccfgd, MPS_AP); - mtdcr (ebccfga, pb1cr); - mtdcr (ebccfgd, MPS_CR); + mtdcr (EBC0_CFGADDR, PB1AP); + mtdcr (EBC0_CFGDATA, MPS_AP); + mtdcr (EBC0_CFGADDR, PB1CR); + mtdcr (EBC0_CFGDATA, MPS_CR); } /* set up UART0 (CS2) and UART1 (CS3) */ - mtdcr (ebccfga, pb2ap); - mtdcr (ebccfgd, UART0_AP); - mtdcr (ebccfga, pb2cr); - mtdcr (ebccfgd, UART0_CR); - mtdcr (ebccfga, pb3ap); - mtdcr (ebccfgd, UART1_AP); - mtdcr (ebccfga, pb3cr); - mtdcr (ebccfgd, UART1_CR); + mtdcr (EBC0_CFGADDR, PB2AP); + mtdcr (EBC0_CFGDATA, UART0_AP); + mtdcr (EBC0_CFGADDR, PB2CR); + mtdcr (EBC0_CFGDATA, UART0_CR); + mtdcr (EBC0_CFGADDR, PB3AP); + mtdcr (EBC0_CFGDATA, UART1_AP); + mtdcr (EBC0_CFGADDR, PB3CR); + mtdcr (EBC0_CFGDATA, UART1_CR); bc = in8 (PLD_BOARD_CFG_REG); #ifdef SDRAM_DEBUG serial_puts ("\nstart SDRAM Setup\n"); @@ -348,8 +348,8 @@ int init_sdram (void) /* trc_clocks is sum of trp_clocks + tras_clocks */ trc_clocks = trp_clocks + tras_clocks; /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - sdram_tim = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ sdram_tim |= ((unsigned long) (cal_val)) << 23; /* insert PTA value */ @@ -369,8 +369,8 @@ int init_sdram (void) /* insert SZ value; */ tmp |= ((unsigned long) sdram_table[i].sz << 17); /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG @@ -380,8 +380,8 @@ int init_sdram (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, sdram_tim); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, sdram_tim); #ifdef SDRAM_DEBUG serial_puts ("mb0cf: "); @@ -390,23 +390,23 @@ int init_sdram (void) #endif /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, sdram_bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, sdram_bank); if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */ /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x07F00000; } else { /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; tmp |= 0x05F00000; } /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable ECC if used */ #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI) if (sdram_table[i].ecc) { @@ -415,19 +415,19 @@ int init_sdram (void) #ifdef SDRAM_DEBUG serial_puts ("disable ECC.. "); #endif - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp &= 0xff0fffff; /* disable all banks */ - mtdcr (memcfga, mem_ecccf); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); /* set up SDRAM Controller with ECC enabled */ #ifdef SDRAM_DEBUG serial_puts ("setup SDRAM Controller.. "); #endif - mtdcr (memcfgd, tmp); - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (600); #ifdef SDRAM_DEBUG serial_puts ("fill the memory..\n"); @@ -447,19 +447,19 @@ int init_sdram (void) serial_puts ("enable ECC\n"); #endif udelay (400); - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); tmp |= 0x00800000; /* enable bank 0 */ - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } else #endif { /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); udelay (400); } serial_puts ("\n"); @@ -631,14 +631,14 @@ phys_size_t initdram (int board_type) ds = 0; /* since the DRAM controller is allready set up, calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -648,8 +648,8 @@ phys_size_t initdram (int board_type) } else ds = 1; } - mtdcr (memcfga, mem_ecccf); - tmp = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_ecccf); + tmp = mfdcr (SDRAM0_CFGDATA); if (!tmp) printf ("No "); @@ -687,7 +687,7 @@ int misc_init_r (void) rtc_get (&tm); start=get_timer(0); /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 61f37d74f2a..18e8b09dde3 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -54,7 +54,7 @@ .globl ext_bus_cntlr_init ext_bus_cntlr_init: mflr r4 /* save link register */ - mfdcr r3,strap /* get strapping reg */ + mfdcr r3,CPC0_PSR /* get strapping reg */ andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ bnelr /* jump back if PCI boot */ @@ -83,9 +83,9 @@ /*----------------------------------------------------------------------- * decide boot up mode *----------------------------------------------------------------------- */ - addi r4,0,pb0cr - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA andi. r0, r4, 0x2000 /* mask out irrelevant bits */ beq 0f /* jump if 8 bit bus width */ @@ -95,18 +95,18 @@ * Memory Bank 0 (16 Bit Flash) initialization *---------------------------------------------------------------------- */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(FLASH_AP_B)@h ori r4,r4,(FLASH_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(FLASH_CR_B)@h ori r4,r4,(FLASH_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 b 1f 0: @@ -115,65 +115,65 @@ * Memory Bank 0 Multi Purpose Socket initialization *----------------------------------------------------------------------- */ /* 0x7F8FFE80 slowest boot */ - addi r4,0,pb0ap - mtdcr ebccfga,r4 + addi r4,0,PB1AP + mtdcr EBC0_CFGADDR,r4 addis r4,0,(MPS_AP_B)@h ori r4,r4,(MPS_AP_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb0cr - mtdcr ebccfga,r4 + addi r4,0,PB0CR + mtdcr EBC0_CFGADDR,r4 /* BS=0x010(4MB),BU=0x3(R/W), */ addis r4,0,(MPS_CR_B)@h ori r4,r4,(MPS_CR_B)@l - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 1: /*----------------------------------------------------------------------- * Memory Bank 2-3-4-5-6 (not used) initialization *-----------------------------------------------------------------------*/ - addi r4,0,pb1cr - mtdcr ebccfga,r4 + addi r4,0,PB1CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb2cr - mtdcr ebccfga,r4 + addi r4,0,PB2CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb3cr - mtdcr ebccfga,r4 + addi r4,0,PB3CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb4cr - mtdcr ebccfga,r4 + addi r4,0,PB4CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb5cr - mtdcr ebccfga,r4 + addi r4,0,PB5CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb6cr - mtdcr ebccfga,r4 + addi r4,0,PB6CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - addi r4,0,pb7cr - mtdcr ebccfga,r4 + addi r4,0,PB7CR + mtdcr EBC0_CFGADDR,r4 addis r4,0,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 nop /* pass2 DCR errata #8 */ blr diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c index 677437d09ea..e00d1d08f5c 100644 --- a/board/mpl/pip405/pip405.c +++ b/board/mpl/pip405/pip405.c @@ -193,10 +193,10 @@ int board_early_init_f (void) unsigned char cal_index, cal_val, spd_version, spd_chksum; unsigned char buf[8]; /* set up the config port */ - mtdcr (ebccfga, pb7ap); - mtdcr (ebccfgd, CONFIG_PORT_AP); - mtdcr (ebccfga, pb7cr); - mtdcr (ebccfgd, CONFIG_PORT_CR); + mtdcr (EBC0_CFGADDR, PB7AP); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_AP); + mtdcr (EBC0_CFGADDR, PB7CR); + mtdcr (EBC0_CFGDATA, CONFIG_PORT_CR); memclk = get_bus_freq (tmemclk); tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ @@ -361,8 +361,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); /* get SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - tmp = mfdcr (memcfgd) & ~0x018FC01F; + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F; /* insert CASL value */ /* tmp |= ((unsigned long)cal_val) << 23; */ tmp |= ((unsigned long) cal_val) << 23; @@ -385,8 +385,8 @@ int board_early_init_f (void) #endif /* write SDRAM timing register */ - mtdcr (memcfga, mem_sdtr1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + mtdcr (SDRAM0_CFGDATA, tmp); baseaddr = CONFIG_SYS_SDRAM_BASE; bank_size = (((unsigned long) density) << 22) / 2; /* insert AM value */ @@ -418,8 +418,8 @@ int board_early_init_f (void) SDRAM_err ("unsupported SDRAM"); } /* endswitch */ /* get SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); #ifdef SDRAM_DEBUG serial_puts ("bank0: baseaddr: "); @@ -434,12 +434,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 0 register */ - mtdcr (memcfga, mem_mb0cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; sdram_size = 0; #ifdef SDRAM_DEBUG @@ -459,12 +459,12 @@ int board_early_init_f (void) serial_puts ("\n"); #endif /* write SDRAM bank 1 register */ - mtdcr (memcfga, mem_mb1cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; bank |= (baseaddr | tmp | 0x01); @@ -482,12 +482,12 @@ int board_early_init_f (void) sdram_size += bank_size; /* write SDRAM bank 2 register */ - mtdcr (memcfga, mem_mb2cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - bank = mfdcr (memcfgd) & ~0xFFCEE001; + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001; #ifdef SDRAM_DEBUG serial_puts ("bank3: baseaddr: "); @@ -509,13 +509,13 @@ int board_early_init_f (void) #endif /* write SDRAM bank 3 register */ - mtdcr (memcfga, mem_mb3cf); - mtdcr (memcfgd, bank); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + mtdcr (SDRAM0_CFGDATA, bank); /* get SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - tmp = mfdcr (memcfgd) & ~0x3FF80000; + mtdcr (SDRAM0_CFGADDR, mem_rtr); + tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000; if (tmemclk < NSto10PS (16)) tmp |= 0x05F00000; @@ -523,14 +523,14 @@ int board_early_init_f (void) tmp |= 0x03F80000; /* write SDRAM refresh interval register */ - mtdcr (memcfga, mem_rtr); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + mtdcr (SDRAM0_CFGDATA, tmp); /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ - mtdcr (memcfga, mem_mcopt1); - tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; - mtdcr (memcfga, mem_mcopt1); - mtdcr (memcfgd, tmp); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80E00000; + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + mtdcr (SDRAM0_CFGDATA, tmp); /*-------------------------------------------------------------------------+ @@ -619,14 +619,14 @@ phys_size_t initdram (int board_type) /* since the DRAM controller is allready set up, * calculate the size with the bank registers */ - mtdcr (memcfga, mem_mb0cf); - bank_reg[0] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb1cf); - bank_reg[1] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb2cf); - bank_reg[2] = mfdcr (memcfgd); - mtdcr (memcfga, mem_mb3cf); - bank_reg[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + bank_reg[0] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + bank_reg[1] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + bank_reg[2] = mfdcr (SDRAM0_CFGDATA); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + bank_reg[3] = mfdcr (SDRAM0_CFGDATA); TotalSize = 0; for (i = 0; i < 4; i++) { if ((bank_reg[i] & 0x1) == 0x1) { @@ -668,7 +668,7 @@ int misc_init_r (void) gd->bd->bi_flashoffset=0; /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ - if (mfdcr(strap) & PSR_ROM_LOC) + if (mfdcr(CPC0_PSR) & PSR_ROM_LOC) mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80)); return (0); diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index aa8a0975cf0..40bec8edcc5 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -92,7 +92,7 @@ int checkboard (void) u16 index = boardVersReg & 0x0f; /* Cannot be done in board_early_init */ - mtdcr(cntrl0, CPC0_CR0_VALUE); + mtdcr(CPC0_CR0, CPC0_CR0_VALUE); /* Force /RTS to active. The board it not wired quite * correctly to use cts/rtc flow control, so just force the diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 5eb33d37fac..836c0346da3 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -94,8 +94,8 @@ int board_early_init_f(void) } mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/ #endif - mtdcr(ebccfga, xbcfg); - mtdcr(ebccfgd, 0xb8400000); + mtdcr(EBC0_CFGADDR, EBC0_CFG); + mtdcr(EBC0_CFGDATA, 0xb8400000); /* * Setup the GPIO pins @@ -152,8 +152,8 @@ int board_early_init_f(void) mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ mtdcr(uic2sr, 0xffffffff); /* clear all */ - mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */ - mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */ + mtsdr(SDR0_PFC0, 0x00003E00); /* Pin function: */ + mtsdr(SDR0_PFC1, 0x00848000); /* Pin function: UART0 has 4 pins */ /* setup BOOT FLASH */ mtsdr(SDR0_CUST0, 0xC0082350); @@ -324,7 +324,7 @@ int board_with_pci(void) { u32 reg; - mfsdr(sdr_pci0, reg); + mfsdr(SDR0_PCI0, reg); return (reg & SDR0_XCR_PAE_MASK); } @@ -350,28 +350,28 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */ + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); /* Sequoia */ + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting * PLB0_ACR[WRP] = 0. */ - mtdcr(plb0_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ - mtdcr(plb1_acr, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); } diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 5c2ec356397..0546cd726d1 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -89,11 +89,11 @@ static int wait_for_dlllock(void) /* -----------------------------------------------------------+ * Wait for the DCC master delay line to finish calibration * ----------------------------------------------------------*/ - mtdcr(memcfga, DDR0_17); + mtdcr(SDRAM0_CFGADDR, DDR0_17); val = DDR0_17_DLLLOCKREG_UNLOCKED; while (wait != 0xffff) { - val = mfdcr(memcfgd); + val = mfdcr(SDRAM0_CFGDATA); if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) /* dlllockreg bit on */ diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index 67c1b0bbeac..9054282c94d 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -71,8 +71,8 @@ int board_early_init_f (void) mtdcr(uictr, 0x00000000); /* set int trigger levels */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(cntrl1, CPC0_CR1_VALUE); - mtdcr(ecr, 0x60606000); + mtdcr(CPC0_CR1, CPC0_CR1_VALUE); + mtdcr(CPC0_ECR, 0x60606000); mtdcr(CPC0_EIRR, 0x7C000000); out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR ); out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); @@ -103,7 +103,7 @@ int checkboard (void) u16 index = boardVersReg & 0xf0; /* Cannot be done in board_early_init */ - mtdcr(cntrl0, CPC0_CR0_VALUE); + mtdcr(CPC0_CR0, CPC0_CR0_VALUE); /* Force /RTS to active. The board it not wired quite * correctly to use cts/rtc flow control, so just force the diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 47d6391469a..f966d02f107 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -143,9 +143,9 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * GPIO's are alreay setup in cpu/ppc4xx/cpu_init.c @@ -174,10 +174,10 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup other serial configuration *-------------------------------------------------------------------*/ - mfsdr(sdr_pci0, reg); - mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */ - mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */ - mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ + mfsdr(SDR0_PCI0, reg); + mtsdr(SDR0_PCI0, 0x80000000 | reg); /* PCI arbiter enabled */ + mtsdr(SDR0_PFC0, 0x00000000); /* Pin function: enable GPIO49-63 */ + mtsdr(SDR0_PFC1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */ return 0; } @@ -444,8 +444,8 @@ int misc_init_r (void) load_ethaddr(); /* Re-do sizing to get full correct info */ - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -473,8 +473,8 @@ int misc_init_r (void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtdcr(ebccfga, pb0cr); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGADDR, PB0CR); + mtdcr(EBC0_CFGDATA, pbcr); /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; @@ -571,35 +571,35 @@ int pci_pre_init(struct pci_controller *hose) | Set priority for all PLB3 devices to 0. | Set PLB3 arbiter to fair mode. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp1, addr); - mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb3_acr); - mtdcr(plb3_acr, addr | 0x80000000); + mfsdr(SD0_AMP1, addr); + mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3_ACR); + mtdcr(PLB3_ACR, addr | 0x80000000); /*-------------------------------------------------------------------------+ | Set priority for all PLB4 devices to 0. +-------------------------------------------------------------------------*/ - mfsdr(sdr_amp0, addr); - mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ - mtdcr(plb4_acr, addr); + mfsdr(SD0_AMP0, addr); + mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4_ACR, addr); /*-------------------------------------------------------------------------+ | Set Nebula PLB4 arbiter to fair mode. +-------------------------------------------------------------------------*/ /* Segment0 */ - addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; - addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; - addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; - addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; - mtdcr(plb0_acr, addr); + addr = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; + addr = (addr & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; + addr = (addr & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; + addr = (addr & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; + mtdcr(PLB0_ACR, addr); /* Segment1 */ - addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; - addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; - addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; - addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; - mtdcr(plb1_acr, addr); + addr = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; + addr = (addr & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; + addr = (addr & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; + addr = (addr & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; + mtdcr(PLB1_ACR, addr); return 1; } diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index dc3431961f4..be79b42bd04 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -39,7 +39,7 @@ int board_early_init_f (void) /*------------------------------------------------------------------------- * Initialize EBC CONFIG *-------------------------------------------------------------------------*/ - mtebc(xbcfg, EBC_CFG_LE_UNLOCK | + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT | @@ -96,7 +96,7 @@ int board_early_init_f (void) out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY)); /* Setup GPIO/IRQ multiplexing */ - mtsdr(sdr_pfc0, 0x01a33e00); + mtsdr(SDR0_PFC0, 0x01a33e00); return 0; } @@ -165,7 +165,7 @@ int pci_pre_init(struct pci_controller * hose ) * The ocotea board is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 1a0486f5c0c..18054e45b6e 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -85,14 +85,14 @@ int board_early_init_f(void) /*-------------------------------------------------------------------- * Setup the external bus controller/chip selects *-------------------------------------------------------------------*/ - mtdcr(ebccfga, xbcfg); - reg = mfdcr(ebccfgd); - mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */ + mtdcr(EBC0_CFGADDR, EBC0_CFG); + reg = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ /*-------------------------------------------------------------------- * Setup pin multiplexing (GPIO/IRQ...) *-------------------------------------------------------------------*/ - mtdcr(cpc0_gpio, 0x03F01F80); + mtdcr(CPC0_GPIO, 0x03F01F80); out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN); @@ -153,12 +153,12 @@ int misc_init_r (void) * Check if only one FLASH bank is available */ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { - mtebc(pb1cr, 0); /* disable cs */ - mtebc(pb1ap, 0); - mtebc(pb2cr, 0); /* disable cs */ - mtebc(pb2ap, 0); - mtebc(pb3cr, 0); /* disable cs */ - mtebc(pb3ap, 0); + mtebc(PB1CR, 0); /* disable cs */ + mtebc(PB1AP, 0); + mtebc(PB2CR, 0); /* disable cs */ + mtebc(PB2AP, 0); + mtebc(PB3CR, 0); /* disable cs */ + mtebc(PB3AP, 0); } return 0; @@ -185,7 +185,7 @@ int pci_pre_init(struct pci_controller *hose) * The P3P440 board is always configured as the host & requires the * PCI arbiter to be disabled because it's an PMC module. *--------------------------------------------------------------------------*/ - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if (strap & 0x00100000) { printf("PCI: CPC0_STRP1[PAE] set.\n"); return 0; diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index b8160c8427d..d8b0564b3be 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -322,7 +322,7 @@ int pci_pre_init(struct pci_controller * hose ) * The metrobox is always configured as the host & requires the * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){ printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); return 0; diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c index 92f52475652..b80c2069400 100644 --- a/board/sandburst/karef/karef.c +++ b/board/sandburst/karef/karef.c @@ -67,7 +67,7 @@ int board_early_init_f (void) ppc440_gpio_regs_t *gpio_regs; /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); + mtsdr(SDR0_PFC0, 0x00103E00); /* Setup access for LEDs, and system topology info */ gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; @@ -80,7 +80,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------*/ - mtebc(xbcfg, + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | @@ -90,7 +90,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | 1/2 MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------*/ - mtebc(pb0ap, + mtebc(PB0AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -98,12 +98,12 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------*/ - mtebc(pb1ap, + mtebc(PB1AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -111,13 +111,13 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb2ap, + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -125,40 +125,40 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | KaRef Scan FPGA. Initialize bank 3 with default values. +-------------------------------------------------------------------*/ - mtebc(pb5ap, + mtebc(PB5AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48200000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | MAC A & B for Kamino. OFEM FPGA decodes the addresses | Initialize bank 4 with default values. +-------------------------------------------------------------------*/ - mtebc(pb4ap, + mtebc(PB4AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | OFEM FPGA Initialize bank 5 with default values. +-------------------------------------------------------------------*/ - mtebc(pb3ap, + mtebc(PB3AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | @@ -166,14 +166,14 @@ int board_early_init_f (void) EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48400000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb6ap, + mtebc(PB6AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -181,20 +181,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | BME-32. Initialize bank 7 with default values. +-------------------------------------------------------------------*/ - mtebc(pb7ap, + mtebc(PB7AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c index 27d7f74088b..ad3f9bc28e1 100644 --- a/board/sandburst/metrobox/metrobox.c +++ b/board/sandburst/metrobox/metrobox.c @@ -57,7 +57,7 @@ int board_early_init_f (void) ppc440_gpio_regs_t *gpio_regs; /* Enable GPIO interrupts */ - mtsdr(sdr_pfc0, 0x00103E00); + mtsdr(SDR0_PFC0, 0x00103E00); /* Setup access for LEDs, and system topology info */ gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE; @@ -70,7 +70,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | Initialize EBC CONFIG +-------------------------------------------------------------------*/ - mtebc(xbcfg, + mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS | @@ -80,7 +80,7 @@ int board_early_init_f (void) /*--------------------------------------------------------------------+ | 1/2 MB FLASH. Initialize bank 0 with default values. +-------------------------------------------------------------------*/ - mtebc(pb0ap, + mtebc(PB0AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -88,12 +88,12 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | + mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | 8KB NVRAM/RTC. Initialize bank 1 with default values. +-------------------------------------------------------------------*/ - mtebc(pb1ap, + mtebc(PB1AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -101,13 +101,13 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) | + mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb2ap, + mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -115,20 +115,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) | + mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0xF0000000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | OPTO & OFEM FPGA. Initialize bank 3 with default values. +-------------------------------------------------------------------*/ - mtebc(pb3ap, + mtebc(PB3AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48200000) | + mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48200000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ @@ -136,34 +136,34 @@ int board_early_init_f (void) | MAC A & B for Kamino. OFEM FPGA decodes the addresses | Initialize bank 4 with default values. +-------------------------------------------------------------------*/ - mtebc(pb4ap, + mtebc(PB4AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) | + mtebc(PB4CR, EBC_BXCR_BAS_ENCODE(0x48600000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Metrobox MAC B Initialize bank 5 with default values. | KA REF FPGA Initialize bank 5 with default values. +-------------------------------------------------------------------*/ - mtebc(pb5ap, + mtebc(PB5AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48700000) | + mtebc(PB5CR, EBC_BXCR_BAS_ENCODE(0x48700000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ | Compact Flash, uses 2 Chip Selects (2 & 6) +-------------------------------------------------------------------*/ - mtebc(pb6ap, + mtebc(PB6AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) | EBC_BXAP_BCE_DISABLE | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) | @@ -171,20 +171,20 @@ int board_early_init_f (void) EBC_BXAP_RE_DISABLED | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); - mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) | + mtebc(PB6CR, EBC_BXCR_BAS_ENCODE(0xF0100000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT); /*--------------------------------------------------------------------+ | BME-32. Initialize bank 7 with default values. +-------------------------------------------------------------------*/ - mtebc(pb7ap, + mtebc(PB7AP, EBC_BXAP_RE_ENABLED | EBC_BXAP_SOR_NONDELAYED | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(3) | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED | EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW); - mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) | + mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48500000) | EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT); /*--------------------------------------------------------------------+ diff --git a/board/sbc405/sbc405.c b/board/sbc405/sbc405.c index 7818cd7e555..66842eaf4da 100644 --- a/board/sbc405/sbc405.c +++ b/board/sbc405/sbc405.c @@ -52,7 +52,7 @@ int board_early_init_f (void) /* * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us */ - mtebc (epcr, 0xa8400000); + mtebc (EBC0_CFG, 0xa8400000); return 0; } diff --git a/board/sc3/init.S b/board/sc3/init.S index f97a5ea6104..6052c665534 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -58,7 +58,7 @@ ext_bus_cntlr_init: * We need the current boot up configuration to set correct * timings into internal flash and external flash */ - mfdcr r24,strap /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx + mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx 0 0 -> 8 bit external ROM 0 1 -> 16 bit internal ROM */ addi r4,0,2 @@ -113,8 +113,8 @@ ext_bus_cntlr_init: * We only have to change the timing. Mapping is ok by boot-strapping *----------------------------------------------------------------------- */ - li r4,pb0ap /* PB0AP=Peripheral Bank 0 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 mr r4,r26 /* assume internal fast flash is boot flash */ cmpwi r24,0x2000 /* assumption true? ... */ @@ -122,27 +122,27 @@ ext_bus_cntlr_init: mr r4,r25 /* ...no, use the slow variant */ mr r25,r26 /* use this for the other flash */ 1: - mtdcr ebccfgd,r4 /* change timing now */ + mtdcr EBC0_CFGDATA,r4 /* change timing now */ - li r4,pb0cr /* PB0CR=Peripheral Bank 0 Control Register */ - mtdcr ebccfga,r4 - mfdcr r4,ebccfgd + li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */ + mtdcr EBC0_CFGADDR,r4 + mfdcr r4,EBC0_CFGDATA lis r3,0x0001 ori r3,r3,0x8000 /* allow reads and writes */ or r4,r4,r3 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- * Memory Bank 3 (Second-Flash) initialization * 0xF0000000...0xF01FFFFF -> 2MB *----------------------------------------------------------------------- */ - li r4,pb3ap /* Peripheral Bank 1 Access Parameter */ - mtdcr ebccfga,r4 - mtdcr ebccfgd,r2 /* change timing */ + li r4,PB3AP /* Peripheral Bank 1 Access Parameter */ + mtdcr EBC0_CFGADDR,r4 + mtdcr EBC0_CFGDATA,r2 /* change timing */ - li r4,pb3cr /* Peripheral Bank 1 Configuration Registers */ - mtdcr ebccfga,r4 + li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */ + mtdcr EBC0_CFGADDR,r4 lis r4,0xF003 ori r4,r4,0x8000 @@ -151,7 +151,7 @@ ext_bus_cntlr_init: */ xori r24,r24,0x2000 /* invert current bus width */ or r4,r4,r24 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /*----------------------------------------------------------------------- * Memory Bank 1 (NAND-Flash) initialization @@ -169,28 +169,28 @@ ext_bus_cntlr_init: * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) *----------------------------------------------------------------------- */ - li r4,pb1ap /* Peripheral Bank 1 Access Parameter */ - mtdcr ebccfga,r4 + li r4,PB1AP /* Peripheral Bank 1 Access Parameter */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x0000 ori r4,r4,0x0200 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb1cr /* Peripheral Bank 1 Configuration Registers */ - mtdcr ebccfga,r4 + li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x77D1 ori r4,r4,0x8000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* USB init (without acceleration) */ #ifndef CONFIG_ISP1161_PRESENT - li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x0180 ori r4,r4,0x5940 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /*----------------------------------------------------------------------- @@ -204,8 +204,8 @@ ext_bus_cntlr_init: A7/A24=0 -> memory cycle A7/ /A24=1 -> I/O cycle */ - li r4,pb2ap /* PB2AP=Peripheral Bank 2 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 /* We emulate an ISA access @@ -226,58 +226,58 @@ ext_bus_cntlr_init: lis r4,0x0100 ori r4,r4,0x0340 #endif - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #ifdef IDE_USES_ISA_EMULATION - li r25,pb5ap /* PB5AP=Peripheral Bank 5 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 + li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 #endif - li r25,pb6ap /* PB6AP=Peripheral Bank 6 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 - li r25,pb7ap /* PB7AP=Peripheral Bank 7 Access Parameters */ - mtdcr ebccfga,r25 - mtdcr ebccfgd,r4 + li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 + li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */ + mtdcr EBC0_CFGADDR,r25 + mtdcr EBC0_CFGDATA,r4 - li r25,pb2cr /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x780B ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* * the other areas are only 1MiB in size */ lis r4,0x7401 ori r4,r4,0xA000 - li r25,pb6cr /* PB6CR=Peripheral Bank 6 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7401 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r25,pb7cr /* PB7CR=Peripheral Bank 7 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7411 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #ifndef CONFIG_ISP1161_PRESENT - li r25,pb4cr /* PB4CR=Peripheral Bank 4 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x7421 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif #ifdef IDE_USES_ISA_EMULATION - li r25,pb5cr /* PB5CR=Peripheral Bank 5 Configuration Register */ - mtdcr ebccfga,r25 + li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */ + mtdcr EBC0_CFGADDR,r25 lis r4,0x0000 ori r4,r4,0x0000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /*----------------------------------------------------------------------- @@ -315,19 +315,19 @@ ext_bus_cntlr_init: #ifdef CONFIG_ISP1161_PRESENT - li r4,pb4ap /* PB4AP=Peripheral Bank 4 Access Parameters */ - mtdcr ebccfga,r4 + li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x030D ori r4,r4,0x5E80 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb4cr /* PB2CR=Peripheral Bank 4 Configuration Register */ - mtdcr ebccfga,r4 + li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x77C1 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif @@ -352,28 +352,28 @@ ext_bus_cntlr_init: * *----------------------------------------------------------------------- */ - li r4,pb5ap - mtdcr ebccfga,r4 + li r4,PB5AP + mtdcr EBC0_CFGADDR,r4 lis r4,0x040C ori r4,r4,0x0200 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 - li r4,pb5cr /* PB2CR=Peripheral Bank 2 Configuration Register */ - mtdcr ebccfga,r4 + li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */ + mtdcr EBC0_CFGADDR,r4 lis r4,0x7A01 ori r4,r4,0xA000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 #endif /* * External Peripheral Control Register */ - li r4,epcr - mtdcr ebccfga,r4 + li r4,EBC0_CFG + mtdcr EBC0_CFGADDR,r4 lis r4,0xB84E ori r4,r4,0xF000 - mtdcr ebccfgd,r4 + mtdcr EBC0_CFGDATA,r4 /* * drive POST code */ diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 6c82fe7e992..5ae7b1244a7 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -199,14 +199,14 @@ int board_start_ide(void) static int sc3_cameron_init (void) { /* Set up the Memory Controller for the CAMERON version */ - mtebc (pb4ap, 0x01805940); - mtebc (pb4cr, 0x7401a000); - mtebc (pb5ap, 0x01805940); - mtebc (pb5cr, 0x7401a000); - mtebc (pb6ap, 0x0); - mtebc (pb6cr, 0x0); - mtebc (pb7ap, 0x0); - mtebc (pb7cr, 0x0); + mtebc (PB4AP, 0x01805940); + mtebc (PB4CR, 0x7401a000); + mtebc (PB5AP, 0x01805940); + mtebc (PB5CR, 0x7401a000); + mtebc (PB6AP, 0x0); + mtebc (PB6CR, 0x0); + mtebc (PB7AP, 0x0); + mtebc (PB7CR, 0x0); return 0; } @@ -312,18 +312,18 @@ int board_early_init_f (void) mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ /* setup other implementation specific details */ - mtdcr (ecr, 0x60606000); + mtdcr (CPC0_ECR, 0x60606000); - mtdcr (cntrl1, 0x000042C0); + mtdcr (CPC0_CR1, 0x000042C0); if (IS_CAMERON) { - mtdcr (cntrl0, 0x01380000); + mtdcr (CPC0_CR0, 0x01380000); /* Setup the GPIOs */ writel (0x08008000, 0xEF600700); /* Output states */ writel (0x00000000, 0xEF600718); /* Open Drain control */ writel (0x68098000, 0xEF600704); /* Output control */ } else { - mtdcr (cntrl0,0x00080000); + mtdcr (CPC0_CR0,0x00080000); /* Setup the GPIOs */ writel (0x08000000, 0xEF600700); /* Output states */ writel (0x14000000, 0xEF600718); /* Open Drain control */ @@ -331,13 +331,13 @@ int board_early_init_f (void) } /* Code decompression disabled */ - mtdcr (kiar, kconf); - mtdcr (kidr, 0x2B); + mtdcr (KIAR, KCONF); + mtdcr (KIDR, 0x2B); /* CPC0_ER: enable sleep mode of (currently) unused components */ /* CPC0_FR: force unused components into sleep mode */ - mtdcr (cpmer, 0x3F800000); - mtdcr (cpmfr, 0x14000000); + mtdcr (CPMER, 0x3F800000); + mtdcr (CPMFR, 0x14000000); /* set PLB priority */ mtdcr (0x87, 0x08000000); @@ -472,19 +472,19 @@ static void printCSConfig(int reg,unsigned long ap,unsigned long cr) #ifdef SC3_DEBUGOUT -static unsigned int ap[] = {pb0ap, pb1ap, pb2ap, pb3ap, pb4ap, - pb5ap, pb6ap, pb7ap}; -static unsigned int cr[] = {pb0cr, pb1cr, pb2cr, pb3cr, pb4cr, - pb5cr, pb6cr, pb7cr}; +static unsigned int ap[] = {PB0AP, PB1AP, PB2AP, PB3AP, PB4AP, + PB5AP, PB6AP, PB7AP}; +static unsigned int cr[] = {PB0CR, PB1CR, PB2CR, PB3CR, PB4CR, + PB5CR, PB6CR, PB7CR}; static int show_reg (int nr) { unsigned long ul1, ul2; - mtdcr (ebccfga, ap[nr]); - ul1 = mfdcr (ebccfgd); - mtdcr (ebccfga, cr[nr]); - ul2 = mfdcr(ebccfgd); + mtdcr (EBC0_CFGADDR, ap[nr]); + ul1 = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, cr[nr]); + ul2 = mfdcr(EBC0_CFGDATA); printCSConfig(nr, ul1, ul2); return 0; } @@ -500,8 +500,8 @@ int checkboard (void) show_reg (i); } - mtdcr (ebccfga, epcr); - ul1 = mfdcr (ebccfgd); + mtdcr (EBC0_CFGADDR, EBC0_CFG); + ul1 = mfdcr (EBC0_CFGDATA); puts ("\nGeneral configuration:\n"); @@ -591,21 +591,21 @@ phys_size_t initdram (int board_type) puts("\nSDRAM configuration:\n"); - mtdcr (memcfga, mem_mcopt1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mcopt1); + ul1 = mfdcr(SDRAM0_CFGDATA); if (!(ul1 & 0x80000000)) { puts(" Controller disabled\n"); return 0; } for (i = 0; i < 4; i++) { - mtdcr (memcfga, mbcf[i]); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mbcf[i]); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (i, ul1); } - mtdcr (memcfga, mem_sdtr1); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_sdtr1); + ul1 = mfdcr(SDRAM0_CFGDATA); printf ("Timing:\n -CAS latency %lu\n", ((ul1 & 0x1800000) >> 23)+1); printf (" -Precharge %lu (PTA) \n", ((ul1 & 0xC0000) >> 18) + 1); @@ -614,15 +614,15 @@ phys_size_t initdram (int board_type) printf (" -CAS to RAS %lu\n", ((ul1 & 0x1C) >> 2) + 4); printf (" -RAS to CAS %lu\n", ((ul1 & 0x3) + 1)); puts ("Misc:\n"); - mtdcr (memcfga, mem_rtr); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_rtr); + ul1 = mfdcr(SDRAM0_CFGDATA); printf (" -Refresh rate: %luns\n", (ul1 >> 16) * 7); - mtdcr(memcfga,mem_pmit); - ul2=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_pmit); + ul2=mfdcr(SDRAM0_CFGDATA); - mtdcr(memcfga,mem_mcopt1); - ul1=mfdcr(memcfgd); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); + ul1=mfdcr(SDRAM0_CFGDATA); if (ul1 & 0x20000000) printf(" -Power Down after: %luns\n", @@ -658,8 +658,8 @@ phys_size_t initdram (int board_type) else puts(" -Memory lines only at write cycles active outputs\n"); - mtdcr (memcfga, mem_status); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_status); + ul1 = mfdcr (SDRAM0_CFGDATA); if (ul1 & 0x80000000) puts(" -SDRAM Controller ready\n"); else @@ -670,20 +670,20 @@ phys_size_t initdram (int board_type) return (mems * 1024 * 1024); #else - mtdcr (memcfga, mem_mb0cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems = printSDRAMConfig (0, ul1); - mtdcr (memcfga, mem_mb1cf); - ul1 = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); + ul1 = mfdcr (SDRAM0_CFGDATA); mems += printSDRAMConfig (1, ul1); - mtdcr (memcfga, mem_mb2cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (2, ul1); - mtdcr (memcfga, mem_mb3cf); - ul1 = mfdcr(memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); + ul1 = mfdcr(SDRAM0_CFGDATA); mems += printSDRAMConfig (3, ul1); return (mems * 1024 * 1024); diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c index 9e276a104a3..a26a67900be 100644 --- a/board/snmc/qs850/flash.c +++ b/board/snmc/qs850/flash.c @@ -104,21 +104,21 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c index 2cb8dcb9d80..48c2258b3f6 100644 --- a/board/snmc/qs860t/flash.c +++ b/board/snmc/qs860t/flash.c @@ -102,21 +102,21 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr(ebccfga, pb0cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb0cr); + mtdcr(EBC0_CFGADDR, PB0CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } if (size_b0) { - mtdcr(ebccfga, pb1cr); - pbcr = mfdcr(ebccfgd); - mtdcr(ebccfga, pb1cr); + mtdcr(EBC0_CFGADDR, PB1CR); + pbcr = mfdcr(EBC0_CFGDATA); + mtdcr(EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17); - mtdcr(ebccfgd, pbcr); + mtdcr(EBC0_CFGDATA, pbcr); } size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]); diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c index 933d5ecc87e..15546421a8f 100644 --- a/board/tb0229/flash.c +++ b/board/tb0229/flash.c @@ -108,25 +108,25 @@ unsigned long flash_init (void) /* Re-do sizing to get full correct info */ if (size_b1) { - mtdcr (ebccfga, pb0cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb0cr); + mtdcr (EBC0_CFGADDR, PB0CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB0CR); base_b1 = -size_b1; pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb1cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB1CR = %x\n", pbcr); */ } if (size_b0) { - mtdcr (ebccfga, pb1cr); - pbcr = mfdcr (ebccfgd); - mtdcr (ebccfga, pb1cr); + mtdcr (EBC0_CFGADDR, PB1CR); + pbcr = mfdcr (EBC0_CFGDATA); + mtdcr (EBC0_CFGADDR, PB1CR); base_b0 = base_b1 - size_b0; pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0 / 1024 / 1024) - 1) << 17); - mtdcr (ebccfgd, pbcr); - /* printf("pb0cr = %x\n", pbcr); */ + mtdcr (EBC0_CFGDATA, pbcr); + /* printf("PB0CR = %x\n", pbcr); */ } size_b0 = diff --git a/board/w7o/init.S b/board/w7o/init.S index 902c6311374..090b07a1e62 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -87,48 +87,48 @@ ext_bus_cntlr_init: /******************************************************************** * Setup External Bus Controller (EBC). *******************************************************************/ - addi r3, 0, epcr - mtdcr ebccfga, r3 + addi r3, 0, EBC0_CFG + mtdcr EBC0_CFGADDR, r3 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ ori r4, r4, 0x0 /* Drive CS with external master */ - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /******************************************************************** * Change PCIINT signal to PerWE *******************************************************************/ - mfdcr r4, cntrl1 + mfdcr r4, CPC0_CR1 ori r4, r4, 0x4000 - mtdcr cntrl1, r4 + mtdcr CPC0_CR1, r4 /******************************************************************** * Memory Bank 0 (Flash Bank 0) initialization *******************************************************************/ - addi r3, 0, pb0ap - mtdcr ebccfga, r3 + addi r3, 0, PB1AP + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 - addi r3, 0, pb0cr - mtdcr ebccfga, r3 + addi r3, 0, PB0CR + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /******************************************************************** * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. *******************************************************************/ - addi r3, 0, pb7ap - mtdcr ebccfga, r3 + addi r3, 0, PB7AP + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 - addi r3, 0, pb7cr - mtdcr ebccfga, r3 + addi r3, 0, PB7CR + mtdcr EBC0_CFGADDR, r3 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /* We are all done */ mtlr r0 /* Restore link register */ @@ -183,35 +183,35 @@ sdram_init: * values to be changed. */ addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ addi r3, 0, mem_mb0cf - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ addi r4, 0, 0 /* Zero the data reg */ addi r3, r3, 4 /* Point to MB1CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ addi r3, r3, 4 /* Point to MB2CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ addi r3, r3, 4 /* Point to MB3CF reg */ - mtdcr memcfga, r3 /* Set the address */ - mtdcr memcfgd, r4 /* Zero the reg */ + mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ + mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ /******************************************************************** * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. @@ -223,18 +223,18 @@ sdram_init: * Set up SDTR1 */ addi r3, 0, mem_sdtr1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /* * Set RTR */ addi r3, 0, mem_rtr - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ - mtdcr memcfgd, r4 + mtdcr SDRAM0_CFGDATA, r4 /******************************************************************** * Delay to ensure 200usec have elapsed since reset. Assume worst @@ -251,10 +251,10 @@ sdram_init: * Set memory controller options reg, MCOPT1. *******************************************************************/ addi r3, 0, mem_mcopt1 - mtdcr memcfga, r3 + mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ - mtdcr memcfgd, r4 /* EMDULR=1 */ + mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */ ..sdri_done: /* restore and return */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 22cdfcd7d75..6479beeb13b 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -170,17 +170,17 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (memcfga, mem_mb0cf); /* get bank 0 config reg */ - regs[0] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb1cf); /* get bank 1 config reg */ - regs[1] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb2cf); /* get bank 2 config reg */ - regs[2] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (memcfga, mem_mb3cf); /* get bank 3 config reg */ - regs[3] = mfdcr (memcfgd); + mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ for (i = 0; i < 4; i++) { diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 4529b7eded8..58041fcd349 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -42,8 +42,8 @@ int board_early_init_f(void) * 23 = #LED_STATUS1 * 24 = #LED_STATUS2 */ - mfsdr(sdr_pfc0, sdrreg); - mtsdr(sdr_pfc0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); + mfsdr(SDR0_PFC0, sdrreg); + mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00); out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); LED0_OFF(); LED1_OFF(); @@ -51,14 +51,14 @@ int board_early_init_f(void) LED3_OFF(); /* Setup the external bus controller/chip selects */ - mtebc(pb0ap, 0x04055200); /* 16MB Strata FLASH */ - mtebc(pb0cr, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ - mtebc(pb1ap, 0x04055200); /* 512KB Socketed AMD FLASH */ - mtebc(pb1cr, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ - mtebc(pb6ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(pb6cr, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ - mtebc(pb7ap, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ - mtebc(pb7cr, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ + mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */ + mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */ + mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */ + mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */ + mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */ + mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */ + mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */ /* * Setup the interrupt controller polarities, triggers, etc. @@ -151,15 +151,15 @@ int pci_pre_init(struct pci_controller * hose) unsigned long strap; /* See if we're supposed to setup the pci */ - mfsdr(sdr_sdstp1, strap); + mfsdr(SDR0_SDSTP1, strap); if ((strap & 0x00010000) == 0) return 0; #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) /* Setup System Device Register PCIX0_XCR */ - mfsdr(sdr_xcr, strap); + mfsdr(SDR0_XCR, strap); strap &= 0x0f000000; - mtsdr(sdr_xcr, strap); + mtsdr(SDR0_XCR, strap); #endif return 1; diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index 9bc390f8379..fc9dfa02c01 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -61,7 +61,7 @@ int board_early_init_f(void) /* * Configure CPC0_PCI to enable PerWE as output */ - mtdcr(cpc0_pci, CPC0_PCI_SPE); + mtdcr(CPC0_PCI, CPC0_PCI_SPE); return 0; } @@ -107,7 +107,7 @@ int misc_init_r(void) /* Re-do sizing to get full correct info */ /* adjust flash start and offset */ - mfebc(pb0cr, pbcr); + mfebc(PB0CR, pbcr); switch (gd->bd->bi_flashsize) { case 1 << 20: size_val = 0; @@ -135,7 +135,7 @@ int misc_init_r(void) break; } pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); - mtebc(pb0cr, pbcr); + mtebc(PB0CR, pbcr); /* * Re-check to get correct base address diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index abb9941afbd..3ed15092ae9 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -108,72 +108,72 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); - mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_besra); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrsa); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_besrsb); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_bear); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); puts ("\n" "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb2cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb3cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_ecccf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_eccerr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" - "dmasr dmasgc dmaadr\n" + "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), - mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), - mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), + mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), + mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), - mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), + mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); puts ("\n" "External Bus\n" - "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); + mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); + mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n"); + mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n\n"); @@ -195,51 +195,51 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts ("\nMemory (SDRAM) Configuration\n" "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); - mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd)); - mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd)); + mtdcr(SDRAM0_CFGADDR,mem_mcopt1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_rtr); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_pmit); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb0cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_mb1cf); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); + mtdcr(SDRAM0_CFGADDR,mem_sdtr1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); printf ("\n\n" "DMA Channels\n" - "dmasr dmasgc dmaadr\n" "%08x %08x %08x\n" + "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr), - mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0), - mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1)); + mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), + mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), + mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); printf ( "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2), - mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) ); + mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), + mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); puts ("\n" "External Bus\n" - "pbear pbesr0 pbesr1 epcr\n"); - mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd)); + "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); + mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n"); - mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); + mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n" - "pb4cr pb4ap\n"); - mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd)); - mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd)); + "PB4CR PB4AP\n"); + mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); + mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); puts ("\n\n"); #elif defined(CONFIG_5xx) diff --git a/cpu/ppc4xx/40x_spd_sdram.c b/cpu/ppc4xx/40x_spd_sdram.c index 75bd70dc661..83fa709da2d 100644 --- a/cpu/ppc4xx/40x_spd_sdram.c +++ b/cpu/ppc4xx/40x_spd_sdram.c @@ -422,7 +422,7 @@ long int spd_sdram(int(read_spd)(uint addr)) * program all the registers. * -------------------------------------------------------------------*/ -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) +#define mtsdram0(reg, data) mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,data) /* disable memcontroller so updates work */ mtsdram0( mem_mcopt1, 0 ); diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index f26fcdaa1e9..c93f23a679f 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -192,8 +192,8 @@ long int spd_sdram(void) { /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif /* @@ -848,11 +848,11 @@ static int short_mem_test(void) 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}}; for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) { - mtdcr(memcfga, mem_b0cr + (bxcr_num << 2)); - if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bxcr_num << 2)); + if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) { /* Bank is enabled */ membase = (unsigned long*) - (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK); + (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK); /* * Run the short memory test @@ -1086,8 +1086,8 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, * Set the BxCR regs. First, wipe out the bank config registers. */ for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { - mtdcr(memcfga, mem_b0cr + (bx_cr_num << 2)); - mtdcr(memcfgd, 0x00000000); + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (bx_cr_num << 2)); + mtdcr(SDRAM0_CFGDATA, 0x00000000); bank_parms[bx_cr_num].bank_size_bytes = 0; } @@ -1232,12 +1232,12 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, /* Set the SDRAM0_BxCR regs thanks to sort tables */ for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) { if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) { - mtdcr(memcfga, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); - temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | + mtdcr(SDRAM0_CFGADDR, mem_b0cr + (sorted_bank_num[bx_cr_num] << 2)); + temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK | SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE); temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) | bank_parms[sorted_bank_num[bx_cr_num]].cr; - mtdcr(memcfgd, temp); + mtdcr(SDRAM0_CFGDATA, temp); bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes; debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp); } diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index 184cef5d114..e97f32c7b07 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -100,7 +100,7 @@ int __pci_pre_init(struct pci_controller *hose) * The arbiter is enabled in this place because of * compatibility reasons. */ - mtdcr(cpc0_pci, mfdcr(cpc0_pci) | CPC0_PCI_ARBIT_EN); + mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); #endif /* CONFIG_405EP */ return 1; @@ -118,10 +118,10 @@ ushort pmc405_pci_subsys_deviceid(void); int __is_pci_host(struct pci_controller *hose) { #if defined(CONFIG_405GP) - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) return 1; #elif defined (CONFIG_405EP) - if (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN) + if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN) return 1; #endif return 0; @@ -491,7 +491,7 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long strap; - mfsdr(sdr_sdstp1,strap); + mfsdr(SDR0_SDSTP1,strap); if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { printf("PCI: SDR0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); @@ -500,7 +500,7 @@ int pci_440_init (struct pci_controller *hose) #elif defined(CONFIG_440GP) unsigned long strap; - strap = mfdcr(cpc0_strp1); + strap = mfdcr(CPC0_STRP1); if ((strap & CPC0_STRP1_PISE_MASK) == 0) { printf("PCI: CPC0_STRP1[PISE] not set.\n"); printf("PCI: Configuration aborted.\n"); diff --git a/cpu/ppc4xx/4xx_uart.c b/cpu/ppc4xx/4xx_uart.c index 0780624e4a0..8de65425c97 100644 --- a/cpu/ppc4xx/4xx_uart.c +++ b/cpu/ppc4xx/4xx_uart.c @@ -90,7 +90,7 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 #define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 +#define UART0_SDR CPC0_CR0 #define MFREG(a, d) d = mfdcr(a) #define MTREG(a, d) mtdcr(a, d) #else /* #if defined(CONFIG_440GP) */ @@ -99,18 +99,18 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_SDR sdr_uart2 +#define UART2_SDR SDR0_UART2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART3_SDR sdr_uart3 +#define UART3_SDR SDR0_UART3 #endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) @@ -130,8 +130,8 @@ DECLARE_GLOBAL_DATA_PTR; #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #else /* CONFIG_405GP || CONFIG_405CR */ #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -282,7 +282,7 @@ static void serial_divs (int baudrate, unsigned long *pudiv, u32 reg; /* check the pll feedback source */ - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLC, cpr_pllc); get_sys_info(&sysinfo); @@ -312,10 +312,10 @@ static void serial_divs (int baudrate, unsigned long *pudiv, } *pudiv = udiv; - mfcpr(cprperd0, reg); + mfcpr(CPC0_PERD0, reg); reg &= ~0x0000ffff; reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(cprperd0, reg); + mtcpr(CPC0_PERD0, reg); *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ @@ -412,7 +412,7 @@ int serial_init_dev (unsigned long base) clk = tmp = reg = 0; #else #ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; @@ -420,9 +420,9 @@ int serial_init_dev (unsigned long base) udiv = UDIV_MAX; reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); + mtdcr (CPC0_UCR, reg); #else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; + reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; @@ -439,7 +439,7 @@ int serial_init_dev (unsigned long base) #endif #endif reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + mtdcr (CPC0_CR0, reg); #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index e9861abe762..22879046694 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -64,7 +64,7 @@ int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num"))); static int pci_async_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ASYNC_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -72,7 +72,7 @@ static int pci_async_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_sdstp1, val); + mfsdr(SDR0_SDSTP1, val); return (val & SDR0_SDSTP1_PAME_MASK); #endif } @@ -84,21 +84,21 @@ static int pci_async_enabled(void) static int pci_arbiter_enabled(void) { #if defined(CONFIG_405GP) - return (mfdcr(strap) & PSR_PCI_ARBIT_EN); + return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN); #endif #if defined(CONFIG_405EP) - return (mfdcr(cpc0_pci) & CPC0_PCI_ARBIT_EN); + return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN); #endif #if defined(CONFIG_440GP) - return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK); + return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK); #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(sdr_xcr, val); + mfsdr(SDR0_XCR, val); return (val & 0x80000000); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ @@ -106,7 +106,7 @@ static int pci_arbiter_enabled(void) defined(CONFIG_460EX) || defined(CONFIG_460GT) unsigned long val; - mfsdr(sdr_pci0, val); + mfsdr(SDR0_PCI0, val); return (val & 0x80000000); #endif } @@ -118,11 +118,11 @@ static int pci_arbiter_enabled(void) static int i2c_bootrom_enabled(void) { #if defined(CONFIG_405EP) - return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP); + return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP); #else unsigned long val; - mfsdr(sdr_sdcs, val); + mfsdr(SDR0_SDCS0, val); return (val & SDR0_SDCS_SDD); #endif } @@ -256,7 +256,7 @@ static int bootstrap_option(void) { unsigned long val; - mfsdr(SDR_PINSTP, val); + mfsdr(SDR0_PINSTP, val); return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT); } #endif /* SDR0_PINSTP_SHIFT */ @@ -265,13 +265,13 @@ static int bootstrap_option(void) #if defined(CONFIG_440) static int do_chip_reset (unsigned long sys0, unsigned long sys1) { - /* Changes to cpc0_sys0 and cpc0_sys1 require chip + /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip * reset. */ - mtdcr (cntrl0, mfdcr (cntrl0) | 0x80000000); /* Set SWE */ - mtdcr (cpc0_sys0, sys0); - mtdcr (cpc0_sys1, sys1); - mtdcr (cntrl0, mfdcr (cntrl0) & ~0x80000000); /* Clr SWE */ + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000); /* Set SWE */ + mtdcr (CPC0_SYS0, sys0); + mtdcr (CPC0_SYS1, sys1); + mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000); /* Clr SWE */ mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */ return 1; @@ -410,13 +410,13 @@ int checkcpu (void) case PVR_440GP_RB: puts("GP Rev. B"); /* See errata 1.12: CHIP_4 */ - if ((mfdcr(cpc0_sys0) != mfdcr(cpc0_strp0)) || - (mfdcr(cpc0_sys1) != mfdcr(cpc0_strp1)) ){ + if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || + (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ puts ( "\n\t CPC0_SYSx DCRs corrupted. " "Resetting chip ...\n"); udelay( 1000 * 1000 ); /* Give time for serial buf to clear */ - do_chip_reset ( mfdcr(cpc0_strp0), - mfdcr(cpc0_strp1) ); + do_chip_reset ( mfdcr(CPC0_STRP0), + mfdcr(CPC0_STRP1) ); } break; diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 65092fb8e47..bd06b9bc22c 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -58,17 +58,17 @@ void reconfigure_pll(u32 new_cpu_freq) target_perdv0 = 4; target_spcid0 = 4; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(clk_primbd, reg); + mtcpr(CPR0_PRIMBD, reg); reset_needed = 1; } - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; fwdva = temp ? temp : 16; @@ -89,35 +89,35 @@ void reconfigure_pll(u32 new_cpu_freq) ((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) | ((target_fbdv == 32 ? 0 : target_fbdv) << 24) | (target_lfbdv == 64 ? 0 : target_lfbdv); - mtcpr(clk_plld, reg); + mtcpr(CPR0_PLLD, reg); reset_needed = 1; } - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24; if (perdv0 != target_perdv0) { reg &= ~CPR0_PERD_PERDV0_MASK; reg |= (target_perdv0 << 24); - mtcpr(clk_perd, reg); + mtcpr(CPR0_PERD, reg); reset_needed = 1; } - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24; spcid0 = temp ? temp : 4; if (spcid0 != target_spcid0) { reg &= ~CPR0_SPCID_SPCIDV0_MASK; reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24); - mtcpr(clk_spcid, reg); + mtcpr(CPR0_SPCID, reg); reset_needed = 1; } /* Set reload inhibit so configuration will persist across * processor resets */ - mfcpr(clk_icfg, reg); + mfcpr(CPR0_ICFG, reg); reg &= ~CPR0_ICFG_RLI_MASK; reg |= 1 << 31; - mtcpr(clk_icfg, reg); + mtcpr(CPR0_ICFG, reg); } /* Reset processor if configuration changed */ @@ -173,7 +173,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(cpc0_epctl, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -204,43 +204,43 @@ cpu_init_f (void) asm volatile("2: bdnz 2b" ::: "ctr", "cr0"); #endif - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); #endif #if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1)) - mtebc(pb1ap, CONFIG_SYS_EBC_PB1AP); - mtebc(pb1cr, CONFIG_SYS_EBC_PB1CR); + mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP); + mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR); #endif #if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2)) - mtebc(pb2ap, CONFIG_SYS_EBC_PB2AP); - mtebc(pb2cr, CONFIG_SYS_EBC_PB2CR); + mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP); + mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR); #endif #if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3)) - mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP); - mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR); + mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP); + mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR); #endif #if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4)) - mtebc(pb4ap, CONFIG_SYS_EBC_PB4AP); - mtebc(pb4cr, CONFIG_SYS_EBC_PB4CR); + mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP); + mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR); #endif #if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5)) - mtebc(pb5ap, CONFIG_SYS_EBC_PB5AP); - mtebc(pb5cr, CONFIG_SYS_EBC_PB5CR); + mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP); + mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR); #endif #if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6)) - mtebc(pb6ap, CONFIG_SYS_EBC_PB6AP); - mtebc(pb6cr, CONFIG_SYS_EBC_PB6CR); + mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP); + mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR); #endif #if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7)) - mtebc(pb7ap, CONFIG_SYS_EBC_PB7AP); - mtebc(pb7cr, CONFIG_SYS_EBC_PB7CR); + mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP); + mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR); #endif #if defined (CONFIG_SYS_EBC_CFG) @@ -276,9 +276,9 @@ cpu_init_f (void) * Compatibility mode and Ethernet Clock select are not * correct in the manual */ - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~0x10000000; - mtsdr(sdr_mfr,val); + mtsdr(SDR0_MFR,val); #endif /* CONFIG_440GX */ #if defined(CONFIG_460EX) @@ -304,10 +304,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | - plb0_acr_rdp_4deep); - mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | - plb1_acr_rdp_4deep); + mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | + PLB0_ACR_RDP_4DEEP); + mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | + PLB1_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } @@ -324,7 +324,7 @@ int cpu_init_r (void) * for compatibility to existing PPC405GP designs. */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { - mtdcr(ecr, 0x60606000); + mtdcr(CPC0_ECR, 0x60606000); } #endif /* defined(CONFIG_405GP) */ diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index ba5c120ad7f..496e0285b5b 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -51,8 +51,8 @@ void __ft_board_setup(void *blob, bd_t *bd) * peripheral banks into the OPB/PLB address space */ for (i = 0; i < EBC_NUM_BANKS; i++) { - mtdcr(ebccfga, EBC_BXCR(i)); - bxcr = mfdcr(ebccfgd); + mtdcr(EBC0_CFGADDR, EBC_BXCR(i)); + bxcr = mfdcr(EBC0_CFGDATA); if ((bxcr & EBC_BXCR_BU_MASK) != EBC_BXCR_BU_NONE) { *p++ = i; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 4365df9879d..5a3336e3c8a 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -375,8 +375,8 @@ phys_size_t initdram(int board_type) /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); #endif for (i=0; i<N_MB0CF; i++) { diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index c0a5824a63a..1f751372cad 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -50,12 +50,12 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode register */ - pllmr = mfdcr (pllmd); + pllmr = mfdcr (CPC0_PLLMR); /* * Read Pin Strapping register */ - psr = mfdcr (strap); + psr = mfdcr (CPC0_PSR); /* * Determine FWD_DIV. @@ -280,8 +280,8 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long plbedv0; /* Extract configured divisors */ - mfsdr(sdr_sdstp0, strp0); - mfsdr(sdr_sdstp1, strp1); + mfsdr(SDR0_SDSTP0, strp0); + mfsdr(SDR0_SDSTP1, strp1); temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 4); sysInfo->pllFwdDivA = get_cpr0_fwdv(temp); @@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo) */ /* Decode CPR0_PLLD0 for divisors */ - mfcpr(clk_plld, reg); + mfcpr(CPR0_PLLD, reg); temp = (reg & PLLD_FWDVA_MASK) >> 16; sysInfo->pllFwdDivA = temp ? temp : 16; temp = (reg & PLLD_FWDVB_MASK) >> 8; @@ -351,28 +351,28 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(clk_opbd, reg); + mfcpr(CPR0_OPBD, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; - mfcpr(clk_perd, reg); + mfcpr(CPR0_PERD, reg); temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(clk_primbd, reg); + mfcpr(CPR0_PRIMBD, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; - mfcpr(clk_spcid, reg); + mfcpr(CPR0_SPCID, reg); temp = (reg & SPCID_MASK) >> 24; sysInfo->pllPciDiv = temp ? temp : 4; /* Calculate 'M' based on feedback source */ - mfsdr(sdr_sdstp0, reg); + mfsdr(SDR0_SDSTP0, reg); temp = (reg & PLLSYS0_SEL_MASK) >> 27; if (temp == 0) { /* PLL output */ /* Figure which pll to use */ - mfcpr(clk_pllc, reg); + mfcpr(CPR0_PLLC, reg); temp = (reg & PLLC_SRC_MASK) >> 29; if (!temp) /* PLLOUTA */ m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA; @@ -426,7 +426,7 @@ void get_sys_info (sys_info_t * sysInfo) unsigned long m; /* Extract configured divisors */ - strp0 = mfdcr( cpc0_strp0 ); + strp0 = mfdcr( CPC0_STRP0 ); sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15); sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12); temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18; @@ -484,8 +484,8 @@ void get_sys_info (sys_info_t * sysInfo) #endif /* Extract configured divisors */ - mfsdr( sdr_sdstp0,strp0 ); - mfsdr( sdr_sdstp1,strp1 ); + mfsdr( SDR0_SDSTP0,strp0 ); + mfsdr( SDR0_SDSTP1,strp1 ); temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8); sysInfo->pllFwdDivA = temp ? temp : 16 ; @@ -531,7 +531,7 @@ void get_sys_info (sys_info_t * sysInfo) /* Determine PCI Clock Period */ pci_clock_per = determine_pci_clock_per(); sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000; - mfsdr(sdr_ddr0, sdr_ddrpll); + mfsdr(SDR0_DDR0, sdr_ddrpll); sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll)); #endif @@ -794,8 +794,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - pllmr0 = mfdcr (cpc0_pllmr0); - pllmr1 = mfdcr (cpc0_pllmr1); + pllmr0 = mfdcr (CPC0_PLLMR0); + pllmr1 = mfdcr (CPC0_PLLMR1); /* * Determine forward divider A @@ -918,8 +918,8 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read PLL Mode registers */ - mfcpr(cprplld, cpr_plld); - mfcpr(cprpllc, cpr_pllc); + mfcpr(CPR0_PLLD, cpr_plld); + mfcpr(CPR0_PLLC, cpr_pllc); /* * Determine forward divider A @@ -943,7 +943,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(cprprimad, cpr_primad); + mfcpr(CPC0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. @@ -1074,7 +1074,7 @@ void get_sys_info (sys_info_t * sysInfo) }; unsigned char sel, cpudv0, plb2xDiv; - mfcpr(cpr0_plld, tmp); + mfcpr(CPR0_PLLD, tmp); /* * Determine forward divider A @@ -1094,29 +1094,29 @@ void get_sys_info (sys_info_t * sysInfo) /* * Determine PERDV0 */ - mfcpr(cpr0_perd, tmp); + mfcpr(CPR0_PERD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllExtBusDiv = (tmp == 0) ? 4 : tmp; /* * Determine OPBDV0 */ - mfcpr(cpr0_opbd, tmp); + mfcpr(CPR0_OPBD, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; /* Determine PLB2XDV0 */ - mfcpr(cpr0_plbd, tmp); + mfcpr(CPR0_PLBD, tmp); tmp = (tmp >> 16) & 0x07; plb2xDiv = (tmp == 0) ? 8 : tmp; /* Determine CPUDV0 */ - mfcpr(cpr0_cpud, tmp); + mfcpr(CPR0_CPUD, tmp); tmp = (tmp >> 24) & 0x07; cpudv0 = (tmp == 0) ? 8 : tmp; /* Determine SEL(5:7) in CPR0_PLLC */ - mfcpr(cpr0_pllc, tmp); + mfcpr(CPR0_PLLC, tmp); sel = (tmp >> 24) & 0x07; /* diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index f967d8464cf..287a912246a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -83,64 +83,64 @@ #ifdef CONFIG_SYS_INIT_DCACHE_CS # if (CONFIG_SYS_INIT_DCACHE_CS == 0) -# define PBxAP pb0ap -# define PBxCR pb0cr +# define PBxAP PB1AP +# define PBxCR PB0CR # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 1) -# define PBxAP pb1ap -# define PBxCR pb1cr +# define PBxAP PB1AP +# define PBxCR PB1CR # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 2) -# define PBxAP pb2ap -# define PBxCR pb2cr +# define PBxAP PB2AP +# define PBxCR PB2CR # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 3) -# define PBxAP pb3ap -# define PBxCR pb3cr +# define PBxAP PB3AP +# define PBxCR PB3CR # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 4) -# define PBxAP pb4ap -# define PBxCR pb4cr +# define PBxAP PB4AP +# define PBxCR PB4CR # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 5) -# define PBxAP pb5ap -# define PBxCR pb5cr +# define PBxAP PB5AP +# define PBxCR PB5CR # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 6) -# define PBxAP pb6ap -# define PBxCR pb6cr +# define PBxAP PB6AP +# define PBxCR PB6CR # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR # endif # endif # if (CONFIG_SYS_INIT_DCACHE_CS == 7) -# define PBxAP pb7ap -# define PBxCR pb7cr +# define PBxAP PB7AP +# define PBxCR PB7CR # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR @@ -998,7 +998,7 @@ _start: /*----------------------------------------------------------------------- */ addis r3,r0, 0xFFFF /* Clear all existing DMA status */ ori r3,r3, 0xFFFF - mtdcr dmasr, r3 + mtdcr DMASR, r3 bl ppc405ep_init /* do ppc405ep specific init */ #endif /* CONFIG_405EP */ @@ -1015,21 +1015,21 @@ _start: lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmdscr1, r3 /* Set Data Side */ - mtdcr ocmiscr1, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC1, r3 /* Set Data Side */ + mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmdscr2, r3 /* Set Data Side */ - mtdcr ocmiscr2, r3 /* Set Instruction Side */ + mtdcr OCM0_DSRC2, r3 /* Set Data Side */ + mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ - mtdcr ocmdsisdpc,r3 + mtdcr OCM0_DISDPC,r3 isync #else /* CONFIG_405EZ */ @@ -1039,19 +1039,19 @@ _start: /* Setup OCM */ lis r0, 0x7FFF ori r0, r0, 0xFFFF - mfdcr r3, ocmiscntl /* get instr-side IRAM config */ - mfdcr r4, ocmdscntl /* get data-side IRAM config */ + mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ + mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ and r3, r3, r0 /* disable data-side IRAM */ and r4, r4, r0 /* disable data-side IRAM */ - mtdcr ocmiscntl, r3 /* set instr-side IRAM config */ - mtdcr ocmdscntl, r4 /* set data-side IRAM config */ + mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ + mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ isync lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l - mtdcr ocmdsarc, r3 + mtdcr OCM0_DSARC, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ - mtdcr ocmdscntl, r4 + mtdcr OCM0_DSCNTL, r4 isync #endif /* CONFIG_405EZ */ #endif @@ -1061,16 +1061,16 @@ _start: /*----------------------------------------------------------------------- */ #ifdef CONFIG_SYS_INIT_DCACHE_CS li r4, PBxAP - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 addi r4, 0, PBxCR - mtdcr ebccfga, r4 + mtdcr EBC0_CFGADDR, r4 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l - mtdcr ebccfgd, r4 + mtdcr EBC0_CFGDATA, r4 /* * Enable the data cache for the 128MB storage access control region @@ -1428,16 +1428,16 @@ relocate_code: /* Restore the EBC parameters */ li r3, PBxAP - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxAP_VAL@h ori r3, r3, PBxAP_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 li r3, PBxCR - mtdcr ebccfga, r3 + mtdcr EBC0_CFGADDR, r3 lis r3, PBxCR_VAL@h ori r3, r3, PBxCR_VAL@l - mtdcr ebccfgd, r3 + mtdcr EBC0_CFGDATA, r3 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ /* Restore registers */ @@ -1860,38 +1860,38 @@ ppc405ep_init: ori r4,r4,CONFIG_SYS_GPIO0_TCR@l stw r4,0(r3) - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb1ap /* program EBC bank 1 for RTC access */ - mtdcr ebccfga,r3 + li r3,PB1AP /* program EBC bank 1 for RTC access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1AP@h ori r3,r3,CONFIG_SYS_EBC_PB1AP@l - mtdcr ebccfgd,r3 - li r3,pb1cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB1CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB1CR@h ori r3,r3,CONFIG_SYS_EBC_PB1CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 - li r3,pb4ap /* program EBC bank 4 for FPGA access */ - mtdcr ebccfga,r3 + li r3,PB4AP /* program EBC bank 4 for FPGA access */ + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4AP@h ori r3,r3,CONFIG_SYS_EBC_PB4AP@l - mtdcr ebccfgd,r3 - li r3,pb4cr - mtdcr ebccfga,r3 + mtdcr EBC0_CFGDATA,r3 + li r3,PB4CR + mtdcr EBC0_CFGADDR,r3 lis r3,CONFIG_SYS_EBC_PB4CR@h ori r3,r3,CONFIG_SYS_EBC_PB4CR@l - mtdcr ebccfgd,r3 + mtdcr EBC0_CFGDATA,r3 #endif /* diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index faf7f0878ff..5bb4f3ce632 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c @@ -206,14 +206,14 @@ void usb_dev_init() #ifdef USB_2_0_DEVICE printf("USB 2.0 Device init\n"); /*select 2.0 device */ - mtsdr(sdr_usb0, 0x0); /* 2.0 */ + mtsdr(SDR0_USB0, 0x0); /* 2.0 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xa1; /* 2.0 */ #else printf("USB 1.1 Device init\n"); /*select 1.1 device */ - mtsdr(sdr_usb0, 0x2); /* 1.1 */ + mtsdr(SDR0_USB0, 0x2); /* 1.1 */ /*usb dev init */ *(unsigned char *)USB2D0_POWER_8 = 0xc0; /* 1.1 */ diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0891936f00d..0dd67895827 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -207,8 +207,8 @@ int board_nand_init(struct nand_chip *nand) */ mtebc(EBC0_CFG, 0xb8400000); - mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR); - mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP); + mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR); + mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP); #endif chip++; diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 329eef07df5..afd108415b9 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -319,9 +319,9 @@ static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -338,9 +338,9 @@ static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) defined(CONFIG_405EX) u32 val; - mfsdr(sdr_mfr, val); + mfsdr(SDR0_MFR, val); val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); - mtsdr(sdr_mfr, val); + mtsdr(SDR0_MFR, val); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) u32 val; @@ -364,14 +364,14 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2))); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); #else - mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); #endif - mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum)); + mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { udelay (1000); /* Delay 1 MS so as not to hammer the register */ val--; if (val == 0) @@ -408,7 +408,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer; unsigned long rmiifer; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); zmiifer = 0; @@ -498,7 +498,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) unsigned long zmiifer=0x0; unsigned long pfc1; - mfsdr(sdr_pfc1, pfc1); + mfsdr(SDR0_PFC1, pfc1); pfc1 &= SDR0_PFC1_SELECT_MASK; switch (pfc1) { @@ -1240,13 +1240,13 @@ get_speed: !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ !defined(CONFIG_460EX) && !defined(CONFIG_460GT) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) - mfsdr(sdr_mfr, reg); + mfsdr(SDR0_MFR, reg); if (speed == 100) { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; } else { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; } - mtsdr(sdr_mfr, reg); + mtsdr(SDR0_MFR, reg); #endif /* Set ZMII/RGMII speed according to the phy link speed */ @@ -1302,13 +1302,13 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif @@ -1398,86 +1398,86 @@ get_speed: case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); #else - mtdcr (maltxctp1r, hw_p->tx_phys); + mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif #if defined(CONFIG_460EX) || defined(CONFIG_460GT) - mtdcr (malrxctp8r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); #else - mtdcr (malrxctp1r, hw_p->rx_phys); + mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); #endif break; #if defined (CONFIG_440GX) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp2r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxbattr, 0x0); - mtdcr (malrxctp3r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_440GX */ #if defined (CONFIG_460GT) case 2: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp2r, hw_p->tx_phys); - mtdcr (malrxctp16r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs16, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); break; case 3: /* setup MAL tx & rx channel pointers */ - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); - mtdcr (maltxctp3r, hw_p->tx_phys); - mtdcr (malrxctp24r, hw_p->rx_phys); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); + mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs24, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); break; #endif /* CONFIG_460GT */ case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, hw_p->tx_phys); - mtdcr (malrxctp0r, hw_p->rx_phys); + mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); + mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); /* set RX buffer size */ - mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16); + mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); @@ -1493,9 +1493,9 @@ get_speed: defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 |= SDR0_PFC1_EM_1000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; } else if (speed == _100BASET) @@ -1665,7 +1665,7 @@ int enetInt (struct eth_device *dev) /* look at MAL and EMAC error interrupts */ if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { /* we have a MAL error interrupt */ - mal_isr = mfdcr(malesr); + mal_isr = mfdcr(MAL0_ESR); mal_err(dev, mal_isr, uic_mal_err, MAL_UIC_DEF, MAL_UIC_ERR); @@ -1691,8 +1691,8 @@ int enetInt (struct eth_device *dev) /* handle MAX TX EOB interrupt from a tx */ if (uic_mal & UIC_MAL_TXEOB) { /* clear MAL interrupt status bits */ - mal_eob = mfdcr(maltxeobisr); - mtdcr(maltxeobisr, mal_eob); + mal_eob = mfdcr(MAL0_TXEOBISR); + mtdcr(MAL0_TXEOBISR, mal_eob); mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); /* indicate that we serviced an interrupt */ @@ -1703,7 +1703,7 @@ int enetInt (struct eth_device *dev) /* handle MAL RX EOB interupt from a receive */ /* check for EOB on valid channels */ if (uic_mal & UIC_MAL_RXEOB) { - mal_eob = mfdcr(malrxeobisr); + mal_eob = mfdcr(MAL0_RXEOBISR); if (mal_eob & (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { /* push packet to upper layer */ @@ -1731,11 +1731,11 @@ static void mal_err (struct eth_device *dev, unsigned long isr, { EMAC_4XX_HW_PST hw_p = dev->priv; - mtdcr (malesr, isr); /* clear interrupt */ + mtdcr (MAL0_ESR, isr); /* clear interrupt */ /* clear DE interrupt */ - mtdcr (maltxdeir, 0xC0000000); - mtdcr (malrxdeir, 0x80000000); + mtdcr (MAL0_TXDEIR, 0xC0000000); + mtdcr (MAL0_RXDEIR, 0x80000000); #ifdef INFO_4XX_ENET printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); @@ -1769,10 +1769,10 @@ static void enet_rcv (struct eth_device *dev, unsigned long malisr) int i; int loop_count = 0; - rx_eob_isr = mfdcr (malrxeobisr); + rx_eob_isr = mfdcr (MAL0_RXEOBISR); if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { /* clear EOB */ - mtdcr (malrxeobisr, rx_eob_isr); + mtdcr (MAL0_RXEOBISR, rx_eob_isr); /* EMAC RX done */ while (1) { /* do all */ @@ -1912,10 +1912,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) #if defined(CONFIG_440GX) unsigned long pfc1; - mfsdr (sdr_pfc1, pfc1); + mfsdr (SDR0_PFC1, pfc1); pfc1 &= ~(0x01e00000); pfc1 |= 0x01200000; - mtsdr (sdr_pfc1, pfc1); + mtsdr (SDR0_PFC1, pfc1); #endif /* first clear all mac-addresses */ @@ -2036,10 +2036,10 @@ int ppc_4xx_eth_initialize (bd_t * bis) MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE | MAL_IER_PLBE; #endif - mtdcr (malesr, 0xffffffff); /* clear pending interrupts */ - mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */ - mtdcr (malier, mal_ier); + mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ + mtdcr (MAL0_IER, mal_ier); /* install MAL interrupt handler */ irq_install_handler (VECNUM_MAL_SERR, diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 553845d6d98..40e4735b681 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -207,9 +207,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD21A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 73d6d24b61d..a62f1b4d578 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -214,9 +214,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD87A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/ppc405.h b/include/ppc405.h index 55649e474fc..5e56897819a 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -42,54 +42,39 @@ * DMA ******************************************************************************/ #define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */ #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller ******************************************************************************/ #define DECOMP_DCR_BASE 0x14 -#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ - /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ - #define kaddr0 0x04 /* address decode definition regsiter 0 */ - #define kaddr1 0x05 /* address decode definition regsiter 1 */ - #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ - #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ - #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ - /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ +#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ +/* values for kiar register - indirect addressing of these regs */ +#define KCONF 0x40 /* decompression core config register */ #endif /****************************************************************************** @@ -100,38 +85,37 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ - /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ + /* values for EBC0_CFGADDR register - indirect addressing of these regs */ + #define PB0CR 0x00 /* periph bank 0 config reg */ + #define PB1CR 0x01 /* periph bank 1 config reg */ + #define PB2CR 0x02 /* periph bank 2 config reg */ + #define PB3CR 0x03 /* periph bank 3 config reg */ + #define PB4CR 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ + #define PB5CR 0x05 /* periph bank 5 config reg */ + #define PB6CR 0x06 /* periph bank 6 config reg */ + #define PB7CR 0x07 /* periph bank 7 config reg */ #endif - #define pb0ap 0x10 /* periph bank 0 access parameters */ - #define pb1ap 0x11 /* periph bank 1 access parameters */ - #define pb2ap 0x12 /* periph bank 2 access parameters */ - #define pb3ap 0x13 /* periph bank 3 access parameters */ - #define pb4ap 0x14 /* periph bank 4 access parameters */ + #define PB0AP 0x10 /* periph bank 0 access parameters */ + #define PB1AP 0x11 /* periph bank 1 access parameters */ + #define PB2AP 0x12 /* periph bank 2 access parameters */ + #define PB3AP 0x13 /* periph bank 3 access parameters */ + #define PB4AP 0x14 /* periph bank 4 access parameters */ #ifndef CONFIG_405EP - #define pb5ap 0x15 /* periph bank 5 access parameters */ - #define pb6ap 0x16 /* periph bank 6 access parameters */ - #define pb7ap 0x17 /* periph bank 7 access parameters */ + #define PB5AP 0x15 /* periph bank 5 access parameters */ + #define PB6AP 0x16 /* periph bank 6 access parameters */ + #define PB7AP 0x17 /* periph bank 7 access parameters */ #endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ + #define PBEAR 0x20 /* periph bus error addr reg */ + #define PBESR0 0x21 /* periph bus error status reg 0 */ + #define PBESR1 0x22 /* periph bus error status reg 1 */ #define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP @@ -139,12 +123,12 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ @@ -401,10 +385,10 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 +#define SDR0_NAND0 0x4000 +#define SDR0_ULTRA0 0x4040 +#define SDR0_ULTRA1 0x4050 +#define SDR0_ICINTSTAT 0x4510 #define SDR_NAND0_NDEN 0x80000000 #define SDR_NAND0_NDBTEN 0x40000000 @@ -429,21 +413,19 @@ #define SDR_ICTX0_STAT 0x40000000 #define SDR_ICTX1_STAT 0x20000000 -#define SDR_PINSTP 0x40 +#define SDR0_PINSTP 0x40 /****************************************************************************** * Control ******************************************************************************/ /* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ +#define CPR0_CLKUP 0x020 /* CPR_CLKUPD */ +#define CPR0_PLLC 0x040 /* CPR_PLLC */ +#define CPR0_PLLD 0x060 /* CPR_PLLD */ +#define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */ +#define CPC0_PERD0 0x0e0 /* CPR_PERD0 */ +#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ +#define CPC0_PERC0 0x180 /* CPR_PERC0 */ #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ @@ -470,21 +452,14 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ - -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ +#define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */ +#define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */ /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ - -#define ecr (0xaa) /* edge conditioner register (405gpr) */ +#define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */ +#define CPC0_ECR 0xaa /* edge conditioner register */ /* Bit definitions */ #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ @@ -557,140 +532,38 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ - -#else /* !defined(CONFIG_405EZ) */ - -#define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#endif /* defined(CONFIG_405EZ) */ +#else +#define MAL_DCR_BASE 0x180 +#endif +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -730,27 +603,19 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */ +#define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */ +#define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */ +#define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */ +#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ +#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ +#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ +#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/ #else #define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */ +#define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */ #endif /* CONFIG_405EZ */ /****************************************************************************** @@ -876,9 +741,9 @@ #define SDR0_SRST_AHB PPC_REG_VAL(30, 1) #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ #define CPC0_EPRCSR_E0NFE 0x80000000 @@ -890,18 +755,16 @@ #define CPC0_EPRCSR_E1PCI 0x00000002 #define CPC0_EPRCSR_E0PCI 0x00000001 -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 - -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 +#define CPR0_CLKUPD 0x020 +#define CPR0_PLLC 0x040 +#define CPR0_PLLD 0x060 +#define CPR0_CPUD 0x080 +#define CPR0_PLBD 0x0a0 +#define CPR0_OPBD 0x0c0 +#define CPR0_PERD 0x0e0 + +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #define SDR0_SDCS_SDD (0x80000000 >> 31) diff --git a/include/ppc440.h b/include/ppc440.h index 7f34fda8cfa..378a9de20a6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,64 +58,55 @@ | Clocking Controller +----------------------------------------------------------------------------*/ /* values for clkcfga register - indirect addressing of these regs */ -#define clk_clkukpd 0x0020 -#define clk_pllc 0x0040 -#define clk_plld 0x0060 -#define clk_primad 0x0080 -#define clk_primbd 0x00a0 -#define clk_opbd 0x00c0 -#define clk_perd 0x00e0 -#define clk_mald 0x0100 -#define clk_spcid 0x0120 -#define clk_icfg 0x0140 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLD 0x0060 +#define CPR0_PRIMAD 0x0080 +#define CPR0_PRIMBD 0x00a0 +#define CPR0_OPBD 0x00c0 +#define CPR0_PERD 0x00e0 +#define CPR0_MALD 0x0100 +#define CPR0_SPCID 0x0120 +#define CPR0_ICFG 0x0140 /* 440gx sdr register definations */ -#define sdr_sdstp0 0x0020 /* */ -#define sdr_sdstp1 0x0021 /* */ -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 -#define sdr_ecid0 0x0080 -#define sdr_ecid1 0x0081 -#define sdr_ecid2 0x0082 -#define sdr_jtag 0x00c0 +#define SDR0_SDSTP0 0x0020 /* */ +#define SDR0_SDSTP1 0x0021 /* */ +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_DDRCFG 0x00e0 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -#define sdr_ebc 0x0100 -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_uart2 0x0122 /* UART2 Config */ -#define sdr_uart3 0x0123 /* UART3 Config */ -#define sdr_cp440 0x0180 -#define sdr_xcr 0x01c0 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_srst 0x0200 -#define sdr_slpipe 0x0220 -#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ -#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ -#define sdr_mirq0 0x0260 -#define sdr_mirq1 0x0261 -#define sdr_maltbl 0x0280 -#define sdr_malrbl 0x02a0 -#define sdr_maltbs 0x02c0 -#define sdr_malrbs 0x02e0 -#define sdr_pci0 0x0300 -#define sdr_usb0 0x0320 -#define sdr_cust0 0x4000 -#define sdr_cust1 0x4002 -#define sdr_pfc0 0x4100 /* Pin Function 0 */ -#define sdr_pfc1 0x4101 /* Pin Function 1 */ -#define sdr_plbtr 0x4200 -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_UART2 0x0122 /* UART2 Config */ +#define SDR0_UART3 0x0123 /* UART3 Config */ +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_PCI0 0x01c0 +#else +#define SDR0_PCI0 0x0300 +#endif +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_PFC0 0x4100 /* Pin Function 0 */ +#define SDR0_PFC1 0x4101 /* Pin Function 1 */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ #ifdef CONFIG_440GX -#define sdr_amp 0x0240 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_xcr 0x01c0 -#define sdr_sdstp2 0x4001 -#define sdr_sdstp3 0x4003 +#define SD0_AMP 0x0240 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_XCR 0x01c0 +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 #endif /* CONFIG_440GX */ /*----------------------------------------------------------------------------+ @@ -143,101 +134,66 @@ #define MMUCR_STID_MASK 0x000000FF #ifdef CONFIG_440SPE -#undef sdr_sdstp2 -#define sdr_sdstp2 0x0022 -#undef sdr_sdstp3 -#define sdr_sdstp3 0x0023 -#define sdr_ddr0 0x00E1 -#define sdr_uart2 0x0122 -#define sdr_xcr0 0x01c0 -/* #define sdr_xcr1 0x01c3 only one PCIX - SG */ -/* #define sdr_xcr2 0x01c6 only one PCIX - SG */ -#define sdr_xpllc0 0x01c1 -#define sdr_xplld0 0x01c2 -#define sdr_xpllc1 0x01c4 /*notRCW - SG */ -#define sdr_xplld1 0x01c5 /*notRCW - SG */ -#define sdr_xpllc2 0x01c7 /*notRCW - SG */ -#define sdr_xplld2 0x01c8 /*notRCW - SG */ -#define sdr_amp0 0x0240 -#define sdr_amp1 0x0241 -#define sdr_cust2 0x4004 -#define sdr_cust3 0x4006 -#define sdr_sdstp4 0x4001 -#define sdr_sdstp5 0x4003 -#define sdr_sdstp6 0x4005 -#define sdr_sdstp7 0x4007 +#undef SDR0_SDSTP2 +#define SDR0_SDSTP2 0x0022 +#undef SDR0_SDSTP3 +#define SDR0_SDSTP3 0x0023 +#define SDR0_DDR0 0x00E1 +#define SDR0_UART2 0x0122 +#define SDR0_XCR0 0x01c0 +#define SDR0_XCR1 0x01c3 +#define SDR0_XCR2 0x01c6 +#define SDR0_XPLLC0 0x01c1 +#define SDR0_XPLLD0 0x01c2 +#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */ +#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */ +#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */ +#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */ +#define SD0_AMP0 0x0240 +#define SD0_AMP1 0x0241 +#define SDR0_CUST2 0x4004 +#define SDR0_CUST3 0x4006 +#define SDR0_SDSTP4 0x4001 +#define SDR0_SDSTP5 0x4003 +#define SDR0_SDSTP6 0x4005 +#define SDR0_SDSTP7 0x4007 #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -/* values for ebccfga register - indirect addressing of these regs */ -#define pb0cr 0x00 /* periph bank 0 config reg */ -#define pb1cr 0x01 /* periph bank 1 config reg */ -#define pb2cr 0x02 /* periph bank 2 config reg */ -#define pb3cr 0x03 /* periph bank 3 config reg */ -#define pb4cr 0x04 /* periph bank 4 config reg */ -#define pb5cr 0x05 /* periph bank 5 config reg */ -#define pb6cr 0x06 /* periph bank 6 config reg */ -#define pb7cr 0x07 /* periph bank 7 config reg */ -#define pb0ap 0x10 /* periph bank 0 access parameters */ -#define pb1ap 0x11 /* periph bank 1 access parameters */ -#define pb2ap 0x12 /* periph bank 2 access parameters */ -#define pb3ap 0x13 /* periph bank 3 access parameters */ -#define pb4ap 0x14 /* periph bank 4 access parameters */ -#define pb5ap 0x15 /* periph bank 5 access parameters */ -#define pb6ap 0x16 /* periph bank 6 access parameters */ -#define pb7ap 0x17 /* periph bank 7 access parameters */ -#define pbear 0x20 /* periph bus error addr reg */ -#define pbesr 0x21 /* periph bus error status reg */ -#define xbcfg 0x23 /* external bus configuration reg */ +/* values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR 0x21 /* periph bus error status reg */ #define EBC0_CFG 0x23 /* external bus configuration reg */ -#define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* PLB4 to PLB3 Bridge OUT */ -#define P4P3_DCR_BASE 0x020 -#define p4p3_esr0_read (P4P3_DCR_BASE+0x0) -#define p4p3_esr0_write (P4P3_DCR_BASE+0x1) -#define p4p3_eadr (P4P3_DCR_BASE+0x2) -#define p4p3_euadr (P4P3_DCR_BASE+0x3) -#define p4p3_esr1_read (P4P3_DCR_BASE+0x4) -#define p4p3_esr1_write (P4P3_DCR_BASE+0x5) -#define p4p3_confg (P4P3_DCR_BASE+0x6) -#define p4p3_pic (P4P3_DCR_BASE+0x7) -#define p4p3_peir (P4P3_DCR_BASE+0x8) -#define p4p3_rev (P4P3_DCR_BASE+0xA) - -/* PLB3 to PLB4 Bridge IN */ -#define P3P4_DCR_BASE 0x030 -#define p3p4_esr0_read (P3P4_DCR_BASE+0x0) -#define p3p4_esr0_write (P3P4_DCR_BASE+0x1) -#define p3p4_eadr (P3P4_DCR_BASE+0x2) -#define p3p4_euadr (P3P4_DCR_BASE+0x3) -#define p3p4_esr1_read (P3P4_DCR_BASE+0x4) -#define p3p4_esr1_write (P3P4_DCR_BASE+0x5) -#define p3p4_confg (P3P4_DCR_BASE+0x6) -#define p3p4_pic (P3P4_DCR_BASE+0x7) -#define p3p4_peir (P3P4_DCR_BASE+0x8) -#define p3p4_rev (P3P4_DCR_BASE+0xA) - /* PLB3 Arbiter */ -#define PLB3_DCR_BASE 0x070 -#define plb3_revid (PLB3_DCR_BASE+0x2) -#define plb3_besr (PLB3_DCR_BASE+0x3) -#define plb3_bear (PLB3_DCR_BASE+0x6) -#define plb3_acr (PLB3_DCR_BASE+0x7) +#define PLB3_DCR_BASE 0x070 +#define PLB3_ACR (PLB3_DCR_BASE + 0x7) /* PLB4 Arbiter - PowerPC440EP Pass1 */ -#define PLB4_DCR_BASE 0x080 -#define plb4_acr (PLB4_DCR_BASE+0x1) -#define plb4_revid (PLB4_DCR_BASE+0x2) -#define plb4_besr (PLB4_DCR_BASE+0x4) -#define plb4_bearl (PLB4_DCR_BASE+0x6) -#define plb4_bearh (PLB4_DCR_BASE+0x7) +#define PLB4_DCR_BASE 0x080 +#define PLB4_ACR (PLB4_DCR_BASE + 0x1) #define PLB4_ACR_WRP (0x80000000 >> 7) @@ -578,24 +534,16 @@ #define CNTRL_DCR_BASE 0x0b0 #endif -#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ -#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ -#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ - -#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ -#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ -#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ -#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ -#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ -#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- | DMA @@ -605,91 +553,59 @@ #else #define DMA_DCR_BASE 0x100 #endif -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ -#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ -#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ -#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ -#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ -#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ -#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ -#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ -#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ -#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ -#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ -#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ -#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ -#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ -#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ -#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ -#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ -#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ -#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ -#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ -#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ /*----------------------------------------------------------------------------- | Memory Access Layer +----------------------------------------------------------------------------*/ #define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ -#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ -#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ #endif /* CONFIG_440GX */ /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ #if defined(CONFIG_440SP) -#define SDR0_SRST 0x0200 - #define SDR0_DDR0 0x00E1 #define SDR0_DDR0_DPLLRST 0x80000000 #define SDR0_DDR0_DDRM_MASK 0x60000000 @@ -923,79 +839,6 @@ #define SDR0_UART0 0x0120 #define SDR0_UART1 0x0121 #define SDR0_UART2 0x0122 -#define SDR0_UARTX_UXICS_MASK 0xF0000000 -#define SDR0_UARTX_UXICS_PLB 0x20000000 -#define SDR0_UARTX_UXEC_MASK 0x00800000 -#define SDR0_UARTX_UXEC_INT 0x00000000 -#define SDR0_UARTX_UXEC_EXT 0x00800000 -#define SDR0_UARTX_UXDIV_MASK 0x000000FF -#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) - -#define SDR0_CP440 0x0180 -#define SDR0_CP440_ERPN_MASK 0x30000000 -#define SDR0_CP440_ERPN_MASK_HI 0x3000 -#define SDR0_CP440_ERPN_MASK_LO 0x0000 -#define SDR0_CP440_ERPN_EBC 0x10000000 -#define SDR0_CP440_ERPN_EBC_HI 0x1000 -#define SDR0_CP440_ERPN_EBC_LO 0x0000 -#define SDR0_CP440_ERPN_PCI 0x20000000 -#define SDR0_CP440_ERPN_PCI_HI 0x2000 -#define SDR0_CP440_ERPN_PCI_LO 0x0000 -#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) -#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) -#define SDR0_CP440_NTO1_MASK 0x00000002 -#define SDR0_CP440_NTO1_NTOP 0x00000000 -#define SDR0_CP440_NTO1_NTO1 0x00000002 -#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) -#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) - -#define SDR0_XCR0 0x01C0 -#define SDR0_XCR1 0x01C3 -#define SDR0_XCR2 0x01C6 -#define SDR0_XCRn_PAE_MASK 0x80000000 -#define SDR0_XCRn_PAE_DISABLE 0x00000000 -#define SDR0_XCRn_PAE_ENABLE 0x80000000 -#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_XCRn_PHCE_MASK 0x40000000 -#define SDR0_XCRn_PHCE_DISABLE 0x00000000 -#define SDR0_XCRn_PHCE_ENABLE 0x40000000 -#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_XCRn_PISE_MASK 0x20000000 -#define SDR0_XCRn_PISE_DISABLE 0x00000000 -#define SDR0_XCRn_PISE_ENABLE 0x20000000 -#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define SDR0_XCRn_PCWE_MASK 0x10000000 -#define SDR0_XCRn_PCWE_DISABLE 0x00000000 -#define SDR0_XCRn_PCWE_ENABLE 0x10000000 -#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) -#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) -#define SDR0_XCRn_PPIM_MASK 0x0F000000 -#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) -#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#define SDR0_XCRn_PR64E_MASK 0x00800000 -#define SDR0_XCRn_PR64E_DISABLE 0x00000000 -#define SDR0_XCRn_PR64E_ENABLE 0x00800000 -#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) -#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) -#define SDR0_XCRn_PXFS_MASK 0x00600000 -#define SDR0_XCRn_PXFS_100_133 0x00000000 -#define SDR0_XCRn_PXFS_66_100 0x00200000 -#define SDR0_XCRn_PXFS_50_66 0x00400000 -#define SDR0_XCRn_PXFS_0_33 0x00600000 -#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) -#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) - -#define SDR0_XPLLC0 0x01C1 -#define SDR0_XPLLD0 0x01C2 -#define SDR0_XPLLC1 0x01C4 -#define SDR0_XPLLD1 0x01C5 -#define SDR0_XPLLC2 0x01C7 -#define SDR0_XPLLD2 0x01C8 -#define SDR0_SRST 0x0200 #define SDR0_SLPIPE 0x0220 #define SDR0_AMP0 0x0240 @@ -1544,8 +1387,7 @@ #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_SRST0 0x0200 -#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */ +#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ @@ -1607,8 +1449,6 @@ #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ -#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */ - #else #define SDR0_SRST_BGO 0x80000000 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index a9954aa3de3..086f8fb7ee3 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -65,49 +65,37 @@ #define PLB_ARBITER_BASE 0x80 -#define plb0_revid (PLB_ARBITER_BASE + 0x00) -#define plb0_acr (PLB_ARBITER_BASE + 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000 - -#define plb0_besrl (PLB_ARBITER_BASE + 0x02) -#define plb0_besrh (PLB_ARBITER_BASE + 0x03) -#define plb0_bearl (PLB_ARBITER_BASE + 0x04) -#define plb0_bearh (PLB_ARBITER_BASE + 0x05) -#define plb0_ccr (PLB_ARBITER_BASE + 0x08) - -#define plb1_acr (PLB_ARBITER_BASE + 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000 - -#define plb1_besrl (PLB_ARBITER_BASE + 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE + 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE + 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE + 0x0D) +#define PLB0_ACR (PLB_ARBITER_BASE + 0x01) +#define PLB0_ACR_PPM_MASK 0xF0000000 +#define PLB0_ACR_PPM_FIXED 0x00000000 +#define PLB0_ACR_PPM_FAIR 0xD0000000 +#define PLB0_ACR_HBU_MASK 0x08000000 +#define PLB0_ACR_HBU_DISABLED 0x00000000 +#define PLB0_ACR_HBU_ENABLED 0x08000000 +#define PLB0_ACR_RDP_MASK 0x06000000 +#define PLB0_ACR_RDP_DISABLED 0x00000000 +#define PLB0_ACR_RDP_2DEEP 0x02000000 +#define PLB0_ACR_RDP_3DEEP 0x04000000 +#define PLB0_ACR_RDP_4DEEP 0x06000000 +#define PLB0_ACR_WRP_MASK 0x01000000 +#define PLB0_ACR_WRP_DISABLED 0x00000000 +#define PLB0_ACR_WRP_2DEEP 0x01000000 + +#define PLB1_ACR (PLB_ARBITER_BASE + 0x09) +#define PLB1_ACR_PPM_MASK 0xF0000000 +#define PLB1_ACR_PPM_FIXED 0x00000000 +#define PLB1_ACR_PPM_FAIR 0xD0000000 +#define PLB1_ACR_HBU_MASK 0x08000000 +#define PLB1_ACR_HBU_DISABLED 0x00000000 +#define PLB1_ACR_HBU_ENABLED 0x08000000 +#define PLB1_ACR_RDP_MASK 0x06000000 +#define PLB1_ACR_RDP_DISABLED 0x00000000 +#define PLB1_ACR_RDP_2DEEP 0x02000000 +#define PLB1_ACR_RDP_3DEEP 0x04000000 +#define PLB1_ACR_RDP_4DEEP 0x06000000 +#define PLB1_ACR_WRP_MASK 0x01000000 +#define PLB1_ACR_WRP_DISABLED 0x00000000 +#define PLB1_ACR_WRP_2DEEP 0x01000000 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ @@ -156,35 +144,35 @@ line aligned data. */ #define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) +#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) +#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) #define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) +#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) +#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) #define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) +#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) +#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) #define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) +#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) +#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) +#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0) -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) +#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0) +#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0) -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0) -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) +#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0) #ifndef __ASSEMBLY__ diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c index 54be2566c0c..df03afe0a47 100644 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ b/nand_spl/board/amcc/bamboo/sdram.c @@ -56,8 +56,8 @@ phys_size_t initdram(int board_type) /* * Soft-reset SDRAM controller. */ - mtsdr(sdr_srst, SDR0_SRST_DMC); - mtsdr(sdr_srst, 0x00000000); + mtsdr(SDR0_SRST, SDR0_SRST_DMC); + mtsdr(SDR0_SRST, 0x00000000); /* * Disable memory controller. diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index e40e19be235..c3665da94a6 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -109,9 +109,9 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* provide clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); sync (); #endif /* reset emac */ @@ -150,13 +150,13 @@ static void ether_post_init (int devnum, int hw_addr) #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | 0x00330000); #else - mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); /* Errata 1.12: MAL_1 -- Disable MAL bursting */ if (get_pvr() == PVR_440GP_RB) { - mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); } #endif /* setup buffer descriptors */ @@ -174,39 +174,39 @@ static void ether_post_init (int devnum, int hw_addr) case 1: /* setup MAL tx & rx channel pointers */ #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) - mtdcr (maltxctp2r, &tx); + mtdcr (MAL0_TXCTP2R, &tx); #else - mtdcr (maltxctp1r, &tx); + mtdcr (MAL0_TXCTP1R, &tx); #endif #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (malrxctp1r, &rx); + mtdcr (MAL0_RXCTP1R, &rx); /* set RX buffer size */ - mtdcr (malrcbs1, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16); break; case 0: default: /* setup MAL tx & rx channel pointers */ #if defined(CONFIG_440) - mtdcr (maltxbattr, 0x0); - mtdcr (malrxbattr, 0x0); + mtdcr (MAL0_TXBADDR, 0x0); + mtdcr (MAL0_RXBADDR, 0x0); #endif - mtdcr (maltxctp0r, &tx); - mtdcr (malrxctp0r, &rx); + mtdcr (MAL0_TXCTP0R, &tx); + mtdcr (MAL0_RXCTP0R, &rx); /* set RX buffer size */ - mtdcr (malrcbs0, PKTSIZE_ALIGN / 16); + mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16); break; } /* Enable MAL transmit and receive channels */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2))); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2))); #else - mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum)); #endif - mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); + mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum)); /* set internal loopback mode */ #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK @@ -257,14 +257,14 @@ static void ether_post_halt (int devnum, int hw_addr) /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2)); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2)); #else - mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum); #endif - mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum); + mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum); /* wait for reset */ - while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) { + while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) { if (i++ >= 1000) break; udelay (1000); @@ -274,9 +274,9 @@ static void ether_post_halt (int devnum, int hw_addr) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ - mfsdr (sdr_mfr, mfr); + mfsdr (SDR0_MFR, mfr); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); - mtsdr (sdr_mfr, mfr); + mtsdr (SDR0_MFR, mfr); #endif } diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index 84a4d0a0d63..be217fcf8db 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -68,7 +68,7 @@ #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 #define UDIV_SUBTRACT 1 -#define UART0_SDR cntrl0 +#define UART0_SDR CPC0_CR0 #define MFREG(a, d) d = mfdcr(a) #define MTREG(a, d) mtdcr(a, d) #else /* #if defined(CONFIG_440GP) */ @@ -77,16 +77,16 @@ #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_SDR sdr_uart2 +#define UART2_SDR SDR0_UART2 #endif #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ defined(CONFIG_440GR) || defined(CONFIG_440GRX) -#define UART3_SDR sdr_uart3 +#define UART3_SDR SDR0_UART3 #endif #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) @@ -106,8 +106,8 @@ #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 #define UDIV_SUBTRACT 0 -#define UART0_SDR sdr_uart0 -#define UART1_SDR sdr_uart1 +#define UART0_SDR SDR0_UART0 +#define UART1_SDR SDR0_UART1 #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) #else /* CONFIG_405GP || CONFIG_405CR */ @@ -276,7 +276,7 @@ static int uart_post_init (unsigned long dev_base) clk = tmp = reg = 0; #else #ifdef CONFIG_405EP - reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; @@ -284,9 +284,9 @@ static int uart_post_init (unsigned long dev_base) udiv = UDIV_MAX; reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (cpc0_ucr, reg); + mtdcr (CPC0_UCR, reg); #else /* CONFIG_405EP */ - reg = mfdcr(cntrl0) & ~CR0_MASK; + reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; @@ -303,7 +303,7 @@ static int uart_post_init (unsigned long dev_base) #endif #endif reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ - mtdcr (cntrl0, reg); + mtdcr (CPC0_CR0, reg); #endif /* CONFIG_405EP */ tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; |