arm: Remove mx31pdk board

DM, OF_CONTROL, DM_SPI and other driver model migration
deadlines are expired for this board.

Remove it.

Acked-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>

8 files changed, 0 insertions, 409 deletions

diff --git a/arch/arm/mach-imx/mx3/Kconfig b/arch/arm/mach-imx/mx3/Kconfig
index 5028d5ea568..42bba4822e6 100644
--- a/arch/arm/mach-imx/mx3/Kconfig
+++ b/arch/arm/mach-imx/mx3/Kconfig
@@ -29,6 +29,5 @@ config MX31_CLK32
          Frequency in Hz of the low frequency input clock. Typically
 	 32768 or 32000 Hz.
 
-source "board/freescale/mx31pdk/Kconfig"
 
 endif
diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig
deleted file mode 100644
index 055545c9306..00000000000
--- a/board/freescale/mx31pdk/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX31PDK
-
-config SYS_BOARD
-	default "mx31pdk"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_SOC
-	default "mx31"
-
-config SYS_CONFIG_NAME
-	default "mx31pdk"
-
-endif
diff --git a/board/freescale/mx31pdk/MAINTAINERS b/board/freescale/mx31pdk/MAINTAINERS
deleted file mode 100644
index ec2a32063b0..00000000000
--- a/board/freescale/mx31pdk/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX31PDK BOARD
-M:	Magnus Lilja <lilja.magnus@gmail.com>
-S:	Maintained
-F:	board/freescale/mx31pdk/
-F:	include/configs/mx31pdk.h
-F:	configs/mx31pdk_defconfig
diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile
deleted file mode 100644
index 7edc60f0d2c..00000000000
--- a/board/freescale/mx31pdk/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-ifdef CONFIG_SPL_BUILD
-obj-y	+= lowlevel_init.o
-endif
-obj-y	+= mx31pdk.o
diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S
deleted file mode 100644
index d78459faf66..00000000000
--- a/board/freescale/mx31pdk/lowlevel_init.S
+++ /dev/null
@@ -1,76 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- */
-
-#include <config.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/macro.h>
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Also setup the Peripheral Port Remap register inside the core */
-	ldr	r0, =ARM_PPMRR      /* start from AIPS 2GB region */
-	mcr	p15, 0, r0, c15, c2, 4
-
-	write32	IPU_CONF, IPU_CONF_DI_EN
-	write32	CCM_CCMR, CCM_CCMR_SETUP
-
-	wait_timer	0x40000
-
-	write32	CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
-	write32	CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
-
-	/* Set up clock to 532MHz */
-	write32	CCM_PDR0, CCM_PDR0_SETUP_532MHZ
-	write32	CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
-
-	write32	CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
-	/* Set up MX31 DDR pins */
-	write32	IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
-	write32	IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
-	write32	IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
-	write32	IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
-	write32	IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
-	write32	IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
-	write32	IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
-	write32	IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
-	write32	IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
-	write32	IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
-	write32	IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
-	write32	IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
-	write32	IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
-	write32	IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
-	write32	IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
-	write32	IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
-	write32	IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
-	write32	IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
-	write32	IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
-	write32	IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
-	write32	IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
-	write32	IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
-	write32	IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
-	write32	IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
-	write32	IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
-	write32	IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
-	write32	IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
-
-	/* Set up MX31 DDR Memory Controller */
-	write32	WEIM_ESDMISC, ESDMISC_MDDR_SETUP
-	write32	WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
-
-	/* Perform DDR init sequence */
-	write32	WEIM_ESDCTL0, ESDCTL_PRECHARGE
-	write32	CSD0_BASE | 0x0f00, 0x12344321
-	write32	WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
-	write32	CSD0_BASE, 0x12344321
-	write32	CSD0_BASE, 0x12344321
-	write32	WEIM_ESDCTL0, ESDCTL_LOADMODEREG
-	write8	CSD0_BASE | 0x00000033, 0xda
-	write8	CSD0_BASE | 0x01000000, 0xff
-	write32	WEIM_ESDCTL0, ESDCTL_RW
-	write32	CSD0_BASE, 0xDEADBEEF
-	write32	WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
-
-	mov	pc, lr
diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c
deleted file mode 100644
index 06fe51db717..00000000000
--- a/board/freescale/mx31pdk/mx31pdk.c
+++ /dev/null
@@ -1,119 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- *
- * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
- */
-
-
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-#include <watchdog.h>
-#include <power/pmic.h>
-#include <fsl_pmic.h>
-#include <errno.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_SPL_BUILD
-void board_init_f(ulong bootflag)
-{
-	/*
-	 * copy ourselves from where we are running to where we were
-	 * linked at. Use ulong pointers as all addresses involved
-	 * are 4-byte-aligned.
-	 */
-	ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
-	asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
-	asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
-	asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
-	asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
-	for (dst = start_ptr; dst < end_ptr; dst++)
-		*dst = *(dst+(run_ptr-link_ptr));
-	/*
-	 * branch to nand_boot's link-time address.
-	 */
-	asm volatile("ldr pc, =nand_boot");
-}
-#endif
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-				PHYS_SDRAM_1_SIZE);
-	return 0;
-}
-
-int board_early_init_f(void)
-{
-	/* CS5: CPLD incl. network controller */
-	static const struct mxc_weimcs cs5 = {
-		/*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-		CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  3, 24, 0,  4,  3),
-		/*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-		CSCR_L(2,  2,   2,   5,  2,  0,  5,  2,  0,  0,   0,   1),
-		/*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-		CSCR_A(2,   2,  2,  2,  0,  0,  2,  2,  0,  0,  0,  0,   0,  0)
-	};
-
-	mxc_setup_weimcs(5, &cs5);
-
-	/* Setup UART1 and SPI2 pins */
-	mx31_uart1_hw_init();
-	mx31_spi2_hw_init();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	u32 val;
-	struct pmic *p;
-	int ret;
-
-	ret = pmic_init(CONFIG_FSL_PMIC_BUS);
-	if (ret)
-		return ret;
-
-	p = pmic_get("FSL_PMIC");
-	if (!p)
-		return -ENODEV;
-	/* Enable RTC battery */
-	pmic_reg_read(p, REG_POWER_CTL0, &val);
-	pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
-	pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
-#ifdef CONFIG_HW_WATCHDOG
-	hw_watchdog_init();
-#endif
-	return 0;
-}
-
-int checkboard(void)
-{
-	printf("Board: MX31PDK\n");
-	return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC911X
-	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
-#endif
-	return rc;
-}
diff --git a/configs/mx31pdk_defconfig b/configs/mx31pdk_defconfig
deleted file mode 100644
index c4f01fc5bbe..00000000000
--- a/configs/mx31pdk_defconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-CONFIG_ARM=y
-# CONFIG_SPL_USE_ARCH_MEMCPY is not set
-# CONFIG_SPL_USE_ARCH_MEMSET is not set
-CONFIG_ARCH_MX31=y
-CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
-CONFIG_SYS_TEXT_BASE=0x87e00000
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x40000
-CONFIG_TARGET_MX31PDK=y
-CONFIG_SPL_TEXT_BASE=0x87dc0000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x60000
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_SUPPORT=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_SPI=y
-CONFIG_DEFAULT_SPI_BUS=1
-CONFIG_DEFAULT_SPI_MODE=4
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_MXC_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_MXC=y
-CONFIG_SMC911X=y
-CONFIG_SMC911X_BASE=0xB6000000
-CONFIG_SMC911X_32_BIT=y
-CONFIG_SPI=y
-CONFIG_MXC_SPI=y
diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
deleted file mode 100644
index f910d6199b2..00000000000
--- a/include/configs/mx31pdk.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
- *
- * (C) Copyright 2004
- * Texas Instruments.
- * Richard Woodruff <r-woodruff2@ti.com>
- * Kshitij Gupta <kshitij@ti.com>
- *
- * Configuration settings for the Freescale i.MX31 PDK board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-/* High Level Configuration Options */
-#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS
-
-#define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
-#define CONFIG_SPL_MAX_SIZE	2048
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE	UART1_BASE
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS	1
-#define CONFIG_FSL_PMIC_CS	2
-#define CONFIG_FSL_PMIC_CLK	1000000
-#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN	32
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"bootargs_base=setenv bootargs console=ttymxc0,115200\0"	\
-	"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "	\
-		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
-	"bootcmd=run bootcmd_net\0"					\
-	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
-		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
-	"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; "		\
-		"nand erase 0x0 0x40000; "				\
-		"nand write 0x81000000 0x0 0x40000\0"
-
-/*
- * Miscellaneous configurable options
- */
-
-/* memtest works on */
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x81000000
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define PHYS_SDRAM_1		CSD0_BASE
-#define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
-						CONFIG_SYS_INIT_RAM_SIZE)
-
-/*
- * environment organization
- */
-
-/*
- * NAND driver
- */
-#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
-#define CONFIG_MXC_NAND_HWECC
-#define CONFIG_SYS_NAND_LARGEPAGE
-
-/* NAND configuration for the NAND_SPL */
-
-/* Start copying real U-Boot from the second page */
-#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x3f800
-/* Load U-Boot to this address */
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_NAND_U_BOOT_DST
-
-#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
-#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
-#define CONFIG_SYS_NAND_PAGE_COUNT	64
-#define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
-
-/* Configuration of lowlevel_init.S (clocks and SDRAM) */
-#define CCM_CCMR_SETUP		0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ	(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
-				 PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) |    \
-				 PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) |    \
-				 PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ	(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |  \
-				 PLL_MFN(12))
-
-#define ESDMISC_MDDR_SETUP	0x00000004
-#define ESDMISC_MDDR_RESET_DL	0x0000000c
-#define ESDCFG0_MDDR_SETUP	0x006ac73a
-
-#define ESDCTL_ROW_COL		(ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
-#define ESDCTL_SETTINGS		(ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
-				 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
-#define ESDCTL_PRECHARGE	(ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
-#define ESDCTL_AUTOREFRESH	(ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
-#define ESDCTL_LOADMODEREG	(ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
-#define ESDCTL_RW		ESDCTL_SETTINGS
-
-#endif /* __CONFIG_H */