diff options
| author | Mike Frysinger | 2008-10-11 21:46:52 -0400 |
|---|---|---|
| committer | Mike Frysinger | 2009-02-05 21:25:35 -0500 |
| commit | 67619982bfc5cd62710a48e3cbffc304cb78c341 (patch) | |
| tree | bee4f08dabe3ad0f893fac71adf594de82ee9329 /cpu | |
| parent | 622a8dc0958dd599743348ea94eb10b9d0be8ae6 (diff) | |
Blackfin: check for reserved settings in DDR MMRs
Some bits of the DDR MMRs should not be set. If they do, bad things may
happen (like random failures or hardware destruction).
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/blackfin/initcode.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c index aafad10bdec..71f33759e00 100644 --- a/cpu/blackfin/initcode.c +++ b/cpu/blackfin/initcode.c @@ -168,11 +168,18 @@ static inline void serial_putc(char c) #ifndef CONFIG_EBIU_RSTCTL_VAL # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */ #endif +#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0) +# error invalid EBIU_RSTCTL value: must not set reserved bits +#endif #ifndef CONFIG_EBIU_MBSCTL_VAL # define CONFIG_EBIU_MBSCTL_VAL 0 #endif +#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0) +# error invalid EBIU_DDRQUE value: must not set reserved bits +#endif + /* Make sure our voltage value is sane so we don't blow up! */ #ifndef CONFIG_VR_CTL_VAL # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV) |