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-rw-r--r--include/ahci.h4
-rw-r--r--include/configs/MPC8349EMDS.h4
-rw-r--r--include/configs/MPC8349EMDS_SDRAM.h4
-rw-r--r--include/configs/MPC837XERDB.h2
-rw-r--r--include/configs/MPC8540ADS.h1
-rw-r--r--include/configs/MPC8560ADS.h1
-rw-r--r--include/configs/UCP1020.h809
-rw-r--r--include/configs/am64x_evm.h31
-rw-r--r--include/configs/j721e_evm.h2
-rw-r--r--include/configs/mv-common.h9
-rw-r--r--include/configs/omap3_evm.h45
-rw-r--r--include/configs/sifive-unmatched.h3
-rw-r--r--include/configs/xilinx_zynqmp.h2
-rw-r--r--include/efi_tcg2.h6
-rw-r--r--include/efi_variable.h6
-rw-r--r--include/environment/ti/k3_dfu.h4
-rw-r--r--include/environment/ti/mmc.h2
-rw-r--r--include/image.h28
-rw-r--r--include/mmc.h2
-rw-r--r--include/pci.h64
-rw-r--r--include/u-boot/md5.h6
21 files changed, 74 insertions, 961 deletions
diff --git a/include/ahci.h b/include/ahci.h
index fb96dd88611..d5453042d15 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -148,16 +148,12 @@ struct ahci_ioports {
* where dev is the controller (although at present it sometimes stands alone).
*/
struct ahci_uc_priv {
-#if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
/*
* TODO(sjg@chromium.org): Drop this once this structure is only used
* in a driver-model context (i.e. attached to a device with
* dev_get_uclass_priv()
*/
struct udevice *dev;
-#else
- pci_dev_t dev;
-#endif
struct ahci_ioports port[AHCI_MAX_PORTS];
u16 *ataid[AHCI_MAX_PORTS];
u32 n_ports;
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 2f1fc6a6a2b..dd11e9841e9 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -251,10 +251,6 @@
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index d6a151d20ce..2a53b14d0b2 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -308,10 +308,6 @@
#define CONFIG_SYS_SICRH 0
#define CONFIG_SYS_SICRL SICRL_LDP_A
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 0e2e034dcd9..26c6180d3a5 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -238,8 +238,6 @@
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 66cf2053f98..fc9d94984e2 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -26,7 +26,6 @@
#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
#endif
-#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
/*
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 22431436643..e1e0717991d 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -27,7 +27,6 @@
* assume U-Boot is less than 0.5MB
*/
-#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h
deleted file mode 100644
index 22b8c3f4e01..00000000000
--- a/include/configs/UCP1020.h
+++ /dev/null
@@ -1,809 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013-2019 Arcturus Networks, Inc.
- * https://www.arcturusnetworks.com/products/ucp1020/
- * based on include/configs/p1_p2_rdb_pc.h
- * original copyright follows:
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * QorIQ uCP1020-xx boards configuration file
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <linux/stringify.h>
-
-/*** Arcturus FirmWare Environment */
-
-#define MAX_SERIAL_SIZE 15
-#define MAX_HWADDR_SIZE 17
-
-#define MAX_FWENV_ADDR 4
-
-#define FWENV_MMC 1
-#define FWENV_SPI_FLASH 2
-#define FWENV_NOR_FLASH 3
-/*
- #define FWENV_TYPE FWENV_MMC
- #define FWENV_TYPE FWENV_SPI_FLASH
-*/
-#define FWENV_TYPE FWENV_NOR_FLASH
-
-#if (FWENV_TYPE == FWENV_MMC)
-#define FWENV_ADDR1 -1
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0
-#endif
-
-#if (FWENV_TYPE == FWENV_SPI_FLASH)
-#ifndef CONFIG_SF_DEFAULT_SPEED
-#define CONFIG_SF_DEFAULT_SPEED 1000000
-#endif
-#ifndef CONFIG_SF_DEFAULT_MODE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE0
-#endif
-#ifndef CONFIG_SF_DEFAULT_CS
-#define CONFIG_SF_DEFAULT_CS 0
-#endif
-#ifndef CONFIG_SF_DEFAULT_BUS
-#define CONFIG_SF_DEFAULT_BUS 0
-#endif
-#define FWENV_ADDR1 (0x200 - sizeof(smac))
-#define FWENV_ADDR2 (0x400 - sizeof(smac))
-#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
-#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
-#define EMPY_CHAR 0xff
-#endif
-
-#if (FWENV_TYPE == FWENV_NOR_FLASH)
-#define FWENV_ADDR1 0xEC080000
-#define FWENV_ADDR2 -1
-#define FWENV_ADDR3 -1
-#define FWENV_ADDR4 -1
-#define EMPY_CHAR 0xff
-#endif
-/***********************************/
-
-#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
-
-#if defined(CONFIG_TARTGET_UCP1020T1)
-
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
-#define CONFIG_IPADDR 10.80.41.229
-#define CONFIG_SERVERIP 10.80.41.227
-#define CONFIG_NETMASK 255.255.252.0
-#define CONFIG_ETHPRIME "eTSEC3"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#if defined(CONFIG_TARGET_UCP1020)
-
-#define CONFIG_UCP1020
-#define CONFIG_UCP1020_REV_1_3
-
-#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
-
-#define CONFIG_TSEC1
-#define CONFIG_TSEC3
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
-#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
-#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
-#define CONFIG_IPADDR 192.168.1.81
-#define CONFIG_IPADDR1 192.168.1.82
-#define CONFIG_IPADDR2 192.168.1.83
-#define CONFIG_SERVERIP 192.168.1.80
-#define CONFIG_GATEWAYIP 102.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_ETHPRIME "eTSEC1"
-
-#define CONFIG_SYS_L2_SIZE (256 << 10)
-
-#endif
-
-#ifdef CONFIG_SDCARD
-#define CONFIG_RAMBOOT_SDCARD
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_RAMBOOT_SPIFLASH
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
-#endif
-
-#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
-#endif
-
-#ifndef CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_SYS_SATA_MAX_DEVICE 2
-#define CONFIG_LBA48
-
-#define CONFIG_SYS_CLK_FREQ 66666666
-
-#define CONFIG_HWCONFIG
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE
-#define CONFIG_BTB
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-#define CONFIG_SYS_CCSRBAR 0xffe00000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
-
-/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
- SPL code*/
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
-#endif
-
-/* DDR Setup */
-#define CONFIG_SYS_SPD_BUS_NUM 1
-
-#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
-#define CONFIG_CHIP_SELECTS_PER_CTRL 1
-#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-
-/* Default settings for DDR3 */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
-#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
-#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
-#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
-
-#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
-#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
-
-#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
-#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
-#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
-#define CONFIG_SYS_DDR_RCW_1 0x00000000
-#define CONFIG_SYS_DDR_RCW_2 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
-#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
-#define CONFIG_SYS_DDR_TIMING_4 0x00220001
-#define CONFIG_SYS_DDR_TIMING_5 0x03402400
-
-#define CONFIG_SYS_DDR_TIMING_3 0x00020000
-#define CONFIG_SYS_DDR_TIMING_0 0x00330004
-#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
-#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
-#define CONFIG_SYS_DDR_MODE_1 0x40461520
-#define CONFIG_SYS_DDR_MODE_2 0x8000c000
-#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
-
-/*
- * Memory map
- *
- * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
- * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
- * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
- * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
- * (early boot only)
- * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
- * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
- * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
-#define CONFIG_SYS_FLASH_BASE 0xec000000
-
-#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
-
-#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
- | BR_PS_16 | BR_V)
-
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
-/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
-/* Size of used area in RAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
- GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
-
-#define CONFIG_SYS_PMC_BASE 0xff980000
-#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
-#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
- BR_PS_8 | BR_V)
-#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
- OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
- OR_GPCM_EAD)
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#ifdef CONFIG_NAND_FSL_ELBC
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
-#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
-
-#define CONFIG_RTC_DS1337
-#define CONFIG_RTC_DS1337_NOOSC
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
-#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
-#define CONFIG_SYS_I2C_IDT6V49205B 0x69
-
-#if defined(CONFIG_PCI)
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
-#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
-
-/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
-#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
-
-#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#endif /* CONFIG_PCI */
-
-/*
- * Environment
- */
-#if !defined(CONFIG_ENV_FIT_UCBOOT) && defined(CONFIG_RAMBOOT_SDCARD)
-#define CONFIG_FSL_FIXED_MMC_LOCATION
-#endif
-
-#define CONFIG_LOADS_ECHO /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
-
-/*
- * USB
- */
-#define CONFIG_HAS_FSL_DR_USB
-
-#if defined(CONFIG_HAS_FSL_DR_USB)
-#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_USB_EHCI_FSL
-#endif
-#endif
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#ifdef CONFIG_MMC
-#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
-#endif
-
-/* Misc Extra Settings */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
-#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3)
-#else
-#error "UCP1020 module revision is not defined !!!"
-#endif
-
-#define CONFIG_BOOTP_SERVERIP
-
-#define CONFIG_TSEC1_NAME "eTSEC1"
-#define CONFIG_TSEC2_NAME "eTSEC2"
-#define CONFIG_TSEC3_NAME "eTSEC3"
-
-#define TSEC1_PHY_ADDR 4
-#define TSEC2_PHY_ADDR 0
-#define TSEC2_PHY_ADDR_SGMII 0x00
-#define TSEC3_PHY_ADDR 6
-
-#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC3_PHYIDX 0
-
-#endif
-
-#define CONFIG_HOSTNAME "UCP1020"
-#define CONFIG_ROOTPATH "/opt/nfsroot"
-#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
-
-#if defined(CONFIG_DONGLE)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run prog_spi_mbrbootcramfs\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020d.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"mmbr=uCP1020Quiet.mbr\0" \
-"mmcpart=0:2\0" \
-"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "mmc erase 1 1; " \
- "mmc write $loadaddr 1 1\0" \
-"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
- "mmc erase 0x40 0x400; " \
- "mmc write $loadaddr 0x40 0x400\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"prog_spi_mbr=run spi__mbr\0" \
-"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
-"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
- "run spi__cramfs\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeFF80000 +$filesize; " \
- "erase 0xEFF80000 +$filesize; " \
- "cp.b $loadaddr 0xEFF80000 $filesize; " \
- "cmp.b $loadaddr 0xEFF80000 $filesize; " \
- "protect on 0xeFF80000 +$filesize\0" \
-"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
- "sf probe 0; sf erase 0x8000 +$filesize; " \
- "sf write $loadaddr 0x8000 $filesize\0" \
-"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
- "protect off 0xec0a0000 +$filesize; " \
- "erase 0xeC0A0000 +$filesize; " \
- "cp.b $loadaddr 0xeC0A0000 $filesize; " \
- "protect on 0xec0a0000 +$filesize\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 1; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"ubootd=u-boot4dongle.bin\0" \
-"upgrade=run flashworking\0" \
-"usb_phy_type=ulpi\0 " \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else
-
-#if defined(CONFIG_UCP1020T1)
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"cramfsfile=image.cramfs\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
- "protect off $nor_recoveryaddr +$filesize; " \
- "erase $nor_recoveryaddr +$filesize; " \
- "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
- "protect on $nor_recoveryaddr +$filesize\0 " \
-"flashuboot=tftp $ubootaddr $ubootfile; " \
- "protect off $nor_ubootaddr +$filesize; " \
- "erase $nor_ubootaddr +$filesize; " \
- "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
- "protect on $nor_ubootaddr +$filesize\0 " \
-"flashworking=tftp $workingaddr $cramfsfile; " \
- "protect off $nor_workingaddr +$filesize; " \
- "erase $nor_workingaddr +$filesize; " \
- "cp.b $workingaddr $nor_workingaddr $filesize; " \
- "protect on $nor_workingaddr +$filesize\0 " \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_recoveryaddr=0xEC0A0000\0" \
-"nor_ubootaddr=0xEFF80000\0" \
-"nor_workingaddr=0xECFA0000\0" \
-"norbootrecovery=setenv bootargs $recoverybootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadrecovery; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norbootworking=setenv bootargs $workingbootargs" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "run norloadworking; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_recoveryaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $nor_workingaddr; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"othbootargs=quiet\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"recoveryaddr=0x02F00000\0" \
-"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"silent=1\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootaddr=0x01000000\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashworking\0" \
-"workingaddr=0x02F00000\0" \
-"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
-
-#else /* For Arcturus Modules */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-"bootcmd=run norkernel\0" \
-"bootfile=uImage\0" \
-"consoledev=ttyS0\0" \
-"dtbaddr=0x00c00000\0" \
-"dtbfile=image.dtb\0" \
-"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
-"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
-"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
-"fileaddr=0x01000000\0" \
-"filesize=0x00080000\0" \
-"flashmbr=sf probe 0; " \
- "tftp $loadaddr $mbr; " \
- "sf erase $mbr_offset +$filesize; " \
- "sf write $loadaddr $mbr_offset $filesize\0" \
-"flashuboot=tftp $loadaddr $ubootfile; " \
- "protect off $nor_ubootaddr0 +$filesize; " \
- "erase $nor_ubootaddr0 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
- "protect on $nor_ubootaddr0 +$filesize; " \
- "protect off $nor_ubootaddr1 +$filesize; " \
- "erase $nor_ubootaddr1 +$filesize; " \
- "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
- "protect on $nor_ubootaddr1 +$filesize\0 " \
-"format0=protect off $part0base +$part0size; " \
- "erase $part0base +$part0size\0" \
-"format1=protect off $part1base +$part1size; " \
- "erase $part1base +$part1size\0" \
-"format2=protect off $part2base +$part2size; " \
- "erase $part2base +$part2size\0" \
-"format3=protect off $part3base +$part3size; " \
- "erase $part3base +$part3size\0" \
-"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
-"kerneladdr=0x01100000\0" \
-"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
-"kernelfile=uImage\0" \
-"loadaddr=0x01000000\0" \
-"mbr=uCP1020.mbr\0" \
-"mbr_offset=0x00000000\0" \
-"netdev=eth0\0" \
-"nor_ubootaddr0=0xEC000000\0" \
-"nor_ubootaddr1=0xEFF80000\0" \
-"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
- "run norkernelload; " \
- "bootm $kerneladdr - $dtbaddr\0" \
-"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
- "setenv cramfsaddr $part0base; " \
- "cramfsload $dtbaddr $dtbfile; " \
- "cramfsload $kerneladdr $kernelfile\0" \
-"part0base=0xEC100000\0" \
-"part0size=0x00700000\0" \
-"part1base=0xEC800000\0" \
-"part1size=0x02000000\0" \
-"part2base=0xEE800000\0" \
-"part2size=0x00800000\0" \
-"part3base=0xEF000000\0" \
-"part3size=0x00F80000\0" \
-"partENVbase=0xEC080000\0" \
-"partENVsize=0x00080000\0" \
-"program0=tftp part0-000000.bin; " \
- "protect off $part0base +$filesize; " \
- "erase $part0base +$filesize; " \
- "cp.b $loadaddr $part0base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part0base $filesize\0" \
-"program1=tftp part1-000000.bin; " \
- "protect off $part1base +$filesize; " \
- "erase $part1base +$filesize; " \
- "cp.b $loadaddr $part1base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part1base $filesize\0" \
-"program2=tftp part2-000000.bin; " \
- "protect off $part2base +$filesize; " \
- "erase $part2base +$filesize; " \
- "cp.b $loadaddr $part2base $filesize; " \
- "echo Verifying...; " \
- "cmp.b $loadaddr $part2base $filesize\0" \
-"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
- " console=$consoledev,$baudrate $othbootargs; " \
- "tftp $rootfsaddr $rootfsfile; " \
- "tftp $loadaddr $kernelfile; " \
- "tftp $dtbaddr $dtbfile; " \
- "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
-"ramdisk_size=120000\0" \
-"ramdiskfile=rootfs.ext2.gz.uboot\0" \
-"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
- "mw.l 0xffe0f008 0x00400000\0" \
-"rootfsaddr=0x02F00000\0" \
-"rootfsfile=rootfs.ext2.gz.uboot\0" \
-"rootpath=/opt/nfsroot\0" \
-"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
- "sf probe 0; sf erase 0 +$filesize; " \
- "sf write $loadaddr 0 $filesize\0" \
-"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
- "protect off 0xeC000000 +$filesize; " \
- "erase 0xEC000000 +$filesize; " \
- "cp.b $loadaddr 0xEC000000 $filesize; " \
- "cmp.b $loadaddr 0xEC000000 $filesize; " \
- "protect on 0xeC000000 +$filesize\0" \
-"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
-"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
-"ubootfile=u-boot.bin\0" \
-"upgrade=run flashuboot\0" \
-"usb_phy_type=ulpi\0 " \
-"boot_nfs= " \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_hd = " \
- "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "usb start;" \
- "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
- "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
- "bootm $loadaddr - $fdtaddr\0" \
-"boot_usb_fat = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "fatload usb 0:2 $loadaddr $bootfile;" \
- "fatload usb 0:2 $fdtaddr $fdtfile;" \
- "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_usb_ext2 = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "usb start;" \
- "ext2load usb 0:4 $loadaddr $bootfile;" \
- "ext2load usb 0:4 $fdtaddr $fdtfile;" \
- "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
-"boot_nor = " \
- "setenv bootargs root=/dev/$jffs2nor rw " \
- "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
- "bootm $norbootaddr - $norfdtaddr\0 " \
-"boot_ram = " \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs " \
- "ramdisk_size=$ramdisk_size;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
-
-#endif
-#endif
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
index 16d095584e0..99624081c3e 100644
--- a/include/configs/am64x_evm.h
+++ b/include/configs/am64x_evm.h
@@ -92,6 +92,34 @@
"${bootdir}/${name_fit}\0" \
"partitions=" PARTS_DEFAULT
+#define EXTRA_ENV_AM642_BOARD_SETTING_USBMSC \
+ "args_usb=run finduuid;setenv bootargs console=${console} " \
+ "${optargs} " \
+ "root=PARTUUID=${uuid} rw " \
+ "rootfstype=${mmcrootfstype}\0" \
+ "init_usb=run args_all args_usb\0" \
+ "get_fdt_usb=load usb ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "get_overlay_usb=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load usb ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
+ "fdt apply ${dtboaddr};" \
+ "done;\0" \
+ "get_kern_usb=load usb ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_usb=load usb ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "usbboot=setenv boot usb;" \
+ "setenv bootpart 0:2;" \
+ "usb start;" \
+ "run findfdt;" \
+ "run init_usb;" \
+ "run get_kern_usb;" \
+ "run get_fdt_usb;" \
+ "run run_kern\0"
+
#define EXTRA_ENV_DFUARGS \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
@@ -104,7 +132,8 @@
DEFAULT_MMC_TI_ARGS \
EXTRA_ENV_AM642_BOARD_SETTINGS \
EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \
- EXTRA_ENV_DFUARGS
+ EXTRA_ENV_DFUARGS \
+ EXTRA_ENV_AM642_BOARD_SETTING_USBMSC
/* Now for the remaining common defines */
#include <configs/ti_armv7_common.h>
diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h
index 18b80ef8ce7..10555d1a6ca 100644
--- a/include/configs/j721e_evm.h
+++ b/include/configs/j721e_evm.h
@@ -155,9 +155,7 @@
#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY
#endif
-/* set default dfu_bufsiz to 128KB (sector size of OSPI) */
#define EXTRA_ENV_DFUARGS \
- "dfu_bufsiz=0x20000\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_EMMC \
DFU_ALT_INFO_RAM \
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 65d7dd1430f..e460f69a087 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -39,6 +39,15 @@
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
#endif
+#if defined(CONFIG_ARMADA_38X) && !defined(CONFIG_SYS_BAUDRATE_TABLE)
+#define CONFIG_SYS_BAUDRATE_TABLE { 300, 600, 1200, 1800, 2400, 4800, \
+ 9600, 19200, 38400, 57600, 115200, \
+ 230400, 460800, 500000, 576000, \
+ 921600, 1000000, 1152000, 1500000, \
+ 2000000, 2500000, 3125000, 4000000, \
+ 5200000 }
+#endif
+
/* auto boot */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 52a22a97584..b12e3a40285 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -45,9 +45,6 @@
#endif /* CONFIG_SPL_OS_BOOT */
#endif /* CONFIG_MTD_RAW_NAND */
-#define MEM_LAYOUT_ENV_SETTINGS \
- DEFAULT_LINUX_BOOT_ENV
-
#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"setenv mmcdev " #instance "; " \
@@ -83,8 +80,12 @@
#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+
#define CONFIG_EXTRA_ENV_SETTINGS \
- MEM_LAYOUT_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
+ DEFAULT_FIT_TI_ARGS \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
@@ -97,42 +98,6 @@
"bootubivol=rootfs\0" \
"bootubipart=rootfs\0" \
"optargs=\0" \
- "mmcdev=0\0" \
- "mmcpart=2\0" \
- "mmcroot=/dev/mmcblk0p2 rw\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${mtdparts} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \
- "env import -t ${loadaddr} ${filesize}\0" \
- "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \
- "mmc dev ${mmcdev}; " \
- "if mmc rescan; then " \
- "run loadbootenv && run importbootenv; " \
- "run ext4bootenv && run importbootenv; " \
- "if test -n $uenvcmd; then " \
- "echo Running uenvcmd ...; " \
- "run uenvcmd; " \
- "fi; " \
- "fi\0" \
- "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
- "loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
- "mmcboot=run mmcbootenv; " \
- "if run loadimage && run loaddtb; then " \
- "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \
- "run mmcargs; " \
- "if test ${bootfile} = uImage; then " \
- "bootm ${loadaddr} - ${fdtaddr}; " \
- "fi; " \
- "if test ${bootfile} = zImage; then " \
- "bootz ${loadaddr} - ${fdtaddr}; " \
- "fi; " \
- "fi\0" \
"nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \
"nandrootfstype=ubifs rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 538cce414c6..f68d7d7676f 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -34,6 +34,8 @@
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
+
/* Environment options */
#ifndef CONFIG_SPL_BUILD
@@ -41,6 +43,7 @@
func(NVME, nvme, 0) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
+ func(SCSI, scsi, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 251a6c9d8e2..e10d90cdc77 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -253,7 +253,7 @@
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU)
# define CONFIG_SPL_ENV_SUPPORT
-# define CONFIG_SPL_HASH_SUPPORT
+# define CONFIG_SPL_HASH
# define CONFIG_ENV_MAX_ENTRIES 10
#endif
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index b6b958da514..5a1a36212e5 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -28,6 +28,8 @@
#define EFI_TCG2_EXTEND_ONLY 0x0000000000000001
#define PE_COFF_IMAGE 0x0000000000000010
+#define EFI_TCG2_MAX_PCR_INDEX 23
+
/* Algorithm Registry */
#define EFI_TCG2_BOOT_HASH_ALG_SHA1 0x00000001
#define EFI_TCG2_BOOT_HASH_ALG_SHA256 0x00000002
@@ -127,8 +129,8 @@ struct efi_tcg2_boot_service_capability {
efi_tcg_event_algorithm_bitmap active_pcr_banks;
};
-#define boot_service_capability_min \
- sizeof(struct efi_tcg2_boot_service_capability) - \
+/* up to and including the vendor ID (manufacturer_id) field */
+#define BOOT_SERVICE_CAPABILITY_MIN \
offsetof(struct efi_tcg2_boot_service_capability, number_of_pcr_banks)
#define TCG_EFI_SPEC_ID_EVENT_SIGNATURE_03 "Spec ID Event03"
diff --git a/include/efi_variable.h b/include/efi_variable.h
index 4623a641427..0440d356bc8 100644
--- a/include/efi_variable.h
+++ b/include/efi_variable.h
@@ -12,6 +12,7 @@
enum efi_auth_var_type {
EFI_AUTH_VAR_NONE = 0,
+ EFI_AUTH_MODE,
EFI_AUTH_VAR_PK,
EFI_AUTH_VAR_KEK,
EFI_AUTH_VAR_DB,
@@ -161,10 +162,13 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *
/**
* efi_var_restore() - restore EFI variables from buffer
*
+ * Only if @safe is set secure boot related variables will be restored.
+ *
* @buf: buffer
+ * @safe: restoring from tamper-resistant storage
* Return: status code
*/
-efi_status_t efi_var_restore(struct efi_var_file *buf);
+efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe);
/**
* efi_var_from_file() - read variables from file
diff --git a/include/environment/ti/k3_dfu.h b/include/environment/ti/k3_dfu.h
index 2f503b8de88..a16a3adecaf 100644
--- a/include/environment/ti/k3_dfu.h
+++ b/include/environment/ti/k3_dfu.h
@@ -40,7 +40,7 @@
#define DFU_ALT_INFO_RAM \
"dfu_alt_info_ram=" \
- "tispl.bin ram 0x80080000 0x100000;" \
- "u-boot.img ram 0x81000000 0x100000\0" \
+ "tispl.bin ram 0x80080000 0x200000;" \
+ "u-boot.img ram 0x81000000 0x400000\0" \
#endif /* __TI_DFU_H */
diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h
index b86c8dc7a4f..769ea9d5ef7 100644
--- a/include/environment/ti/mmc.h
+++ b/include/environment/ti/mmc.h
@@ -11,7 +11,7 @@
#define DEFAULT_MMC_TI_ARGS \
"mmcdev=0\0" \
"mmcrootfstype=ext4 rootwait\0" \
- "finduuid=part uuid mmc ${bootpart} uuid\0" \
+ "finduuid=part uuid ${boot} ${bootpart} uuid\0" \
"args_mmc=run finduuid;setenv bootargs console=${console} " \
"${optargs} " \
"root=PARTUUID=${uuid} rw " \
diff --git a/include/image.h b/include/image.h
index e20f0b69d58..73a763a6936 100644
--- a/include/image.h
+++ b/include/image.h
@@ -31,9 +31,7 @@ struct fdt_region;
#define IMAGE_ENABLE_OF_LIBFDT 1
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
#define CONFIG_FIT_RSASSA_PSS 1
-#define CONFIG_FIT_SHA256
-#define CONFIG_FIT_SHA384
-#define CONFIG_FIT_SHA512
+#define CONFIG_MD5
#define CONFIG_SHA1
#define CONFIG_SHA256
#define CONFIG_SHA384
@@ -62,26 +60,6 @@ struct fdt_region;
#include <hash.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
-# ifdef CONFIG_SPL_BUILD
-# ifdef CONFIG_SPL_CRC32
-# define IMAGE_ENABLE_CRC32 1
-# endif
-# ifdef CONFIG_SPL_MD5
-# define IMAGE_ENABLE_MD5 1
-# endif
-# else
-# define IMAGE_ENABLE_CRC32 1
-# define IMAGE_ENABLE_MD5 1
-# endif
-
-#ifndef IMAGE_ENABLE_CRC32
-#define IMAGE_ENABLE_CRC32 0
-#endif
-
-#ifndef IMAGE_ENABLE_MD5
-#define IMAGE_ENABLE_MD5 0
-#endif
-
#endif /* IMAGE_ENABLE_FIT */
#ifdef CONFIG_SYS_BOOT_GET_CMDLINE
@@ -1334,6 +1312,10 @@ struct padding_algo {
const uint8_t *hash, int hash_len);
};
+/* Declare a new U-Boot padding algorithm handler */
+#define U_BOOT_PADDING_ALGO(__name) \
+ll_entry_declare(struct padding_algo, __name, paddings)
+
/**
* image_get_checksum_algo() - Look up a checksum algorithm
*
diff --git a/include/mmc.h b/include/mmc.h
index 0bf19de20e5..b92e2553402 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -726,6 +726,8 @@ struct mmc {
*/
u32 quirks;
u8 hs400_tuning;
+
+ enum bus_mode user_speed_mode; /* input speed mode from user */
};
#if CONFIG_IS_ENABLED(DM_MMC)
diff --git a/include/pci.h b/include/pci.h
index 4d771133b2a..0fc22adffd0 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -623,13 +623,9 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev
* about a small subset of PCI devices. This is normally false.
*/
struct pci_controller {
-#ifdef CONFIG_DM_PCI
struct udevice *bus;
struct udevice *ctlr;
bool skip_auto_config_until_reloc;
-#else
- struct pci_controller *next;
-#endif
int first_busno;
int last_busno;
@@ -655,54 +651,12 @@ struct pci_controller {
struct pci_config_table *config_table;
void (*fixup_irq)(struct pci_controller *, pci_dev_t);
-#ifndef CONFIG_DM_PCI
- /* Low-level architecture-dependent routines */
- int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
- int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
- int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
- int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
- int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
- int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
-#endif
/* Used by auto config */
struct pci_region *pci_mem, *pci_io, *pci_prefetch;
-
-#ifndef CONFIG_DM_PCI
- int current_busno;
-
- void *priv_data;
-#endif
};
-#ifndef CONFIG_DM_PCI
-static inline void pci_set_ops(struct pci_controller *hose,
- int (*read_byte)(struct pci_controller*,
- pci_dev_t, int where, u8 *),
- int (*read_word)(struct pci_controller*,
- pci_dev_t, int where, u16 *),
- int (*read_dword)(struct pci_controller*,
- pci_dev_t, int where, u32 *),
- int (*write_byte)(struct pci_controller*,
- pci_dev_t, int where, u8),
- int (*write_word)(struct pci_controller*,
- pci_dev_t, int where, u16),
- int (*write_dword)(struct pci_controller*,
- pci_dev_t, int where, u32)) {
- hose->read_byte = read_byte;
- hose->read_word = read_word;
- hose->read_dword = read_dword;
- hose->write_byte = write_byte;
- hose->write_word = write_word;
- hose->write_dword = write_dword;
-}
-#endif
-
-#ifdef CONFIG_PCI_INDIRECT_BRIDGE
-extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
-#endif
-
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
pci_addr_t addr, unsigned long flags);
extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
@@ -752,15 +706,6 @@ extern int pci_hose_write_config_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u32 val);
#endif
-#ifndef CONFIG_DM_PCI
-extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
-extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
-extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
-extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
-extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
-extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
-#endif
-
void pciauto_region_init(struct pci_region *res);
void pciauto_region_align(struct pci_region *res, pci_size_t size);
void pciauto_config_init(struct pci_controller *hose);
@@ -780,7 +725,7 @@ void pciauto_config_init(struct pci_controller *hose);
int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
pci_addr_t *bar, bool supports_64bit);
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
pci_dev_t dev, int where, u8 *val);
extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
@@ -827,7 +772,7 @@ int pci_find_next_ext_capability(struct pci_controller *hose,
int pci_hose_find_ext_capability(struct pci_controller *hose,
pci_dev_t dev, int cap);
-#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
+#endif /* defined(CONFIG_DM_PCI_COMPAT) */
const char * pci_class_str(u8 class);
int pci_last_busno(void);
@@ -890,7 +835,6 @@ enum pci_size_t {
struct udevice;
-#ifdef CONFIG_DM_PCI
/**
* struct pci_child_plat - information stored about each PCI device
*
@@ -1691,8 +1635,6 @@ int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
*/
extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
-#endif /* CONFIG_DM_PCI */
-
/**
* PCI_DEVICE - macro used to describe a specific pci device
* @vend: the 16 bit PCI Vendor ID
diff --git a/include/u-boot/md5.h b/include/u-boot/md5.h
index e5cb923d770..d61364c0ae3 100644
--- a/include/u-boot/md5.h
+++ b/include/u-boot/md5.h
@@ -8,6 +8,8 @@
#include "compiler.h"
+#define MD5_SUM_LEN 16
+
struct MD5Context {
__u32 buf[4];
__u32 bits[2];
@@ -32,7 +34,7 @@ void md5 (unsigned char *input, int len, unsigned char output[16]);
* 'output' must have enough space to hold 16 bytes. If 'chunk' Trigger the
* watchdog every 'chunk_sz' bytes of input processed.
*/
-void md5_wd (unsigned char *input, int len, unsigned char output[16],
- unsigned int chunk_sz);
+void md5_wd(const unsigned char *input, unsigned int len,
+ unsigned char output[16], unsigned int chunk_sz);
#endif /* _MD5_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 21:22:07 +0000