diff options
| author | Mugunthan V N | 2017-04-07 13:42:00 +0200 |
|---|---|---|
| committer | Simon Glass | 2017-04-14 19:38:57 -0600 |
| commit | 01a072c6cf0539e7b8e78cce7f1f53884121646a (patch) | |
| tree | f0eba8cdb29569344f03edf18156c26e0969b3a3 | |
| parent | fbeb33752999e7317113199ef89873d6b6916814 (diff) | |
arm: omap: sata: move enable sata clocks to enable_basic_clocks()
All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | arch/arm/mach-omap2/omap5/hw_data.c | 12 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/sata.c | 23 |
2 files changed, 12 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 5d956b5b14a..a8a6b8a869e 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -361,6 +361,9 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, +#ifdef CONFIG_SCSI_AHCI_PLAT + (*prcm)->cm_l3init_ocp2scp3_clkctrl, +#endif 0 }; @@ -379,6 +382,9 @@ void enable_basic_clocks(void) #ifdef CONFIG_TI_QSPI (*prcm)->cm_l4per_qspi_clkctrl, #endif +#ifdef CONFIG_SCSI_AHCI_PLAT + (*prcm)->cm_l3init_sata_clkctrl, +#endif 0 }; @@ -411,6 +417,12 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); #endif +#ifdef CONFIG_SCSI_AHCI_PLAT + /* Enable optional functional clock for SATA */ + setbits_le32((*prcm)->cm_l3init_sata_clkctrl, + SATA_CLKCTRL_OPTFCLKEN_MASK); +#endif + /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c index 2c2d1bce363..0c8268905aa 100644 --- a/arch/arm/mach-omap2/sata.c +++ b/arch/arm/mach-omap2/sata.c @@ -37,29 +37,6 @@ int init_sata(int dev) int ret; u32 val; - u32 const clk_domains_sata[] = { - 0 - }; - - u32 const clk_modules_hw_auto_sata[] = { - (*prcm)->cm_l3init_ocp2scp3_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_sata[] = { - (*prcm)->cm_l3init_sata_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_sata, - clk_modules_hw_auto_sata, - clk_modules_explicit_en_sata, - 0); - - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; /* Power up the PHY */ |