i2c: ihs_i2c: Dual channel support

Support two i2c masters per FPGA.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Acked-by: Heiko Schocher <hs@denx.de>

3 files changed, 79 insertions, 18 deletions

diff --git a/README b/README
index ef8d437fbd4..e98c49b6b7a 100644
--- a/README
+++ b/README
@@ -2438,6 +2438,15 @@ CBFS (Coreboot Filesystem) support
 		  - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3
 		  - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3
 		  - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3
+		  - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL
+		  - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1
+		  - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1
+		  - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1
 
 		additional defines:
 
diff --git a/drivers/i2c/ihs_i2c.c b/drivers/i2c/ihs_i2c.c
index 19fbe596f4b..737beaf2183 100644
--- a/drivers/i2c/ihs_i2c.c
+++ b/drivers/i2c/ihs_i2c.c
@@ -11,6 +11,28 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+#define I2C_SET_REG(fld, val) \
+	{ if (I2C_ADAP_HWNR & 0x10) \
+		FPGA_SET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
+	else \
+		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
+#else
+#define I2C_SET_REG(fld, val) \
+		FPGA_SET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
+#endif
+
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+#define I2C_GET_REG(fld, val) \
+	{ if (I2C_ADAP_HWNR & 0x10) \
+		FPGA_GET_REG(I2C_ADAP_HWNR & 0xf, i2c1.fld, val); \
+	else \
+		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val); }
+#else
+#define I2C_GET_REG(fld, val) \
+		FPGA_GET_REG(I2C_ADAP_HWNR, i2c0.fld, val);
+#endif
+
 enum {
 	I2CINT_ERROR_EV = 1 << 13,
 	I2CINT_TRANSMIT_EV = 1 << 14,
@@ -29,14 +51,14 @@ static int wait_for_int(bool read)
 	u16 val;
 	unsigned int ctr = 0;
 
-	FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+	I2C_GET_REG(interrupt_status, &val);
 	while (!(val & (I2CINT_ERROR_EV
 	       | (read ? I2CINT_RECEIVE_EV : I2CINT_TRANSMIT_EV)))) {
 		udelay(10);
 		if (ctr++ > 5000) {
 			return 1;
 		}
-		FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+		I2C_GET_REG(interrupt_status, &val);
 	}
 
 	return (val & I2CINT_ERROR_EV) ? 1 : 0;
@@ -47,30 +69,30 @@ static int ihs_i2c_transfer(uchar chip, uchar *buffer, int len, bool read,
 {
 	u16 val;
 
-	FPGA_SET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, I2CINT_ERROR_EV
+	I2C_SET_REG(interrupt_status, I2CINT_ERROR_EV
 		     | I2CINT_RECEIVE_EV | I2CINT_TRANSMIT_EV);
-	FPGA_GET_REG(I2C_ADAP_HWNR, i2c.interrupt_status, &val);
+	I2C_GET_REG(interrupt_status, &val);
 
 	if (!read && len) {
 		val = buffer[0];
 
 		if (len > 1)
 			val |= buffer[1] << 8;
-		FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox_ext, val);
+		I2C_SET_REG(write_mailbox_ext, val);
 	}
 
-	FPGA_SET_REG(I2C_ADAP_HWNR, i2c.write_mailbox,
-		     I2CMB_NATIVE
-		     | (read ? 0 : I2CMB_WRITE)
-		     | (chip << 1)
-		     | ((len > 1) ? I2CMB_2BYTE : 0)
-		     | (is_last ? 0 : I2CMB_HOLD_BUS));
+	I2C_SET_REG(write_mailbox,
+		    I2CMB_NATIVE
+		    | (read ? 0 : I2CMB_WRITE)
+		    | (chip << 1)
+		    | ((len > 1) ? I2CMB_2BYTE : 0)
+		    | (is_last ? 0 : I2CMB_HOLD_BUS));
 
 	if (wait_for_int(read))
 		return 1;
 
 	if (read) {
-		FPGA_GET_REG(I2C_ADAP_HWNR, i2c.read_mailbox_ext, &val);
+		I2C_GET_REG(read_mailbox_ext, &val);
 		buffer[0] = val & 0xff;
 		if (len > 1)
 			buffer[1] = val >> 8;
@@ -163,7 +185,7 @@ static int ihs_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 }
 
 static unsigned int ihs_i2c_set_bus_speed(struct i2c_adapter *adap,
-					     unsigned int speed)
+					  unsigned int speed)
 {
 	if (speed != adap->speed)
 		return 1;
@@ -179,6 +201,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs0, ihs_i2c_init, ihs_i2c_probe,
 			 ihs_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_IHS_SPEED_0,
 			 CONFIG_SYS_I2C_IHS_SLAVE_0, 0)
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+U_BOOT_I2C_ADAP_COMPLETE(ihs0_1, ihs_i2c_init, ihs_i2c_probe,
+			 ihs_i2c_read, ihs_i2c_write,
+			 ihs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_IHS_SPEED_0_1,
+			 CONFIG_SYS_I2C_IHS_SLAVE_0_1, 16)
+#endif
 #endif
 #ifdef CONFIG_SYS_I2C_IHS_CH1
 U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
@@ -186,6 +215,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs1, ihs_i2c_init, ihs_i2c_probe,
 			 ihs_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_IHS_SPEED_1,
 			 CONFIG_SYS_I2C_IHS_SLAVE_1, 1)
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+U_BOOT_I2C_ADAP_COMPLETE(ihs1_1, ihs_i2c_init, ihs_i2c_probe,
+			 ihs_i2c_read, ihs_i2c_write,
+			 ihs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_IHS_SPEED_1_1,
+			 CONFIG_SYS_I2C_IHS_SLAVE_1_1, 17)
+#endif
 #endif
 #ifdef CONFIG_SYS_I2C_IHS_CH2
 U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
@@ -193,6 +229,13 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs2, ihs_i2c_init, ihs_i2c_probe,
 			 ihs_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_IHS_SPEED_2,
 			 CONFIG_SYS_I2C_IHS_SLAVE_2, 2)
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+U_BOOT_I2C_ADAP_COMPLETE(ihs2_1, ihs_i2c_init, ihs_i2c_probe,
+			 ihs_i2c_read, ihs_i2c_write,
+			 ihs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_IHS_SPEED_2_1,
+			 CONFIG_SYS_I2C_IHS_SLAVE_2_1, 18)
+#endif
 #endif
 #ifdef CONFIG_SYS_I2C_IHS_CH3
 U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
@@ -200,4 +243,11 @@ U_BOOT_I2C_ADAP_COMPLETE(ihs3, ihs_i2c_init, ihs_i2c_probe,
 			 ihs_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_IHS_SPEED_3,
 			 CONFIG_SYS_I2C_IHS_SLAVE_3, 3)
+#ifdef CONFIG_SYS_I2C_IHS_DUAL
+U_BOOT_I2C_ADAP_COMPLETE(ihs3_1, ihs_i2c_init, ihs_i2c_probe,
+			 ihs_i2c_read, ihs_i2c_write,
+			 ihs_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_IHS_SPEED_3_1,
+			 CONFIG_SYS_I2C_IHS_SLAVE_3_1, 19)
+#endif
 #endif
diff --git a/include/gdsys_fpga.h b/include/gdsys_fpga.h
index 8a5efe732ad..f8d8322d591 100644
--- a/include/gdsys_fpga.h
+++ b/include/gdsys_fpga.h
@@ -143,7 +143,7 @@ struct ihs_fpga {
 	u16 reserved_2[2];	/* 0x001c */
 	struct ihs_io_ep ep;	/* 0x0020 */
 	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c;	/* 0x0040 */
+	struct ihs_i2c i2c0;	/* 0x0040 */
 	u16 reserved_4[10];	/* 0x004c */
 	u16 mc_int;		/* 0x0060 */
 	u16 mc_int_en;		/* 0x0062 */
@@ -177,7 +177,7 @@ struct ihs_fpga {
 	u16 reserved_2[2];	/* 0x001c */
 	struct ihs_io_ep ep;	/* 0x0020 */
 	u16 reserved_3[9];	/* 0x002e */
-	struct ihs_i2c i2c;	/* 0x0040 */
+	struct ihs_i2c i2c0;	/* 0x0040 */
 	u16 reserved_4[10];	/* 0x004c */
 	u16 mc_int;		/* 0x0060 */
 	u16 mc_int_en;		/* 0x0062 */
@@ -208,10 +208,12 @@ struct ihs_fpga {
 	u16 reserved_1[29];	/* 0x001e */
 	u16 mpc3w_control;	/* 0x0058 */
 	u16 reserved_2[3];	/* 0x005a */
-	struct ihs_i2c i2c;	/* 0x0060 */
-	u16 reserved_3[205];	/* 0x0066 */
+	struct ihs_i2c i2c0;	/* 0x0060 */
+	u16 reserved_3[2];	/* 0x006c */
+	struct ihs_i2c i2c1;	/* 0x0070 */
+	u16 reserved_4[194];	/* 0x007c */
 	struct ihs_osd osd;	/* 0x0200 */
-	u16 reserved_4[761];	/* 0x020e */
+	u16 reserved_5[761];	/* 0x020e */
 	u16 videomem[31736];	/* 0x0800 */
 };
 #endif