diff options
| author | Bryan Brattlof | 2022-06-21 16:36:03 -0500 |
|---|---|---|
| committer | Tom Rini | 2022-07-06 14:30:51 -0400 |
| commit | 10c8bafbc3cd9a6434318b82b64444488b7dd677 (patch) | |
| tree | 8e648ee8a11b64aa1bee55d3cfcc34e3a794367c | |
| parent | fdd08f896bcfc513a4cb7799d0094e4fabc73531 (diff) | |
soc: soc_ti_k3: identify j7200 SR2.0 SoCs
Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.
Rather than defining a revision string array for each SoC, use a
default revision string array for all TI SoCs that continue to follow
the typical 1.0 -> 2.0 revision scheme.
Signed-off-by: Bryan Brattlof <bb@ti.com>
| -rw-r--r-- | drivers/soc/soc_ti_k3.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c index 42344145f9f..b1e7c4ae5f6 100644 --- a/drivers/soc/soc_ti_k3.c +++ b/drivers/soc/soc_ti_k3.c @@ -64,8 +64,8 @@ static char *j721e_rev_string_map[] = { "1.0", "1.1", }; -static char *am65x_rev_string_map[] = { - "1.0", "2.0", +static char *typical_rev_string_map[] = { + "1.0", "2.0", "3.0", }; static const char *get_rev_string(u32 idreg) @@ -82,16 +82,10 @@ static const char *get_rev_string(u32 idreg) goto bail; return j721e_rev_string_map[rev]; - case AM65X: - if (rev > ARRAY_SIZE(am65x_rev_string_map)) - goto bail; - return am65x_rev_string_map[rev]; - - case AM64X: - case J7200: default: - if (!rev) - return "1.0"; + if (rev > ARRAY_SIZE(typical_rev_string_map)) + goto bail; + return typical_rev_string_map[rev]; }; bail: |