diff options
| author | Rasmus Villemoes | 2021-09-16 16:53:14 +0200 |
|---|---|---|
| committer | Tom Rini | 2021-09-28 12:03:21 -0400 |
| commit | 24ea366add54b8ca753eb3259bff8b50693dc8ef (patch) | |
| tree | 1fa564e36db8678724af5817e5163060f2852d54 | |
| parent | b8919eaa6835c8a606569ea596dd4ed209bd1d67 (diff) | |
imx: imx7d-sdb: fix ethernet, sync .dts with linux
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).
I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb3 (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.
Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.
Without this, one gets
Net: Could not get PHY for FEC0: addr 0
No ethernet found.
With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
| -rw-r--r-- | arch/arm/dts/imx7d-sdb.dts | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 8191ac7c334..ea2e58dd5aa 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -44,9 +44,9 @@ compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; |