diff options
| author | Jacky Bai | 2019-06-05 11:26:12 +0800 |
|---|---|---|
| committer | Peng Fan | 2020-07-14 15:23:46 +0800 |
| commit | 355c620666c205b55164aeb16f86b775f8c5d1fd (patch) | |
| tree | efd13459d7738348989161b40dc1eab5c82b6e8f | |
| parent | 497c7598c4e713eb9ad88fd7963e57b21b8b35e1 (diff) | |
driver: ddr: imx: skip ddr_ss_gpr config on imx8mn
There is no DDR_SS_GPR0 exits on i.MX8MN, so skip setting
this register on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | drivers/ddr/imx/imx8m/ddr_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index bbddee6ca89..1c5c7f99cff 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -74,7 +74,7 @@ int ddr_init(struct dram_timing_info *dram_timing) /* if ddr type is LPDDR4, do it */ tmp = reg32_read(DDRC_MSTR(0)); - if (tmp & (0x1 << 5)) + if (tmp & (0x1 << 5) && !is_imx8mn()) reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */ /* determine the initial boot frequency */ |