diff options
| author | Andre Przywara | 2022-12-02 20:30:40 +0000 |
|---|---|---|
| committer | Andre Przywara | 2023-10-22 23:41:51 +0100 |
| commit | 39ba474698bb4bc3dc48fd0c024f7cf06b08077a (patch) | |
| tree | 9388def037d809f9fd4cc60eb8e467a1fb0b8421 | |
| parent | b9a91b98e8d81d2f7fdbc0d59c544a7bbb5e3679 (diff) | |
sunxi: clock: D1/R528: Enable PLL LDO during PLL1 setup
The D1/R528/T113s SoCs introduce a new "LDO enable" bit in the CPUX_PLL.
Just enable that when we program that PLL.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-sunxi/clock_sun50i_h6.c | 12 |
2 files changed, 8 insertions, 5 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index 37df4410eaa..9895c2c220e 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h @@ -228,6 +228,7 @@ struct sunxi_ccm_reg { /* pll1 bit field */ #define CCM_PLL1_CTRL_EN BIT(31) +#define CCM_PLL1_LDO_EN BIT(30) #define CCM_PLL1_LOCK_EN BIT(29) #define CCM_PLL1_LOCK BIT(28) #define CCM_PLL1_OUT_EN BIT(27) diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 767a39fa2ab..d32e33465f5 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -89,11 +89,13 @@ void clock_set_pll1(unsigned int clk) writel(val, &ccm->cpu_axi_cfg); /* clk = 24*n/p, p is ignored if clock is >288MHz */ - writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 | -#ifdef CONFIG_MACH_SUN50I_H616 - CCM_PLL1_OUT_EN | -#endif - CCM_PLL1_CTRL_N(clk / 24000000), &ccm->pll1_cfg); + val = CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2; + val |= CCM_PLL1_CTRL_N(clk / 24000000); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) + val |= CCM_PLL1_OUT_EN; + if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) + val |= CCM_PLL1_OUT_EN | CCM_PLL1_LDO_EN; + writel(val, &ccm->pll1_cfg); while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {} /* Switch CPU to PLL1 */ |