diff options
| author | Frank Wunderlich | 2023-08-03 20:00:01 +0200 |
|---|---|---|
| committer | Tom Rini | 2023-08-17 16:39:20 -0400 |
| commit | 44bab4366fe12188003bc38c585d9f02967cbae7 (patch) | |
| tree | 1e05f4f7a237fbdfbbddac30926043188db720c3 | |
| parent | 3139a77c6028273a2a9e387285982b3f05cd4ec7 (diff) | |
arm: mediatek: add usb support for MT7988
MT7988 has a t-phy and an x-phy controller. There is already a driver for
t-phy so we can add USB support for this phy type.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
| -rw-r--r-- | arch/arm/dts/mt7988.dtsi | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi index ddd629e8c99..ac476d5cdd7 100644 --- a/arch/arm/dts/mt7988.dtsi +++ b/arch/arm/dts/mt7988.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/mt7988-clk.h> #include <dt-bindings/reset/mt7988-reset.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> / { compatible = "mediatek,mt7988-rfb"; @@ -161,6 +162,65 @@ #clock-cells = <1>; }; + dummy_clk: dummy12m { + compatible = "fixed-clock"; + clock-frequency = <12000000>; + #clock-cells = <0>; + /* must need this line, or uart uanable to get dummy_clk */ + bootph-all; + }; + + xhci1: xhci@11200000 { + compatible = "mediatek,mt7988-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + phys = <&tphyu2port0 PHY_TYPE_USB2>, + <&tphyu3port0 PHY_TYPE_USB3>; + clocks = <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>, + <&dummy_clk>; + clock-names = "sys_ck", + "xhci_ck", + "ref_ck", + "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + status = "okay"; + }; + + usbtphy: usb-phy@11c50000 { + compatible = "mediatek,mt7988", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + tphyu2port0: usb-phy@11c50000 { + reg = <0 0x11c50000 0 0x700>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + tphyu3port0: usb-phy@11c50700 { + reg = <0 0x11c50700 0 0x900>; + clocks = <&dummy_clk>; + clock-names = "ref"; + #phy-cells = <1>; + mediatek,usb3-pll-ssc-delta; + mediatek,usb3-pll-ssc-delta1; + status = "okay"; + }; + }; + xfi_pextp0: syscon@11f20000 { compatible = "mediatek,mt7988-xfi_pextp_0", "syscon"; reg = <0 0x11f20000 0 0x10000>; |