Merge branch 'master' of git://www.denx.de/git/u-boot-imx

author: Tom Rini 2016-11-30 09:57:52 -0500
committer: Tom Rini 2016-11-30 09:57:52 -0500
commit: 4d6647ab17ab9d33c60f7a9f07576c5fbdf6336f (patch)
tree: e3bde11276fcf8ce1c02d797a71fa23d974c66f3
parent: 6b29a395b62965eef6b5065d3a526a8588a92038 (diff)
parent: 4db4d42ee290a8cad00b358b2e7ef6a00483893b (diff)
48 files changed, 2144 insertions, 157 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fcbf1d81f40..3d009482abc 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -575,6 +575,11 @@ config ARCH_SUNXI
 	select USB_KEYBOARD if DISTRO_DEFAULTS
 	select USE_TINY_PRINTF
 
+config TARGET_TS4600
+	bool "Support TS4600"
+	select CPU_ARM926EJS
+	select SUPPORT_SPL
+
 config TARGET_TS4800
 	bool "Support TS4800"
 	select CPU_V7
@@ -1026,6 +1031,7 @@ source "board/ti/ti816x/Kconfig"
 source "board/timll/devkit3250/Kconfig"
 source "board/toradex/colibri_pxa270/Kconfig"
 source "board/toradex/colibri_vf/Kconfig"
+source "board/technologic/ts4600/Kconfig"
 source "board/technologic/ts4800/Kconfig"
 source "board/vscom/baltos/Kconfig"
 source "board/woodburn/Kconfig"
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a5814d7d..8c96ba37c39 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,6 +35,14 @@ config MX6ULL
 	bool
 	select MX6UL
 
+config MX6_DDRCAL
+	bool "Include dynamic DDR calibration routines"
+	depends on SPL
+	default n
+	help
+	  Say "Y" if your board uses dynamic (per-boot) DDR calibration.
+	  If unsure, say N.
+
 choice
 	prompt "MX6 board select"
 	optional
@@ -192,6 +200,16 @@ config TARGET_UDOO
 	bool "udoo"
 	select SUPPORT_SPL
 
+config TARGET_UDOO_NEO
+	bool "UDOO Neo"
+	select SUPPORT_SPL
+
+config TARGET_SAMTEC_VINING_2000
+	bool "samtec VIN|ING 2000"
+	select MX6SX
+	select DM
+	select DM_THERMAL
+
 config TARGET_WANDBOARD
 	bool "wandboard"
 	select SUPPORT_SPL
@@ -247,12 +265,14 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
+source "board/samtec/vining_2000/Kconfig"
 source "board/seco/Kconfig"
 source "board/solidrun/mx6cuboxi/Kconfig"
 source "board/technexion/pico-imx6ul/Kconfig"
 source "board/tbs/tbs2910/Kconfig"
 source "board/tqc/tqma6/Kconfig"
 source "board/udoo/Kconfig"
+source "board/udoo/neo/Kconfig"
 source "board/wandboard/Kconfig"
 source "board/warp/Kconfig"
 
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ae3143c7607..299562884ad 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -881,6 +881,11 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	writel(reg, &anatop->pll_enet);
 
 #ifdef CONFIG_MX6SX
+	/* Disable enet system clcok before switching clock parent */
+	reg = readl(&imx_ccm->CCGR3);
+	reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+	writel(reg, &imx_ccm->CCGR3);
+
 	/*
 	 * Set enet ahb clock to 200MHz
 	 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
@@ -1379,6 +1384,20 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
+#ifndef CONFIG_SYS_NO_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(&imx_ccm->CCGR6);
+	if (enable)
+		reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+	else
+		reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+	__raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7beb7eabf7f..0cf391eb9ca 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -14,8 +14,7 @@
 #include <asm/types.h>
 #include <wait_bit.h>
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-
+#if defined(CONFIG_MX6_DDRCAL)
 static void reset_read_data_fifos(void)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
@@ -86,14 +85,15 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, u32 *reg_ctrl)
 	writel(val_ctrl, reg_ctrl);
 }
 
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 	u32 esdmisc_val, zq_val;
 	u32 errors = 0;
-	u32 ldectrl[4];
+	u32 ldectrl[4] = {0};
 	u32 ddr_mr1 = 0x4;
+	u32 rwalat_max;
 
 	/*
 	 * Stash old values in case calibration fails,
@@ -101,8 +101,10 @@ int mmdc_do_write_level_calibration(void)
 	 */
 	ldectrl[0] = readl(&mmdc0->mpwldectrl0);
 	ldectrl[1] = readl(&mmdc0->mpwldectrl1);
-	ldectrl[2] = readl(&mmdc1->mpwldectrl0);
-	ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+	if (sysinfo->dsize == 2) {
+		ldectrl[2] = readl(&mmdc1->mpwldectrl0);
+		ldectrl[3] = readl(&mmdc1->mpwldectrl1);
+	}
 
 	/* disable DDR logic power down timer */
 	clrbits_le32(&mmdc0->mdpdc, 0xff00);
@@ -122,10 +124,10 @@ int mmdc_do_write_level_calibration(void)
 	writel(zq_val & ~0x3, &mmdc0->mpzqhwctrl);
 
 	/* 3. increase walat and ralat to maximum */
-	setbits_le32(&mmdc0->mdmisc,
-		     (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
-	setbits_le32(&mmdc1->mdmisc,
-		     (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+	rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+	setbits_le32(&mmdc0->mdmisc, rwalat_max);
+	if (sysinfo->dsize == 2)
+		setbits_le32(&mmdc1->mdmisc, rwalat_max);
 	/*
 	 * 4 & 5. Configure the external DDR device to enter write-leveling
 	 * mode through Load Mode Register command.
@@ -152,21 +154,25 @@ int mmdc_do_write_level_calibration(void)
 	 */
 	if (readl(&mmdc0->mpwlgcr) & 0x00000F00)
 		errors |= 1;
-	if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
-		errors |= 2;
+	if (sysinfo->dsize == 2)
+		if (readl(&mmdc1->mpwlgcr) & 0x00000F00)
+			errors |= 2;
 
 	debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
 
 	/* check to see if cal failed */
 	if ((readl(&mmdc0->mpwldectrl0) == 0x001F001F) &&
 	    (readl(&mmdc0->mpwldectrl1) == 0x001F001F) &&
-	    (readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
-	    (readl(&mmdc1->mpwldectrl1) == 0x001F001F)) {
+	    ((sysinfo->dsize < 2) ||
+	     ((readl(&mmdc1->mpwldectrl0) == 0x001F001F) &&
+	      (readl(&mmdc1->mpwldectrl1) == 0x001F001F)))) {
 		debug("Cal seems to have soft-failed due to memory not supporting write leveling on all channels. Restoring original write leveling values.\n");
 		writel(ldectrl[0], &mmdc0->mpwldectrl0);
 		writel(ldectrl[1], &mmdc0->mpwldectrl1);
-		writel(ldectrl[2], &mmdc1->mpwldectrl0);
-		writel(ldectrl[3], &mmdc1->mpwldectrl1);
+		if (sysinfo->dsize == 2) {
+			writel(ldectrl[2], &mmdc1->mpwldectrl0);
+			writel(ldectrl[3], &mmdc1->mpwldectrl1);
+		}
 		errors |= 4;
 	}
 
@@ -189,16 +195,20 @@ int mmdc_do_write_level_calibration(void)
 	      readl(&mmdc0->mpwldectrl0));
 	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
 	      readl(&mmdc0->mpwldectrl1));
-	debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
-	      readl(&mmdc1->mpwldectrl0));
-	debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
-	      readl(&mmdc1->mpwldectrl1));
+	if (sysinfo->dsize == 2) {
+		debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+		      readl(&mmdc1->mpwldectrl0));
+		debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+		      readl(&mmdc1->mpwldectrl1));
+	}
 
 	/* We must force a readback of these values, to get them to stick */
 	readl(&mmdc0->mpwldectrl0);
 	readl(&mmdc0->mpwldectrl1);
-	readl(&mmdc1->mpwldectrl0);
-	readl(&mmdc1->mpwldectrl1);
+	if (sysinfo->dsize == 2) {
+		readl(&mmdc1->mpwldectrl0);
+		readl(&mmdc1->mpwldectrl1);
+	}
 
 	/* enable DDR logic power down timer: */
 	setbits_le32(&mmdc0->mdpdc, 0x00005500);
@@ -212,7 +222,7 @@ int mmdc_do_write_level_calibration(void)
 	return errors;
 }
 
-int mmdc_do_dqs_calibration(void)
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 {
 	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
 	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
@@ -223,7 +233,6 @@ int mmdc_do_dqs_calibration(void)
 	bool cs0_enable_initial;
 	bool cs1_enable_initial;
 	u32 esdmisc_val;
-	u32 bus_size;
 	u32 temp_ref;
 	u32 pddword = 0x00ffff00; /* best so far, place into MPPDCMPR1 */
 	u32 errors = 0;
@@ -292,10 +301,6 @@ int mmdc_do_dqs_calibration(void)
 	cs0_enable = readl(&mmdc0->mdctl) & 0x80000000;
 	cs1_enable = readl(&mmdc0->mdctl) & 0x40000000;
 
-	/* Check to see what the data bus size is */
-	bus_size = (readl(&mmdc0->mdctl) & 0x30000) >> 16;
-	debug("Data bus size: %d (%d bits)\n", bus_size, 1 << (bus_size + 4));
-
 	precharge_all(cs0_enable, cs1_enable);
 
 	/* Write the pre-defined value into MPPDCMPR1 */
@@ -314,11 +319,11 @@ int mmdc_do_dqs_calibration(void)
 	 * Both PHYs for x64 configuration, if x32, do only PHY0.
 	 */
 	writel(initdelay, &mmdc0->mprddlctl);
-	if (bus_size == 0x2)
+	if (sysinfo->dsize == 0x2)
 		writel(initdelay, &mmdc1->mprddlctl);
 
 	/* Force a measurment, for previous delay setup to take effect. */
-	force_delay_measurement(bus_size);
+	force_delay_measurement(sysinfo->dsize);
 
 	/*
 	 * ***************************
@@ -347,6 +352,8 @@ int mmdc_do_dqs_calibration(void)
 	 * 16 before comparing read data.
 	 */
 	setbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+	if (sysinfo->dsize == 2)
+		setbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
 
 	/* Set bit 28 to start automatic read DQS gating calibration */
 	setbits_le32(&mmdc0->mpdgctrl0, 5 << 28);
@@ -362,9 +369,14 @@ int mmdc_do_dqs_calibration(void)
 	if (readl(&mmdc0->mpdgctrl0) & 0x00001000)
 		errors |= 1;
 
-	if ((bus_size == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
+	if ((sysinfo->dsize == 0x2) && (readl(&mmdc1->mpdgctrl0) & 0x00001000))
 		errors |= 2;
 
+	/* now disable mpdgctrl0[DG_CMP_CYC] */
+	clrbits_le32(&mmdc0->mpdgctrl0, 1 << 30);
+	if (sysinfo->dsize == 2)
+		clrbits_le32(&mmdc1->mpdgctrl0, 1 << 30);
+
 	/*
 	 * DQS gating absolute offset should be modified from
 	 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
@@ -374,7 +386,7 @@ int mmdc_do_dqs_calibration(void)
 			 &mmdc0->mpdgctrl0);
 	modify_dg_result(&mmdc0->mpdghwst2, &mmdc0->mpdghwst3,
 			 &mmdc0->mpdgctrl1);
-	if (bus_size == 0x2) {
+	if (sysinfo->dsize == 0x2) {
 		modify_dg_result(&mmdc1->mpdghwst0, &mmdc1->mpdghwst1,
 				 &mmdc1->mpdgctrl0);
 		modify_dg_result(&mmdc1->mpdghwst2, &mmdc1->mpdghwst3,
@@ -417,7 +429,8 @@ int mmdc_do_dqs_calibration(void)
 	if (readl(&mmdc0->mprddlhwctl) & 0x0000000f)
 		errors |= 4;
 
-	if ((bus_size == 0x2) && (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
+	if ((sysinfo->dsize == 0x2) &&
+	    (readl(&mmdc1->mprddlhwctl) & 0x0000000f))
 		errors |= 8;
 
 	debug("Ending Read Delay calibration. Error mask: 0x%x\n", errors);
@@ -443,14 +456,14 @@ int mmdc_do_dqs_calibration(void)
 	 * Both PHYs for x64 configuration, if x32, do only PHY0.
 	 */
 	writel(initdelay, &mmdc0->mpwrdlctl);
-	if (bus_size == 0x2)
+	if (sysinfo->dsize == 0x2)
 		writel(initdelay, &mmdc1->mpwrdlctl);
 
 	/*
 	 * XXX This isn't in the manual. Force a measurement,
 	 * for previous delay setup to effect.
 	 */
-	force_delay_measurement(bus_size);
+	force_delay_measurement(sysinfo->dsize);
 
 	/*
 	 * 9. 10. Start the automatic write calibration process
@@ -470,7 +483,8 @@ int mmdc_do_dqs_calibration(void)
 	if (readl(&mmdc0->mpwrdlhwctl) & 0x0000000f)
 		errors |= 16;
 
-	if ((bus_size == 0x2) && (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
+	if ((sysinfo->dsize == 0x2) &&
+	    (readl(&mmdc1->mpwrdlhwctl) & 0x0000000f))
 		errors |= 32;
 
 	debug("Ending Write Delay calibration. Error mask: 0x%x\n", errors);
@@ -522,14 +536,18 @@ int mmdc_do_dqs_calibration(void)
 	debug("Read DQS gating calibration:\n");
 	debug("\tMPDGCTRL0 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl0));
 	debug("\tMPDGCTRL1 PHY0 = 0x%08X\n", readl(&mmdc0->mpdgctrl1));
-	debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
-	debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+	if (sysinfo->dsize == 2) {
+		debug("\tMPDGCTRL0 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl0));
+		debug("\tMPDGCTRL1 PHY1 = 0x%08X\n", readl(&mmdc1->mpdgctrl1));
+	}
 	debug("Read calibration:\n");
 	debug("\tMPRDDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mprddlctl));
-	debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
+	if (sysinfo->dsize == 2)
+		debug("\tMPRDDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mprddlctl));
 	debug("Write calibration:\n");
 	debug("\tMPWRDLCTL PHY0 = 0x%08X\n", readl(&mmdc0->mpwrdlctl));
-	debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
+	if (sysinfo->dsize == 2)
+		debug("\tMPWRDLCTL PHY1 = 0x%08X\n", readl(&mmdc1->mpwrdlctl));
 
 	/*
 	 * Registers below are for debugging purposes.  These print out
@@ -541,10 +559,12 @@ int mmdc_do_dqs_calibration(void)
 	debug("\tMPDGHWST1 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst1));
 	debug("\tMPDGHWST2 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst2));
 	debug("\tMPDGHWST3 PHY0 = 0x%08x\n", readl(&mmdc0->mpdghwst3));
-	debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
-	debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
-	debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
-	debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+	if (sysinfo->dsize == 2) {
+		debug("\tMPDGHWST0 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst0));
+		debug("\tMPDGHWST1 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst1));
+		debug("\tMPDGHWST2 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst2));
+		debug("\tMPDGHWST3 PHY1 = 0x%08x\n", readl(&mmdc1->mpdghwst3));
+	}
 
 	debug("Final do_dqs_calibration error mask: 0x%x\n", errors);
 
@@ -1480,6 +1500,29 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	mdelay(1);
 }
 
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+                           struct mx6_mmdc_calibration *calib)
+{
+	struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+	struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+	calib->p0_mpwldectrl0 = readl(&mmdc0->mpwldectrl0);
+	calib->p0_mpwldectrl1 = readl(&mmdc0->mpwldectrl1);
+	calib->p0_mpdgctrl0 = readl(&mmdc0->mpdgctrl0);
+	calib->p0_mpdgctrl1 = readl(&mmdc0->mpdgctrl1);
+	calib->p0_mprddlctl = readl(&mmdc0->mprddlctl);
+	calib->p0_mpwrdlctl = readl(&mmdc0->mpwrdlctl);
+
+	if (sysinfo->dsize == 2) {
+		calib->p1_mpwldectrl0 = readl(&mmdc1->mpwldectrl0);
+		calib->p1_mpwldectrl1 = readl(&mmdc1->mpwldectrl1);
+		calib->p1_mpdgctrl0 = readl(&mmdc1->mpdgctrl0);
+		calib->p1_mpdgctrl1 = readl(&mmdc1->mpdgctrl1);
+		calib->p1_mprddlctl = readl(&mmdc1->mprddlctl);
+		calib->p1_mpwrdlctl = readl(&mmdc1->mpwrdlctl);
+	}
+}
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		  const struct mx6_mmdc_calibration *calib,
 		  const void *ddr_cfg)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 7b53bfdeb40..dd947975144 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -300,9 +300,17 @@ static void clear_mmdc_ch_mask(void)
 	writel(reg, &mxc_ccm->ccdr);
 }
 
+#define OCOTP_MEM0_REFTOP_TRIM_SHIFT          8
+
 static void init_bandgap(void)
 {
 	struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+	uint32_t val;
+
 	/*
 	 * Ensure the bandgap has stabilized.
 	 */
@@ -315,13 +323,26 @@ static void init_bandgap(void)
 	 */
 	writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
 	/*
-	 * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
-	 * VBGADJ bits to 2b'110 to adjust it.
+	 * On i.MX6ULL,we need to set VBGADJ bits according to the
+	 * REFTOP_TRIM[3:0] in fuse table
+	 *	000 - set REFTOP_VBGADJ[2:0] to 3b'110,
+	 *	110 - set REFTOP_VBGADJ[2:0] to 3b'000,
+	 *	001 - set REFTOP_VBGADJ[2:0] to 3b'001,
+	 *	010 - set REFTOP_VBGADJ[2:0] to 3b'010,
+	 *	011 - set REFTOP_VBGADJ[2:0] to 3b'011,
+	 *	100 - set REFTOP_VBGADJ[2:0] to 3b'100,
+	 *	101 - set REFTOP_VBGADJ[2:0] to 3b'101,
+	 *	111 - set REFTOP_VBGADJ[2:0] to 3b'111,
 	 */
-	if (is_mx6ull())
-		writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
-}
+	if (is_mx6ull()) {
+		val = readl(&fuse->mem0);
+		val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
+		val &= 0x7;
 
+		writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
+		       &anatop->ana_misc0_set);
+	}
+}
 
 #ifdef CONFIG_MX6SL
 static void set_preclk_from_osc(void)
diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index bdcda7de937..325ba263403 100644
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -14,6 +14,9 @@
 #include <spl.h>
 
 #if defined(CONFIG_MX6)
+#define MX6_MMC_PORT_MASK	GENMASK(12, 11)
+#define MX6_MMC_PORT_2		BIT(11)
+
 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
 {
@@ -55,10 +58,11 @@ u32 spl_boot_device(void)
 	/* SD/eSD: 8.5.3, Table 8-15  */
 	case 0x4:
 	case 0x5:
-		return BOOT_DEVICE_MMC1;
 	/* MMC/eMMC: 8.5.3 */
 	case 0x6:
 	case 0x7:
+		if ((reg & MX6_MMC_PORT_MASK) == MX6_MMC_PORT_2)
+			return BOOT_DEVICE_MMC2;
 		return BOOT_DEVICE_MMC1;
 	/* NAND Flash: 8.5.2 */
 	case 0x8 ... 0xf:
diff --git a/arch/arm/imx-common/video.c b/arch/arm/imx-common/video.c
index fdc987f469f..549bf9d957a 100644
--- a/arch/arm/imx-common/video.c
+++ b/arch/arm/imx-common/video.c
@@ -34,7 +34,7 @@ int board_video_skip(void)
 	}
 
 	if (i < display_count) {
-		ret = ipuv3_fb_init(&displays[i].mode, 0,
+		ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0,
 				    displays[i].pixfmt);
 		if (!ret) {
 			if (displays[i].enable)
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h
index 82f9f92b83d..ed1433ebc68 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -79,4 +79,5 @@ void enable_qspi_clk(int qspi_num);
 void enable_thermal_clk(void);
 void mxs_set_lcdclk(u32 base_addr, u32 freq);
 void select_ldb_di_clock_source(enum ldb_di_clock clk);
+void enable_eim_clk(unsigned char enable);
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index f74737a68e6..29674ce54d8 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1272,6 +1272,7 @@ struct mxc_ccm_reg {
 
 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
+#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
 
 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 99224091baa..2a8d4431eaa 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -458,9 +458,11 @@ void mx6sl_dram_iocfg(unsigned width,
 		      const struct mx6sl_iomux_ddr_regs *,
 		      const struct mx6sl_iomux_grp_regs *);
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-int mmdc_do_write_level_calibration(void);
-int mmdc_do_dqs_calibration(void);
+#if defined(CONFIG_MX6_DDRCAL)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+                           struct mx6_mmdc_calibration *calib);
 #endif
 
 /* configure mx6 mmdc registers */
@@ -495,6 +497,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
 #define MX6_MMDC_P0_MPDGCTRL1	0x021b0840
 #define MX6_MMDC_P0_MPRDDLCTL	0x021b0848
 #define MX6_MMDC_P0_MPWRDLCTL	0x021b0850
+#define MX6_MMDC_P0_MPZQLP2CTL	0x021b085C
 #define MX6_MMDC_P0_MPMUR0	0x021b08b8
 
 #define MX6_MMDC_P1_MDCTL	0x021b4000
@@ -522,6 +525,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
 #define MX6_MMDC_P1_MPDGCTRL1	0x021b4840
 #define MX6_MMDC_P1_MPRDDLCTL	0x021b4848
 #define MX6_MMDC_P1_MPWRDLCTL	0x021b4850
+#define MX6_MMDC_P1_MPZQLP2CTL	0x021b485C
 #define MX6_MMDC_P1_MPMUR0	0x021b48b8
 
 #endif	/*__ASM_ARCH_MX6_DDR_H__ */
diff --git a/arch/arm/include/asm/imx-common/video.h b/arch/arm/include/asm/imx-common/video.h
index cad5f861cb8..941a031964c 100644
--- a/arch/arm/include/asm/imx-common/video.h
+++ b/arch/arm/include/asm/imx-common/video.h
@@ -12,6 +12,7 @@ struct display_info_t {
 	int	bus;
 	int	addr;
 	int	pixfmt;
+	int	di;
 	int	(*detect)(struct display_info_t const *dev);
 	void	(*enable)(struct display_info_t const *dev);
 	struct	fb_videomode mode;
diff --git a/board/CarMediaLab/flea3/flea3.c b/board/CarMediaLab/flea3/flea3.c
index 2463077475a..3cd4dc95fe3 100644
--- a/board/CarMediaLab/flea3/flea3.c
+++ b/board/CarMediaLab/flea3/flea3.c
@@ -19,6 +19,9 @@
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <netdev.h>
+#include <fdt_support.h>
+#include <mtd_node.h>
+#include <jffs2/load_kernel.h>
 
 #ifndef CONFIG_BOARD_EARLY_INIT_F
 #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
@@ -27,18 +30,6 @@
 #define CCM_CCMR_CONFIG		0x003F4208
 
 #define ESDCTL_DDR2_CONFIG	0x007FFC3F
-#define ESDCTL_0x92220000	0x92220000
-#define ESDCTL_0xA2220000	0xA2220000
-#define ESDCTL_0xB2220000	0xB2220000
-#define ESDCTL_0x82228080	0x82228080
-#define ESDCTL_DDR2_EMR2	0x04000000
-#define ESDCTL_DDR2_EMR3	0x06000000
-#define ESDCTL_PRECHARGE	0x00000400
-#define ESDCTL_DDR2_EN_DLL	0x02000400
-#define ESDCTL_DDR2_RESET_DLL	0x00000333
-#define ESDCTL_DDR2_MR		0x00000233
-#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
-#define ESDCTL_DELAY_LINE5	0x00F49F00
 
 static inline void dram_wait(unsigned int count)
 {
@@ -58,83 +49,6 @@ int dram_init(void)
 	return 0;
 }
 
-static void board_setup_sdram_bank(u32 start_address)
-
-{
-	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
-	u32 *cfg_reg, *ctl_reg;
-	u32 val;
-
-	switch (start_address) {
-	case CSD0_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg0;
-		ctl_reg = &esdc->esdctl0;
-		break;
-	case CSD1_BASE_ADDR:
-		cfg_reg = &esdc->esdcfg1;
-		ctl_reg = &esdc->esdctl1;
-		break;
-	default:
-		return;
-	}
-
-	/* Initialize MISC register for DDR2 */
-	val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
-		ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
-	writel(val, &esdc->esdmisc);
-	val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
-	writel(val, &esdc->esdmisc);
-
-	/*
-	 * according to DDR2 specs, wait a while before
-	 * the PRECHARGE_ALL command
-	 */
-	dram_wait(0x20000);
-
-	/* Load DDR2 config and timing */
-	writel(ESDCTL_DDR2_CONFIG, cfg_reg);
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Load mode */
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-	writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
-
-	/* Precharge ALL */
-	writel(ESDCTL_0x92220000,
-		ctl_reg);
-	writel(0xda, start_address + ESDCTL_PRECHARGE);
-
-	/* Set mode auto refresh : at least two refresh are required */
-	writel(ESDCTL_0xA2220000,
-		ctl_reg);
-	writel(0xda, start_address);
-	writel(0xda, start_address);
-
-	writel(ESDCTL_0xB2220000,
-		ctl_reg);
-	writeb(0xda, start_address + ESDCTL_DDR2_MR);
-	writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
-
-	/* OCD mode exit */
-	writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
-
-	/* Set normal mode */
-	writel(ESDCTL_0x82228080,
-		ctl_reg);
-
-	dram_wait(0x20000);
-
-	/* Do not set delay lines, only for MDDR */
-}
-
 static void board_setup_sdram(void)
 {
 	struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
@@ -143,7 +57,9 @@ static void board_setup_sdram(void)
 	writel(0x2000, &esdc->esdctl0);
 	writel(0x2000, &esdc->esdctl1);
 
-	board_setup_sdram_bank(CSD0_BASE_ADDR);
+
+	mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
+			     13, 10, 2, 0x8080);
 }
 
 static void setup_iomux_uart3(void)
@@ -206,6 +122,8 @@ static void setup_iomux_fec(void)
 		MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
 		MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
 		MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+		/* GPIO used to power off ethernet */
+		MX35_PAD_STXFS4__GPIO2_31,
 	};
 
 	/* setup pins for FEC */
@@ -267,6 +185,11 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	/* Enable power for ethernet */
+	gpio_direction_output(63, 0);
+
+	udelay(2000);
+
 	return 0;
 }
 
@@ -276,3 +199,24 @@ u32 get_board_rev(void)
 
 	return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
 }
+
+/*
+ * called prior to booting kernel or by 'fdt boardsetup' command
+ *
+ */
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	struct node_info nodes[] = {
+		{ "physmap-flash.0", MTD_DEV_TYPE_NOR, },  /* NOR flash */
+		{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
+	};
+
+	if (getenv("fdt_noauto")) {
+		puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
+		return 0;
+	}
+
+	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
+
+	return 0;
+}
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index b9365445e85..6ccdd4b33b2 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -50,6 +50,9 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
 
+#define SPI_PAD_CTRL \
+  (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
+
 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
@@ -68,6 +71,23 @@ static struct i2c_pads_info i2c_pad_info1 = {
 };
 #endif
 
+static iomux_v3_cfg_t const ecspi3_pads[] = {
+    MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+    MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+int board_spi_cs_gpio(unsigned bus, unsigned cs)
+{
+         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
+}
+
+static void setup_spi(void)
+{
+         imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
+}
+
 int dram_init(void)
 {
 	gd->ram_size = PHYS_SDRAM_SIZE;
@@ -553,6 +573,10 @@ int board_init(void)
 	board_qspi_init();
 #endif
 
+#ifdef CONFIG_MXC_SPI
+       setup_spi();
+#endif
+
 	return 0;
 }
 
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index 7e62aef07e1..2fc1144cdae 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -596,6 +596,57 @@ static const struct boot_mode board_boot_modes[] = {
 };
 #endif
 
+void pmic_init(void)
+{
+#define I2C_PMIC                0x2
+#define DA9063_I2C_ADDR         0x58
+#define DA9063_REG_BCORE2_CFG   0x9D
+#define DA9063_REG_BCORE1_CFG   0x9E
+#define DA9063_REG_BPRO_CFG     0x9F
+#define DA9063_REG_BIO_CFG      0xA0
+#define DA9063_REG_BMEM_CFG     0xA1
+#define DA9063_REG_BPERI_CFG    0xA2
+#define DA9063_BUCK_MODE_MASK   0xC0
+#define DA9063_BUCK_MODE_MANUAL 0x00
+#define DA9063_BUCK_MODE_SLEEP  0x40
+#define DA9063_BUCK_MODE_SYNC   0x80
+#define DA9063_BUCK_MODE_AUTO   0xC0
+
+	uchar val;
+
+	i2c_set_bus_num(I2C_PMIC);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE2_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BCORE1_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPRO_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BIO_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BMEM_CFG, 1, &val, 1);
+
+	i2c_read(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+	val &= ~DA9063_BUCK_MODE_MASK;
+	val |= DA9063_BUCK_MODE_SYNC;
+	i2c_write(DA9063_I2C_ADDR, DA9063_REG_BPERI_CFG, 1, &val, 1);
+}
+
 int board_late_init(void)
 {
 #ifdef CONFIG_CMD_BMODE
@@ -619,6 +670,9 @@ int board_late_init(void)
 	pwm_enable(0);
 #endif
 
+	/* board specific pmic init */
+	pmic_init();
+
 	return 0;
 }
 
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index 92c61aebb10..b934d367881 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -605,8 +605,8 @@ void board_init_f(ulong dummy)
 
 	/* Perform DDR DRAM calibration */
 	udelay(100);
-	mmdc_do_write_level_calibration();
-	mmdc_do_dqs_calibration();
+	mmdc_do_write_level_calibration(&novena_ddr_info);
+	mmdc_do_dqs_calibration(&novena_ddr_info);
 
 	/* Clear the BSS. */
 	memset(__bss_start, 0, __bss_end - __bss_start);
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
new file mode 100644
index 00000000000..3447c27fa4f
--- /dev/null
+++ b/board/samtec/vining_2000/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAMTEC_VINING_2000
+
+config SYS_BOARD
+	default "vining_2000"
+
+config SYS_VENDOR
+	default "samtec"
+
+config SYS_CONFIG_NAME
+	default "vining_2000"
+
+endif
diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS
new file mode 100644
index 00000000000..027e52736fa
--- /dev/null
+++ b/board/samtec/vining_2000/MAINTAINERS
@@ -0,0 +1,6 @@
+VINING_2000 BOARD
+M:	Ingo Schroeck <open-source@samtec.de>
+S:	Maintained
+F:	board/samtec/vining_2000/
+F:	include/configs/vining_2000.h
+F:	configs/vining_2000_defconfig
diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile
new file mode 100644
index 00000000000..1b32f66aaaf
--- /dev/null
+++ b/board/samtec/vining_2000/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 samtec automotive software & electronics gmbh
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := vining_2000.o
diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg
new file mode 100644
index 00000000000..4133ddad2e1
--- /dev/null
+++ b/board/samtec/vining_2000/imximage.cfg
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+
+/* Enable all clocks */
+DATA 4 0x020c4068 0xffffffff
+DATA 4 0x020c406c 0xffffffff
+DATA 4 0x020c4070 0xffffffff
+DATA 4 0x020c4074 0xffffffff
+DATA 4 0x020c4078 0xffffffff
+DATA 4 0x020c407c 0xffffffff
+DATA 4 0x020c4080 0xffffffff
+DATA 4 0x020c4084 0xffffffff
+
+/* IOMUX - DDR IO Type */
+DATA 4 0x020e0618 0x000c0000
+DATA 4 0x020e05fc 0x00000000
+
+/* Clock */
+DATA 4 0x020e032c 0x00000030
+
+/* Address */
+DATA 4 0x020e0300 0x00000028
+DATA 4 0x020e02fc 0x00000028
+DATA 4 0x020e05f4 0x00000028
+
+/* Control */
+DATA 4 0x020e0340 0x00000028
+
+DATA 4 0x020e0320 0x00000000
+DATA 4 0x020e0310 0x00000028
+DATA 4 0x020e0314 0x00000028
+DATA 4 0x020e0614 0x00000028
+
+/* Data Strobe */
+DATA 4 0x020e05f8 0x00020000
+DATA 4 0x020e0330 0x00000028
+DATA 4 0x020e0334 0x00000028
+DATA 4 0x020e0338 0x00000028
+DATA 4 0x020e033c 0x00000028
+
+/* Data */
+DATA 4 0x020e0608 0x00020000
+DATA 4 0x020e060c 0x00000028
+DATA 4 0x020e0610 0x00000028
+DATA 4 0x020e061c 0x00000028
+DATA 4 0x020e0620 0x00000028
+DATA 4 0x020e02ec 0x00000028
+DATA 4 0x020e02f0 0x00000028
+DATA 4 0x020e02f4 0x00000028
+DATA 4 0x020e02f8 0x00000028
+
+/* Calibrations - ZQ */
+DATA 4 0x021b0800 0xa1390003
+
+/* Write leveling */
+DATA 4 0x021b080c 0x00290025
+DATA 4 0x021b0810 0x00210022
+
+/* DQS Read Gate */
+DATA 4 0x021b083c 0x4142013a
+DATA 4 0x021b0840 0x012e0123
+
+/* Read/Write Delay */
+DATA 4 0x021b0848 0x43474949
+DATA 4 0x021b0850 0x38383c38
+
+/* Read data bit delay */
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+/* Complete calibration by forced measurement */
+DATA 4 0x021b08b8 0x00000800
+
+/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
+DATA 4 0x021b0004 0x0002002d
+DATA 4 0x021b0008 0x00333040
+DATA 4 0x021b000c 0x676b52f2
+DATA 4 0x021b0010 0x926e8b63
+DATA 4 0x021b0014 0x01ff00db
+DATA 4 0x021b0018 0x00011740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006b1023
+DATA 4 0x021b0040 0x0000005f
+DATA 4 0x021b0000 0x84190000
+
+/* Initialize MT41K256M16HA-125 - MR2 */
+DATA 4 0x021b001c 0x02008032
+/* MR3 */
+DATA 4 0x021b001c 0x00008033
+/* MR1 */
+DATA 4 0x021b001c 0x00048031
+/* MR0 */
+DATA 4 0x021b001c 0x15108030
+/* DDR device ZQ calibration */
+DATA 4 0x021b001c 0x04008040
+
+/* Final DDR setup, before operation start */
+DATA 4 0x021b0020 0x00007800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b001c 0x00000000
diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c
new file mode 100644
index 00000000000..c92f37c9bb5
--- /dev/null
+++ b/board/samtec/vining_2000/vining_2000.c
@@ -0,0 +1,517 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Author: Christoph Fritz <chf.fritz@googlemail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/io.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <linux/sizes.h>
+#include <common.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include <usb.h>
+#include <usb/ehci-ci.h>
+#include <pwm.h>
+#include <wait_bit.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE |	\
+	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm |		\
+	PAD_CTL_SRE_FAST)
+
+#define ENET_CLK_PAD_CTRL  PAD_CTL_DSE_34ohm
+
+#define ENET_RX_PAD_CTRL  (PAD_CTL_PKE |			\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH |		\
+	PAD_CTL_SRE_FAST)
+
+#define I2C_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm)
+
+#define USDHC_CLK_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST)
+
+#define USDHC_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP |	\
+	PAD_CTL_PKE |  PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm |	\
+	PAD_CTL_SRE_FAST)
+
+#define GPIO_PAD_CTRL  (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP |	\
+	PAD_CTL_PKE)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL),
+	MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const fec1_pads[] = {
+	MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
+	MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) |
+		MUX_MODE_SION,
+	/* LAN8720 PHY Reset */
+	MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const pwm_led_pads[] = {
+	MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */
+	MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */
+	MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#define PHY_RESET IMX_GPIO_NR(5, 9)
+
+int board_eth_init(bd_t *bis)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+	int ret;
+	unsigned char eth1addr[6];
+
+	/* just to get secound mac address */
+	imx_get_mac_from_fuse(1, eth1addr);
+	if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr))
+		eth_setenv_enetaddr("eth1addr", eth1addr);
+
+	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
+
+	/*
+	 * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing
+	 * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by
+	 * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver.
+	 */
+	clrsetbits_le32(&iomuxc_regs->gpr[1],
+			IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
+			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK |
+			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
+
+	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
+	if (ret)
+		goto eth_fail;
+
+	/* reset phy */
+	gpio_direction_output(PHY_RESET, 0);
+	mdelay(16);
+	gpio_set_value(PHY_RESET, 1);
+	mdelay(1);
+
+	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR,
+					IMX_FEC_BASE);
+	if (ret)
+		goto eth_fail;
+
+	return ret;
+
+eth_fail:
+	printf("FEC MXC: %s:failed (%i)\n", __func__, ret);
+	gpio_set_value(PHY_RESET, 0);
+	return ret;
+}
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+/* I2C1 for PMIC */
+static struct i2c_pads_info i2c_pad_info1 = {
+	.scl = {
+		.i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
+		.gp = IMX_GPIO_NR(1, 0),
+	},
+	.sda = {
+		.i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
+		.gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
+		.gp = IMX_GPIO_NR(1, 1),
+	},
+};
+
+static struct pmic *pfuze_init(unsigned char i2cbus)
+{
+	struct pmic *p;
+	int ret;
+	u32 reg;
+
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
+		return NULL;
+
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+
+	/* Set SW1AB stanby volage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+
+	/* Set SW1C standby voltage to 0.975V */
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg &= ~SW1x_STBY_MASK;
+	reg |= SW1x_0_975V;
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg &= ~SW1xCONF_DVSSPEED_MASK;
+	reg |= SW1xCONF_DVSSPEED_4US;
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+
+	return p;
+}
+
+static int pfuze_mode_init(struct pmic *p, u32 mode)
+{
+	unsigned char offset, i, switch_num;
+	u32 id;
+	int ret;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = id & 0xf;
+
+	if (id == 0) {
+		switch_num = 6;
+		offset = PFUZE100_SW1CMODE;
+	} else if (id == 1) {
+		switch_num = 4;
+		offset = PFUZE100_SW2MODE;
+	} else {
+		printf("Not supported, id=%d\n", id);
+		return -EINVAL;
+	}
+
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	if (ret < 0) {
+		printf("Set SW1AB mode error!\n");
+		return ret;
+	}
+
+	for (i = 0; i < switch_num - 1; i++) {
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		if (ret < 0) {
+			printf("Set switch 0x%x mode error!\n",
+			       offset + i * SWITCH_SIZE);
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+int power_init_board(void)
+{
+	struct pmic *p;
+	int ret;
+
+	p = pfuze_init(I2C_PMIC);
+	if (!p)
+		return -ENODEV;
+
+	ret = pfuze_mode_init(p, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_EHCI_MX6
+static iomux_v3_cfg_t const usb_otg_pads[] = {
+	/* OGT1 */
+	MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* OTG2 */
+	MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
+};
+
+static void setup_iomux_usb(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
+					 ARRAY_SIZE(usb_otg_pads));
+}
+
+int board_usb_phy_mode(int port)
+{
+	if (port == 1)
+		return USB_INIT_HOST;
+	else
+		return usb_phy_mode(port);
+}
+#endif
+
+#ifdef CONFIG_PWM_IMX
+static int set_pwm_leds(void)
+{
+	int ret;
+
+	imx_iomux_v3_setup_multiple_pads(pwm_led_pads,
+					 ARRAY_SIZE(pwm_led_pads));
+	/* enable backlight PWM 2, green LED */
+	ret = pwm_init(1, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(1, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(1);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 1, blue LED */
+	ret = pwm_init(0, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(0, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(0);
+	if (ret)
+		goto error;
+
+	/* enable backlight PWM 6, red LED */
+	ret = pwm_init(5, 0, 0);
+	if (ret)
+		goto error;
+	/* duty cycle 200ns, period: 8000ns */
+	ret = pwm_config(5, 200, 8000);
+	if (ret)
+		goto error;
+	ret = pwm_enable(5);
+
+error:
+	return ret;
+}
+#else
+static int set_pwm_leds(void)
+{
+	return 0;
+}
+#endif
+
+#define ADCx_HC0        0x00
+#define ADCx_HS         0x08
+#define ADCx_HS_C0      BIT(0)
+#define ADCx_R0         0x0c
+#define ADCx_CFG        0x14
+#define ADCx_CFG_SWMODE 0x308
+#define ADCx_GC         0x18
+#define ADCx_GC_CAL     BIT(7)
+
+static int read_adc(u32 *val)
+{
+	int ret;
+	void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE);
+
+	/* use software mode */
+	writel(ADCx_CFG_SWMODE, b + ADCx_CFG);
+
+	/* start auto calibration */
+	setbits_le32(b + ADCx_GC, ADCx_GC_CAL);
+	ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* start conversion */
+	writel(0, b + ADCx_HC0);
+
+	/* wait for conversion */
+	ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0);
+	if (ret)
+		goto adc_exit;
+
+	/* read result */
+	*val = readl(b + ADCx_R0);
+
+adc_exit:
+	if (ret)
+		printf("ADC failure (ret=%i)\n", ret);
+	unmap_physmem(b, MAP_NOCACHE);
+	return ret;
+}
+
+#define VAL_UPPER	2498
+#define VAL_LOWER	1550
+
+static int set_pin_state(void)
+{
+	u32 val;
+	int ret;
+
+	ret = read_adc(&val);
+	if (ret)
+		return ret;
+
+	if (val >= VAL_UPPER)
+		setenv("pin_state", "connected");
+	else if (val < VAL_UPPER && val > VAL_LOWER)
+		setenv("pin_state", "open");
+	else
+		setenv("pin_state", "button");
+
+	return ret;
+}
+
+int board_late_init(void)
+{
+	int ret;
+
+	ret = set_pwm_leds();
+	if (ret)
+		return ret;
+
+	ret = set_pin_state();
+
+	return ret;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	setup_iomux_usb();
+
+	return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC4_BASE_ADDR, 0, 8},
+	{USDHC2_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC4_BASE_ADDR)
+		return 1;
+	if (cfg->esdhc_base == USDHC2_BASE_ADDR)
+		return !gpio_get_value(USDHC2_CD_GPIO);
+
+	return -EINVAL;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC4
+	 * mmc1                    USDHC2
+	 */
+	imx_iomux_v3_setup_multiple_pads(
+		usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(
+		usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+	gpio_direction_input(USDHC2_CD_GPIO);
+	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	if (ret) {
+		printf("Warning: failed to initialize USDHC4\n");
+		return ret;
+	}
+
+	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
+	if (ret) {
+		printf("Warning: failed to initialize USDHC2\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+#endif
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: VIN|ING 2000\n");
+
+	return 0;
+}
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index 0d9d17ae54c..db0c58f6f56 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -359,6 +359,39 @@ static void setup_display(void)
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 
+static int ar8035_phy_fixup(struct phy_device *phydev)
+{
+	unsigned short val;
+
+	/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+	val &= 0xffe3;
+	val |= 0x18;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+	/* introduce tx clock delay */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+	val |= 0x0100;
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+	return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+	ar8035_phy_fixup(phydev);
+
+	if (phydev->drv->config)
+		phydev->drv->config(phydev);
+
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	setup_iomux_enet();
diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig
new file mode 100644
index 00000000000..d0dc2e1b734
--- /dev/null
+++ b/board/technologic/ts4600/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_TS4600
+
+config SYS_BOARD
+	default "ts4600"
+
+config SYS_VENDOR
+	default "technologic"
+
+config SYS_SOC
+	default "mxs"
+
+config SYS_CONFIG_NAME
+	default "ts4600"
+
+endif
diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS
new file mode 100644
index 00000000000..6f683b5995e
--- /dev/null
+++ b/board/technologic/ts4600/MAINTAINERS
@@ -0,0 +1,6 @@
+TS4600 BOARD
+M:	Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+S:	Maintained
+F:	board/technologic/ts4600/
+F:	include/configs/ts4600.h
+F:	configs/ts4600_defconfig
diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile
new file mode 100644
index 00000000000..faa29705829
--- /dev/null
+++ b/board/technologic/ts4600/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2016 Savoir-faire Linux
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifndef	CONFIG_SPL_BUILD
+obj-y	:= ts4600.o
+else
+obj-y	:= iomux.o
+endif
diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c
new file mode 100644
index 00000000000..1398bbe0ccc
--- /dev/null
+++ b/board/technologic/ts4600/iomux.c
@@ -0,0 +1,149 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ *   Kris Bahnsen <kris@embeddedarm.com>
+ *   Mark Featherston <mark@embeddedarm.com>
+ *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ *   Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <config.h>
+#include <asm/io.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+
+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
+
+const iomux_cfg_t iomux_setup[] = {
+	/* DUART */
+	MX28_PAD_PWM0__DUART_RX,
+	MX28_PAD_PWM1__DUART_TX,
+
+	/* MMC0 */
+	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
+	MX28_PAD_SSP0_SCK__SSP0_SCK |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+	/* MMC0 slot power enable */
+	MX28_PAD_PWM3__GPIO_3_28 |
+		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+
+	/* EMI */
+	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
+	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
+
+	/* I2C */
+	MX28_PAD_I2C0_SCL__I2C0_SCL,
+	MX28_PAD_I2C0_SDA__I2C0_SDA,
+
+};
+
+#define HW_DRAM_CTL29	(0x74 >> 2)
+#define CS_MAP		0xf
+#define COLUMN_SIZE	0x2
+#define ADDR_PINS	0x1
+#define APREBIT		0xa
+
+#define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
+					ADDR_PINS << 8 | APREBIT)
+
+#define HW_DRAM_CTL39	(0x9c >> 2)
+#define TFAW		0xb
+#define TDLL		0xc8
+
+#define HW_DRAM_CTL39_CONFIG	(TFAW << 24 | TDLL)
+
+#define HW_DRAM_CTL41	(0xa4 >> 2)
+#define TPDEX		0x2
+#define TRCD_INT	0x4
+#define TRC		0xd
+
+#define HW_DRAM_CTL41_CONFIG	(TPDEX << 24 | TRCD_INT << 8 | TRC)
+
+#define HW_DRAM_CTL42	(0xa8 >> 2)
+#define TRAS_MAX	0x36a6
+#define TRAS_MIN	0xa
+
+#define HW_DRAM_CTL42_CONFIG  (TRAS_MAX << 8 | TRAS_MIN)
+
+#define HW_DRAM_CTL43	(0xac >> 2)
+#define TRP		0x4
+#define TRFC		0x27
+#define TREF		0x2a0
+
+#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
+
+void mxs_adjust_memory_params(uint32_t *dram_vals)
+{
+	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
+	dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
+	dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
+	dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
+	dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
+}
+
+void board_init_ll(const uint32_t arg, const uint32_t *resptr)
+{
+	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
+}
diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c
new file mode 100644
index 00000000000..70dfeadbccd
--- /dev/null
+++ b/board/technologic/ts4600/ts4600.c
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Based on work from TS7680 code by:
+ *   Kris Bahnsen <kris@embeddedarm.com>
+ *   Mark Featherston <mark@embeddedarm.com>
+ *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
+ *
+ * Derived from MX28EVK code by
+ *   Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux-mx28.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <linux/mii.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	/* IO0 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK0, 480000);
+	/* IO1 clock at 480MHz */
+	mxs_set_ioclk(MXC_IOCLK1, 480000);
+
+	/* SSP0 clocks at 96MHz */
+	mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	return mxs_dram_init();
+}
+
+int board_init(void)
+{
+	/* Adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_CMD_MMC
+static int ts4600_mmc_cd(int id)
+{
+	return 1;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret;
+
+	mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28);
+
+	/* Power-on SD */
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1);
+	udelay(1000);
+	gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
+
+	/* SD card */
+	ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd);
+	if(ret != 0) {
+		printf("SD controller initialized with %d\n", ret);
+	}
+
+	return ret;
+}
+#endif
+
+int checkboard(void)
+{
+	puts("Board: TS4600\n");
+
+	return 0;
+}
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
new file mode 100644
index 00000000000..8f474df2487
--- /dev/null
+++ b/board/udoo/neo/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_UDOO_NEO
+
+config SYS_VENDOR
+	default "udoo"
+
+config SYS_BOARD
+	default "neo"
+
+config SYS_CONFIG_NAME
+	default "udoo_neo"
+
+endif
diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS
new file mode 100644
index 00000000000..743fe33d059
--- /dev/null
+++ b/board/udoo/neo/MAINTAINERS
@@ -0,0 +1,7 @@
+UDOO NEO BOARD
+M:	Breno Lima <breno.lima@nxp.com>
+M:	Francesco Montefoschi <francesco.montefoschi@udoo.org>
+S:	Maintained
+F:	board/udoo/neo/
+F:	include/configs/udoo_neo.h
+F:	configs/udoo_neo_defconfig
diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile
new file mode 100644
index 00000000000..150cbc1a971
--- /dev/null
+++ b/board/udoo/neo/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2015 UDOO Team
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := neo.o
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
new file mode 100644
index 00000000000..7f17469d9af
--- /dev/null
+++ b/board/udoo/neo/neo.c
@@ -0,0 +1,441 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) Jasbir Matharu
+ * Copyright (C) UDOO Team
+ *
+ * Author: Breno Lima <breno.lima@nxp.com>
+ * Author: Francesco Montefoschi <francesco.monte@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <spl.h>
+#include <linux/sizes.h>
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+enum {
+	UDOO_NEO_TYPE_BASIC,
+	UDOO_NEO_TYPE_BASIC_KS,
+	UDOO_NEO_TYPE_FULL,
+	UDOO_NEO_TYPE_EXTENDED,
+};
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm)
+
+#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
+#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) |	\
+	MUX_MODE_SION)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+	MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	/* CD pin */
+	MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* Power */
+	MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const board_recognition_pads[] = {
+	/*Connected to R184*/
+	MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG,
+	/*Connected to R185*/
+	MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG,
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+    /* Configured for WLAN */
+	MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_b_pad = {
+	MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const peri_3v3_pads[] = {
+	MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+int board_init(void)
+{
+	/* Address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	/*
+	 * Because kernel set WDOG_B mux before pad with the commone pinctrl
+	 * framwork now and wdog reset will be triggered once set WDOG_B mux
+	 * with default pad setting, we set pad setting here to workaround this.
+	 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
+	 * as GPIO mux firstly here to workaround it.
+	 */
+	imx_iomux_v3_setup_pad(wdog_b_pad);
+
+	/* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
+	imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
+					 ARRAY_SIZE(peri_3v3_pads));
+
+	/* Active high for ncp692 */
+	gpio_direction_output(IMX_GPIO_NR(4, 16) , 1);
+
+	return 0;
+}
+
+static int get_board_value(void)
+{
+	int r184, r185;
+
+	imx_iomux_v3_setup_multiple_pads(board_recognition_pads,
+					 ARRAY_SIZE(board_recognition_pads));
+
+	gpio_direction_input(IMX_GPIO_NR(4, 13));
+	gpio_direction_input(IMX_GPIO_NR(4, 0));
+
+	r184 = gpio_get_value(IMX_GPIO_NR(4, 13));
+	r185 = gpio_get_value(IMX_GPIO_NR(4, 0));
+
+	/*
+	 * Machine selection -
+	 * Machine          r184,    r185
+	 * ---------------------------------
+	 * Basic              0        0
+	 * Basic Ks           0        1
+	 * Full               1        0
+	 * Extended           1        1
+	 */
+
+	return (r184 << 1) + r185;
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 0, 4},
+	{USDHC3_BASE_ADDR, 0, 4},
+};
+
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1)
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(6, 2)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC2_BASE_ADDR:
+		ret = !gpio_get_value(USDHC2_CD_GPIO);
+		break;
+	}
+
+	return ret;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+#ifndef CONFIG_SPL_BUILD
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			gpio_direction_input(USDHC2_CD_GPIO);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers\
+				(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret) {
+				printf("Warning:\
+					failed to initialize mmc dev %d\n", i);
+				return ret;
+			}
+	}
+
+	return 0;
+#else
+	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+	u32 val;
+	u32 port;
+
+	val = readl(&src_regs->sbmr1);
+
+	if ((val & 0xc0) != 0x40) {
+		printf("Not boot from USDHC!\n");
+		return -EINVAL;
+	}
+
+	port = (val >> 11) & 0x3;
+	printf("port %d\n", port);
+	switch (port) {
+	case 1:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
+		gpio_direction_input(USDHC2_CD_GPIO);
+		gpio_direction_output(USDHC2_PWR_GPIO, 1);
+		break;
+	case 2:
+		imx_iomux_v3_setup_multiple_pads(
+			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+		usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
+		break;
+	}
+
+	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
+	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+#endif
+}
+
+char *board_string(void)
+{
+	switch (get_board_value()) {
+	case UDOO_NEO_TYPE_BASIC:
+		return "BASIC";
+	case UDOO_NEO_TYPE_BASIC_KS:
+		return "BASICKS";
+	case UDOO_NEO_TYPE_FULL:
+		return "FULL";
+	case UDOO_NEO_TYPE_EXTENDED:
+		return "EXTENDED";
+	}
+	return "UNDEFINED";
+}
+
+int checkboard(void)
+{
+	printf("Board: UDOO Neo %s\n", board_string());
+	return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	setenv("board_name", board_string());
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+
+#include <libfdt.h>
+#include <asm/arch/mx6-ddr.h>
+
+static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
+	.dram_dqm0 = 0x00000028,
+	.dram_dqm1 = 0x00000028,
+	.dram_dqm2 = 0x00000028,
+	.dram_dqm3 = 0x00000028,
+	.dram_ras = 0x00000020,
+	.dram_cas = 0x00000020,
+	.dram_odt0 = 0x00000020,
+	.dram_odt1 = 0x00000020,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdcke0 = 0x00003000,
+	.dram_sdcke1 = 0x00003000,
+	.dram_sdclk_0 = 0x00000030,
+	.dram_sdqs0 = 0x00000028,
+	.dram_sdqs1 = 0x00000028,
+	.dram_sdqs2 = 0x00000028,
+	.dram_sdqs3 = 0x00000028,
+	.dram_reset = 0x00000020,
+};
+
+static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
+	.grp_addds = 0x00000020,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = 0x00000028,
+	.grp_b1ds = 0x00000028,
+	.grp_ctlds = 0x00000020,
+	.grp_ddr_type = 0x000c0000,
+	.grp_b2ds = 0x00000028,
+	.grp_b3ds = 0x00000028,
+};
+
+static const struct mx6_mmdc_calibration neo_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x000E000B,
+	.p0_mpwldectrl1 = 0x000E0010,
+	.p0_mpdgctrl0 = 0x41600158,
+	.p0_mpdgctrl1 = 0x01500140,
+	.p0_mprddlctl = 0x3A383E3E,
+	.p0_mpwrdlctl = 0x3A383C38,
+};
+
+static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = {
+	.p0_mpwldectrl0 = 0x001E0022,
+	.p0_mpwldectrl1 = 0x001C0019,
+	.p0_mpdgctrl0 = 0x41540150,
+	.p0_mpdgctrl1 = 0x01440138,
+	.p0_mprddlctl = 0x403E4644,
+	.p0_mpwrdlctl = 0x3C3A4038,
+};
+
+/* MT41K256M16 */
+static struct mx6_ddr3_cfg neo_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+/* MT41K128M16 */
+static struct mx6_ddr3_cfg neo_basic_mem_ddr = {
+	.mem_speed = 1600,
+	.density = 2,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 14,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	int board = get_board_value();
+
+	struct mx6_ddr_sysinfo sysinfo = {
+		.dsize = 1, /* width of data bus: 1 = 32 bits */
+		.cs_density = 24,
+		.ncs = 1,
+		.cs1_mirror = 0,
+		.rtt_wr = 2,
+		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
+		.walat = 1,		/* Write additional latency */
+		.ralat = 5,		/* Read additional latency */
+		.mif3_mode = 3,		/* Command prediction working mode */
+		.bi_on = 1,		/* Bank interleaving enabled */
+		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
+		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
+	};
+
+	mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS)
+		mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib,
+			     &neo_basic_mem_ddr);
+	else
+		mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr);
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+#endif
diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index b3f3b34f440..2c9dc8b7c55 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -442,11 +442,13 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#if defined(CONFIG_VIDEO_IPUV3)
 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
 	if (is_mx6dq())
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
 	else
 		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
+#endif
 
 	return 0;
 }
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index 0b681c23de9..a3d6b36cb41 100644
--- a/common/spl/spl_mmc.c
+++ b/common/spl/spl_mmc.c
@@ -342,7 +342,6 @@ static int spl_mmc_load_image(struct spl_image_info *spl_image,
 			return err;
 
 		break;
-	case MMCSD_MODE_UNDEFINED:
 #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
 	default:
 		puts("spl: mmc: wrong boot mode\n");
diff --git a/configs/flea3_defconfig b/configs/flea3_defconfig
index 7aa1ba8aea2..c5ccbd6cd91 100644
--- a/configs/flea3_defconfig
+++ b/configs/flea3_defconfig
@@ -1,6 +1,7 @@
 CONFIG_ARM=y
 CONFIG_TARGET_FLEA3=y
 CONFIG_FIT=y
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
@@ -12,3 +13,6 @@ CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig
index 126ce31ff73..ef935221c48 100644
--- a/configs/mx7dsabresd_secure_defconfig
+++ b/configs/mx7dsabresd_secure_defconfig
@@ -45,3 +45,6 @@ CONFIG_G_DNL_MANUFACTURER="FSL"
 CONFIG_G_DNL_VENDOR_NUM=0x0525
 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5
 CONFIG_OF_LIBFDT=y
+CONFIG_SPI_FLASH=y
+CONFIG_CMD_SF=y
+CONFIG_SPI_FLASH_EON=y
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index e0d6f2ee532..4a3e266d7c4 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig
new file mode 100644
index 00000000000..c052dedf136
--- /dev/null
+++ b/configs/ts4600_defconfig
@@ -0,0 +1,18 @@
+CONFIG_ARM=y
+CONFIG_TARGET_TS4600=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC"
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SPL=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
new file mode 100644
index 00000000000..3304afb33c2
--- /dev/null
+++ b/configs/udoo_neo_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_TARGET_UDOO_NEO=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_DHCP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_LIBFDT=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
new file mode 100644
index 00000000000..b1f64f1c0f4
--- /dev/null
+++ b/configs/vining_2000_defconfig
@@ -0,0 +1,31 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_SAMTEC_VINING_2000=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg"
+CONFIG_BOOTDELAY=0
+CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_PCI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
diff --git a/drivers/pwm/pwm-imx-util.c b/drivers/pwm/pwm-imx-util.c
index 285564a6dba..534dd8eece3 100644
--- a/drivers/pwm/pwm-imx-util.c
+++ b/drivers/pwm/pwm-imx-util.c
@@ -15,7 +15,7 @@
 #include <div64.h>
 #include <asm/arch/imx-regs.h>
 
-/* pwm_id from 0..3 */
+/* pwm_id from 0..7 */
 struct pwm_regs *pwm_id_to_reg(int pwm_id)
 {
 	switch (pwm_id) {
@@ -27,6 +27,16 @@ struct pwm_regs *pwm_id_to_reg(int pwm_id)
 		return (struct pwm_regs *)PWM3_BASE_ADDR;
 	case 3:
 		return (struct pwm_regs *)PWM4_BASE_ADDR;
+#ifdef CONFIG_MX6SX
+	case 4:
+		return (struct pwm_regs *)PWM5_BASE_ADDR;
+	case 5:
+		return (struct pwm_regs *)PWM6_BASE_ADDR;
+	case 6:
+		return (struct pwm_regs *)PWM7_BASE_ADDR;
+	case 7:
+		return (struct pwm_regs *)PWM8_BASE_ADDR;
+#endif
 	default:
 		printf("unknown pwm_id: %d\n", pwm_id);
 		break;
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index 0cd77fff51a..d58145e59d5 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -116,9 +116,9 @@
 	"ubiboot=run setup; " \
 	"setenv bootargs ${defargs} ${ubiargs} ${mtdparts} "   \
 	"${setupargs} ${vidargs}; echo Booting from NAND...; " \
-	"ubi part ubi && ubifsmount ubi0:rootfs && " \
-	"ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \
-	"ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \
+	"ubi part ubi && " \
+	"ubi read ${kernel_addr_r} kernel && " \
+	"ubi read ${fdt_addr_r} dtb && " \
 	"bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \
 
 #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot"
diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index 11d9391139f..0f7b3c82dbe 100644
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -101,10 +101,9 @@
 #define CONFIG_CMDLINE_EDITING
 
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE	512	/* Console I/O Buffer Size */
 /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32	/* max number of command args */
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 
 #define CONFIG_SYS_MEMTEST_START	0	/* memtest works on */
@@ -227,8 +226,8 @@
 	"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0"		\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
 	"uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0"		\
-	"update=protect off ${uboot_addr} +40000;"			\
-		"erase ${uboot_addr} +40000;"				\
+	"update=protect off ${uboot_addr} +80000;"			\
+		"erase ${uboot_addr} +80000;"				\
 		"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0"		\
 	"upd=if run load;then echo Updating u-boot;if run update;"	\
 		"then echo U-Boot updated;"				\
diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h
index dce44387979..c5a035fccfa 100644
--- a/include/configs/imx6_spl.h
+++ b/include/configs/imx6_spl.h
@@ -29,6 +29,12 @@
 #define CONFIG_SPL_TEXT_BASE		0x00908000
 #define CONFIG_SPL_MAX_SIZE		0x10000
 #define CONFIG_SPL_STACK		0x0091FFB8
+/*
+ * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the
+ * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a
+ * boot media (given that boot media specific offset is configured properly).
+ */
+#define CONFIG_SPL_PAD_TO		0x11000
 
 /* NAND support */
 #if defined(CONFIG_SPL_NAND_SUPPORT)
diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h
index 360a5e0d9c5..ca5f9db568b 100644
--- a/include/configs/mx7dsabresd.h
+++ b/include/configs/mx7dsabresd.h
@@ -201,6 +201,9 @@
 #define CONFIG_ENV_SIZE			SZ_8K
 #define CONFIG_ENV_IS_IN_MMC
 
+/* MXC SPI driver support */
+#define CONFIG_MXC_SPI
+
 /*
  * If want to use nand, define CONFIG_NAND_MXS and rework board
  * to support nand, since emmc has pin conflicts with nand
diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h
new file mode 100644
index 00000000000..9b7bd1b91dd
--- /dev/null
+++ b/include/configs/ts4600.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2016 Savoir-faire Linux Inc.
+ *
+ * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
+ *
+ * Derived from MX28EVK code by
+ *   Fabio Estevam <fabio.estevam@freescale.com>
+ *   Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the TS4600 Board
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIGS_TS4600_H__
+#define __CONFIGS_TS4600_H__
+
+/* System configurations */
+#define CONFIG_MX28				/* i.MX28 SoC */
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH			/* No NOR Flash */
+#define CONFIG_DOS_PARTITION
+
+/* Memory configuration */
+#define CONFIG_NR_DRAM_BANKS		1		/* 1 bank of DRAM */
+#define PHYS_SDRAM_1			0x40000000	/* Base address */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* Max 1 GB RAM */
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+
+/* Environment */
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+/* Environment is in MMC */
+#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET		(256 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#endif
+
+/* Boot Linux */
+#define CONFIG_LOADADDR		0x42000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_addr=0x41000000\0" \
+	"loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \
+	"loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \
+	"bootscript=echo Running bootscript from mmc...; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"run loadbootscript && source ${loadaddr}; \0" \
+	"sdboot=echo Booting from SD card ...; " \
+		"setenv mmcdev 0; " \
+		"setenv mmcpart 2; " \
+		"setenv root /dev/mmcblk0p3; " \
+		"run loadkernel && run loadfdt; \0" \
+	"startbootsequence=run bootscript || run sdboot \0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc rescan; " \
+	"run startbootsequence; " \
+	"setenv cmdline_append console=ttyAMA0,115200; " \
+	"setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \
+	"bootz ${loadaddr} - ${fdt_addr}; "
+
+/* The rest of the configuration is shared */
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_TS4600_H__ */
diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h
new file mode 100644
index 00000000000..81e04810eb5
--- /dev/null
+++ b/include/configs/udoo_neo.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright Jasbir Matharu
+ * Copyright 2015 UDOO Team
+ *
+ * Configuration settings for the UDOO NEO board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <config_distro_defaults.h>
+#include "mx6_common.h"
+
+#include "imx6_spl.h"
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_MXC_UART
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
+
+/* Command definition */
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_MMC_ENV_DEV		0  /*USDHC2*/
+
+/* Linux only */
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttymxc0,115200\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=undefined\0" \
+	"fdt_addr=0x83000000\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev=0\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcautodetect=no\0" \
+	"findfdt="\
+		"if test $board_name = BASIC; then " \
+			"setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
+		"if test $board_name = BASICKS; then " \
+			"setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \
+		"if test $board_name = FULL; then " \
+			"setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \
+		"if test $board_name = EXTENDED; then " \
+			"setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \
+		"if test $fdt_file = UNDEFINED; then " \
+			"echo WARNING: Could not determine dtb to use; fi; \0" \
+	"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
+	"ramdisk_addr_r=0x83000000\0" \
+	"ramdiskaddr=0x83000000\0" \
+	"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
+	BOOTENV
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0)
+
+#define CONFIG_BOOTCOMMAND \
+	"run findfdt; " \
+	"run distro_bootcmd"
+
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Environment organization */
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_IS_IN_MMC
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h
new file mode 100644
index 00000000000..235574d55dc
--- /dev/null
+++ b/include/configs/vining_2000.h
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2016 samtec automotive software & electronics gmbh
+ *
+ * Configuration settings for the Samtec VIN|ING 2000 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "mx6_common.h"
+
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+#endif
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(3 * SZ_1M)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART1_BASE
+
+#define BOOT_TARGET_DEVICES(func) \
+	func(MMC, mmc, 0) \
+	func(MMC, mmc, 1) \
+	func(USB, usb, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+#include <config_distro_bootcmd.h>
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x10000)
+
+#define CONFIG_STACKSIZE		SZ_128K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Configuration */
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC4_BASE_ADDR
+
+/* I2C Configs */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		  100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
+
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x0
+
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX6
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+#endif
+
+#define CONFIG_CMD_PCI
+#ifdef CONFIG_CMD_PCI
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_PCIE_IMX
+#define CONFIG_PCIE_IMX_PERST_GPIO	IMX_GPIO_NR(4, 6)
+#endif
+
+#define CONFIG_IMX_THERMAL
+
+#define CONFIG_PWM_IMX
+#define CONFIG_IMX6_PWM_PER_CLK 66000000
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+#define CONFIG_ENV_OFFSET		(8 * SZ_64K)
+#define CONFIG_ENV_SIZE			SZ_8K
+#define CONFIG_ENV_OFFSET_REDUND	(9 * SZ_64K)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE
+#define CONFIG_ENV_IS_IN_MMC
+
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SUPPORT_EMMC_BOOT
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_RPMB
+#define CONFIG_SYS_MMC_ENV_DEV		0 /* USDHC4 eMMC */
+/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */
+#define CONFIG_SYS_MMC_ENV_PART		1 /* boot0 */
+#endif
+
+#endif				/* __CONFIG_H */
diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 8c5cf332fa9..406591ce2d5 100644
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -74,6 +74,7 @@
 #define CONFIG_PHY_ATHEROS
 
 /* Framebuffer */
+#ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IPUV3
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
@@ -85,6 +86,7 @@
 #define CONFIG_CMD_HDMIDETECT
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
+#endif
 
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/tools/imximage.c b/tools/imximage.c
index c9e42ec5cab..2cd8d884873 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -281,7 +281,6 @@ static void set_dcd_rst_v2(struct imx_header *imxhdr, uint32_t dcd_len,
 			d = (struct dcd_v2_cmd *)(((char *)d) + len);
 
 		len = (char *)d - (char *)&dcd_v2->header;
-
 		dcd_v2->header.tag = DCD_HEADER_TAG;
 		dcd_v2->header.length = cpu_to_be16(len);
 		dcd_v2->header.version = DCD_VERSION;
@@ -501,10 +500,19 @@ static void print_hdr_v2(struct imx_header *imx_hdr)
 		printf("Entry Point:  %08x\n", (uint32_t)fhdr_v2->entry);
 		if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
 		    (imximage_csf_size != UNDEFINED)) {
+			uint16_t dcdlen;
+			int offs;
+
+			dcdlen = hdr_v2->data.dcd_table.header.length;
+			offs = (char *)&hdr_v2->data.dcd_table
+				- (char *)hdr_v2;
+
 			printf("HAB Blocks:   %08x %08x %08x\n",
 			       (uint32_t)fhdr_v2->self, 0,
 			       hdr_v2->boot_data.size - imximage_ivt_offset -
 			       imximage_csf_size);
+			printf("DCD Blocks:   00910000 %08x %08x\n",
+			       offs, be16_to_cpu(dcdlen));
 		}
 	} else {
 		imx_header_v2_t *next_hdr_v2;
author	Tom Rini	2016-11-30 09:57:52 -0500
committer	Tom Rini	2016-11-30 09:57:52 -0500
commit	4d6647ab17ab9d33c60f7a9f07576c5fbdf6336f (patch)
tree	e3bde11276fcf8ce1c02d797a71fa23d974c66f3
parent	6b29a395b62965eef6b5065d3a526a8588a92038 (diff)
parent	4db4d42ee290a8cad00b358b2e7ef6a00483893b (diff)