powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boards

These boards are still non-generic boards.

It is a good thing that we can drop board-specific hack code
from drivers/mtd/nand/nand_base.c

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>

22 files changed, 2 insertions, 2175 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index a40ae3b38af..5db5e346271 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -101,12 +101,6 @@ config TARGET_FX12MM
 config TARGET_V5FX30TEVAL
 	bool "Support v5fx30teval"
 
-config TARGET_CATCENTER
-	bool "Support CATcenter"
-
-config TARGET_PPCHAMELEONEVB
-	bool "Support PPChameleonEVB"
-
 config TARGET_CPCI2DP
 	bool "Support CPCI2DP"
 
@@ -199,7 +193,6 @@ source "board/avnet/fx12mm/Kconfig"
 source "board/avnet/v5fx30teval/Kconfig"
 source "board/csb272/Kconfig"
 source "board/csb472/Kconfig"
-source "board/dave/PPChameleonEVB/Kconfig"
 source "board/esd/cpci2dp/Kconfig"
 source "board/esd/cpci405/Kconfig"
 source "board/esd/plu405/Kconfig"
diff --git a/board/dave/PPChameleonEVB/Kconfig b/board/dave/PPChameleonEVB/Kconfig
deleted file mode 100644
index bfe00116490..00000000000
--- a/board/dave/PPChameleonEVB/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_CATCENTER
-
-config SYS_BOARD
-	default "PPChameleonEVB"
-
-config SYS_VENDOR
-	default "dave"
-
-config SYS_CONFIG_NAME
-	default "CATcenter"
-
-endif
-
-if TARGET_PPCHAMELEONEVB
-
-config SYS_BOARD
-	default "PPChameleonEVB"
-
-config SYS_VENDOR
-	default "dave"
-
-config SYS_CONFIG_NAME
-	default "PPChameleonEVB"
-
-endif
diff --git a/board/dave/PPChameleonEVB/MAINTAINERS b/board/dave/PPChameleonEVB/MAINTAINERS
deleted file mode 100644
index d43c6d03f2b..00000000000
--- a/board/dave/PPChameleonEVB/MAINTAINERS
+++ /dev/null
@@ -1,20 +0,0 @@
-PPCHAMELEONEVB BOARD
-#M:	-
-S:	Maintained
-F:	board/dave/PPChameleonEVB/
-F:	include/configs/CATcenter.h
-F:	configs/CATcenter_defconfig
-F:	configs/CATcenter_25_defconfig
-F:	configs/CATcenter_33_defconfig
-
-PPCHAMELEONEVB BOARD
-M:	Andrea "llandre" Marson <andrea.marson@dave-tech.it>
-S:	Maintained
-F:	include/configs/PPChameleonEVB.h
-F:	configs/PPChameleonEVB_defconfig
-F:	configs/PPChameleonEVB_BA_25_defconfig
-F:	configs/PPChameleonEVB_BA_33_defconfig
-F:	configs/PPChameleonEVB_HI_25_defconfig
-F:	configs/PPChameleonEVB_HI_33_defconfig
-F:	configs/PPChameleonEVB_ME_25_defconfig
-F:	configs/PPChameleonEVB_ME_33_defconfig
diff --git a/board/dave/PPChameleonEVB/Makefile b/board/dave/PPChameleonEVB/Makefile
deleted file mode 100644
index 31edc4a57d0..00000000000
--- a/board/dave/PPChameleonEVB/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= PPChameleonEVB.o flash.o nand.o
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
deleted file mode 100644
index c9ab50e1269..00000000000
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * (C) Copyright 2003
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-
-int board_early_init_f (void)
-{
-	out32(GPIO0_OR, CONFIG_SYS_NAND0_CE);                 /* set initial outputs     */
-	out32(GPIO0_OR, CONFIG_SYS_NAND1_CE);                 /* set initial outputs     */
-
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0)
-	 * IRQ 26 (EXT IRQ 1)
-	 * IRQ 27 (EXT IRQ 2)
-	 * IRQ 28 (EXT IRQ 3)
-	 * IRQ 29 (EXT IRQ 4)
-	 * IRQ 30 (EXT IRQ 5)
-	 * IRQ 31 (EXT IRQ 6)
-	 */
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-	mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
-	mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
-	mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
-	mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
-	mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
-
-	/*
-	 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
-	 */
-#if 1 /* test-only */
-	mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-#else
-	mtebc (EBC0_CFG, 0x28400000); /* ebc in high-z */
-#endif
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int misc_init_f (void)
-{
-	return 0;  /* dummy implementation */
-}
-
-extern flash_info_t flash_info[];	/* info for FLASH chips */
-
-int misc_init_r (void)
-{
-	/* adjust flash start and size as well as the offset */
-	gd->bd->bi_flashstart = 0 - flash_info[0].size;
-	gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
-#if 0
-	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
-	volatile unsigned char *duart0_mcr =
-		(unsigned char *)((ulong)DUART0_BA + 4);
-	volatile unsigned char *duart1_mcr =
-		(unsigned char *)((ulong)DUART1_BA + 4);
-
-	bd_t *bd = gd->bd;
-	char *	tmp;                    /* Temporary char pointer      */
-	unsigned char *dst;
-	ulong len = sizeof(fpgadata);
-	int status;
-	int index;
-	int i;
-	unsigned long CPC0_CR0Reg;
-
-	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
-	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
-		printf ("GUNZIP ERROR - must RESET board to recover\n");
-		do_reset (NULL, 0, 0, NULL);
-	}
-
-	status = fpga_boot(dst, len);
-	if (status != 0) {
-		printf("\nFPGA: Booting failed ");
-		switch (status) {
-		case ERROR_FPGA_PRG_INIT_LOW:
-			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_INIT_HIGH:
-			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
-			break;
-		case ERROR_FPGA_PRG_DONE:
-			printf("(Timeout: DONE not high after programming FPGA)\n ");
-			break;
-		}
-
-		/* display infos on fpgaimage */
-		index = 15;
-		for (i=0; i<4; i++) {
-			len = dst[index];
-			printf("FPGA: %s\n", &(dst[index+1]));
-			index += len+3;
-		}
-		putc ('\n');
-		/* delayed reboot */
-		for (i=20; i>0; i--) {
-			printf("Rebooting in %2d seconds \r",i);
-			for (index=0;index<1000;index++)
-				udelay(1000);
-		}
-		putc ('\n');
-		do_reset(NULL, 0, 0, NULL);
-	}
-
-	puts("FPGA:  ");
-
-	/* display infos on fpgaimage */
-	index = 15;
-	for (i=0; i<4; i++) {
-		len = dst[index];
-		printf("%s ", &(dst[index+1]));
-		index += len+3;
-	}
-	putc ('\n');
-
-	free(dst);
-
-	/*
-	 * Reset FPGA via FPGA_DATA pin
-	 */
-	SET_FPGA(FPGA_PRG | FPGA_CLK);
-	udelay(1000); /* wait 1ms */
-	SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
-	udelay(1000); /* wait 1ms */
-#endif
-
-#if 0
-	/*
-	 * Enable power on PS/2 interface
-	 */
-	*fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
-
-	/*
-	 * Enable interrupts in exar duart mcr[3]
-	 */
-	*duart0_mcr = 0x08;
-	*duart1_mcr = 0x08;
-#endif
-	return (0);
-}
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof(str));
-
-	puts ("Board: ");
-
-	if (i == -1) {
-		puts ("### No HW ID - assuming PPChameleonEVB");
-	} else {
-		puts(str);
-	}
-
-	putc ('\n');
-
-	return 0;
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: 16 MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
-#ifdef CONFIG_CFB_CONSOLE
-# ifdef CONFIG_CONSOLE_EXTRA_INFO
-# include <video_fb.h>
-extern GraphicDevice smi;
-
-void video_get_info_str (int line_number, char *info)
-{
-	uint pvr = get_pvr ();
-
-	/* init video info strings for graphic console */
-	switch (line_number) {
-	case 1:
-		switch (pvr) {
-		case PVR_405EP_RB:
-			sprintf (info, " AMCC PowerPC 405EP Rev. B");
-			break;
-		default:
-			sprintf (info, " AMCC PowerPC 405EP Rev. <unknown>");
-			break;
-		}
-		return;
-	case 2:
-		sprintf (info, " DAVE Srl PPChameleonEVB - www.dave-tech.it");
-		return;
-	case 3:
-		sprintf (info, " %s", smi.modeIdent);
-		return;
-	}
-
-	/* no more info lines */
-	*info = 0;
-	return;
-}
-# endif	/* CONFIG_CONSOLE_EXTRA_INFO */
-#endif	/* CONFIG_CFB_CONSOLE */
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
deleted file mode 100644
index 771151b80b0..00000000000
--- a/board/dave/PPChameleonEVB/flash.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-#ifdef __DEBUG_START_FROM_SRAM__
-	return CONFIG_SYS_DUMMY_FLASH_SIZE;
-#else
-	unsigned long size;
-	int i;
-	uint pbcr;
-	unsigned long base;
-	int size_val = 0;
-
-	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
-	debug("[%s, %d] flash_info = 0x%p ...\n", __func__, __LINE__,
-						flash_info);
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	debug("[%s, %d] Calling flash_get_size ...\n", __FUNCTION__, __LINE__);
-	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size, size<<20);
-	}
-
-	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
-	/* Setup offsets */
-	flash_get_offsets (-size, &flash_info[0]);
-	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
-	/* Re-do sizing to get full correct info */
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	pbcr = mfdcr(EBC0_CFGDATA);
-	mtdcr(EBC0_CFGADDR, PB0CR);
-	base = -size;
-	switch (size) {
-	case 1 << 20:
-		size_val = 0;
-		break;
-	case 2 << 20:
-		size_val = 1;
-		break;
-	case 4 << 20:
-		size_val = 2;
-		break;
-	case 8 << 20:
-		size_val = 3;
-		break;
-	case 16 << 20:
-		size_val = 4;
-		break;
-	}
-	pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
-	mtdcr(EBC0_CFGDATA, pbcr);
-	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-
-	/* Monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CONFIG_SYS_MONITOR_LEN,
-			    0xffffffff,
-			    &flash_info[0]);
-
-	debug("[%s, %d] Test point ...\n", __FUNCTION__, __LINE__);
-	flash_info[0].size  = size;
-
-	return (size);
-#endif
-}
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
deleted file mode 100644
index a191a0c3a92..00000000000
--- a/board/dave/PPChameleonEVB/nand.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * (C) Copyright 2006 DENX Software Engineering
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-#if defined(CONFIG_CMD_NAND)
-
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- * function borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static void ppchameleonevb_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-	struct nand_chip *this = mtd->priv;
-	ulong base = (ulong) this->IO_ADDR_W;
-
-	if (ctrl & NAND_CTRL_CHANGE) {
-		if ( ctrl & NAND_CLE )
-			MACRO_NAND_CTL_SETCLE((unsigned long)base);
-		else
-			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
-		if ( ctrl & NAND_ALE )
-			MACRO_NAND_CTL_CLRCLE((unsigned long)base);
-		else
-			MACRO_NAND_CTL_CLRALE((unsigned long)base);
-		if ( ctrl & NAND_NCE )
-			MACRO_NAND_ENABLE_CE((unsigned long)base);
-		else
-			MACRO_NAND_DISABLE_CE((unsigned long)base);
-	}
-
-	if (cmd != NAND_CMD_NONE)
-		writeb(cmd, this->IO_ADDR_W);
-}
-
-
-/*
- * read device ready pin
- * function +/- borrowed from Linux 2.6 (drivers/mtd/nand/ppchameleonevb.c)
- */
-static int ppchameleonevb_device_ready(struct mtd_info *mtdinfo)
-{
-	struct nand_chip *this = mtdinfo->priv;
-	ulong rb_gpio_pin;
-
-	/* use the base addr to find out which chip are we dealing with */
-	switch((ulong) this->IO_ADDR_W) {
-	case CONFIG_SYS_NAND0_BASE:
-		rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
-		break;
-	case CONFIG_SYS_NAND1_BASE:
-		rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
-		break;
-	default: /* this should never happen */
-		return 0;
-		break;
-	}
-
-	if (in32(GPIO0_IR) & rb_gpio_pin)
-		return 1;
-	return 0;
-}
-
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a "?" were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-
-	nand->cmd_ctrl = ppchameleonevb_hwcontrol;
-	nand->dev_ready = ppchameleonevb_device_ready;
-	nand->ecc.mode = NAND_ECC_SOFT;
-	nand->chip_delay = NAND_BIG_DELAY_US;
-	nand->options = NAND_SAMSUNG_LP_OPTIONS;
-	return 0;
-}
-#endif
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
deleted file mode 100644
index 94b7076148c..00000000000
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "config.h"
-
-#ifndef RESET_VECTOR_ADDRESS
-#define RESET_VECTOR_ADDRESS	0xfffffffc
-#endif
-
-OUTPUT_ARCH(powerpc)
-
-PHDRS
-{
-  text PT_LOAD;
-  bss PT_LOAD;
-}
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  . = + SIZEOF_HEADERS;
-  .text      :
-  {
-    *(.text*)
-   } :text
-    _etext = .;
-    PROVIDE (etext = .);
-    .rodata    :
-   {
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  } :text
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x00FF) & 0xFFFFFF00;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(256);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(256);
-  __init_end = .;
-
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
-  . = 0xFFFF8000;
-  .ppcenv :
-  {
-    common/env_embedded.o(.ppcenv);
-  }
-
-  .resetvec RESET_VECTOR_ADDRESS :
-  {
-    KEEP(*(.resetvec))
-  } :text = 0xffff
-
-  . = RESET_VECTOR_ADDRESS + 0x4;
-
-  /*
-   * Make sure that the bss segment isn't linked at 0x0, otherwise its
-   * address won't be updated during relocation fixups.  Note that
-   * this is a temporary fix.  Code to dynamically the fixup the bss
-   * location will be added in the future.  When the bss relocation
-   * fixup code is present this workaround should be removed.
-   */
-#if (RESET_VECTOR_ADDRESS == 0xfffffffc)
-  . |= 0x10;
-#endif
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   *(COMMON)
-  } :bss
-
-  . = ALIGN(4);
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/configs/CATcenter_25_defconfig b/configs/CATcenter_25_defconfig
deleted file mode 100644
index 1a8903c4f57..00000000000
--- a/configs/CATcenter_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_33_defconfig b/configs/CATcenter_33_defconfig
deleted file mode 100644
index 4b0eb8d9ff1..00000000000
--- a/configs/CATcenter_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/CATcenter_defconfig b/configs/CATcenter_defconfig
deleted file mode 100644
index 53e00ad222e..00000000000
--- a/configs/CATcenter_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_CATCENTER=y
diff --git a/configs/PPChameleonEVB_BA_25_defconfig b/configs/PPChameleonEVB_BA_25_defconfig
deleted file mode 100644
index e367299a524..00000000000
--- a/configs/PPChameleonEVB_BA_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_BA_33_defconfig b/configs/PPChameleonEVB_BA_33_defconfig
deleted file mode 100644
index f4041c98ace..00000000000
--- a/configs/PPChameleonEVB_BA_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_25_defconfig b/configs/PPChameleonEVB_HI_25_defconfig
deleted file mode 100644
index a9de221c5ca..00000000000
--- a/configs/PPChameleonEVB_HI_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_HI_33_defconfig b/configs/PPChameleonEVB_HI_33_defconfig
deleted file mode 100644
index 882262b68d1..00000000000
--- a/configs/PPChameleonEVB_HI_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_25_defconfig b/configs/PPChameleonEVB_ME_25_defconfig
deleted file mode 100644
index f9a04400dfa..00000000000
--- a/configs/PPChameleonEVB_ME_25_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_ME_33_defconfig b/configs/PPChameleonEVB_ME_33_defconfig
deleted file mode 100644
index 8ee09b8a33e..00000000000
--- a/configs/PPChameleonEVB_ME_33_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33"
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/configs/PPChameleonEVB_defconfig b/configs/PPChameleonEVB_defconfig
deleted file mode 100644
index 2d83330706c..00000000000
--- a/configs/PPChameleonEVB_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_PPCHAMELEONEVB=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 719b970d61e..976fca13ce9 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+CATcenter        powerpc     ppc4xx         -           -
+PPChameleonEVB   powerpc     ppc4xx         -           -           Andrea "llandre" Marson <andrea.marson@dave-tech.it>
 P2020DS          powerpc     mpc85xx        -           -
 P2020COME        powerpc     mpc85xx        -           -           Ira W. Snyder <iws@ovro.caltech.edu>
 P2020RDB         powerpc     mpc85xx        -           -           Poonam Aggrwal <poonam.aggrwal@freescale.com>
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 63bdf65f82c..6db6566e733 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -1065,11 +1065,6 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 		}
 	}
 #endif
-#ifdef PPCHAMELON_NAND_TIMER_HACK
-	time_start = get_timer(0);
-	while (get_timer(time_start) < 10)
-		;
-#endif /*  PPCHAMELON_NAND_TIMER_HACK */
 	led_trigger_event(nand_led_trigger, LED_OFF);
 
 	status = (int)chip->read_byte(mtd);
diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h
deleted file mode 100644
index 27539d27d72..00000000000
--- a/include/configs/CATcenter.h
+++ /dev/null
@@ -1,750 +0,0 @@
-/*
- * ueberarbeitet durch Christoph Seyfert
- *
- * (C) Copyright 2004-2005 DENX Software Engineering,
- *     Wolfgang Grandegger <wg@denx.de>
- * (C) Copyright 2003
- *     DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef	__DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT	"board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll   */
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#define CONFIG_VERSION_VARIABLE	1	/* add version variable		*/
-#define CONFIG_IDENT_STRING	"1"
-
-#undef	CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-
-#define CONFIG_PPC4xx_EMAC
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#ifndef	 CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
-#define CONFIG_PHY1_ADDR	16	/* EMAC1 PHY address		*/
-#else
-#define CONFIG_PHY_ADDR		2	/* PHY address			*/
-#endif
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
-
-#define	CONFIG_TIMESTAMP		/* Print image info with timestamp */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#define	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE }
-#define NAND_BIG_DELAY_US	25
-
-/* For CATcenter there is only NAND on the module */
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#define NAND_NO_RB
-
-#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
-
-#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
-
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
-	switch((unsigned long)nandptr) { \
-	case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
-		break; \
-	case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-#ifdef NAND_NO_RB
-/* constant delay (see also tR in the datasheet) */
-#define NAND_WAIT_READY(nand) do { \
-	udelay(12); \
-} while (0)
-#else
-/* use the R/B pin */
-/* TBD */
-#endif
-
-#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
-#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
-#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#if 0	/* No PCI on CATcenter */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-#endif	/* No PCI */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
-#define CONFIG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND	0x2000
-
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization					*/
-/* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB2AP		0x92015480
-#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB3AP		0x92015480
-#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE		0x00
-#define CONFIG_SYS_FPGA_STATUS		0x02
-#define CONFIG_SYS_FPGA_TS		0x04
-#define CONFIG_SYS_FPGA_TS_LOW		0x06
-#define CONFIG_SYS_FPGA_TS_CAP0	0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
-#define CONFIG_SYS_FPGA_TS_CAP1	0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
-#define CONFIG_SYS_FPGA_TS_CAP2	0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	*/
-#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	*/
-#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	*/
-#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	*/
-#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	*/
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30]	- EMAC0 input
- * GPIO0[31]	- EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL		0x40000550
-#define CONFIG_SYS_GPIO0_OSRH		0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H	0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H		0x15555444
-#define CONFIG_SYS_GPIO0_TSRL		0x00000000
-#define CONFIG_SYS_GPIO0_TSRH		0x00000000
-#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!	are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef		AUTO_MEMORY_CONFIG
-#define		DIMM_READ_ADDR 0xAB
-#define		DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		0x80000000
-#define CPC0_PLLMR1_SSCS	0x80000000
-#define PLL_RESET		0x40000000
-#define CPC0_PLLMR1_PLLR	0x40000000
-    /* Feedback multiplier */
-#define PLL_FBKDIV		0x00F00000
-#define CPC0_PLLMR1_FBDV	0x00F00000
-#define PLL_FBKDIV_16		0x00000000
-#define PLL_FBKDIV_1		0x00100000
-#define PLL_FBKDIV_2		0x00200000
-#define PLL_FBKDIV_3		0x00300000
-#define PLL_FBKDIV_4		0x00400000
-#define PLL_FBKDIV_5		0x00500000
-#define PLL_FBKDIV_6		0x00600000
-#define PLL_FBKDIV_7		0x00700000
-#define PLL_FBKDIV_8		0x00800000
-#define PLL_FBKDIV_9		0x00900000
-#define PLL_FBKDIV_10		0x00A00000
-#define PLL_FBKDIV_11		0x00B00000
-#define PLL_FBKDIV_12		0x00C00000
-#define PLL_FBKDIV_13		0x00D00000
-#define PLL_FBKDIV_14		0x00E00000
-#define PLL_FBKDIV_15		0x00F00000
-    /* Forward A divisor */
-#define PLL_FWDDIVA		0x00070000
-#define CPC0_PLLMR1_FWDVA	0x00070000
-#define PLL_FWDDIVA_8		0x00000000
-#define PLL_FWDDIVA_7		0x00010000
-#define PLL_FWDDIVA_6		0x00020000
-#define PLL_FWDDIVA_5		0x00030000
-#define PLL_FWDDIVA_4		0x00040000
-#define PLL_FWDDIVA_3		0x00050000
-#define PLL_FWDDIVA_2		0x00060000
-#define PLL_FWDDIVA_1		0x00070000
-    /* Forward B divisor */
-#define PLL_FWDDIVB		0x00007000
-#define CPC0_PLLMR1_FWDVB	0x00007000
-#define PLL_FWDDIVB_8		0x00000000
-#define PLL_FWDDIVB_7		0x00001000
-#define PLL_FWDDIVB_6		0x00002000
-#define PLL_FWDDIVB_5		0x00003000
-#define PLL_FWDDIVB_4		0x00004000
-#define PLL_FWDDIVB_3		0x00005000
-#define PLL_FWDDIVB_2		0x00006000
-#define PLL_FWDDIVB_1		0x00007000
-    /* PLL tune bits */
-#define PLL_TUNE_MASK		0x000003FF
-#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
-#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
-#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
-#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
-#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
-#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
-#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
-
-/* Defines for CPC0_PLLMR0 Register fields */
-    /* CPU divisor */
-#define PLL_CPUDIV		0x00300000
-#define CPC0_PLLMR0_CCDV	0x00300000
-#define PLL_CPUDIV_1		0x00000000
-#define PLL_CPUDIV_2		0x00100000
-#define PLL_CPUDIV_3		0x00200000
-#define PLL_CPUDIV_4		0x00300000
-    /* PLB divisor */
-#define PLL_PLBDIV		0x00030000
-#define CPC0_PLLMR0_CBDV	0x00030000
-#define PLL_PLBDIV_1		0x00000000
-#define PLL_PLBDIV_2		0x00010000
-#define PLL_PLBDIV_3		0x00020000
-#define PLL_PLBDIV_4		0x00030000
-    /* OPB divisor */
-#define PLL_OPBDIV		0x00003000
-#define CPC0_PLLMR0_OPDV	0x00003000
-#define PLL_OPBDIV_1		0x00000000
-#define PLL_OPBDIV_2		0x00001000
-#define PLL_OPBDIV_3		0x00002000
-#define PLL_OPBDIV_4		0x00003000
-    /* EBC divisor */
-#define PLL_EXTBUSDIV		0x00000300
-#define CPC0_PLLMR0_EPDV	0x00000300
-#define PLL_EXTBUSDIV_2		0x00000000
-#define PLL_EXTBUSDIV_3		0x00000100
-#define PLL_EXTBUSDIV_4		0x00000200
-#define PLL_EXTBUSDIV_5		0x00000300
-    /* MAL divisor */
-#define PLL_MALDIV		0x00000030
-#define CPC0_PLLMR0_MPDV	0x00000030
-#define PLL_MALDIV_1		0x00000000
-#define PLL_MALDIV_2		0x00000010
-#define PLL_MALDIV_3		0x00000020
-#define PLL_MALDIV_4		0x00000030
-    /* PCI divisor */
-#define PLL_PCIDIV		0x00000003
-#define CPC0_PLLMR0_PPFD	0x00000003
-#define PLL_PCIDIV_1		0x00000000
-#define PLL_PCIDIV_2		0x00000001
-#define PLL_PCIDIV_3		0x00000002
-#define PLL_PCIDIV_4		0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
-				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ	55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ	66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ	66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nand"
-#define CONFIG_JFFS2_PART_SIZE		0x00200000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nand0=catcenter"
-#define MTDPARTS_DEFAULT	"mtdparts=catcenter:2m(nand)"
-*/
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h
deleted file mode 100644
index e277d0d9338..00000000000
--- a/include/configs/PPChameleonEVB.h
+++ /dev/null
@@ -1,777 +0,0 @@
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2003
- * DAVE Srl
- *
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * Credits: Stefan Roese, Wolfgang Denk
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PPCHAMELEON_MODULE_BA	0	/* Basic    Model */
-#define CONFIG_PPCHAMELEON_MODULE_ME	1	/* Medium   Model */
-#define CONFIG_PPCHAMELEON_MODULE_HI	2	/* High-End Model */
-#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
-#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
-#endif
-
-
-/* Only one of the following two symbols must be defined (default is 25 MHz)
- * CONFIG_PPCHAMELEON_CLK_25
- * CONFIG_PPCHAMELEON_CLK_33
- */
-#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
-#define CONFIG_PPCHAMELEON_CLK_25
-#endif
-
-#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
-#error "* Two external frequencies (SysClk) are defined! *"
-#endif
-
-#undef	CONFIG_PPCHAMELEON_SMI712
-
-/*
- * Debug stuff
- */
-#undef	__DEBUG_START_FROM_SRAM__
-#define __DISABLE_MACHINE_EXCEPTION__
-
-#ifdef __DEBUG_START_FROM_SRAM__
-#define CONFIG_SYS_DUMMY_FLASH_SIZE		1024*1024*4
-#endif
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_PPCHAMELEONEVB	1	/* ...on a PPChameleonEVB board */
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFB0000	/* Reserve 320 kB for Monitor */
-#define CONFIG_SYS_LDSCRIPT	"board/dave/PPChameleonEVB/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-#define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-# define CONFIG_SYS_CLK_FREQ	25000000 /* external frequency to pll	*/
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-# define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-#else
-# error "* External frequency (SysClk) not defined! *"
-#endif
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR	00:50:c2:1e:af:fe
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#undef CONFIG_EXT_PHY
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#ifndef	 CONFIG_EXT_PHY
-#define CONFIG_PHY_ADDR		1	/* EMAC0 PHY address		*/
-#define CONFIG_PHY1_ADDR	2	/* EMAC1 PHY address		*/
-#else
-#define CONFIG_PHY_ADDR		2	/* PHY address			*/
-#endif
-#define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_RTC_M41T11	1	/* uses a M41T00 RTC		*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68
-#define CONFIG_SYS_M41T11_BASE_YEAR	1900
-
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/* SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL            2
-#define CONFIG_SYS_SDRAM_tRP           20
-#define CONFIG_SYS_SDRAM_tRC           65
-#define CONFIG_SYS_SDRAM_tRCD          20
-#undef  CONFIG_SYS_SDRAM_tRFC
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-
-#undef	CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_DEVICE_NULLDEV	1	/* include nulldev device	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK		/* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD		691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-
-/*
- * nand device 1 on dave (PPChameleonEVB) needs more time,
- * so we just introduce additional wait in nand_wait(),
- * effectively for both devices.
- */
-#define PPCHAMELON_NAND_TIMER_HACK
-
-#define CONFIG_SYS_NAND0_BASE 0xFF400000
-#define CONFIG_SYS_NAND1_BASE 0xFF000000
-#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
-#define NAND_BIG_DELAY_US	25
-#define CONFIG_SYS_MAX_NAND_DEVICE	2	/* Max number of NAND devices */
-
-#define CONFIG_SYS_NAND0_CE  (0x80000000 >> 1)	 /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)	 /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)	 /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)	 /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND1_CE  (0x80000000 >> 14)  /* our CE is GPIO14 */
-#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)  /* our RDY is GPIO31 */
-#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)  /* our CLE is GPIO15 */
-#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)  /* our ALE is GPIO16 */
-
-#define MACRO_NAND_DISABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_ENABLE_CE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETALE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
-{ \
-	switch((unsigned long)nandptr) \
-	{ \
-	    case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
-		break; \
-	    case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
-	switch((unsigned long)nandptr) { \
-	case CONFIG_SYS_NAND0_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
-		break; \
-	case CONFIG_SYS_NAND1_BASE: \
-		out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
-		break; \
-	} \
-} while(0)
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE	 /* select pci host function	 */
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014	/* PCI Vendor ID: IBM	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: ---	*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-
-/* Reserve 256 kB for Monitor	*/
-/*
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-*/
-
-/* Reserve 320 kB for Monitor	*/
-#define CONFIG_SYS_FLASH_BASE		0xFFFB0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(320 * 1024)
-
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#ifdef ENVIRONMENT_IN_EEPROM
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x100	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x700	/* 2048-256 bytes may be used for env vars (total size of a CAT24WC16 is 2048 bytes)*/
-
-#else	/* DEFAULT: environment in flash, using redundand flash sectors */
-
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars */
-#define CONFIG_ENV_ADDR		0xFFFF8000	/* environment starts at the first small sector */
-#define CONFIG_ENV_SECT_SIZE	0x2000	/* 8196 bytes may be used for env vars*/
-#define CONFIG_ENV_ADDR_REDUND	0xFFFFA000
-#define CONFIG_ENV_SIZE_REDUND	0x2000
-
-#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
-
-#endif	/* ENVIRONMENT_IN_EEPROM */
-
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (External SRAM) initialization					*/
-/* Since this must replace NOR Flash, we use the same settings for CS0		*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB2AP		0x92015480
-#define CONFIG_SYS_EBC_PB2CR		0xFF458000  /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB3AP		0x92015480
-#define CONFIG_SYS_EBC_PB3CR		0xFF058000  /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit	*/
-
-#ifdef CONFIG_PPCHAMELEON_SMI712
-/*
- * Video console (graphic: SMI LynxEM)
- */
-#define CONFIG_VIDEO
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VIDEO_SMI_LYNXEM
-#define CONFIG_VIDEO_LOGO
-/*#define CONFIG_VIDEO_BMP_LOGO*/
-#define CONFIG_CONSOLE_EXTRA_INFO
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
-#define CONFIG_SYS_ISA_IO 0xE8000000
-/* see also drivers/video/videomodes.c */
-#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
-#endif
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-/* FPGA internal regs */
-#define CONFIG_SYS_FPGA_MODE		0x00
-#define CONFIG_SYS_FPGA_STATUS		0x02
-#define CONFIG_SYS_FPGA_TS		0x04
-#define CONFIG_SYS_FPGA_TS_LOW		0x06
-#define CONFIG_SYS_FPGA_TS_CAP0	0x10
-#define CONFIG_SYS_FPGA_TS_CAP0_LOW	0x12
-#define CONFIG_SYS_FPGA_TS_CAP1	0x14
-#define CONFIG_SYS_FPGA_TS_CAP1_LOW	0x16
-#define CONFIG_SYS_FPGA_TS_CAP2	0x18
-#define CONFIG_SYS_FPGA_TS_CAP2_LOW	0x1a
-#define CONFIG_SYS_FPGA_TS_CAP3	0x1c
-#define CONFIG_SYS_FPGA_TS_CAP3_LOW	0x1e
-
-/* FPGA Mode Reg */
-#define CONFIG_SYS_FPGA_MODE_CF_RESET	0x0001
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
-#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
-#define CONFIG_SYS_FPGA_MODE_TS_CLEAR	0x2000
-
-/* FPGA Status Reg */
-#define CONFIG_SYS_FPGA_STATUS_DIP0	0x0001
-#define CONFIG_SYS_FPGA_STATUS_DIP1	0x0002
-#define CONFIG_SYS_FPGA_STATUS_DIP2	0x0004
-#define CONFIG_SYS_FPGA_STATUS_FLASH	0x0008
-#define CONFIG_SYS_FPGA_STATUS_TS_IRQ	0x1000
-
-#define CONFIG_SYS_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
-#define CONFIG_SYS_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
-#define CONFIG_SYS_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
-#define CONFIG_SYS_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
-#define CONFIG_SYS_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0]	- External Bus Controller BLAST output
- * GPIO0[1-9]	- Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30]	- EMAC0 input
- * GPIO0[31]	- EMAC1 reject packet as output
- */
-#define CONFIG_SYS_GPIO0_OSRL		0x40000550
-#define CONFIG_SYS_GPIO0_OSRH		0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L		0x00000000
-/*#define CONFIG_SYS_GPIO0_ISR1H	0x15555445*/
-#define CONFIG_SYS_GPIO0_ISR1H		0x15555444
-#define CONFIG_SYS_GPIO0_TSRL		0x00000000
-#define CONFIG_SYS_GPIO0_TSRH		0x00000000
-#define CONFIG_SYS_GPIO0_TCR		0xF7FF8014
-
-#define CONFIG_NO_SERIAL_EEPROM
-
-/*--------------------------------------------------------------------*/
-
-#ifdef CONFIG_NO_SERIAL_EEPROM
-
-/*
-!-----------------------------------------------------------------------
-! Defines for entry options.
-! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
-!	are plugged in the board will be utilized as non-ECC DIMMs.
-!-----------------------------------------------------------------------
-*/
-#undef		AUTO_MEMORY_CONFIG
-#define		DIMM_READ_ADDR 0xAB
-#define		DIMM_WRITE_ADDR 0xAA
-
-/* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		0x80000000
-#define CPC0_PLLMR1_SSCS	0x80000000
-#define PLL_RESET		0x40000000
-#define CPC0_PLLMR1_PLLR	0x40000000
-    /* Feedback multiplier */
-#define PLL_FBKDIV		0x00F00000
-#define CPC0_PLLMR1_FBDV	0x00F00000
-#define PLL_FBKDIV_16		0x00000000
-#define PLL_FBKDIV_1		0x00100000
-#define PLL_FBKDIV_2		0x00200000
-#define PLL_FBKDIV_3		0x00300000
-#define PLL_FBKDIV_4		0x00400000
-#define PLL_FBKDIV_5		0x00500000
-#define PLL_FBKDIV_6		0x00600000
-#define PLL_FBKDIV_7		0x00700000
-#define PLL_FBKDIV_8		0x00800000
-#define PLL_FBKDIV_9		0x00900000
-#define PLL_FBKDIV_10		0x00A00000
-#define PLL_FBKDIV_11		0x00B00000
-#define PLL_FBKDIV_12		0x00C00000
-#define PLL_FBKDIV_13		0x00D00000
-#define PLL_FBKDIV_14		0x00E00000
-#define PLL_FBKDIV_15		0x00F00000
-    /* Forward A divisor */
-#define PLL_FWDDIVA		0x00070000
-#define CPC0_PLLMR1_FWDVA	0x00070000
-#define PLL_FWDDIVA_8		0x00000000
-#define PLL_FWDDIVA_7		0x00010000
-#define PLL_FWDDIVA_6		0x00020000
-#define PLL_FWDDIVA_5		0x00030000
-#define PLL_FWDDIVA_4		0x00040000
-#define PLL_FWDDIVA_3		0x00050000
-#define PLL_FWDDIVA_2		0x00060000
-#define PLL_FWDDIVA_1		0x00070000
-    /* Forward B divisor */
-#define PLL_FWDDIVB		0x00007000
-#define CPC0_PLLMR1_FWDVB	0x00007000
-#define PLL_FWDDIVB_8		0x00000000
-#define PLL_FWDDIVB_7		0x00001000
-#define PLL_FWDDIVB_6		0x00002000
-#define PLL_FWDDIVB_5		0x00003000
-#define PLL_FWDDIVB_4		0x00004000
-#define PLL_FWDDIVB_3		0x00005000
-#define PLL_FWDDIVB_2		0x00006000
-#define PLL_FWDDIVB_1		0x00007000
-    /* PLL tune bits */
-#define PLL_TUNE_MASK		0x000003FF
-#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
-#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
-#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
-#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
-#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
-#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
-#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/
-
-/* Defines for CPC0_PLLMR0 Register fields */
-    /* CPU divisor */
-#define PLL_CPUDIV		0x00300000
-#define CPC0_PLLMR0_CCDV	0x00300000
-#define PLL_CPUDIV_1		0x00000000
-#define PLL_CPUDIV_2		0x00100000
-#define PLL_CPUDIV_3		0x00200000
-#define PLL_CPUDIV_4		0x00300000
-    /* PLB divisor */
-#define PLL_PLBDIV		0x00030000
-#define CPC0_PLLMR0_CBDV	0x00030000
-#define PLL_PLBDIV_1		0x00000000
-#define PLL_PLBDIV_2		0x00010000
-#define PLL_PLBDIV_3		0x00020000
-#define PLL_PLBDIV_4		0x00030000
-    /* OPB divisor */
-#define PLL_OPBDIV		0x00003000
-#define CPC0_PLLMR0_OPDV	0x00003000
-#define PLL_OPBDIV_1		0x00000000
-#define PLL_OPBDIV_2		0x00001000
-#define PLL_OPBDIV_3		0x00002000
-#define PLL_OPBDIV_4		0x00003000
-    /* EBC divisor */
-#define PLL_EXTBUSDIV		0x00000300
-#define CPC0_PLLMR0_EPDV	0x00000300
-#define PLL_EXTBUSDIV_2		0x00000000
-#define PLL_EXTBUSDIV_3		0x00000100
-#define PLL_EXTBUSDIV_4		0x00000200
-#define PLL_EXTBUSDIV_5		0x00000300
-    /* MAL divisor */
-#define PLL_MALDIV		0x00000030
-#define CPC0_PLLMR0_MPDV	0x00000030
-#define PLL_MALDIV_1		0x00000000
-#define PLL_MALDIV_2		0x00000010
-#define PLL_MALDIV_3		0x00000020
-#define PLL_MALDIV_4		0x00000030
-    /* PCI divisor */
-#define PLL_PCIDIV		0x00000003
-#define CPC0_PLLMR0_PPFD	0x00000003
-#define PLL_PCIDIV_1		0x00000000
-#define PLL_PCIDIV_2		0x00000001
-#define PLL_PCIDIV_3		0x00000002
-#define PLL_PCIDIV_4		0x00000003
-
-#ifdef CONFIG_PPCHAMELEON_CLK_25
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_8	|  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
-
-/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
-#define PPCHAMELEON_PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
-				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-
-#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-				  PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
-
-#else
-#error "* External frequency (SysClk) not defined! *"
-#endif
-
-#if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
-/* Model HI */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_333_111_37_55_55
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_333_111_37_55_55
-#define CONFIG_SYS_OPB_FREQ	55555555
-/* Model ME */
-#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_266_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_266_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ	66666666
-#else
-/* Model BA (default) */
-#define PLLMR0_DEFAULT	PPCHAMELEON_PLLMR0_133_133_33_66_33
-#define PLLMR1_DEFAULT	PPCHAMELEON_PLLMR1_133_133_33_66_33
-#define CONFIG_SYS_OPB_FREQ	66666666
-#endif
-
-#endif /* CONFIG_NO_SERIAL_EEPROM */
-
-#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
-#define NAND_CACHE_PAGES 16			/* size of nand cache in 512 bytes pages */
-
-/*
- * JFFS2 partitions
- */
-
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV		"nand0"
-#define CONFIG_JFFS2_PART_SIZE		0x00400000
-#define CONFIG_JFFS2_PART_OFFSET	0x00000000
-
-/* mtdparts command line support */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT		"nor0=PPChameleon-0,nand0=ppchameleonevb-nand"
-*/
-
-/* 256 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
-					"1792k(user),256k(u-boot);" \
-				"ppchameleonevb-nand:-(nand)"
-*/
-
-/* 320 kB U-boot image */
-/*
-#define MTDPARTS_DEFAULT	"mtdparts=PPChameleon-0:1m(kernel1),1m(kernel2)," \
-					"1728k(user),320k(u-boot);" \
-				"ppchameleonevb-nand:-(nand)"
-*/
-
-#endif	/* __CONFIG_H */