diff options
| author | Ley Foon Tan | 2020-12-22 09:53:25 +0800 |
|---|---|---|
| committer | Ley Foon Tan | 2021-01-15 17:48:39 +0800 |
| commit | 53b59290c59a4b699d829655987d1b96e4810aaf (patch) | |
| tree | 878711025dde22e36e24691d405f377a7b309d8a | |
| parent | bcf33fac64998d4c0c030d0711e6b02039f71a8d (diff) | |
configs: socfpga: Add CONFIG_SPL_PAD_TO
Add CONFIG_SPL_PAD_TO for Gen5 and Arria 10. CONFIG_SPL_PAD_TO is set to
size of OCRAM.
This is preparation for image padding change in socfpgaimage.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
| -rw-r--r-- | include/configs/socfpga_common.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 3d71759da4b..62b327cd6e5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -22,8 +22,10 @@ #if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE +#define CONFIG_SPL_PAD_TO 0x10000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SPL_PAD_TO 0x40000 /* SPL memory allocation configuration, this is for FAT implementation */ #ifndef CONFIG_SYS_SPL_MALLOC_SIZE #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 |