aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSimon Glass2019-01-21 14:53:21 -0700
committerPhilipp Tomsich2019-02-01 16:59:12 +0100
commit5c01d1c0d0e673dbd5739256e77e9dca9dc74816 (patch)
treeca8627bed692af68d73aa2bd5f9f3a6ffef9d071
parent66f657d15b5d95a80ea8329002762118a97aae17 (diff)
gpio: Add a simple GPIO API for SPL
In space-constrained environments or before driver model is available, it is sometimes necessary to set GPIO values. Add an SPL API for this, to allow early board code to change GPIOs. The caller must provide the register address, so that the drivers can be fairly generic. This API can be implemented by GPIO drivers, behind a suitable guard, like #ifdef CONFIG_SPL_BUILD. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
-rw-r--r--include/spl_gpio.h62
1 files changed, 62 insertions, 0 deletions
diff --git a/include/spl_gpio.h b/include/spl_gpio.h
new file mode 100644
index 00000000000..e410e62914d
--- /dev/null
+++ b/include/spl_gpio.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Simple GPIO access from SPL. This only supports a single GPIO space,
+ * typically the SoC GPIO banks.
+ *
+ * Copyright 2018 Google LLC
+ */
+
+#ifndef __SPL_GPIO_H
+#define __SPL_GPIO_H
+
+#include <asm/gpio.h>
+
+/*
+ * The functions listed here should be implemented in the SoC GPIO driver.
+ * They correspond to the normal GPIO API (asm-generic/gpio.h). The GPIO
+ * number is encoded in an unsigned int by an SoC-specific means. Pull
+ * values are also SoC-specific.
+ *
+ * This API should only be used in TPL/SPL where GPIO access is needed but
+ * driver model is not available (yet) or adds too much overhead.
+ *
+ * The caller must supply the GPIO register base since this information is
+ * often specific to a particular SoC generation. This allows the GPIO
+ * code to be fairly generic.
+ *
+ * Only a single implementation of each of these functions can be provided.
+ *
+ * The 'gpio' value can include both a bank and a GPIO number, if desired. The
+ * encoding is SoC-specific.
+ */
+
+/**
+ * spl_gpio_set_pull() - Set the pull up/down state of a GPIO
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @pull: Pull value (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_set_pull(void *regs, uint gpio, int pull);
+
+/**
+ * spl_gpio_output() - Set a GPIO as an output
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @value: 0 to set the output low, 1 to set it high
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_output(void *regs, uint gpio, int value);
+
+/**
+ * spl_gpio_input() - Set a GPIO as an input
+ *
+ * @regs: Pointer to GPIO registers
+ * @gpio: GPIO to adjust (SoC-specific)
+ * @return return 0 if OK, -ve on error
+ */
+int spl_gpio_input(void *regs, uint gpio);
+
+#endif /* __SPL_GPIO_H */