diff options
| author | Zhao Qiang | 2020-07-14 13:53:36 +0800 |
|---|---|---|
| committer | Priyanka Jain | 2020-07-27 14:24:15 +0530 |
| commit | 5c64d07f764d269b51aa636044f7a66fbd1ad4fc (patch) | |
| tree | b3ff7b037f7da4a8b1667b012f5509d137c97a4b | |
| parent | e5d8fe9c9a7770a3bbae9d15366b884698f3c329 (diff) | |
arm: dts: ls1028a: Add dspi flash device node to qds
Add dspi flash device node to fsl-ls1028a-qds.dtsi
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| -rw-r--r-- | arch/arm/dts/fsl-ls1028a-qds.dtsi | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 4f56f40bd32..6cdcce1b92f 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -15,20 +15,94 @@ compatible = "fsl,ls1028a-qds", "fsl,ls1028a"; aliases { spi0 = &fspi; + spi1 = &dspi0; + spi2 = &dspi1; + spi3 = &dspi2; }; }; &dspi0 { + bus-num = <0>; status = "okay"; + + dflash0: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + + dflash1: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash2: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; }; &dspi1 { + bus-num = <0>; status = "okay"; + + dflash3: sst25wf040b { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; + + dflash4: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <1>; + }; + dflash5: n25q128a { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <2>; + }; }; &dspi2 { + bus-num = <0>; status = "okay"; + + dflash8: en25s64 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <3000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; }; &esdhc0 { |