diff options
| author | Alison Wang | 2017-04-11 15:02:13 +0800 |
|---|---|---|
| committer | York Sun | 2017-04-24 08:59:43 -0700 |
| commit | 5d267ec67901d9e5fd6e535eec84bd9176501403 (patch) | |
| tree | 1cca1ed7acdbe9abef543f0b964075492be2f8a0 | |
| parent | 3c476d841daa491f87c8f07851038afbdf4d90a8 (diff) | |
arm: ls1021atwr: Enable RGMII TX/RX clock internal delay for AR8033
Since commit ce412b7, RGMII TX clock internal delay is not enabled
for AR8033 unconditionally. On LS1021ATWR board, the third port
eTSEC3 uses AR8033 in RGMII mode. The TX/RX internal delay needs to
be enabled.
This patch will set PHY_INTERFACE_MODE_RGMII_ID to enable RGMII TX/RX
clock internal delay for AR8033 on the third port.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
| -rw-r--r-- | board/freescale/ls1021atwr/ls1021atwr.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index d96fd774d36..ff32d5cb28e 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis) #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; num++; #endif if (!num) { |