diff options
| author | Marek Vasut | 2023-09-17 16:11:38 +0200 |
|---|---|---|
| committer | Marek Vasut | 2023-10-01 00:08:28 +0200 |
| commit | 635811a106f6b0a5ffdd398d08f04377f4f88942 (patch) | |
| tree | 115feab6553697e0485833f5bdac1a66a772a0dd | |
| parent | 47ce17386bbeffe8f307b8902f6f8f3ebca67467 (diff) | |
clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| -rw-r--r-- | drivers/clk/renesas/r8a774a1-cpg-mssr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 1f76d6b2c2e..6280061af89 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -47,7 +47,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a774a1_core_clks[] = { +static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -121,7 +121,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = { DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a774a1_mod_clks[] = { +static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6), DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2), DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2), @@ -276,7 +276,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, |