diff options
| author | Mugunthan V N | 2016-04-28 15:36:05 +0530 |
|---|---|---|
| committer | Joe Hershberger | 2016-05-24 11:42:02 -0500 |
| commit | 70c5b7b37e34099c428366bdaf266f472dc24377 (patch) | |
| tree | e857c2e5ec259064f5ec2d8cb73a368c93249c6c | |
| parent | b2003c5458e883c691f3a7f5f770e6ed36e1b9d7 (diff) | |
ARM: omap5: add platform specific ethernet phy modes configurations
Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| -rw-r--r-- | arch/arm/include/asm/arch-omap5/cpu.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index b1513e9aaf4..683d9053337 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -116,4 +116,16 @@ struct watchdog { #define CPSW_BASE 0x48484000 #define CPSW_MDIO_BASE 0x48485000 +/* gmii_sel register defines */ +#define GMII1_SEL_MII 0x0 +#define GMII1_SEL_RMII 0x1 +#define GMII1_SEL_RGMII 0x2 +#define GMII2_SEL_MII (GMII1_SEL_MII << 4) +#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4) +#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4) + +#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII) +#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII) +#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII) + #endif /* _CPU_H */ |