arm: Remove wb50n board

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Ben Whitten <ben.whitten@lairdtech.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

7 files changed, 0 insertions, 386 deletions

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 5880e651baf..22f6e4114e8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -303,14 +303,6 @@ config TARGET_VINCO
 	select SUPPORT_SPL
 	imply CMD_DM
 
-config TARGET_WB50N
-	bool "Support Laird WB50N"
-	select BOARD_EARLY_INIT_F
-	select BOARD_LATE_INIT
-	select CPU_V7A
-	select SUPPORT_SPL
-	select ATMEL_SFR
-
 endchoice
 
 config ATMEL_SFR
@@ -353,7 +345,6 @@ source "board/ronetix/pm9g45/Kconfig"
 source "board/siemens/corvus/Kconfig"
 source "board/siemens/taurus/Kconfig"
 source "board/siemens/smartweb/Kconfig"
-source "board/laird/wb50n/Kconfig"
 
 config SPL_LDSCRIPT
 	default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS
diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig
deleted file mode 100644
index 2e7090ec34b..00000000000
--- a/board/laird/wb50n/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_WB50N
-
-config SYS_BOARD
-	default "wb50n"
-
-config SYS_VENDOR
-	default "laird"
-
-config SYS_CONFIG_NAME
-	default "wb50n"
-
-endif
diff --git a/board/laird/wb50n/MAINTAINERS b/board/laird/wb50n/MAINTAINERS
deleted file mode 100644
index 3d38fc4e9fa..00000000000
--- a/board/laird/wb50n/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WB50N CPU MODULE
-M:	Ben Whitten <ben.whitten@lairdtech.com>
-S:	Maintained
-F:	board/laird/wb50n/
-F:	include/configs/wb50n.h
-F:	configs/wb50n_defconfig
diff --git a/board/laird/wb50n/Makefile b/board/laird/wb50n/Makefile
deleted file mode 100644
index f4c3831db46..00000000000
--- a/board/laird/wb50n/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y += wb50n.o
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
deleted file mode 100644
index 8fa989a2a4f..00000000000
--- a/board/laird/wb50n/wb50n.c
+++ /dev/null
@@ -1,206 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch/at91_sfr.h>
-#include <asm/arch/sama5d3_smc.h>
-#include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/clk.h>
-#include <env.h>
-#include <micrel.h>
-#include <net.h>
-#include <netdev.h>
-#include <spl.h>
-#include <asm/arch/atmel_mpddrc.h>
-#include <asm/arch/at91_wdt.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* ------------------------------------------------------------------------- */
-/*
- * Miscelaneous platform dependent initialisations
- */
-
-void wb50n_nand_hw_init(void)
-{
-	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
-
-	at91_periph_clk_enable(ATMEL_ID_SMC);
-
-	/* Configure SMC CS3 for NAND/SmartMedia */
-	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(1) |
-	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(1),
-	       &smc->cs[3].setup);
-	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(5) |
-	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(5),
-	       &smc->cs[3].pulse);
-	writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
-	       &smc->cs[3].cycle);
-	writel(AT91_SMC_TIMINGS_TCLR(3) | AT91_SMC_TIMINGS_TADL(10) |
-	       AT91_SMC_TIMINGS_TAR(3) | AT91_SMC_TIMINGS_TRR(4) |
-	       AT91_SMC_TIMINGS_TWB(5) | AT91_SMC_TIMINGS_RBNSEL(3) |
-	       AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
-	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
-	       AT91_SMC_MODE_EXNW_DISABLE |
-	       AT91_SMC_MODE_DBW_8 |
-	       AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode);
-
-	/* Disable Flash Write Protect Line */
-	at91_set_pio_output(AT91_PIO_PORTE, 14, 1);
-}
-
-int board_early_init_f(void)
-{
-	at91_periph_clk_enable(ATMEL_ID_PIOA);
-	at91_periph_clk_enable(ATMEL_ID_PIOB);
-	at91_periph_clk_enable(ATMEL_ID_PIOC);
-	at91_periph_clk_enable(ATMEL_ID_PIOD);
-	at91_periph_clk_enable(ATMEL_ID_PIOE);
-
-	at91_seriald_hw_init();
-
-	return 0;
-}
-
-int board_init(void)
-{
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
-	wb50n_nand_hw_init();
-
-	at91_macb_hw_init();
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
-	                            CONFIG_SYS_SDRAM_SIZE);
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	/* rx data delay */
-	ksz9021_phy_extended_write(phydev,
-	                           MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222);
-	/* tx data delay */
-	ksz9021_phy_extended_write(phydev,
-	                           MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222);
-	/* rx/tx clock delay */
-	ksz9021_phy_extended_write(phydev,
-	                           MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4);
-
-	return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
-	int rc = 0;
-
-	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
-
-	return rc;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-#include <linux/ctype.h>
-int board_late_init(void)
-{
-#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-	const char *LAIRD_NAME = "lrd_name";
-	char name[32], *p;
-
-	strcpy(name, get_cpu_name());
-	for (p = name; *p != '\0'; *p = tolower(*p), p++)
-		;
-	strcat(name, "-wb50n");
-	env_set(LAIRD_NAME, name);
-
-#endif
-
-	return 0;
-}
-#endif
-
-/* SPL */
-#ifdef CONFIG_SPL_BUILD
-void spl_board_init(void)
-{
-	wb50n_nand_hw_init();
-}
-
-static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
-{
-	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR_SDRAM);
-
-	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
-	            ATMEL_MPDDRC_CR_NR_ROW_13 |
-	            ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
-	            ATMEL_MPDDRC_CR_NDQS_DISABLED |
-	            ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
-	            ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
-
-	ddr2->rtr = 0x411;
-
-	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
-	              8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
-
-	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
-	              200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
-	              19 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
-	              18 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
-
-	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
-	              3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
-	              7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
-	              2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
-}
-
-void mem_init(void)
-{
-	struct atmel_mpddrc_config ddr2;
-
-	ddr2_conf(&ddr2);
-
-	configure_ddrcfg_input_buffers(true);
-
-	/* enable MPDDR clock */
-	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
-	at91_system_clk_enable(AT91_PMC_DDR);
-
-	/* DDRAM2 Controller initialize */
-	ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
-}
-
-void at91_pmc_init(void)
-{
-	u32 tmp;
-
-	tmp = AT91_PMC_PLLAR_29 |
-	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
-	      AT91_PMC_PLLXR_MUL(43) | AT91_PMC_PLLXR_DIV(1);
-	at91_plla_init(tmp);
-
-	at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x3));
-
-	tmp = AT91_PMC_MCKR_MDIV_4 | AT91_PMC_MCKR_CSS_PLLA;
-	at91_mck_init(tmp);
-}
-#endif
diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig
deleted file mode 100644
index 0ffc5b4d73a..00000000000
--- a/configs/wb50n_defconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_CPU_INIT=y
-CONFIG_ARCH_AT91=y
-CONFIG_SYS_TEXT_BASE=0x23f00000
-CONFIG_TARGET_WB50N=y
-CONFIG_SPL_GPIO_SUPPORT=y
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SYS_MEMTEST_START=0x21000000
-CONFIG_SYS_MEMTEST_END=0x22000000
-CONFIG_ENV_OFFSET=0xA0000
-CONFIG_SPL_TEXT_BASE=0x300000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0xC0000
-CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="SAMA5D3,SYS_USE_NANDFLASH"
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs"
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_SPL_NAND_DRIVERS=y
-CONFIG_SPL_NAND_BASE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_BOOTZ=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-# CONFIG_CMD_FLASH is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_NAND=y
-CONFIG_CMD_NAND_TRIMFFS=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_NAND=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_AT91_GPIO=y
-CONFIG_MTD=y
-CONFIG_MTD_RAW_NAND=y
-# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_PMECC_CAP=8
-CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_MICREL=y
-CONFIG_PHY_MICREL_KSZ90X1=y
-CONFIG_ATMEL_USART=y
-CONFIG_LZMA=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
deleted file mode 100644
index b1f3b8452cb..00000000000
--- a/include/configs/wb50n.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the WB50N CPU Module.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/hardware.h>
-
-/* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000	/* from 12 MHz crystal */
-
-#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SKIP_LOWLEVEL_INIT
-#endif
-
-/* serial console */
-#define CONFIG_USART_BASE       ATMEL_BASE_DBGU
-#define CONFIG_USART_ID         ATMEL_ID_DBGU
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE       ATMEL_BASE_DDRCS
-#define CONFIG_SYS_SDRAM_SIZE       0x04000000
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_INIT_SP_ADDR     0x310000
-#else
-#define CONFIG_SYS_INIT_SP_ADDR \
-    (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
-#endif
-
-/* NAND flash */
-#define CONFIG_SYS_MAX_NAND_DEVICE  1
-#define CONFIG_SYS_NAND_BASE        ATMEL_BASE_CS3
-/* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE    (1 << 21)
-/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE    (1 << 22)
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
-/* Ethernet Hardware */
-#define CONFIG_MACB
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT      20
-#define CONFIG_MACB_SEARCH_PHY
-#define CONFIG_RGMII
-#define CONFIG_ETHADDR              C0:EE:40:00:00:00
-
-#define CONFIG_SYS_LOAD_ADDR        0x22000000	/* load address */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-    "autoload=no\0" \
-    "autostart=no\0"
-
-/* bootstrap + u-boot + env in nandflash */
-#define CONFIG_BOOTCOMMAND \
-    "nand read 0x22000000 0x000e0000 0x500000; " \
-    "bootm"
-
-#define CONFIG_SYS_CBSIZE           1024
-#define CONFIG_SYS_MAXARGS          16
-#define CONFIG_SYS_PBSIZE \
-    (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN       (2 * 1024 * 1024)
-
-/* SPL */
-#define CONFIG_SPL_MAX_SIZE         0x10000
-#define CONFIG_SPL_BSS_START_ADDR   0x20000000
-#define CONFIG_SPL_BSS_MAX_SIZE     0x80000
-#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
-#define CONFIG_SYS_SPL_MALLOC_SIZE  0x80000
-
-#define CONFIG_SYS_MONITOR_LEN      (512 << 10)
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
-#define CONFIG_SYS_NAND_5_ADDR_CYCLE
-#define CONFIG_SYS_NAND_PAGE_SIZE   0x800
-#define CONFIG_SYS_NAND_PAGE_COUNT  64
-#define CONFIG_SYS_NAND_OOBSIZE     64
-#define CONFIG_SYS_NAND_BLOCK_SIZE  0x20000
-#define CONFIG_SYS_NAND_BAD_BLOCK_POS   0x0
-
-#endif