diff options
| author | Kishon Vijay Abraham I | 2018-01-30 16:01:34 +0100 |
|---|---|---|
| committer | Jaehoon Chung | 2018-02-19 16:58:54 +0900 |
| commit | 9b3fc21837dc32eda9656f264f74719ea77311a2 (patch) | |
| tree | 066b0b655cabb565d1ed4e67a0869d8940f4dc82 | |
| parent | 8fc238bfada16d61dee4240de2d49f38a6a6f941 (diff) | |
mmc: omap_hsmmc: Enable DDR mode support
In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
| -rw-r--r-- | arch/arm/include/asm/omap_mmc.h | 1 | ||||
| -rw-r--r-- | drivers/mmc/omap_hsmmc.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 507435a11f3..6aca9e90cfd 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -89,6 +89,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index c6b74a1263f..2f4909e34bd 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; + if (mmc_is_mode_ddr(priv->mode)) + writel(readl(&mmc_base->con) | DDR, &mmc_base->con); + else + writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); + switch (priv->mode) { case MMC_HS_200: case UHS_SDR104: |