diff options
| author | Ye Li | 2019-05-15 09:56:59 +0000 |
|---|---|---|
| committer | Stefano Babic | 2019-07-19 20:14:50 +0200 |
| commit | 9c1563e3fd24ca7161c089dfd999d031f95094de (patch) | |
| tree | 2427c80f845acaaaca1c198f46f06fa63c89a0c2 | |
| parent | 285aea01d2f9398b9c127c7a7fbaa401adf6969f (diff) | |
mx7ulp: Select the SCG1 APLL PFD as a system clock source
Due to the APLL out glitch issue, the APLLCFG PLLS bit must
be set to select SCG1 APLL PFD for generating system clock to align
with the design.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | board/freescale/mx7ulp_evk/imximage.cfg | 2 | ||||
| -rw-r--r-- | board/freescale/mx7ulp_evk/plugin.S | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index d4f6c3c62df..6bc7c199f51 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -45,7 +45,7 @@ DATA 4 0x403f00dc 0x00000000 DATA 4 0x403e0040 0x01000020 DATA 4 0x403e0500 0x01000000 DATA 4 0x403e050c 0x80808080 -DATA 4 0x403e0508 0x00160000 +DATA 4 0x403e0508 0x00160002 DATA 4 0x403E0510 0x00000002 DATA 4 0x403E0514 0x00000005 DATA 4 0x403e0500 0x00000001 diff --git a/board/freescale/mx7ulp_evk/plugin.S b/board/freescale/mx7ulp_evk/plugin.S index ccd2fc03a43..55dfecc7512 100644 --- a/board/freescale/mx7ulp_evk/plugin.S +++ b/board/freescale/mx7ulp_evk/plugin.S @@ -18,7 +18,7 @@ ldr r3, =0x80808080 str r3, [r2, #0x50c] - ldr r3, =0x00160000 + ldr r3, =0x00160002 str r3, [r2, #0x508] ldr r3, =0x00000002 str r3, [r2, #0x510] |