diff options
| author | Anton Staaf | 2011-10-17 16:46:04 -0700 |
|---|---|---|
| committer | Wolfgang Denk | 2011-10-23 20:50:42 +0200 |
| commit | a8fc12eb8e7ff6a97c45d921fdf28dcaaba9c8b6 (patch) | |
| tree | c7dc3e047de38980770e2207b37a96a15322fcc9 | |
| parent | 44d6cbb6a77665caa14be2a561c4148446b3ba7e (diff) | |
m68k: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Jason Jin <jason.jin@freescale.com>
| -rw-r--r-- | arch/m68k/include/asm/cache.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 7c84e484711..5c9bb308356 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -207,4 +207,14 @@ void dcache_invalid(void); #endif +/* + * m68k uses 16 byte L1 data cache line sizes. Use this for DMA buffer + * alignment unless the board configuration has specified a new value. + */ +#ifdef CONFIG_SYS_CACHELINE_SIZE +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 16 +#endif + #endif /* __CACHE_H */ |