diff options
| author | Tom Rini | 2019-07-14 09:09:49 -0400 |
|---|---|---|
| committer | Tom Rini | 2019-07-14 09:09:49 -0400 |
| commit | a9a3a37f92b072a56693ad665ab4c5cc73028d16 (patch) | |
| tree | d0a4e94e94d77ba06983abbe4b89d2c39a0c5d7f | |
| parent | 6070ef409c1018860e8dd1f077297546d9d80115 (diff) | |
| parent | 291f00bb3ea7e9f9acdddbe680991e76313732d6 (diff) | |
Merge tag 'u-boot-stm32-20190712' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- syscon: add support for power off
- stm32mp1: add op-tee config
- stm32mp1: add specific commands: stboard and stm32key
- add stm32 mailbox driver
- solve many stm32 warnings when building with W=1
- update stm32 gpio driver
64 files changed, 1690 insertions, 529 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index e91684191fe..bc67c499657 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -297,10 +297,12 @@ ARM STM STM32MP M: Patrick Delaunay <patrick.delaunay@st.com> M: Patrice Chotard <patrice.chotard@st.com> L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +T: git https://gitlab.denx.de/u-boot/custodians/u-boot-stm S: Maintained F: arch/arm/mach-stm32mp/ F: drivers/clk/clk_stm32mp1.c F: drivers/i2c/stm32f7_i2c.c +F: drivers/mailbox/stm32-ipcc.c F: drivers/misc/stm32mp_fuse.c F: drivers/mmc/stm32_sdmmc2.c F: drivers/phy/phy-stm32-usbphyc.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 87541977259..5ab9cbe8321 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1498,6 +1498,7 @@ config ARCH_STM32MP select MISC select OF_CONTROL select OF_LIBFDT + select OF_SYSTEM_SETUP select PINCTRL select REGMAP select SUPPORT_SPL diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi index 6da0a636c1b..fe437bbfe2f 100644 --- a/arch/arm/dts/stm32429i-eval-u-boot.dtsi +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -92,57 +92,46 @@ }; &gpioa { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiob { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioc { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiod { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioe { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiof { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiog { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioh { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioi { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioj { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiok { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f429-disco-u-boot.dtsi b/arch/arm/dts/stm32f429-disco-u-boot.dtsi index 0cc3100440c..52f80320bc8 100644 --- a/arch/arm/dts/stm32f429-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f429-disco-u-boot.dtsi @@ -79,57 +79,46 @@ }; &gpioa { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiob { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioc { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiod { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioe { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiof { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiog { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioh { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioi { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioj { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiok { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f469-disco-u-boot.dtsi b/arch/arm/dts/stm32f469-disco-u-boot.dtsi index 3da308e6a43..2409cf746ab 100644 --- a/arch/arm/dts/stm32f469-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f469-disco-u-boot.dtsi @@ -94,57 +94,46 @@ }; &gpioa { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiob { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioc { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiod { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioe { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiof { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiog { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioh { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioi { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioj { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiok { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 29b157324e6..3ba7f8410d2 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -65,58 +65,41 @@ }; &gpioa { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiob { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioc { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiod { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioe { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiof { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiog { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioh { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioi { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; -&gpioj { - compatible = "st,stm32-gpio"; -}; - -&gpiok { - compatible = "st,stm32-gpio"; -}; - &pinctrl { u-boot,dm-pre-reloc; diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi index 4172c02f0a2..479b700c868 100644 --- a/arch/arm/dts/stm32mp15-ddr.dtsi +++ b/arch/arm/dts/stm32mp15-ddr.dtsi @@ -5,7 +5,7 @@ / { soc { - ddr: ddr@0x5A003000{ + ddr: ddr@5A003000 { u-boot,dm-pre-reloc; compatible = "st,stm32mp1-ddr"; diff --git a/arch/arm/dts/stm32mp157-pinctrl.dtsi b/arch/arm/dts/stm32mp157-pinctrl.dtsi index 4c424c488d3..9bae85045a1 100644 --- a/arch/arm/dts/stm32mp157-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp157-pinctrl.dtsi @@ -14,6 +14,7 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hwspinlock 0>; pins-are-numbered; gpioa: gpio@50002000 { @@ -164,6 +165,27 @@ }; }; + cec_pins_sleep_a: cec-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ + }; + }; + + cec_pins_b: cec-1 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF5)>; + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + cec_pins_sleep_b: cec-sleep-1 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ @@ -269,7 +291,14 @@ }; }; - i2c1_pins_b: i2c1-1 { + i2c1_pins_sleep_a: i2c1-1 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c1_pins_b: i2c1-2 { pins { pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ @@ -289,7 +318,14 @@ }; }; - i2c2_pins_b: i2c2-1 { + i2c2_pins_sleep_a: i2c2-1 { + pins { + pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ + <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ + }; + }; + + i2c2_pins_b: i2c2-2 { pins { pinmux = <STM32_PINMUX('Z', 0, AF3)>, /* I2C2_SCL */ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ @@ -309,6 +345,152 @@ }; }; + i2c5_pins_sleep_a: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ + + }; + }; + + ltdc_pins_a: ltdc-a-0 { + pins { + pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ + <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_a: ltdc-a-1 { + pins { + pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ + }; + }; + + ltdc_pins_b: ltdc-b-0 { + pins { + pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ + <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ + <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ + <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ + <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ + <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ + <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ + <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_pins_sleep_b: ltdc-b-1 { + pins { + pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ + <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ + <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ + <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ + <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ + <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ + <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ + <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ + <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ + <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ + <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ + <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ + <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ + <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ + <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ + <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ + <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ + <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ + <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ + <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ + <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ + <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ + <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ + <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ + <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ + <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ + <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ + <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ + }; + }; + m_can1_pins_a: m-can1-0 { pins1 { pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ @@ -322,6 +504,13 @@ }; }; + m_can1_sleep_pins_a: m_can1-sleep@0 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ + }; + }; + pwm2_pins_a: pwm2-0 { pins { pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ @@ -393,7 +582,8 @@ slew-rate = <3>; }; }; - sdmmc1_b4_pins_a: sdmmc1-b4@0 { + + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ @@ -407,18 +597,61 @@ }; }; - sdmmc1_dir_pins_a: sdmmc1-dir@0 { + sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { + pins1 { + pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ + slew-rate = <3>; + drive-push-pull; + bias-disable; + }; + pins2{ + pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ + slew-rate = <3>; + drive-open-drain; + bias-disable; + }; + }; + + sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { + pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ + <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ + <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ + <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ + <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ + <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ + }; + }; + + sdmmc1_dir_pins_a: sdmmc1-dir-0 { + pins1 { pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ - <STM32_PINMUX('B', 9, AF11)>, /* SDMMC1_CDIR */ - <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ slew-rate = <3>; drive-push-pull; bias-pull-up; }; + pins2{ + pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ + bias-pull-up; + }; }; - sdmmc2_b4_pins_a: sdmmc2-b4@0 { + + sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ + <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ + <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ + }; + }; + + sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ @@ -432,7 +665,7 @@ }; }; - sdmmc2_d47_pins_a: sdmmc2-d47@0 { + sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ @@ -444,6 +677,19 @@ }; }; + spdifrx_pins_a: spdifrx-0 { + pins { + pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ + bias-disable; + }; + }; + + spdifrx_sleep_pins_a: spdifrx-1 { + pins { + pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ + }; + }; + spi2_pins_a: spi2-0 { pins1 { pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */ @@ -522,6 +768,7 @@ pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + hwlocks = <&hwspinlock 0>; gpioz: gpio@54004000 { gpio-controller; @@ -546,6 +793,13 @@ }; }; + i2c4_pins_sleep_a: i2c4-1 { + pins { + pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ + <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ + }; + }; + spi1_pins_a: spi1-0 { pins1 { pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ diff --git a/arch/arm/dts/stm32mp157-u-boot.dtsi b/arch/arm/dts/stm32mp157-u-boot.dtsi index 09560e2d915..8102ce20d0d 100644 --- a/arch/arm/dts/stm32mp157-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157-u-boot.dtsi @@ -21,126 +21,119 @@ pinctrl1 = &pinctrl_z; }; - config { + clocks { u-boot,dm-pre-reloc; }; - clocks { + reboot { u-boot,dm-pre-reloc; }; soc { u-boot,dm-pre-reloc; - - stgen: stgen@5C008000 { - compatible = "st,stm32-stgen"; - reg = <0x5C008000 0x1000>; - status = "okay"; - u-boot,dm-pre-reloc; - }; }; }; &bsec { - u-boot,dm-pre-reloc; -}; - -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_hse { - u-boot,dm-pre-reloc; -}; - -&clk_lse { - u-boot,dm-pre-reloc; -}; - -&clk_lsi { - u-boot,dm-pre-reloc; + u-boot,dm-pre-proper; }; &clk_csi { u-boot,dm-pre-reloc; }; -&rcc { +&clk_hsi { u-boot,dm-pre-reloc; }; -&rcc_reboot { +&clk_hse { u-boot,dm-pre-reloc; }; -&pinctrl { +&clk_lsi { u-boot,dm-pre-reloc; }; -&pinctrl_z { +&clk_lse { u-boot,dm-pre-reloc; }; &gpioa { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiob { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioc { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiod { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioe { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiof { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiog { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioh { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioi { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioj { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpiok { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; &gpioz { - compatible = "st,stm32-gpio"; u-boot,dm-pre-reloc; }; -&iwdg2 { +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pinctrl_z { + u-boot,dm-pre-reloc; +}; + +&pwr { u-boot,dm-pre-reloc; }; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&sdmmc1 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc2 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&sdmmc3 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +}; + +&usbotg_hs { + compatible = "st,stm32mp1-hsotg", "snps,dwc2"; +}; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 0f32a38dc94..36c852d28b3 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -194,7 +194,3 @@ u-boot,force-b-session-valid; hnp-srp-disable; }; - -&v3v3 { - regulator-always-on; -}; diff --git a/arch/arm/dts/stm32mp157a-dk1.dts b/arch/arm/dts/stm32mp157a-dk1.dts index e36773dde91..adb24649209 100644 --- a/arch/arm/dts/stm32mp157a-dk1.dts +++ b/arch/arm/dts/stm32mp157a-dk1.dts @@ -39,12 +39,19 @@ }; }; +&cec { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cec_pins_b>; + pinctrl-1 = <&cec_pins_sleep_b>; + status = "okay"; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_a>; pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>; pinctrl-names = "default", "sleep"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; @@ -58,12 +65,14 @@ }; }; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; @@ -88,17 +97,13 @@ pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; - st,main-control-register = <0x04>; - st,vin-control-register = <0xc0>; - st,usb-control-register = <0x20>; - regulators { compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; @@ -107,7 +112,7 @@ vddcore: buck1 { regulator-name = "vddcore"; - regulator-min-microvolt = <1200000>; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; regulator-initial-mode = <0>; @@ -187,7 +192,6 @@ regulator-max-microvolt = <1200000>; regulator-always-on; interrupts = <IT_CURLIM_LDO6 0>; - }; vref_ddr: vref_ddr { @@ -204,7 +208,6 @@ vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - regulator-active-discharge; }; vbus_sw: pwr_sw2 { @@ -216,8 +219,9 @@ onkey { compatible = "st,stpmic1-onkey"; - interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; status = "okay"; }; @@ -228,6 +232,10 @@ }; }; +&ipcc { + status = "okay"; +}; + &iwdg2 { timeout-sec = <32>; status = "okay"; @@ -246,8 +254,10 @@ }; &sdmmc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; broken-cd; st,neg-edge; bus-width = <4>; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 9a81d2d4728..020ea0f0e2f 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -42,6 +42,7 @@ compatible = "orisetech,otm8009a"; reg = <0>; reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply = <&v3v3>; status = "okay"; port { diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 55f99037b26..200601edff6 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -156,6 +156,10 @@ }; }; +&sdmmc1 { + u-boot,dm-spl; +}; + &sdmmc1_b4_pins_a { u-boot,dm-spl; pins { @@ -165,12 +169,15 @@ &sdmmc1_dir_pins_a { u-boot,dm-spl; - pins { + pins1 { + u-boot,dm-spl; + }; + pins2 { u-boot,dm-spl; }; }; -&sdmmc1 { +&sdmmc2 { u-boot,dm-spl; }; @@ -188,10 +195,6 @@ }; }; -&sdmmc2 { - u-boot,dm-spl; -}; - &uart4 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index b10208f6987..11981d6dd4f 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -19,6 +19,7 @@ }; memory@c0000000 { + device_type = "memory"; reg = <0xC0000000 0x40000000>; }; @@ -40,7 +41,7 @@ }; }; -&hwspinlock { +&dts { status = "okay"; }; @@ -50,23 +51,20 @@ i2c-scl-rising-time-ns = <185>; i2c-scl-falling-time-ns = <20>; status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; - pmic: stpmic1@33 { + pmic: stpmic@33 { compatible = "st,stpmic1"; reg = <0x33>; - interrupts = <0 2>; - interrupt-parent = <&gpioa>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; status = "okay"; - st,main_control_register = <0x04>; - st,vin_control_register = <0xc0>; - st,usb_control_register = <0x30>; - regulators { compatible = "st,stpmic1-regulators"; - ldo1-supply = <&v3v3>; ldo2-supply = <&v3v3>; ldo3-supply = <&vdd_ddr>; @@ -80,20 +78,8 @@ regulator-min-microvolt = <800000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-on-in-suspend; - regulator-suspend-microvolt = <1200000>; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vdd_ddr: buck2 { @@ -101,22 +87,8 @@ regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; regulator-always-on; - regulator-initial-mode = <2>; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-suspend-microvolt = <1350000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-suspend-microvolt = <1350000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vdd: buck3 { @@ -124,46 +96,18 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - st,mask_reset; - regulator-initial-mode = <8>; + st,mask-reset; + regulator-initial-mode = <0>; regulator-over-current-protection; - - regulator-state-standby { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; - regulator-state-disk { - regulator-suspend-microvolt = <3300000>; - regulator-on-in-suspend; - regulator-mode = <8>; - }; }; v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-boot-on; + regulator-always-on; regulator-over-current-protection; - regulator-initial-mode = <8>; - - regulator-state-standby { - regulator-suspend-microvolt = <3300000>; - regulator-unchanged-in-suspend; - regulator-mode = <8>; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; + regulator-initial-mode = <0>; }; vdda: ldo1 { @@ -171,18 +115,6 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO1 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <2900000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; v2v8: ldo2 { @@ -190,36 +122,14 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; interrupts = <IT_CURLIM_LDO2 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <2800000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; - regulator-min-microvolt = <0000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; regulator-always-on; regulator-over-current-protection; - - regulator-state-standby { - regulator-off-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vdd_usb: ldo4 { @@ -227,17 +137,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; interrupts = <IT_CURLIM_LDO4 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vdd_sd: ldo5 { @@ -245,19 +144,7 @@ regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; interrupts = <IT_CURLIM_LDO5 0>; - interrupt-parent = <&pmic>; regulator-boot-on; - - regulator-state-standby { - regulator-suspend-microvolt = <2900000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; v1v8: ldo6 { @@ -265,66 +152,53 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; interrupts = <IT_CURLIM_LDO6 0>; - interrupt-parent = <&pmic>; - - regulator-state-standby { - regulator-suspend-microvolt = <1800000>; - regulator-unchanged-in-suspend; - }; - regulator-state-mem { - regulator-off-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; regulator-over-current-protection; - - regulator-state-standby { - regulator-on-in-suspend; - }; - regulator-state-mem { - regulator-on-in-suspend; - }; - regulator-state-disk { - regulator-off-in-suspend; - }; }; bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>; - interrupt-parent = <&pmic>; }; vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; - interrupt-parent = <&pmic>; - regulator-active-discharge; }; vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; - interrupt-parent = <&pmic>; regulator-active-discharge; }; }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 0>; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; }; }; -&iwdg2 { - timeout-sec = <32>; +&ipcc { status = "okay"; }; -&pinctrl { - hwlocks = <&hwspinlock 0>; +&iwdg2 { + timeout-sec = <32>; + status = "okay"; }; &pwr { @@ -340,7 +214,10 @@ }; &sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_dir_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a &sdmmc1_dir_sleep_pins_a>; broken-cd; st,sig-dir; st,neg-edge; @@ -348,11 +225,6 @@ bus-width = <4>; vmmc-supply = <&vdd_sd>; vqmmc-supply = <&sd_switch>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-ddr50; - sd-uhs-sdr104; status = "okay"; }; @@ -371,6 +243,9 @@ &timers6 { status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; timer@5 { status = "okay"; }; @@ -382,6 +257,10 @@ status = "okay"; }; +&usbotg_hs { + vbus-supply = <&vbus_otg>; +}; + &usbphyc_port0 { phy-supply = <&vdd_usb>; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index 994092a195b..b656eb120db 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -56,6 +56,3 @@ }; }; -&v3v3 { - regulator-always-on; -}; diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 663e52aa314..ca2a333d432 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "stm32mp157c-ed1.dts" +#include <dt-bindings/gpio/gpio.h> / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -157,8 +158,9 @@ }; &m_can1 { - pinctrl-names = "default"; + pinctrl-names = "default", "sleep"; pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; status = "okay"; }; @@ -194,6 +196,9 @@ }; &timers2 { + /* spare dmas for other usage (un-delete to enable pwm capture) */ + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm2_pins_a>; @@ -206,6 +211,8 @@ }; &timers8 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm8_pins_a>; @@ -218,6 +225,8 @@ }; &timers12 { + /delete-property/dmas; + /delete-property/dma-names; status = "disabled"; pwm { pinctrl-0 = <&pwm12_pins_a>; @@ -232,7 +241,6 @@ &usbh_ehci { phys = <&usbphyc_port0>; phy-names = "usb"; - vbus-supply = <&vbus_sw>; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi index 73215855ccd..d15fba0c802 100644 --- a/arch/arm/dts/stm32mp157c.dtsi +++ b/arch/arm/dts/stm32mp157c.dtsi @@ -35,28 +35,6 @@ cpu_on = <0x84000003>; }; - aliases { - gpio0 = &gpioa; - gpio1 = &gpiob; - gpio2 = &gpioc; - gpio3 = &gpiod; - gpio4 = &gpioe; - gpio5 = &gpiof; - gpio6 = &gpiog; - gpio7 = &gpioh; - gpio8 = &gpioi; - gpio9 = &gpioj; - gpio10 = &gpiok; - serial0 = &usart1; - serial1 = &usart2; - serial2 = &usart3; - serial3 = &uart4; - serial4 = &uart5; - serial5 = &usart6; - serial6 = &uart7; - serial7 = &uart8; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -106,6 +84,38 @@ }; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x404>; + mask = <0x1>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -120,6 +130,12 @@ reg = <0x40000000 0x400>; clocks = <&rcc TIM2_K>; clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; status = "disabled"; pwm { @@ -141,6 +157,13 @@ reg = <0x40001000 0x400>; clocks = <&rcc TIM3_K>; clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -162,6 +185,11 @@ reg = <0x40002000 0x400>; clocks = <&rcc TIM4_K>; clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; status = "disabled"; pwm { @@ -183,6 +211,13 @@ reg = <0x40003000 0x400>; clocks = <&rcc TIM5_K>; clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; status = "disabled"; pwm { @@ -204,6 +239,8 @@ reg = <0x40004000 0x400>; clocks = <&rcc TIM6_K>; clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@5 { @@ -220,6 +257,8 @@ reg = <0x40005000 0x400>; clocks = <&rcc TIM7_K>; clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; status = "disabled"; timer@6 { @@ -347,6 +386,19 @@ status = "disabled"; }; + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; + reg = <0x4000d000 0x400>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + usart2: serial@4000e000 { compatible = "st,stm32h7-uart"; reg = <0x4000e000 0x400>; @@ -487,6 +539,15 @@ reg = <0x44000000 0x400>; clocks = <&rcc TIM1_K>; clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -508,6 +569,15 @@ reg = <0x44001000 0x400>; clocks = <&rcc TIM8_K>; clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; status = "disabled"; pwm { @@ -565,6 +635,11 @@ reg = <0x44006000 0x400>; clocks = <&rcc TIM15_K>; clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; status = "disabled"; pwm { @@ -586,6 +661,9 @@ reg = <0x44007000 0x400>; clocks = <&rcc TIM16_K>; clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { @@ -606,6 +684,9 @@ reg = <0x44008000 0x400>; clocks = <&rcc TIM17_K>; clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; status = "disabled"; pwm { @@ -706,14 +787,14 @@ m_can1: can@4400e000 { compatible = "bosch,m_can"; - reg = <0x4400e000 0x400>, <0x44011000 0x2800>; + reg = <0x4400e000 0x400>, <0x44011000 0x1400>; reg-names = "m_can", "message_ram"; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; - bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; @@ -811,13 +892,14 @@ }; sdmmc3: sdmmc@48004000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x48004000 0x400>, <0x48005000 0x400>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x48004000 0x400>; + reg-names = "sdmmc"; interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC3_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC3_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -825,7 +907,7 @@ }; usbotg_hs: usb-otg@49000000 { - compatible = "st,stm32mp1-hsotg", "snps,dwc2"; + compatible = "snps,dwc2"; reg = <0x49000000 0x10000>; clocks = <&rcc USBO_K>; clock-names = "otg"; @@ -846,6 +928,20 @@ reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hwspinlock"; + }; + + ipcc: mailbox@4c001000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <&exti 61 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc IPCC>; + wakeup-source; status = "disabled"; }; @@ -856,13 +952,6 @@ #reset-cells = <1>; }; - rcc_reboot: rcc-reboot@50000000 { - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - pwr: pwr@50001000 { compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; reg = <0x50001000 0x400>; @@ -872,7 +961,7 @@ clocks = <&rcc PLL2_R>; clock-names = "phyclk"; - pwr-regulators@c { + pwr-regulators { compatible = "st,stm32mp1,pwr-reg"; st,tzcr = <&rcc 0x0 0x1>; @@ -906,6 +995,7 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; + clocks = <&rcc SYSCFG>; }; lptimer2: timer@50021000 { @@ -994,6 +1084,16 @@ status = "disabled"; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc TMPSENS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + cryp1: cryp@54001000 { compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; @@ -1059,26 +1159,27 @@ }; sdmmc1: sdmmc@58005000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58005000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC1_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; - status = "disabled"; }; sdmmc2: sdmmc@58007000 { - compatible = "st,stm32-sdmmc2"; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - reg-names = "sdmmc", "delay"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x10153180>; + reg = <0x58007000 0x1000>; interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; - st,idma = <1>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; @@ -1102,25 +1203,21 @@ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; reg = <0x5800a000 0x2000>; reg-names = "stmmaceth"; - interrupts-extended = - <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, - <&exti 70 1>; - interrupt-names = "macirq", - "eth_wake_irq", - "stm32_pwr_wakeup"; + interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx", - "ethstp"; + "ethstp", + "syscfg-clk"; clocks = <&rcc ETHMAC>, <&rcc ETHTX>, <&rcc ETHRX>, - <&rcc ETHSTP>; + <&rcc ETHSTP>, + <&rcc SYSCFG>; st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>; - snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; status = "disabled"; @@ -1245,6 +1342,12 @@ reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; + ts_cal1: calib@5c { + reg = <0x5c 0x2>; + }; + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; }; i2c6: i2c@5c009000 { diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index d9ad6b423b0..9dc3c4d1c5f 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -38,6 +38,7 @@ config TARGET_STM32MP1 select CPU_V7A select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED select CPU_V7_HAS_VIRT + select OF_BOARD_SETUP select PINCTRL_STM32 select STM32_RCC select STM32_RESET @@ -62,7 +63,17 @@ config STM32MP1_TRUSTED Say Y here to enable boot with TF-A Trusted boot chain is : BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32 - TF-A monitor provides proprietary smc to manage secure devices + TF-A monitor provides proprietary SMC to manage secure devices + +config STM32MP1_OPTEE + bool "Support trusted boot with TF-A and OP-TEE" + depends on STM32MP1_TRUSTED + default n + help + Say Y here to enable boot with TF-A and OP-TEE + Trusted boot chain is : + BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32 + OP-TEE monitor provides ST SMC to access to secure resources config SYS_TEXT_BASE prompt "U-Boot base address" @@ -83,6 +94,21 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 Partition on the second MMC to load U-Boot from when the MMC is being used in raw mode +config STM32_ETZPC + bool "STM32 Extended TrustZone Protection" + depends on TARGET_STM32MP1 + default y + help + Say y to enable STM32 Extended TrustZone Protection + +config CMD_STM32KEY + bool "command stm32key to fuse public key hash" + default y + depends on CMD_FUSE + help + fuse public key hash in corresponding fuse used to authenticate + binary. + config BOOTSTAGE_STASH_ADDR default 0xC3000000 diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index 1493914a110..77450604b0f 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -11,9 +11,11 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += bsec.o +obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o ifndef CONFIG_STM32MP1_TRUSTED obj-$(CONFIG_SYSRESET) += cmd_poweroff.o endif endif obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_$(SPL_)DM_REGULATOR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 01666496854..80183668856 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -358,12 +358,13 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, bool shadow = true; int nb_otp = size / sizeof(u32); int otp; + unsigned int offs = offset; - if (offset >= STM32_BSEC_OTP_OFFSET) { - offset -= STM32_BSEC_OTP_OFFSET; + if (offs >= STM32_BSEC_OTP_OFFSET) { + offs -= STM32_BSEC_OTP_OFFSET; shadow = false; } - otp = offset / sizeof(u32); + otp = offs / sizeof(u32); if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { dev_err(dev, "wrong value for otp, max value : %i\n", @@ -393,12 +394,13 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, bool shadow = true; int nb_otp = size / sizeof(u32); int otp; + unsigned int offs = offset; - if (offset >= STM32_BSEC_OTP_OFFSET) { - offset -= STM32_BSEC_OTP_OFFSET; + if (offs >= STM32_BSEC_OTP_OFFSET) { + offs -= STM32_BSEC_OTP_OFFSET; shadow = false; } - otp = offset / sizeof(u32); + otp = offs / sizeof(u32); if (otp < 0 || (otp + nb_otp - 1) > BSEC_OTP_MAX_VALUE) { dev_err(dev, "wrong value for otp, max value : %d\n", diff --git a/arch/arm/mach-stm32mp/cmd_stm32key.c b/arch/arm/mach-stm32mp/cmd_stm32key.c new file mode 100644 index 00000000000..f1f26e7c943 --- /dev/null +++ b/arch/arm/mach-stm32mp/cmd_stm32key.c @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <command.h> +#include <console.h> +#include <misc.h> +#include <dm/device.h> +#include <dm/uclass.h> + +#define STM32_OTP_HASH_KEY_START 24 +#define STM32_OTP_HASH_KEY_SIZE 8 + +static void read_hash_value(u32 addr) +{ + int i; + + for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { + printf("OTP value %i: %x\n", STM32_OTP_HASH_KEY_START + i, + __be32_to_cpu(*(u32 *)addr)); + addr += 4; + } +} + +static void fuse_hash_value(u32 addr, bool print) +{ + struct udevice *dev; + u32 word, val; + int i, ret; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + if (ret) { + pr_err("Can't find stm32mp_bsec driver\n"); + return; + } + + for (i = 0; i < STM32_OTP_HASH_KEY_SIZE; i++) { + if (print) + printf("Fuse OTP %i : %x\n", + STM32_OTP_HASH_KEY_START + i, + __be32_to_cpu(*(u32 *)addr)); + + word = STM32_OTP_HASH_KEY_START + i; + val = __be32_to_cpu(*(u32 *)addr); + misc_write(dev, STM32_BSEC_OTP(word), &val, 4); + + addr += 4; + } +} + +static int confirm_prog(void) +{ + puts("Warning: Programming fuses is an irreversible operation!\n" + " This may brick your system.\n" + " Use this command only if you are sure of what you are doing!\n" + "\nReally perform this fuse programming? <y/N>\n"); + + if (confirm_yesno()) + return 1; + + puts("Fuse programming aborted\n"); + return 0; +} + +static int do_stm32key(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr; + const char *op = argc >= 2 ? argv[1] : NULL; + int confirmed = argc > 3 && !strcmp(argv[2], "-y"); + + argc -= 2 + confirmed; + argv += 2 + confirmed; + + if (argc < 1) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[0], NULL, 16); + if (!addr) + return CMD_RET_USAGE; + + if (!strcmp(op, "read")) + read_hash_value(addr); + + if (!strcmp(op, "fuse")) { + if (!confirmed && !confirm_prog()) + return CMD_RET_FAILURE; + fuse_hash_value(addr, !confirmed); + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(stm32key, 4, 1, do_stm32key, + "Fuse ST Hash key", + "read <addr>: Read the hash store at addr in memory\n" + "stm32key fuse [-y] <addr> : Fuse hash store at addr in otp\n"); diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c index e1a0a136809..10190f40d4e 100644 --- a/arch/arm/mach-stm32mp/cpu.c +++ b/arch/arm/mach-stm32mp/cpu.c @@ -78,11 +78,6 @@ #define PKG_SHIFT 27 #define PKG_MASK GENMASK(2, 0) -#define PKG_AA_LBGA448 4 -#define PKG_AB_LBGA354 3 -#define PKG_AC_TFBGA361 2 -#define PKG_AD_TFBGA257 1 - #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) #ifndef CONFIG_STM32MP1_TRUSTED static void security_init(void) @@ -277,7 +272,7 @@ u32 get_cpu_type(void) } /* Get Package options from OTP */ -static u32 get_cpu_package(void) +u32 get_cpu_package(void) { return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); } @@ -366,7 +361,7 @@ static void setup_boot_mode(void) u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); u32 boot_mode = (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; - int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); struct udevice *dev; int alias; diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c new file mode 100644 index 00000000000..82c430b7c77 --- /dev/null +++ b/arch/arm/mach-stm32mp/fdt.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <fdt_support.h> +#include <asm/arch/sys_proto.h> +#include <dt-bindings/pinctrl/stm32-pinfunc.h> +#include <linux/io.h> + +#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) +#define ETZPC_DECPROT_NB 6 + +#define DECPROT_MASK 0x03 +#define NB_PROT_PER_REG 0x10 +#define DECPROT_NB_BITS 2 + +#define DECPROT_SECURED 0x00 +#define DECPROT_WRITE_SECURE 0x01 +#define DECPROT_MCU_ISOLATION 0x02 +#define DECPROT_NON_SECURED 0x03 + +#define ETZPC_RESERVED 0xffffffff + +static const u32 stm32mp1_ip_addr[] = { + 0x5c008000, /* 00 stgenc */ + 0x54000000, /* 01 bkpsram */ + 0x5c003000, /* 02 iwdg1 */ + 0x5c000000, /* 03 usart1 */ + 0x5c001000, /* 04 spi6 */ + 0x5c002000, /* 05 i2c4 */ + ETZPC_RESERVED, /* 06 reserved */ + 0x54003000, /* 07 rng1 */ + 0x54002000, /* 08 hash1 */ + 0x54001000, /* 09 cryp1 */ + 0x5a003000, /* 0A ddrctrl */ + 0x5a004000, /* 0B ddrphyc */ + 0x5c009000, /* 0C i2c6 */ + ETZPC_RESERVED, /* 0D reserved */ + ETZPC_RESERVED, /* 0E reserved */ + ETZPC_RESERVED, /* 0F reserved */ + 0x40000000, /* 10 tim2 */ + 0x40001000, /* 11 tim3 */ + 0x40002000, /* 12 tim4 */ + 0x40003000, /* 13 tim5 */ + 0x40004000, /* 14 tim6 */ + 0x40005000, /* 15 tim7 */ + 0x40006000, /* 16 tim12 */ + 0x40007000, /* 17 tim13 */ + 0x40008000, /* 18 tim14 */ + 0x40009000, /* 19 lptim1 */ + 0x4000a000, /* 1A wwdg1 */ + 0x4000b000, /* 1B spi2 */ + 0x4000c000, /* 1C spi3 */ + 0x4000d000, /* 1D spdifrx */ + 0x4000e000, /* 1E usart2 */ + 0x4000f000, /* 1F usart3 */ + 0x40010000, /* 20 uart4 */ + 0x40011000, /* 21 uart5 */ + 0x40012000, /* 22 i2c1 */ + 0x40013000, /* 23 i2c2 */ + 0x40014000, /* 24 i2c3 */ + 0x40015000, /* 25 i2c5 */ + 0x40016000, /* 26 cec */ + 0x40017000, /* 27 dac */ + 0x40018000, /* 28 uart7 */ + 0x40019000, /* 29 uart8 */ + ETZPC_RESERVED, /* 2A reserved */ + ETZPC_RESERVED, /* 2B reserved */ + 0x4001c000, /* 2C mdios */ + ETZPC_RESERVED, /* 2D reserved */ + ETZPC_RESERVED, /* 2E reserved */ + ETZPC_RESERVED, /* 2F reserved */ + 0x44000000, /* 30 tim1 */ + 0x44001000, /* 31 tim8 */ + ETZPC_RESERVED, /* 32 reserved */ + 0x44003000, /* 33 usart6 */ + 0x44004000, /* 34 spi1 */ + 0x44005000, /* 35 spi4 */ + 0x44006000, /* 36 tim15 */ + 0x44007000, /* 37 tim16 */ + 0x44008000, /* 38 tim17 */ + 0x44009000, /* 39 spi5 */ + 0x4400a000, /* 3A sai1 */ + 0x4400b000, /* 3B sai2 */ + 0x4400c000, /* 3C sai3 */ + 0x4400d000, /* 3D dfsdm */ + 0x4400e000, /* 3E tt_fdcan */ + ETZPC_RESERVED, /* 3F reserved */ + 0x50021000, /* 40 lptim2 */ + 0x50022000, /* 41 lptim3 */ + 0x50023000, /* 42 lptim4 */ + 0x50024000, /* 43 lptim5 */ + 0x50027000, /* 44 sai4 */ + 0x50025000, /* 45 vrefbuf */ + 0x4c006000, /* 46 dcmi */ + 0x4c004000, /* 47 crc2 */ + 0x48003000, /* 48 adc */ + 0x4c002000, /* 49 hash2 */ + 0x4c003000, /* 4A rng2 */ + 0x4c005000, /* 4B cryp2 */ + ETZPC_RESERVED, /* 4C reserved */ + ETZPC_RESERVED, /* 4D reserved */ + ETZPC_RESERVED, /* 4E reserved */ + ETZPC_RESERVED, /* 4F reserved */ + ETZPC_RESERVED, /* 50 sram1 */ + ETZPC_RESERVED, /* 51 sram2 */ + ETZPC_RESERVED, /* 52 sram3 */ + ETZPC_RESERVED, /* 53 sram4 */ + ETZPC_RESERVED, /* 54 retram */ + 0x49000000, /* 55 otg */ + 0x48004000, /* 56 sdmmc3 */ + 0x48005000, /* 57 dlybsd3 */ + 0x48000000, /* 58 dma1 */ + 0x48001000, /* 59 dma2 */ + 0x48002000, /* 5A dmamux */ + 0x58002000, /* 5B fmc */ + 0x58003000, /* 5C qspi */ + 0x58004000, /* 5D dlybq */ + 0x5800a000, /* 5E eth */ + ETZPC_RESERVED, /* 5F reserved */ +}; + +/* fdt helper */ +static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) +{ + int node; + + for (node = fdt_first_subnode(fdt, offset); + node >= 0; + node = fdt_next_subnode(fdt, node)) { + if (addr == (u32)fdt_getprop(fdt, node, "reg", 0)) { + if (fdtdec_get_is_enabled(fdt, node)) { + fdt_status_disabled(fdt, node); + + return true; + } + return false; + } + } + + return false; +} + +static int stm32_fdt_fixup_etzpc(void *fdt) +{ + const u32 *array; + int array_size, i; + int soc_node, offset, shift; + u32 addr, status, decprot[ETZPC_DECPROT_NB]; + + array = stm32mp1_ip_addr; + array_size = ARRAY_SIZE(stm32mp1_ip_addr); + + for (i = 0; i < ETZPC_DECPROT_NB; i++) + decprot[i] = readl(ETZPC_DECPROT(i)); + + soc_node = fdt_path_offset(fdt, "/soc"); + if (soc_node < 0) + return soc_node; + + for (i = 0; i < array_size; i++) { + offset = i / NB_PROT_PER_REG; + shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; + status = (decprot[offset] >> shift) & DECPROT_MASK; + addr = array[i]; + + debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); + + if (addr == ETZPC_RESERVED || + status == DECPROT_NON_SECURED) + continue; + + if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) + printf("ETZPC: 0x%08x node disabled, decprot %d=%d\n", + addr, i, status); + } + + return 0; +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, bd_t *bd) +{ + int ret = 0; + u32 pkg; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob); + if (ret) + return ret; + } + + switch (get_cpu_package()) { + case PKG_AA_LBGA448: + pkg = STM32MP_PKG_AA; + break; + case PKG_AB_LBGA354: + pkg = STM32MP_PKG_AB; + break; + case PKG_AC_TFBGA361: + pkg = STM32MP_PKG_AC; + break; + case PKG_AD_TFBGA257: + pkg = STM32MP_PKG_AD; + break; + default: + pkg = 0; + break; + } + if (pkg) { + do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl", + "st,package", pkg, false); + do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", + "st,package", pkg, false); + } + + return ret; +} diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 67953520448..1d4b5482acc 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -15,6 +15,7 @@ #define STM32_DBGMCU_BASE 0x50081000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 +#define STM32_STGEN_BASE 0x5C008000 #define STM32_TAMP_BASE 0x5C00A000 #define STM32_USART1_BASE 0x5C000000 @@ -36,9 +37,7 @@ /* enumerated used to identify the SYSCON driver instance */ enum { STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_ETZPC, STM32MP_SYSCON_PWR, - STM32MP_SYSCON_STGEN, STM32MP_SYSCON_SYSCFG, }; diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 71a3ba794d1..99eefabf6ec 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -19,5 +19,14 @@ u32 get_cpu_type(void); /* return CPU_REV constants */ u32 get_cpu_rev(void); + +/* Get Package options from OTP */ +u32 get_cpu_package(void); + +#define PKG_AA_LBGA448 4 +#define PKG_AB_LBGA354 3 +#define PKG_AC_TFBGA361 2 +#define PKG_AD_TFBGA257 1 + /* return boot mode */ u32 get_bootmode(void); diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index 242f8340abb..6070837bf01 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -9,9 +9,7 @@ #include <asm/arch/stm32.h> static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp1-etzpc", .data = STM32MP_SYSCON_ETZPC }, { .compatible = "st,stm32mp1-pwr", .data = STM32MP_SYSCON_PWR }, - { .compatible = "st,stm32-stgen", .data = STM32MP_SYSCON_STGEN }, { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, { } diff --git a/board/st/stm32f429-discovery/led.c b/board/st/stm32f429-discovery/led.c index 8320ad4fac2..ae6df78f56f 100644 --- a/board/st/stm32f429-discovery/led.c +++ b/board/st/stm32f429-discovery/led.c @@ -9,7 +9,9 @@ void coloured_LED_init(void) { + gpio_request(CONFIG_RED_LED, "red led"); gpio_direction_output(CONFIG_RED_LED, 0); + gpio_request(CONFIG_GREEN_LED, "green led"); gpio_direction_output(CONFIG_GREEN_LED, 0); } diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig index 5ab94151a9a..87216c09638 100644 --- a/board/st/stm32mp1/Kconfig +++ b/board/st/stm32mp1/Kconfig @@ -9,4 +9,17 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "stm32mp1" +config ENV_SECT_SIZE + default 0x40000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x280000 if ENV_IS_IN_SPI_FLASH + +config CMD_STBOARD + bool "stboard - command for OTP board information" + default y + help + This compile the stboard command to + read and write the board in the OTP. + endif diff --git a/board/st/stm32mp1/MAINTAINERS b/board/st/stm32mp1/MAINTAINERS index 0a2eddbe03d..3bf4c21b602 100644 --- a/board/st/stm32mp1/MAINTAINERS +++ b/board/st/stm32mp1/MAINTAINERS @@ -5,5 +5,6 @@ S: Maintained F: arch/arm/dts/stm32mp157* F: board/st/stm32mp1 F: configs/stm32mp15_basic_defconfig +F: configs/stm32mp15_optee_defconfig F: configs/stm32mp15_trusted_defconfig F: include/configs/stm32mp1.h diff --git a/board/st/stm32mp1/Makefile b/board/st/stm32mp1/Makefile index 8188075b1a3..3c6c035b118 100644 --- a/board/st/stm32mp1/Makefile +++ b/board/st/stm32mp1/Makefile @@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else obj-y += stm32mp1.o +obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o endif obj-y += board.o diff --git a/board/st/stm32mp1/README b/board/st/stm32mp1/README index b0c83250612..428357cfa09 100644 --- a/board/st/stm32mp1/README +++ b/board/st/stm32mp1/README @@ -25,6 +25,10 @@ It features: Everything is supported in Linux but U-Boot is limited to: 1. UART 2. SDCard/MMC controller (SDMMC) +3. NAND controller (FMC) +4. NOR controller (QSPI) +5. USB controller (OTG DWC2) +6. Ethernet controller And the necessary drivers 1. I2C @@ -47,20 +51,28 @@ BootRom => FSBL in SYSRAM => SSBL in DDR => OS (Linux Kernel) with FSBL = First Stage Bootloader SSBL = Second Stage Bootloader -2 boot configurations are supported: +3 boot configurations are supported: 1) The "Trusted" boot chain (defconfig_file : stm32mp15_trusted_defconfig) BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot TF-A performs a full initialization of Secure peripherals and installs a secure monitor. U-Boot is running in normal world and uses TF-A monitor - to access to secure resources + to access to secure resources. -2) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) +2) The "Trusted" boot chain with OP-TEE + (defconfig_file : stm32mp15_optee_defconfig) + BootRom => FSBL = Trusted Firmware-A (TF-A) => SSBL = U-Boot + TF-A performs a full initialization of Secure peripherals and installs OP-TEE + from specific partitions (teeh, teed, teex). + U-Boot is running in normal world and uses OP-TEE monitor to access + to secure resources. + +3) The "Basic" boot chain (defconfig_file : stm32mp15_basic_defconfig) BootRom => FSBL = U-Boot SPL => SSBL = U-Boot SPL has limited security initialisation U-Boot is running in secure mode and provide a secure monitor to the kernel - with only PSCI support (Power State Coordination Interface defined by ARM) + with only PSCI support (Power State Coordination Interface defined by ARM). All the STM32MP1 boards supported by U-Boot use the same generic board stm32mp1 which support all the bootable devices. @@ -109,13 +121,18 @@ the supported device trees for stm32mp157 are: for example: use one output directory for each configuration # export KBUILD_OUTPUT=stm32mp15_trusted + # export KBUILD_OUTPUT=stm32mp15_optee # export KBUILD_OUTPUT=stm32mp15_basic + you can build outside of code directory: + # export KBUILD_OUTPUT=../build/stm32mp15_trusted + 4. Configure U-Boot: # make <defconfig_file> - For trusted boot mode : "stm32mp15_trusted_defconfig" + - For trusted with OP-TEE boot mode : "stm32mp15_optee_defconfig" - For basic boot mode: "stm32mp15_basic_defconfig" 5. Configure the device-tree and build the U-Boot image: @@ -129,22 +146,27 @@ the supported device trees for stm32mp157 are: # make stm32mp15_trusted_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - b) basic boot on ev1 + b) trusted with OP-TEE boot on dk2 + # export KBUILD_OUTPUT=stm32mp15_optee + # make stm32mp15_optee_defconfig + # make DEVICE_TREE=stm32mp157c-dk2 all + + c) basic boot on ev1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ev1 all - c) basic boot on ed1 + d) basic boot on ed1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157c-ed1 all - d) basic boot on dk2 + e) basic boot on dk1 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig - # make DEVICE_TREE=stm32mp157c-dk2 all + # make DEVICE_TREE=stm32mp157a-dk1 all - d) basic boot on avenger96 + f) basic boot on avenger96 # export KBUILD_OUTPUT=stm32mp15_basic # make stm32mp15_basic_defconfig # make DEVICE_TREE=stm32mp157a-avenger96 all @@ -157,7 +179,7 @@ the supported device trees for stm32mp157 are: So in the output directory (selected by KBUILD_OUTPUT), you can found the needed files: - a) For Trusted boot + a) For Trusted boot (with or without OP-TEE) + FSBL = tf-a.stm32 (provided by TF-A compilation) + SSBL = u-boot.stm32 @@ -170,6 +192,8 @@ the supported device trees for stm32mp157 are: You can select the boot mode, on the board ed1 with the switch SW1 +- on the daugther board ed1 with the switch SW1 : BOOT0, BOOT1, BOOT2 + ----------------------------------- Boot Mode BOOT2 BOOT1 BOOT0 ----------------------------------- @@ -267,7 +291,7 @@ for example: with gpt table with 128 entries # dd if=tf-a.stm32 of=/dev/mmcblk0p2 # dd if=u-boot.stm32 of=/dev/mmcblk0p3 -To boot from SDCard, select BootPinMode = 1 1 1 and reset. +To boot from SDCard, select BootPinMode = 1 0 1 and reset. 8. Prepare eMMC =============== diff --git a/board/st/stm32mp1/cmd_stboard.c b/board/st/stm32mp1/cmd_stboard.c new file mode 100644 index 00000000000..f781c364cf6 --- /dev/null +++ b/board/st/stm32mp1/cmd_stboard.c @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <console.h> +#include <misc.h> +#include <dm/device.h> +#include <dm/uclass.h> + +static bool check_stboard(u16 board) +{ + unsigned int i; + const u16 st_board_id[] = { + 0x1272, + 0x1263, + 0x1264, + 0x1298, + 0x1341, + 0x1497, + }; + + for (i = 0; i < ARRAY_SIZE(st_board_id); i++) + if (board == st_board_id[i]) + return true; + + return false; +} + +static void display_stboard(u32 otp) +{ + printf("Board: MB%04x Var%d Rev.%c-%02d\n", + otp >> 16, + (otp >> 12) & 0xF, + ((otp >> 8) & 0xF) - 1 + 'A', + otp & 0xF); +} + +static int do_stboard(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + u32 otp; + u8 revision; + unsigned long board, variant, bom; + struct udevice *dev; + int confirmed = argc == 6 && !strcmp(argv[1], "-y"); + + argc -= 1 + confirmed; + argv += 1 + confirmed; + + if (argc != 0 && argc != 4) + return CMD_RET_USAGE; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_GET_DRIVER(stm32mp_bsec), + &dev); + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + + if (ret) { + puts("OTP read error"); + return CMD_RET_FAILURE; + } + + if (argc == 0) { + if (!otp) + puts("Board : OTP board FREE\n"); + else + display_stboard(otp); + return CMD_RET_SUCCESS; + } + + if (otp) { + display_stboard(otp); + printf("ERROR: OTP board not FREE\n"); + return CMD_RET_FAILURE; + } + + if (strict_strtoul(argv[0], 16, &board) < 0 || + board == 0 || board > 0xFFFF) { + printf("argument %d invalid: %s\n", 1, argv[0]); + return CMD_RET_USAGE; + } + + if (strict_strtoul(argv[1], 10, &variant) < 0 || + variant == 0 || variant > 15) { + printf("argument %d invalid: %s\n", 2, argv[1]); + return CMD_RET_USAGE; + } + + revision = argv[2][0] - 'A' + 1; + if (strlen(argv[2]) > 1 || revision == 0 || revision > 15) { + printf("argument %d invalid: %s\n", 3, argv[2]); + return CMD_RET_USAGE; + } + + if (strict_strtoul(argv[3], 10, &bom) < 0 || + bom == 0 || bom > 15) { + printf("argument %d invalid: %s\n", 4, argv[3]); + return CMD_RET_USAGE; + } + + otp = (board << 16) | (variant << 12) | (revision << 8) | bom; + display_stboard(otp); + printf("=> OTP[%d] = %08X\n", BSEC_OTP_BOARD, otp); + + if (!check_stboard((u16)board)) { + printf("Unknown board MB%04x\n", (u16)board); + return CMD_RET_FAILURE; + } + if (!confirmed) { + printf("Warning: Programming BOARD in OTP is irreversible!\n"); + printf("Really perform this OTP programming? <y/N>\n"); + + if (!confirm_yesno()) { + puts("BOARD programming aborted\n"); + return CMD_RET_FAILURE; + } + } + + ret = misc_write(dev, STM32_BSEC_OTP(BSEC_OTP_BOARD), + &otp, sizeof(otp)); + + if (ret) { + puts("BOARD programming error\n"); + return CMD_RET_FAILURE; + } + puts("BOARD programming done\n"); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(stboard, 6, 0, do_stboard, + "read/write board reference in OTP", + "\n" + " Print current board information\n" + "stboard [-y] <Board> <Variant> <Revision> <BOM>\n" + " Write board information\n" + " - Board: xxxx, example 1264 for MB1264\n" + " - Variant: 1 ... 15\n" + " - Revision: A...O\n" + " - BOM: 1...15\n"); diff --git a/board/st/stm32mp1/spl.c b/board/st/stm32mp1/spl.c index a7844f244bc..e19be0f7701 100644 --- a/board/st/stm32mp1/spl.c +++ b/board/st/stm32mp1/spl.c @@ -9,7 +9,6 @@ #include <dm.h> #include <ram.h> #include <asm/io.h> -#include <post.h> #include <power/pmic.h> #include <power/stpmic1.h> #include <asm/arch/ddr.h> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 776929350f9..b99c6c08a34 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -4,6 +4,7 @@ */ #include <common.h> #include <adc.h> +#include <bootm.h> #include <config.h> #include <clk.h> #include <dm.h> @@ -13,6 +14,8 @@ #include <i2c.h> #include <led.h> #include <misc.h> +#include <mtd.h> +#include <mtd_node.h> #include <phy.h> #include <reset.h> #include <syscon.h> @@ -21,6 +24,7 @@ #include <asm/gpio.h> #include <asm/arch/stm32.h> #include <asm/arch/sys_proto.h> +#include <jffs2/load_kernel.h> #include <power/regulator.h> #include <usb/dwc2_udc.h> @@ -76,7 +80,9 @@ int checkboard(void) const char *fdt_compat; int fdt_compat_len; - if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) + if (IS_ENABLED(CONFIG_STM32MP1_OPTEE)) + mode = "trusted with OP-TEE"; + else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED)) mode = "trusted"; else mode = "basic"; @@ -515,6 +521,10 @@ int board_init(void) board_key_check(); +#ifdef CONFIG_DM_REGULATOR + regulators_enable_boot_on(_DEBUG); +#endif + sysconf_init(); if (IS_ENABLED(CONFIG_LED)) @@ -745,3 +755,18 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts) debug("%s:mtdids=%s & mtdparts=%s\n", __func__, ids, parts); } #endif + +#if defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, bd_t *bd) +{ +#ifdef CONFIG_FDT_FIXUP_PARTITIONS + struct node_info nodes[] = { + { "st,stm32f469-qspi", MTD_DEV_TYPE_NOR, }, + { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, + }; + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); +#endif + + return 0; +} +#endif diff --git a/cmd/pinmux.c b/cmd/pinmux.c index 6c8ec5164d3..de909a163d8 100644 --- a/cmd/pinmux.c +++ b/cmd/pinmux.c @@ -27,6 +27,7 @@ static int do_dev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("Can't get the pin-controller: %s!\n", name); return CMD_RET_FAILURE; } + /* fall through */ case 1: if (!currdev) { printf("Pin-controller device is not set!\n"); diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 79687d3dfd4..adf7b616eee 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -4,6 +4,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x3000 CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL=y CONFIG_TARGET_STM32MP1=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" @@ -11,6 +13,7 @@ CONFIG_SPL_TEXT_BASE=0x2FFC2500 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SYS_PROMPT="STM32MP> " # CONFIG_CMD_BOOTD is not set @@ -43,6 +46,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_IS_IN_SPI_FLASH=y @@ -66,6 +70,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y @@ -111,5 +117,4 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stm32mp15_optee_defconfig b/configs/stm32mp15_optee_defconfig new file mode 100644 index 00000000000..a205f47cd89 --- /dev/null +++ b/configs/stm32mp15_optee_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_TARGET_STM32MP1=y +CONFIG_STM32MP1_OPTEE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_BOOTCOMMAND="run bootcmd_stm32mp" +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_ADC=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_EXT4=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_EXT4_INTERFACE="mmc" +CONFIG_ENV_EXT4_DEVICE_AND_PART="0:auto" +CONFIG_ENV_EXT4_FILE="/uboot.env" +CONFIG_ENV_UBI_PART="UBI" +CONFIG_ENV_UBI_VOLUME="uboot_config" +CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" +CONFIG_STM32_ADC=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 +CONFIG_FASTBOOT_BUF_SIZE=0x02000000 +CONFIG_FASTBOOT_USB_DEV=1 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_DM_HWSPINLOCK=y +CONFIG_HWSPINLOCK_STM32=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_STM32_SDMMC2=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_STM32_FMC2=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DWC_ETH_QOS=y +CONFIG_PHY=y +CONFIG_PHY_STM32_USBPHYC=y +CONFIG_PINCONF=y +CONFIG_PINCTRL_STMFX=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_STPMIC1=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_STM32_VREFBUF=y +CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_SERIAL_RX_BUFFER=y +CONFIG_STM32_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" +CONFIG_USB_GADGET_VENDOR_NUM=0x0483 +CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index e1ab2ab0d54..cdb4d95bf6f 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -58,6 +58,8 @@ CONFIG_DM_I2C=y CONFIG_SYS_I2C_STM32F7=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_DM_MAILBOX=y +CONFIG_STM32_IPCC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y @@ -101,5 +103,4 @@ CONFIG_USB_GADGET_MANUFACTURER="STMicroelectronics" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y -CONFIG_WDT=y -CONFIG_WDT_STM32MP=y +CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt index c41ae91f7ab..00169255e48 100644 --- a/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt +++ b/doc/device-tree-bindings/pinctrl/st,stm32-pinctrl.txt @@ -8,8 +8,13 @@ controllers onto these pads. Pin controller node: Required properies: - compatible: value should be one of the following: - (a) "st,stm32f429-pinctrl" - (b) "st,stm32f746-pinctrl" + "st,stm32f429-pinctrl" + "st,stm32f469-pinctrl" + "st,stm32f746-pinctrl" + "st,stm32f769-pinctrl" + "st,stm32h743-pinctrl" + "st,stm32mp157-pinctrl" + "st,stm32mp157-z-pinctrl" - #address-cells: The value of this property must be 1 - #size-cells : The value of this property must be 1 - ranges : defines mapping between pin controller node (parent) to @@ -32,13 +37,30 @@ Required properties: Optional properties: - reset: : Reference to the reset controller - - interrupt-parent: phandle of the interrupt parent to which the external - GPIO interrupts are forwarded to. - - st,syscfg: Should be phandle/offset pair. The phandle to the syscon node - which includes IRQ mux selection register, and the offset of the IRQ mux - selection register. + - st,syscfg: Should be phandle/offset/mask. + -The phandle to the syscon node which includes IRQ mux selection register. + -The offset of the IRQ mux selection register + -The field mask of IRQ mux, needed if different of 0xf. + - gpio-ranges: Define a dedicated mapping between a pin-controller and + a gpio controller. Format is <&phandle a b c> with: + -(phandle): phandle of pin-controller. + -(a): gpio base offset in range. + -(b): pin base offset in range. + -(c): gpio count in range + This entry has to be used either if there are holes inside a bank: + GPIOB0/B1/B2/B14/B15 (see example 2) + or if banks are not contiguous: + GPIOA/B/C/E... + NOTE: If "gpio-ranges" is used for a gpio controller, all gpio-controller + have to use a "gpio-ranges" entry. + More details in Documentation/devicetree/bindings/gpio/gpio.txt. + - st,bank-ioport: should correspond to the EXTI IOport selection (EXTI line + used to select GPIOs as interrupts). + - hwlocks: reference to a phandle of a hardware spinlock provider node. + - st,package: Indicates the SOC package used. + More details in include/dt-bindings/pinctrl/stm32-pinfunc.h -Example: +Example 1: #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> ... @@ -60,6 +82,43 @@ Example: pin-functions nodes follow... }; +Example 2: +#include <dt-bindings/pinctrl/stm32f429-pinfunc.h> +... + + pinctrl: pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32f429-pinctrl"; + ranges = <0 0x40020000 0x3000>; + pins-are-numbered; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@40020400 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOB"; + ngpios = 4; + gpio-ranges = <&pinctrl 0 16 3>, + <&pinctrl 14 30 2>; + }; + + + ... + pin-functions nodes follow... + }; + + Contents of function subnode node: ---------------------------------- Subnode format @@ -83,14 +142,31 @@ Required properties: - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11) - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15) - function: The function number, can be: - * 0 : GPIO IN + * 0 : GPIO * 1 : Alternate Function 0 * 2 : Alternate Function 1 * 3 : Alternate Function 2 * ... * 16 : Alternate Function 15 * 17 : Analog - * 18 : GPIO OUT + + To simplify the usage, macro is available to generate "pinmux" field. + This macro is available here: + - include/dt-bindings/pinctrl/stm32-pinfunc.h + + Some examples of using macro: + /* GPIO A9 set as alernate function 2 */ + ... { + pinmux = <STM32_PINMUX('A', 9, AF2)>; + }; + /* GPIO A9 set as GPIO */ + ... { + pinmux = <STM32_PINMUX('A', 9, GPIO)>; + }; + /* GPIO A9 set as analog */ + ... { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; + }; Optional properties: - GENERIC_PINCONFIG: is the generic pinconfig options to use. @@ -114,13 +190,13 @@ pin-controller { ... usart1_pins_a: usart1@0 { pins1 { - pinmux = <STM32F429_PA9_FUNC_USART1_TX>; + pinmux = <STM32_PINMUX('A', 9, AF7)>; bias-disable; drive-push-pull; slew-rate = <0>; }; pins2 { - pinmux = <STM32F429_PA10_FUNC_USART1_RX>; + pinmux = <STM32_PINMUX('A', 10, AF7)>; bias-disable; }; }; @@ -129,5 +205,4 @@ pin-controller { &usart1 { pinctrl-0 = <&usart1_pins_a>; pinctrl-names = "default"; - status = "okay"; }; diff --git a/drivers/adc/stm32-adc-core.c b/drivers/adc/stm32-adc-core.c index a9aa143bfe7..04b6a8a2f5b 100644 --- a/drivers/adc/stm32-adc-core.c +++ b/drivers/adc/stm32-adc-core.c @@ -60,7 +60,8 @@ static int stm32h7_adc_clk_sel(struct udevice *dev, { u32 ckmode, presc; unsigned long rate; - int i, div; + unsigned int i; + int div; /* stm32h7 bus clock is common for all ADC instances (mandatory) */ if (!clk_valid(&common->bclk)) { diff --git a/drivers/adc/stm32-adc.c b/drivers/adc/stm32-adc.c index e108062f2fe..029338e4af6 100644 --- a/drivers/adc/stm32-adc.c +++ b/drivers/adc/stm32-adc.c @@ -163,15 +163,16 @@ static int stm32_adc_chan_of_init(struct udevice *dev) struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev); struct stm32_adc *adc = dev_get_priv(dev); u32 chans[STM32_ADC_CH_MAX]; - int i, num_channels, ret; + unsigned int i, num_channels; + int ret; /* Retrieve single ended channels listed in device tree */ - num_channels = dev_read_size(dev, "st,adc-channels"); - if (num_channels < 0) { - dev_err(dev, "can't get st,adc-channels: %d\n", num_channels); - return num_channels; + ret = dev_read_size(dev, "st,adc-channels"); + if (ret < 0) { + dev_err(dev, "can't get st,adc-channels: %d\n", ret); + return ret; } - num_channels /= sizeof(u32); + num_channels = ret / sizeof(u32); if (num_channels > adc->cfg->max_channels) { dev_err(dev, "too many st,adc-channels: %d\n", num_channels); diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index f295e4864b3..6ffa05b8fd7 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -805,10 +805,11 @@ static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv, const struct stm32mp1_clk_sel *sel = priv->data->sel; int i; int s, p; + unsigned int idx; - for (i = 0; i < ARRAY_SIZE(stm32mp1_clks); i++) - if (stm32mp1_clks[i][0] == id) - return stm32mp1_clks[i][1]; + for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++) + if (stm32mp1_clks[idx][0] == id) + return stm32mp1_clks[idx][1]; i = stm32mp1_clk_get_id(priv, id); if (i < 0) @@ -1542,8 +1543,7 @@ static void stgen_config(struct stm32mp1_clk_priv *priv) u32 stgenc, cntfid0; ulong rate; - stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); - + stgenc = STM32_STGEN_BASE; cntfid0 = readl(stgenc + STGENC_CNTFID0); p = stm32mp1_clk_get_parent(priv, STGEN_K); rate = stm32mp1_clk_get(priv, p); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index fa1c99700f7..068c6d02d88 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -265,13 +265,13 @@ config PIC32_GPIO help Say yes here to support Microchip PIC32 GPIOs. -config STM32F7_GPIO +config STM32_GPIO bool "ST STM32 GPIO driver" depends on DM_GPIO && (STM32 || ARCH_STM32MP) default y help Device model driver support for STM32 GPIO controller. It should be - usable on many stm32 families like stm32f4 & stm32H7. + usable on many stm32 families like stm32f4/f7/h7 and stm32mp1. Tested on STM32F7. config MVEBU_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 7337153e0e6..4a8aa0ff6fe 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -47,7 +47,7 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o obj-$(CONFIG_TCA642X) += tca642x.o obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o -obj-$(CONFIG_STM32F7_GPIO) += stm32f7_gpio.o +obj-$(CONFIG_STM32_GPIO) += stm32_gpio.o obj-$(CONFIG_GPIO_UNIPHIER) += gpio-uniphier.o obj-$(CONFIG_ZYNQ_GPIO) += zynq_gpio.o obj-$(CONFIG_VYBRID_GPIO) += vybrid_gpio.o diff --git a/drivers/gpio/stm32f7_gpio.c b/drivers/gpio/stm32_gpio.c index 5c9f2fe64d4..302a4349477 100644 --- a/drivers/gpio/stm32f7_gpio.c +++ b/drivers/gpio/stm32_gpio.c @@ -27,7 +27,7 @@ int stm32_offset_to_index(struct udevice *dev, unsigned int offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); - int idx = 0; + unsigned int idx = 0; int i; for (i = 0; i < STM32_GPIOS_PER_BANK; i++) { @@ -210,15 +210,9 @@ static int gpio_stm32_probe(struct udevice *dev) return 0; } -static const struct udevice_id stm32_gpio_ids[] = { - { .compatible = "st,stm32-gpio" }, - { } -}; - U_BOOT_DRIVER(gpio_stm32) = { .name = "gpio_stm32", .id = UCLASS_GPIO, - .of_match = stm32_gpio_ids, .probe = gpio_stm32_probe, #ifndef CONFIG_SPL_BUILD .ops = &gpio_stm32_ops, diff --git a/drivers/i2c/stm32f7_i2c.c b/drivers/i2c/stm32f7_i2c.c index 50c4fd0de23..2b18735fea6 100644 --- a/drivers/i2c/stm32f7_i2c.c +++ b/drivers/i2c/stm32f7_i2c.c @@ -519,13 +519,13 @@ static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, /* Compute possible values for PRESC, SCLDEL and SDADEL */ for (p = 0; p < STM32_PRESC_MAX; p++) { for (l = 0; l < STM32_SCLDEL_MAX; l++) { - u32 scldel = (l + 1) * (p + 1) * i2cclk; + int scldel = (l + 1) * (p + 1) * i2cclk; if (scldel < scldel_min) continue; for (a = 0; a < STM32_SDADEL_MAX; a++) { - u32 sdadel = (a * (p + 1) + 1) * i2cclk; + int sdadel = (a * (p + 1) + 1) * i2cclk; if (((sdadel >= sdadel_min) && (sdadel <= sdadel_max)) && @@ -613,10 +613,12 @@ static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, if ((tscl >= clk_min) && (tscl <= clk_max) && (tscl_h >= i2c_specs[setup->speed].h_min) && (i2cclk < tscl_h)) { - int clk_error = tscl - i2cbus; + u32 clk_error; - if (clk_error < 0) - clk_error = -clk_error; + if (tscl > i2cbus) + clk_error = tscl - i2cbus; + else + clk_error = i2cbus - tscl; if (clk_error < clk_error_prev) { clk_error_prev = clk_error; diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index 2836ee4a7b0..11bf5522db5 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -24,6 +24,13 @@ config TEGRA_HSP This enables support for the NVIDIA Tegra HSP Hw module, which implements doorbells, mailboxes, semaphores, and shared interrupts. +config STM32_IPCC + bool "Enable STM32 IPCC controller support" + depends on DM_MAILBOX && ARCH_STM32MP + help + This enables support for the STM32MP IPCC Hw module, which + implements doorbells between 2 processors. + config K3_SEC_PROXY bool "Texas Instruments K3 Secure Proxy Driver" depends on DM_MAILBOX && ARCH_K3 diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index cd237698ba6..a753cc4e680 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -6,5 +6,6 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o +obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o diff --git a/drivers/mailbox/stm32-ipcc.c b/drivers/mailbox/stm32-ipcc.c new file mode 100644 index 00000000000..c3df9678a74 --- /dev/null +++ b/drivers/mailbox/stm32-ipcc.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) STMicroelectronics 2019 - All Rights Reserved + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <mailbox-uclass.h> +#include <asm/io.h> + +/* + * IPCC has one set of registers per CPU + * IPCC_PROC_OFFST allows to define cpu registers set base address + * according to the assigned proc_id. + */ + +#define IPCC_PROC_OFFST 0x010 + +#define IPCC_XSCR 0x008 +#define IPCC_XTOYSR 0x00c + +#define IPCC_HWCFGR 0x3f0 +#define IPCFGR_CHAN_MASK GENMASK(7, 0) + +#define RX_BIT_CHAN(chan) BIT(chan) +#define TX_BIT_SHIFT 16 +#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) + +#define STM32_MAX_PROCS 2 + +struct stm32_ipcc { + void __iomem *reg_base; + void __iomem *reg_proc; + u32 proc_id; + u32 n_chans; +}; + +static int stm32_ipcc_request(struct mbox_chan *chan) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + + debug("%s(chan=%p)\n", __func__, chan); + + if (chan->id >= ipcc->n_chans) { + debug("%s failed to request channel: %ld\n", + __func__, chan->id); + return -EINVAL; + } + + return 0; +} + +static int stm32_ipcc_free(struct mbox_chan *chan) +{ + debug("%s(chan=%p)\n", __func__, chan); + + return 0; +} + +static int stm32_ipcc_send(struct mbox_chan *chan, const void *data) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + if (readl(ipcc->reg_proc + IPCC_XTOYSR) & BIT(chan->id)) + return -EBUSY; + + /* set channel n occupied */ + setbits_le32(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan->id)); + + return 0; +} + +static int stm32_ipcc_recv(struct mbox_chan *chan, void *data) +{ + struct stm32_ipcc *ipcc = dev_get_priv(chan->dev); + u32 val; + int proc_offset; + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + /* read 'channel occupied' status from other proc */ + proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; + val = readl(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); + + if (!(val & BIT(chan->id))) + return -ENODATA; + + setbits_le32(ipcc->reg_proc + IPCC_XSCR, RX_BIT_CHAN(chan->id)); + + return 0; +} + +static int stm32_ipcc_probe(struct udevice *dev) +{ + struct stm32_ipcc *ipcc = dev_get_priv(dev); + fdt_addr_t addr; + const fdt32_t *cell; + struct clk clk; + int len, ret; + + debug("%s(dev=%p)\n", __func__, dev); + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + ipcc->reg_base = (void __iomem *)addr; + + /* proc_id */ + cell = dev_read_prop(dev, "st,proc_id", &len); + if (len < sizeof(fdt32_t)) { + dev_dbg(dev, "Missing st,proc_id\n"); + return -EINVAL; + } + + ipcc->proc_id = fdtdec_get_number(cell, 1); + + if (ipcc->proc_id >= STM32_MAX_PROCS) { + dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); + return -EINVAL; + } + + ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + goto clk_free; + + /* get channel number */ + ipcc->n_chans = readl(ipcc->reg_base + IPCC_HWCFGR); + ipcc->n_chans &= IPCFGR_CHAN_MASK; + + return 0; + +clk_free: + clk_free(&clk); + + return ret; +} + +static const struct udevice_id stm32_ipcc_ids[] = { + { .compatible = "st,stm32mp1-ipcc" }, + { } +}; + +struct mbox_ops stm32_ipcc_mbox_ops = { + .request = stm32_ipcc_request, + .free = stm32_ipcc_free, + .send = stm32_ipcc_send, + .recv = stm32_ipcc_recv, +}; + +U_BOOT_DRIVER(stm32_ipcc) = { + .name = "stm32_ipcc", + .id = UCLASS_MAILBOX, + .of_match = stm32_ipcc_ids, + .probe = stm32_ipcc_probe, + .priv_auto_alloc_size = sizeof(struct stm32_ipcc), + .ops = &stm32_ipcc_mbox_ops, +}; diff --git a/drivers/misc/stm32mp_fuse.c b/drivers/misc/stm32mp_fuse.c index 8dc246b0dbe..801d946b773 100644 --- a/drivers/misc/stm32mp_fuse.c +++ b/drivers/misc/stm32mp_fuse.c @@ -5,6 +5,7 @@ #include <common.h> #include <command.h> +#include <fuse.h> #include <misc.h> #include <errno.h> #include <dm/device.h> diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index ed31ca126e9..867ed569ebc 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -669,6 +669,7 @@ static int stm32_sdmmc2_probe(struct udevice *dev) switch (dev_read_u32_default(dev, "bus-width", 1)) { case 8: cfg->host_caps |= MMC_MODE_8BIT; + /* fall through */ case 4: cfg->host_caps |= MMC_MODE_4BIT; break; @@ -692,7 +693,7 @@ clk_free: return ret; } -int stm32_sdmmc_bind(struct udevice *dev) +static int stm32_sdmmc_bind(struct udevice *dev) { struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index 2bb749d7f73..f3179cc21f5 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -627,21 +627,16 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, struct stm32_fmc2_timings *tims = &nand->timings; unsigned long hclk = clk_get_rate(&fmc2->clk); unsigned long hclkp = FMC2_NSEC_PER_SEC / (hclk / 1000); - int tar, tclr, thiz, twait, tset_mem, tset_att, thold_mem, thold_att; - - tar = hclkp; - if (tar < sdrt->tAR_min) - tar = sdrt->tAR_min; - tims->tar = DIV_ROUND_UP(tar, hclkp) - 1; - if (tims->tar > FMC2_PCR_TIMING_MASK) - tims->tar = FMC2_PCR_TIMING_MASK; - - tclr = hclkp; - if (tclr < sdrt->tCLR_min) - tclr = sdrt->tCLR_min; - tims->tclr = DIV_ROUND_UP(tclr, hclkp) - 1; - if (tims->tclr > FMC2_PCR_TIMING_MASK) - tims->tclr = FMC2_PCR_TIMING_MASK; + unsigned long timing, tar, tclr, thiz, twait; + unsigned long tset_mem, tset_att, thold_mem, thold_att; + + tar = max_t(unsigned long, hclkp, sdrt->tAR_min); + timing = DIV_ROUND_UP(tar, hclkp) - 1; + tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); + + tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min); + timing = DIV_ROUND_UP(tclr, hclkp) - 1; + tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); tims->thiz = FMC2_THIZ; thiz = (tims->thiz + 1) * hclkp; @@ -651,18 +646,11 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, * tWAIT > tWP * tWAIT > tREA + tIO */ - twait = hclkp; - if (twait < sdrt->tRP_min) - twait = sdrt->tRP_min; - if (twait < sdrt->tWP_min) - twait = sdrt->tWP_min; - if (twait < sdrt->tREA_max + FMC2_TIO) - twait = sdrt->tREA_max + FMC2_TIO; - tims->twait = DIV_ROUND_UP(twait, hclkp); - if (tims->twait == 0) - tims->twait = 1; - else if (tims->twait > FMC2_PMEM_PATT_TIMING_MASK) - tims->twait = FMC2_PMEM_PATT_TIMING_MASK; + twait = max_t(unsigned long, hclkp, sdrt->tRP_min); + twait = max_t(unsigned long, twait, sdrt->tWP_min); + twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO); + timing = DIV_ROUND_UP(twait, hclkp); + tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); /* * tSETUP_MEM > tCS - tWAIT @@ -677,20 +665,15 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, if (twait > thiz && (sdrt->tDS_min > twait - thiz) && (tset_mem < sdrt->tDS_min - (twait - thiz))) tset_mem = sdrt->tDS_min - (twait - thiz); - tims->tset_mem = DIV_ROUND_UP(tset_mem, hclkp); - if (tims->tset_mem == 0) - tims->tset_mem = 1; - else if (tims->tset_mem > FMC2_PMEM_PATT_TIMING_MASK) - tims->tset_mem = FMC2_PMEM_PATT_TIMING_MASK; + timing = DIV_ROUND_UP(tset_mem, hclkp); + tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); /* * tHOLD_MEM > tCH * tHOLD_MEM > tREH - tSETUP_MEM * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) */ - thold_mem = hclkp; - if (thold_mem < sdrt->tCH_min) - thold_mem = sdrt->tCH_min; + thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min); if (sdrt->tREH_min > tset_mem && (thold_mem < sdrt->tREH_min - tset_mem)) thold_mem = sdrt->tREH_min - tset_mem; @@ -700,11 +683,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, if ((sdrt->tWC_min > tset_mem + twait) && (thold_mem < sdrt->tWC_min - (tset_mem + twait))) thold_mem = sdrt->tWC_min - (tset_mem + twait); - tims->thold_mem = DIV_ROUND_UP(thold_mem, hclkp); - if (tims->thold_mem == 0) - tims->thold_mem = 1; - else if (tims->thold_mem > FMC2_PMEM_PATT_TIMING_MASK) - tims->thold_mem = FMC2_PMEM_PATT_TIMING_MASK; + timing = DIV_ROUND_UP(thold_mem, hclkp); + tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); /* * tSETUP_ATT > tCS - tWAIT @@ -726,11 +706,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, if (twait > thiz && (sdrt->tDS_min > twait - thiz) && (tset_att < sdrt->tDS_min - (twait - thiz))) tset_att = sdrt->tDS_min - (twait - thiz); - tims->tset_att = DIV_ROUND_UP(tset_att, hclkp); - if (tims->tset_att == 0) - tims->tset_att = 1; - else if (tims->tset_att > FMC2_PMEM_PATT_TIMING_MASK) - tims->tset_att = FMC2_PMEM_PATT_TIMING_MASK; + timing = DIV_ROUND_UP(tset_att, hclkp); + tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); /* * tHOLD_ATT > tALH @@ -745,17 +722,11 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) */ - thold_att = hclkp; - if (thold_att < sdrt->tALH_min) - thold_att = sdrt->tALH_min; - if (thold_att < sdrt->tCH_min) - thold_att = sdrt->tCH_min; - if (thold_att < sdrt->tCLH_min) - thold_att = sdrt->tCLH_min; - if (thold_att < sdrt->tCOH_min) - thold_att = sdrt->tCOH_min; - if (thold_att < sdrt->tDH_min) - thold_att = sdrt->tDH_min; + thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min); + thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min); + thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min); + thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min); + thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min); if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; @@ -774,11 +745,8 @@ static void stm32_fmc2_calc_timings(struct nand_chip *chip, if ((sdrt->tWC_min > tset_att + twait) && (thold_att < sdrt->tWC_min - (tset_att + twait))) thold_att = sdrt->tWC_min - (tset_att + twait); - tims->thold_att = DIV_ROUND_UP(thold_att, hclkp); - if (tims->thold_att == 0) - tims->thold_att = 1; - else if (tims->thold_att > FMC2_PMEM_PATT_TIMING_MASK) - tims->thold_att = FMC2_PMEM_PATT_TIMING_MASK; + timing = DIV_ROUND_UP(thold_att, hclkp); + tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); } static int stm32_fmc2_setup_interface(struct mtd_info *mtd, int chipnr, @@ -932,7 +900,8 @@ static int stm32_fmc2_probe(struct udevice *dev) struct nand_ecclayout *ecclayout; struct resource resource; struct reset_ctl reset; - int oob_index, chip_cs, mem_region, ret, i; + int oob_index, chip_cs, mem_region, ret; + unsigned int i; spin_lock_init(&fmc2->controller.lock); init_waitqueue_head(&fmc2->controller.wq); diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 43dbdd9d6a8..cdbe463cff7 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -1,5 +1,6 @@ #include <common.h> #include <dm.h> +#include <dm/lists.h> #include <dm/pinctrl.h> #include <hwspinlock.h> #include <asm/arch/gpio.h> @@ -136,7 +137,7 @@ static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev, */ *idx = stm32_offset_to_index(gpio_bank->gpio_dev, selector - pin_count); - if (*idx < 0) + if (IS_ERR_VALUE(*idx)) return NULL; return gpio_bank->gpio_dev; @@ -215,7 +216,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, #endif -int stm32_pinctrl_probe(struct udevice *dev) +static int stm32_pinctrl_probe(struct udevice *dev) { struct stm32_pinctrl_priv *priv = dev_get_priv(dev); int ret; @@ -364,6 +365,35 @@ static int stm32_pinctrl_config(int offset) return 0; } +static int stm32_pinctrl_bind(struct udevice *dev) +{ + ofnode node; + const char *name; + int ret; + + dev_for_each_subnode(node, dev) { + debug("%s: bind %s\n", __func__, ofnode_get_name(node)); + + ofnode_get_property(node, "gpio-controller", &ret); + if (ret < 0) + continue; + /* Get the name of each gpio node */ + name = ofnode_get_name(node); + if (!name) + return -EINVAL; + + /* Bind each gpio node */ + ret = device_bind_driver_to_node(dev, "gpio_stm32", + name, node, NULL); + if (ret) + return ret; + + debug("%s: bind %s\n", __func__, name); + } + + return 0; +} + #if CONFIG_IS_ENABLED(PINCTRL_FULL) static int stm32_pinctrl_set_state(struct udevice *dev, struct udevice *config) { @@ -433,7 +463,7 @@ U_BOOT_DRIVER(pinctrl_stm32) = { .id = UCLASS_PINCTRL, .of_match = stm32_pinctrl_ids, .ops = &stm32_pinctrl_ops, - .bind = dm_scan_fdt_dev, + .bind = stm32_pinctrl_bind, .probe = stm32_pinctrl_probe, .priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv), }; diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index 65296c5fc3a..c3381489dda 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -221,7 +221,7 @@ static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type) struct udevice *pmic_dev; int ret; - if (type != SYSRESET_POWER) + if (type != SYSRESET_POWER && type != SYSRESET_POWER_OFF) return -EPROTONOSUPPORT; ret = uclass_get_device_by_driver(UCLASS_PMIC, @@ -235,8 +235,13 @@ static int stpmic1_sysreset_request(struct udevice *dev, enum sysreset_t type) if (ret < 0) return ret; - ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, - ret | STPMIC1_SWOFF | STPMIC1_RREQ_EN); + ret |= STPMIC1_SWOFF; + ret &= ~STPMIC1_RREQ_EN; + /* request Power Cycle */ + if (type == SYSRESET_POWER) + ret |= STPMIC1_RREQ_EN; + + ret = pmic_reg_write(pmic_dev, STPMIC1_MAIN_CR, ret); if (ret < 0) return ret; diff --git a/drivers/power/regulator/stm32-vrefbuf.c b/drivers/power/regulator/stm32-vrefbuf.c index 0ad6833ed04..645528e84e8 100644 --- a/drivers/power/regulator/stm32-vrefbuf.c +++ b/drivers/power/regulator/stm32-vrefbuf.c @@ -30,7 +30,7 @@ struct stm32_vrefbuf { struct udevice *vdda_supply; }; -static const unsigned int stm32_vrefbuf_voltages[] = { +static const int stm32_vrefbuf_voltages[] = { /* Matches resp. VRS = 000b, 001b, 010b, 011b */ 2500000, 2048000, 1800000, 1500000, }; diff --git a/drivers/power/regulator/stpmic1.c b/drivers/power/regulator/stpmic1.c index 50ef2a21d18..1e3f96f3a08 100644 --- a/drivers/power/regulator/stpmic1.c +++ b/drivers/power/regulator/stpmic1.c @@ -422,6 +422,7 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode) case STPMIC1_LDO_MODE_SINK_SOURCE: ret &= ~STPMIC1_LDO12356_VOUT_MASK; ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT; + /* fallthrough */ case STPMIC1_LDO_MODE_NORMAL: ret &= ~STPMIC1_LDO3_MODE; break; diff --git a/drivers/ram/stm32mp1/stm32mp1_ram.c b/drivers/ram/stm32mp1/stm32mp1_ram.c index 84e39d093b5..a362cf98bfc 100644 --- a/drivers/ram/stm32mp1/stm32mp1_ram.c +++ b/drivers/ram/stm32mp1/stm32mp1_ram.c @@ -26,7 +26,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) unsigned long ddr_clk; struct clk clk; int ret; - int idx; + unsigned int idx; for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) { ret = clk_get_by_name(priv->dev, clkname[idx], &clk); @@ -59,7 +59,8 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev) { struct ddr_info *priv = dev_get_priv(dev); - int ret, idx; + int ret; + unsigned int idx; struct clk axidcg; struct stm32mp1_ddr_config config; diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index cca8b707acc..3ab536a52ac 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -195,9 +195,9 @@ static int stm32_serial_probe(struct udevice *dev) } plat->clock_rate = clk_get_rate(&clk); - if (plat->clock_rate < 0) { + if (!plat->clock_rate) { clk_disable(&clk); - return plat->clock_rate; + return -EINVAL; }; _stm32_serial_init(plat->base, plat->uart_info); diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index bb1067ff4a9..8d612f22d69 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -361,9 +361,9 @@ static int stm32_qspi_probe(struct udevice *bus) } priv->clock_rate = clk_get_rate(&clk); - if (priv->clock_rate < 0) { + if (!priv->clock_rate) { clk_disable(&clk); - return priv->clock_rate; + return -EINVAL; } ret = reset_get_by_index(bus, 0, &reset_ctl); @@ -395,14 +395,15 @@ static int stm32_qspi_claim_bus(struct udevice *dev) { struct stm32_qspi_priv *priv = dev_get_priv(dev->parent); struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + int slave_cs = slave_plat->cs; - if (slave_plat->cs >= STM32_QSPI_MAX_CHIP) + if (slave_cs >= STM32_QSPI_MAX_CHIP) return -ENODEV; - if (priv->cs_used != slave_plat->cs) { - struct stm32_qspi_flash *flash = &priv->flash[slave_plat->cs]; + if (priv->cs_used != slave_cs) { + struct stm32_qspi_flash *flash = &priv->flash[slave_cs]; - priv->cs_used = slave_plat->cs; + priv->cs_used = slave_cs; if (flash->initialized) { /* Set the configuration: speed + cs */ @@ -444,11 +445,12 @@ static int stm32_qspi_set_speed(struct udevice *bus, uint speed) int ret; if (speed > 0) { - prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; - if (prescaler > 255) - prescaler = 255; - else if (prescaler < 0) - prescaler = 0; + prescaler = 0; + if (qspi_clk) { + prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; + if (prescaler > 255) + prescaler = 255; + } } csht = DIV_ROUND_UP((5 * qspi_clk) / (prescaler + 1), 100000000); diff --git a/drivers/spi/stm32_spi.c b/drivers/spi/stm32_spi.c index 34b217584dd..75b6006b454 100644 --- a/drivers/spi/stm32_spi.c +++ b/drivers/spi/stm32_spi.c @@ -99,8 +99,8 @@ struct stm32_spi_priv { unsigned int cur_bpw; unsigned int cur_hz; unsigned int cur_xferlen; /* current transfer length in bytes */ - int tx_len; /* number of data to be written in bytes */ - int rx_len; /* number of data to be read in bytes */ + unsigned int tx_len; /* number of data to be written in bytes */ + unsigned int rx_len; /* number of data to be read in bytes */ const void *tx_buf; /* data to be written, or NULL */ void *rx_buf; /* data to be read, or NULL */ u32 cur_mode; @@ -322,7 +322,8 @@ static int stm32_spi_set_fthlv(struct udevice *dev, u32 xfer_len) static int stm32_spi_set_speed(struct udevice *bus, uint hz) { struct stm32_spi_priv *priv = dev_get_priv(bus); - u32 div, mbrdiv; + u32 mbrdiv; + long div; debug("%s: hz=%d\n", __func__, hz); @@ -341,7 +342,7 @@ static int stm32_spi_set_speed(struct udevice *bus, uint hz) else mbrdiv = fls(div) - 1; - if ((mbrdiv - 1) < 0) + if (!mbrdiv) return -EINVAL; clrsetbits_le32(priv->base + STM32_SPI_CFG1, SPI_CFG1_MBR, @@ -481,7 +482,7 @@ static int stm32_spi_probe(struct udevice *dev) struct stm32_spi_priv *priv = dev_get_priv(dev); unsigned long clk_rate; int ret; - int i; + unsigned int i; priv->base = dev_remap_addr(dev); if (!priv->base) diff --git a/drivers/sysreset/sysreset_syscon.c b/drivers/sysreset/sysreset_syscon.c index 1028160247a..d0e586f66f6 100644 --- a/drivers/sysreset/sysreset_syscon.c +++ b/drivers/sysreset/sysreset_syscon.c @@ -23,8 +23,9 @@ struct syscon_reboot_priv { static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type) { struct syscon_reboot_priv *priv = dev_get_priv(dev); + ulong driver_data = dev_get_driver_data(dev); - if (type == SYSRESET_POWER) + if (type != driver_data) return -EPROTONOSUPPORT; regmap_write(priv->regmap, priv->offset, priv->mask); @@ -53,7 +54,8 @@ int syscon_reboot_probe(struct udevice *dev) } static const struct udevice_id syscon_reboot_ids[] = { - { .compatible = "syscon-reboot" }, + { .compatible = "syscon-reboot", .data = SYSRESET_COLD }, + { .compatible = "syscon-poweroff", .data = SYSRESET_POWER_OFF }, { /* sentinel */ } }; diff --git a/env/Kconfig b/env/Kconfig index d86a9bfa308..74db2f38cc1 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -468,8 +468,7 @@ if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC config ENV_OFFSET hex "Environment Offset" - depends on !ENV_IS_IN_UBI - depends on !ENV_IS_NOWHERE + depends on (!ENV_IS_IN_UBI && !ENV_IS_NOWHERE) || ARCH_STM32MP default 0x3f8000 if ARCH_ROCKCHIP default 0x88000 if ARCH_SUNXI default 0xE0000 if ARCH_ZYNQ @@ -492,7 +491,7 @@ config ENV_SIZE config ENV_SECT_SIZE hex "Environment Sector-Size" - depends on !ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91) + depends on (!ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91) )|| ARCH_STM32MP default 0x40000 if ARCH_ZYNQMP default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91 help diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h index 0ce2fcb8b7a..24f7b9d463f 100644 --- a/include/configs/stm32mp1.h +++ b/include/configs/stm32mp1.h @@ -28,6 +28,10 @@ #define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE +#ifdef CONFIG_STM32MP1_OPTEE +#define CONFIG_SYS_MEM_TOP_HIDE SZ_32M +#endif /* CONFIG_STM32MP1_OPTEE */ + /* * Console I/O buffer size */ @@ -38,11 +42,6 @@ */ #define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_SECT_SIZE SZ_256K -#define CONFIG_ENV_OFFSET 0x00280000 -#endif - /* ATAGs */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS @@ -73,6 +72,10 @@ /*MMC SD*/ #define CONFIG_SYS_MMC_MAX_DEVICE 3 +/* NAND support */ +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + /* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS #define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ @@ -81,17 +84,18 @@ #define CONFIG_SYS_AUTOLOAD "no" #endif +/* Dynamic MTD partition support */ +#define CONFIG_SYS_MTDPARTS_RUNTIME + /*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS /*****************************************************************************/ #if !defined(CONFIG_SPL_BUILD) -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 1) \ + func(UBIFS, ubifs, 0) \ func(MMC, mmc, 0) \ func(MMC, mmc, 2) \ func(PXE, pxe, na) @@ -108,6 +112,7 @@ "if test ${boot_device} = serial || test ${boot_device} = usb;" \ "then stm32prog ${boot_device} ${boot_instance}; " \ "else " \ + "run env_check;" \ "if test ${boot_device} = mmc;" \ "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ "if test ${boot_device} = nand;" \ @@ -117,14 +122,24 @@ #include <config_distro_bootcmd.h> -#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC) -#define CONFIG_SYS_MTDPARTS_RUNTIME -#endif +#ifdef CONFIG_STM32MP1_OPTEE +/* with OPTEE: define specific MTD partitions = teeh, teed, teex */ +#define STM32MP_MTDPARTS \ + "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \ + "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0" +#else /* CONFIG_STM32MP1_OPTEE */ #define STM32MP_MTDPARTS \ "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \ "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" +#endif /* CONFIG_STM32MP1_OPTEE */ + +#ifndef CONFIG_SYS_MTDPARTS_RUNTIME +#undef STM32MP_MTDPARTS +#define STM32MP_MTDPARTS +#endif + /* * memory layout for 32M uncompressed/compressed kernel, * 1M fdt, 1M script, 1M pxe and 1M for splashimage @@ -139,9 +154,13 @@ "ramdisk_addr_r=0xc4400000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ + "env_default=1\0" \ + "env_check=if test $env_default -eq 1;"\ + " then env set env_default 0;env save;fi\0" \ STM32MP_BOOTCMD \ STM32MP_MTDPARTS \ - BOOTENV + BOOTENV \ + "boot_net_usb_start=true\0" #endif /* ifndef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index b5a2174a638..e6fb8ada3f4 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -32,5 +32,11 @@ #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) +/* package information */ +#define STM32MP_PKG_AA 0x1 +#define STM32MP_PKG_AB 0x2 +#define STM32MP_PKG_AC 0x4 +#define STM32MP_PKG_AD 0x8 + #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ |