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authorSimon Glass2023-01-17 10:47:11 -0700
committerTom Rini2023-01-23 18:11:39 -0500
commitc0f19fedaa742adbe0f4e29e9a956ea05fe22057 (patch)
treec925a02ce88ab1b47ac6caca2dd367247fbb1332
parentdd31cd58b02729807934cb699b164b1f8736620f (diff)
dm: core: Correct ordering of uclasses IDs
A few of these are out of order. Fix them. Signed-off-by: Simon Glass <sjg@chromium.org>
-rw-r--r--include/dm/uclass-id.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 376f741cc2b..33e43c20db6 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -47,9 +47,9 @@ enum uclass_id {
UCLASS_CPU, /* CPU, typically part of an SoC */
UCLASS_CROS_EC, /* Chrome OS EC */
UCLASS_DISPLAY, /* Display (e.g. DisplayPort, HDMI) */
- UCLASS_DSI_HOST, /* Display Serial Interface host */
UCLASS_DMA, /* Direct Memory Access */
UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */
+ UCLASS_DSI_HOST, /* Display Serial Interface host */
UCLASS_ECDSA, /* Elliptic curve cryptographic device */
UCLASS_EFI_LOADER, /* Devices created by UEFI applications */
UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
@@ -101,6 +101,7 @@ enum uclass_id {
UCLASS_PINCTRL, /* Pinctrl (pin muxing/configuration) device */
UCLASS_PMIC, /* PMIC I/O device */
UCLASS_POWER_DOMAIN, /* (SoC) Power domains */
+ UCLASS_PVBLOCK, /* Xen virtual block device */
UCLASS_PWM, /* Pulse-width modulator */
UCLASS_PWRSEQ, /* Power sequence device */
UCLASS_QFW, /* QEMU firmware config device */
@@ -142,7 +143,6 @@ enum uclass_id {
UCLASS_W1, /* Dallas 1-Wire bus */
UCLASS_W1_EEPROM, /* one-wire EEPROMs */
UCLASS_WDT, /* Watchdog Timer driver */
- UCLASS_PVBLOCK, /* Xen virtual block device */
UCLASS_COUNT,
UCLASS_INVALID = -1,