diff options
| author | Marek Vasut | 2015-07-21 05:29:05 +0200 |
|---|---|---|
| committer | Marek Vasut | 2015-08-08 14:14:23 +0200 |
| commit | c65408720670819a9a7174a6b0ed59968cd8ffb7 (patch) | |
| tree | 85fdd58e6897b3c4399007bdeb2ddbf82ca38ec9 | |
| parent | c8570afa04b6d5db236b2426922f78fc26f647b5 (diff) | |
ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
Zap the useless addr variable.
Signed-off-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | drivers/ddr/altera/sequencer.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c index cc5db16e367..986f0889f25 100644 --- a/drivers/ddr/altera/sequencer.c +++ b/drivers/ddr/altera/sequencer.c @@ -2977,7 +2977,6 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, int i; u32 sticky_bit_chk; u32 min_index; - u32 addr; int left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; int right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS]; int mid; @@ -2996,8 +2995,8 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group, dm_margin = 0; - addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET; - start_dqs = readl(addr + + start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS | + SCC_MGR_IO_OUT1_DELAY_OFFSET) + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2)); /* Per-bit deskew. */ |