Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

[trini: Drop CMD_BOOTI as it's now on by default on ARM64]
Signed-off-by: Tom Rini <trini@konsulko.com>

114 files changed, 11604 insertions, 221 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index e0bf6794bf0..8e67202693e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -126,6 +126,12 @@ T:	git git://git.denx.de/u-boot-pxa.git
 F:	arch/arm/cpu/pxa/
 F:	arch/arm/include/asm/arch-pxa/
 
+ARM RENESAS RMOBILE/R-CAR
+M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:	Maintained
+T:	git git://git.denx.de/u-boot-sh.git
+F:	arch/arm/mach-rmobile/
+
 ARM ROCKCHIP
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5ac94011047..aef901c3f44 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -579,9 +579,10 @@ config AM43XX
 	  protocols, dual camera support, optional 3D graphics
 	  and an optional customer programmable secure boot.
 
-config RMOBILE
+config ARCH_RMOBILE
 	bool "Renesas ARM SoCs"
-	select CPU_V7
+	select DM
+	select DM_SERIAL
 
 config TARGET_S32V234EVB
 	bool "Support s32v234evb"
@@ -897,7 +898,7 @@ source "arch/arm/cpu/armv7/omap-common/Kconfig"
 
 source "arch/arm/mach-orion5x/Kconfig"
 
-source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-rmobile/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 82f2fd0839d..42093c2b5e2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -67,6 +67,7 @@ machine-$(CONFIG_ARCH_S5PC1XX)		+= s5pc1xx
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
 machine-$(CONFIG_ARCH_SNAPDRAGON)	+= snapdragon
 machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
+machine-$(CONFIG_ARCH_RMOBILE)		+= rmobile
 machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
 machine-$(CONFIG_STM32)			+= stm32
 machine-$(CONFIG_TEGRA)			+= tegra
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
new file mode 100644
index 00000000000..4b05d78839c
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -0,0 +1,20 @@
+if ARCH_RMOBILE
+
+choice
+	prompt "Target Renesas SoC select"
+	default RCAR_32
+
+config RCAR_32
+	bool "Renesas ARM SoCs R-Car Gen1/Gen2 (32bit)"
+	select CPU_V7
+
+config RCAR_GEN3
+	bool "Renesas ARM SoCs R-Car Gen3 (64bit)"
+	select ARM64
+
+endchoice
+
+source "arch/arm/mach-rmobile/Kconfig.32"
+source "arch/arm/mach-rmobile/Kconfig.64"
+
+endif
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig.32
index 85c06eb45f3..89588aaf729 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig.32
@@ -1,4 +1,4 @@
-if RMOBILE
+if RCAR_32
 
 choice
 	prompt "Renesus ARM SoCs board select"
@@ -7,6 +7,11 @@ choice
 config TARGET_ARMADILLO_800EVA
 	bool "armadillo 800 eva board"
 
+config TARGET_BLANCHE
+	bool "Blanche board"
+	select DM
+	select DM_SERIAL
+
 config TARGET_GOSE
 	bool "Gose board"
 	select DM
@@ -52,12 +57,12 @@ config SYS_SOC
 
 config RMOBILE_EXTRAM_BOOT
 	bool "Enable boot from RAM"
-	depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
+	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT
 	default n
 
 choice
 	prompt "Qos setting primary"
-	depends on TARGET_ALT || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
+	depends on TARGET_ALT || TARGET_BLANCHE || TARGET_GOSE || TARGET_KOELSCH || TARGET_LAGER
 	default QOS_PRI_NORMAL
 
 config QOS_PRI_NORMAL
@@ -78,6 +83,7 @@ config QOS_PRI_GFX
 endchoice
 
 source "board/atmark-techno/armadillo-800eva/Kconfig"
+source "board/renesas/blanche/Kconfig"
 source "board/renesas/gose/Kconfig"
 source "board/renesas/koelsch/Kconfig"
 source "board/renesas/lager/Kconfig"
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
new file mode 100644
index 00000000000..2a7eeba828c
--- /dev/null
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -0,0 +1,28 @@
+if RCAR_GEN3
+
+config R8A7795
+	bool
+
+choice
+	prompt "Renesus ARM64 SoCs board select"
+	optional
+
+config TARGET_SALVATOR_X
+	bool "Salvator-X board"
+	select R8A7795
+	help
+          Support for Renesas R-Car Gen3 R8a7795 platform
+
+endchoice
+
+config SYS_SOC
+	default "rmobile"
+
+config RCAR_GEN3_EXTRAM_BOOT
+	bool "Enable boot from RAM"
+	depends on TARGET_SALVATOR_X
+	default n
+
+source "board/renesas/salvator-x/Kconfig"
+
+endif
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/mach-rmobile/Makefile
index 647e426d0b5..3b56fcf96f8 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/mach-rmobile/Makefile
@@ -13,7 +13,9 @@ obj-$(CONFIG_GLOBAL_TIMER) += timer.o
 obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
 obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7790.o
 obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7791.o
+obj-$(CONFIG_R8A7792) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7792.o
 obj-$(CONFIG_R8A7793) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7793.o
 obj-$(CONFIG_R8A7794) += lowlevel_init_ca15.o cpu_info-rcar.o pfc-r8a7794.o
+obj-$(CONFIG_R8A7795) += lowlevel_init_gen3.o cpu_info-rcar.o pfc-r8a7795.o memmap-r8a7795.o
 obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
-obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
+obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/board.c b/arch/arm/mach-rmobile/board.c
index d91bc26703a..d91bc26703a 100644
--- a/arch/arm/cpu/armv7/rmobile/board.c
+++ b/arch/arm/mach-rmobile/board.c
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
index dfe8950ae19..dfe8950ae19 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7740.c
+++ b/arch/arm/mach-rmobile/cpu_info-r8a7740.c
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c b/arch/arm/mach-rmobile/cpu_info-rcar.c
index 42ee30fbe7a..42ee30fbe7a 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c
+++ b/arch/arm/mach-rmobile/cpu_info-rcar.c
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c b/arch/arm/mach-rmobile/cpu_info-sh73a0.c
index 186b4b5cbb8..186b4b5cbb8 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info-sh73a0.c
+++ b/arch/arm/mach-rmobile/cpu_info-sh73a0.c
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index d47c47c07ee..129ab0c0f72 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -53,6 +53,7 @@ static const struct {
 	{ 0x40, "R8A7740" },
 	{ 0x45, "R8A7790" },
 	{ 0x47, "R8A7791" },
+	{ 0x4A, "R8A7792" },
 	{ 0x4B, "R8A7793" },
 	{ 0x4C, "R8A7794" },
 	{ 0x0, "CPU" },
diff --git a/arch/arm/cpu/armv7/rmobile/emac.c b/arch/arm/mach-rmobile/emac.c
index 0710cfd3c19..0710cfd3c19 100644
--- a/arch/arm/cpu/armv7/rmobile/emac.c
+++ b/arch/arm/mach-rmobile/emac.c
diff --git a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h b/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h
index 463654efd33..463654efd33 100644
--- a/arch/arm/include/asm/arch-rmobile/ehci-rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/ehci-rmobile.h
diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h
index 93b20af7ea2..4861bfe0664 100644
--- a/arch/arm/include/asm/arch-rmobile/gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/gpio.h
@@ -13,12 +13,18 @@ void r8a7790_pinmux_init(void);
 #elif defined(CONFIG_R8A7791)
 #include "r8a7791-gpio.h"
 void r8a7791_pinmux_init(void);
+#elif defined(CONFIG_R8A7792)
+#include "r8a7792-gpio.h"
+void r8a7792_pinmux_init(void);
 #elif defined(CONFIG_R8A7793)
 #include "r8a7793-gpio.h"
 void r8a7793_pinmux_init(void);
 #elif defined(CONFIG_R8A7794)
 #include "r8a7794-gpio.h"
 void r8a7794_pinmux_init(void);
+#elif defined(CONFIG_R8A7795)
+#include "r8a7795-gpio.h"
+void r8a7795_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-rmobile/irqs.h b/arch/arm/mach-rmobile/include/mach/irqs.h
index dcb714f4d75..dcb714f4d75 100644
--- a/arch/arm/include/asm/arch-rmobile/irqs.h
+++ b/arch/arm/mach-rmobile/include/mach/irqs.h
diff --git a/arch/arm/include/asm/arch-rmobile/mmc.h b/arch/arm/mach-rmobile/include/mach/mmc.h
index 4e0fef11981..4e0fef11981 100644
--- a/arch/arm/include/asm/arch-rmobile/mmc.h
+++ b/arch/arm/mach-rmobile/include/mach/mmc.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h
index 28f483c4593..28f483c4593 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7740-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7740.h b/arch/arm/mach-rmobile/include/mach/r8a7740.h
index 989da337fec..989da337fec 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7740.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7740.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h
index 74b5f1df598..74b5f1df598 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/mach-rmobile/include/mach/r8a7790.h
index 748b8025460..748b8025460 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7790.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7790.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h
index 42e82597e78..42e82597e78 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/mach-rmobile/include/mach/r8a7791.h
index 1d06b651f48..1d06b651f48 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7791.h
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
new file mode 100644
index 00000000000..86931c3fee7
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792-gpio.h
@@ -0,0 +1,220 @@
+#ifndef __ASM_R8A7792_GPIO_H__
+#define __ASM_R8A7792_GPIO_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+	GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
+	GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
+	GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
+	GPIO_GP_7_16,
+
+	GPIO_GP_8_0, GPIO_GP_8_1, GPIO_GP_8_2, GPIO_GP_8_3,
+	GPIO_GP_8_4, GPIO_GP_8_5, GPIO_GP_8_6, GPIO_GP_8_7,
+	GPIO_GP_8_8, GPIO_GP_8_9, GPIO_GP_8_10, GPIO_GP_8_11,
+	GPIO_GP_8_12, GPIO_GP_8_13, GPIO_GP_8_14, GPIO_GP_8_15,
+	GPIO_GP_8_16,
+
+	GPIO_GP_9_0, GPIO_GP_9_1, GPIO_GP_9_2, GPIO_GP_9_3,
+	GPIO_GP_9_4, GPIO_GP_9_5, GPIO_GP_9_6, GPIO_GP_9_7,
+	GPIO_GP_9_8, GPIO_GP_9_9, GPIO_GP_9_10, GPIO_GP_9_11,
+	GPIO_GP_9_12, GPIO_GP_9_13, GPIO_GP_9_14, GPIO_GP_9_15,
+	GPIO_GP_9_16,
+
+	GPIO_GP_10_0, GPIO_GP_10_1, GPIO_GP_10_2, GPIO_GP_10_3,
+	GPIO_GP_10_4, GPIO_GP_10_5, GPIO_GP_10_6, GPIO_GP_10_7,
+	GPIO_GP_10_8, GPIO_GP_10_9, GPIO_GP_10_10, GPIO_GP_10_11,
+	GPIO_GP_10_12, GPIO_GP_10_13, GPIO_GP_10_14, GPIO_GP_10_15,
+	GPIO_GP_10_16, GPIO_GP_10_17, GPIO_GP_10_18, GPIO_GP_10_19,
+	GPIO_GP_10_20, GPIO_GP_10_21, GPIO_GP_10_22, GPIO_GP_10_23,
+	GPIO_GP_10_24, GPIO_GP_10_25, GPIO_GP_10_26, GPIO_GP_10_27,
+	GPIO_GP_10_28, GPIO_GP_10_29, GPIO_GP_10_30, GPIO_GP_10_31,
+
+	GPIO_GP_11_0, GPIO_GP_11_1, GPIO_GP_11_2, GPIO_GP_11_3,
+	GPIO_GP_11_4, GPIO_GP_11_5, GPIO_GP_11_6, GPIO_GP_11_7,
+	GPIO_GP_11_8, GPIO_GP_11_9, GPIO_GP_11_10, GPIO_GP_11_11,
+	GPIO_GP_11_12, GPIO_GP_11_13, GPIO_GP_11_14, GPIO_GP_11_15,
+	GPIO_GP_11_16, GPIO_GP_11_17, GPIO_GP_11_18, GPIO_GP_11_19,
+	GPIO_GP_11_20, GPIO_GP_11_21, GPIO_GP_11_22, GPIO_GP_11_23,
+	GPIO_GP_11_24, GPIO_GP_11_25, GPIO_GP_11_26, GPIO_GP_11_27,
+	GPIO_GP_11_28, GPIO_GP_11_29,
+
+	GPIO_FN_DU1_DB2_C0_DATA12, GPIO_FN_DU1_DB3_C1_DATA13,
+	GPIO_FN_DU1_DB4_C2_DATA14, GPIO_FN_DU1_DB5_C3_DATA15,
+	GPIO_FN_DU1_DB6_C4, GPIO_FN_DU1_DB7_C5, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC,
+	GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_DU1_DISP, GPIO_FN_DU1_CDE,
+
+	GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
+	GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10, GPIO_FN_D11,
+	GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15, GPIO_FN_A0, GPIO_FN_A1,
+	GPIO_FN_A2, GPIO_FN_A3, GPIO_FN_A4, GPIO_FN_A5, GPIO_FN_A6, GPIO_FN_A7,
+	GPIO_FN_A8, GPIO_FN_A9, GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
+	GPIO_FN_A14, GPIO_FN_A15,
+
+	GPIO_FN_A16, GPIO_FN_A17, GPIO_FN_A18, GPIO_FN_A19,
+	GPIO_FN_CS1_A26, GPIO_FN_EX_CS0, GPIO_FN_EX_CS1, GPIO_FN_EX_CS2,
+	GPIO_FN_EX_CS3, GPIO_FN_EX_CS4, GPIO_FN_EX_CS5, GPIO_FN_BS,
+	GPIO_FN_RD, GPIO_FN_RD_WR, GPIO_FN_WE0, GPIO_FN_WE1, GPIO_FN_EX_WAIT0,
+	GPIO_FN_IRQ0, GPIO_FN_IRQ1, GPIO_FN_IRQ2, GPIO_FN_IRQ3, GPIO_FN_CS0,
+
+	GPIO_FN_VI0_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_VSYNC,
+	GPIO_FN_VI0_D0_B0_C0, GPIO_FN_VI0_D1_B1_C1, GPIO_FN_VI0_D2_B2_C2, GPIO_FN_VI0_D3_B3_C3,
+	GPIO_FN_VI0_D4_B4_C4, GPIO_FN_VI0_D5_B5_C5, GPIO_FN_VI0_D6_B6_C6, GPIO_FN_VI0_D7_B7_C7,
+	GPIO_FN_VI0_D8_G0_Y0, GPIO_FN_VI0_D9_G1_Y1, GPIO_FN_VI0_D10_G2_Y2, GPIO_FN_VI0_D11_G3_Y3,
+	GPIO_FN_VI0_FIELD,
+
+	GPIO_FN_VI1_CLK, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_HSYNC,
+	GPIO_FN_VI1_VSYNC, GPIO_FN_VI1_D0_B0_C0, GPIO_FN_VI1_D1_B1_C1,
+	GPIO_FN_VI1_D2_B2_C2, GPIO_FN_VI1_D3_B3_C3, GPIO_FN_VI1_D4_B4_C4,
+	GPIO_FN_VI1_D5_B5_C5, GPIO_FN_VI1_D6_B6_C6, GPIO_FN_VI1_D7_B7_C7,
+	GPIO_FN_VI1_D8_G0_Y0, GPIO_FN_VI1_D9_G1_Y1, GPIO_FN_VI1_D10_G2_Y2,
+	GPIO_FN_VI1_D11_G3_Y3, GPIO_FN_VI1_FIELD,
+
+	GPIO_FN_VI3_D10_Y2, GPIO_FN_VI3_FIELD,
+
+	GPIO_FN_VI4_CLK,
+
+	GPIO_FN_VI5_CLK, GPIO_FN_VI5_D9_Y1, GPIO_FN_VI5_D10_Y2, GPIO_FN_VI5_D11_Y3, GPIO_FN_VI5_FIELD,
+
+	GPIO_FN_HRTS0, GPIO_FN_HCTS1, GPIO_FN_SCK0, GPIO_FN_CTS0, GPIO_FN_RTS0, GPIO_FN_TX0,
+	GPIO_FN_RX0, GPIO_FN_SCK1, GPIO_FN_CTS1, GPIO_FN_RTS1, GPIO_FN_TX1, GPIO_FN_RX1,
+	GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_TX, GPIO_FN_CAN0_RX,
+	GPIO_FN_CAN_CLK, GPIO_FN_CAN1_TX, GPIO_FN_CAN1_RX,
+
+	GPIO_FN_SD0_CLK, GPIO_FN_SD0_CMD, GPIO_FN_SD0_DAT0,
+	GPIO_FN_SD0_DAT1, GPIO_FN_SD0_DAT2, GPIO_FN_SD0_DAT3,
+	GPIO_FN_SD0_CD, GPIO_FN_SD0_WP, GPIO_FN_ADICLK,
+	GPIO_FN_ADICS_SAMP, GPIO_FN_ADIDATA, GPIO_FN_ADICHS0,
+	GPIO_FN_ADICHS1, GPIO_FN_ADICHS2, GPIO_FN_AVS1, GPIO_FN_AVS2,
+
+	GPIO_FN_DU0_DR0_DATA0, GPIO_FN_DU0_DR1_DATA1, GPIO_FN_DU0_DR2_Y4_DATA2,
+	GPIO_FN_DU0_DR3_Y5_DATA3, GPIO_FN_DU0_DR4_Y6_DATA4, GPIO_FN_DU0_DR5_Y7_DATA5,
+	GPIO_FN_DU0_DR6_Y8_DATA6, GPIO_FN_DU0_DR7_Y9_DATA7, GPIO_FN_DU0_DG0_DATA8,
+	GPIO_FN_DU0_DG1_DATA9, GPIO_FN_DU0_DG2_C6_DATA10, GPIO_FN_DU0_DG3_C7_DATA11,
+	GPIO_FN_DU0_DG4_Y0_DATA12, GPIO_FN_DU0_DG5_Y1_DATA13, GPIO_FN_DU0_DG6_Y2_DATA14,
+	GPIO_FN_DU0_DG7_Y3_DATA15, GPIO_FN_DU0_DB0, GPIO_FN_DU0_DB1,
+	GPIO_FN_DU0_DB2_C0, GPIO_FN_DU0_DB3_C1, GPIO_FN_DU0_DB4_C2,
+	GPIO_FN_DU0_DB5_C3, GPIO_FN_DU0_DB6_C4, GPIO_FN_DU0_DB7_C5,
+
+	GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_DU0_EXVSYNC_DU0_VSYNC,
+	GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_DU0_DISP, GPIO_FN_DU0_CDE,
+	GPIO_FN_DU1_DR2_Y4_DATA0, GPIO_FN_DU1_DR3_Y5_DATA1, GPIO_FN_DU1_DR4_Y6_DATA2,
+	GPIO_FN_DU1_DR5_Y7_DATA3, GPIO_FN_DU1_DR6_DATA4, GPIO_FN_DU1_DR7_DATA5,
+	GPIO_FN_DU1_DG2_C6_DATA6, GPIO_FN_DU1_DG3_C7_DATA7, GPIO_FN_DU1_DG4_Y0_DATA8,
+	GPIO_FN_DU1_DG5_Y1_DATA9, GPIO_FN_DU1_DG6_Y2_DATA10, GPIO_FN_DU1_DG7_Y3_DATA11,
+	GPIO_FN_A20, GPIO_FN_MOSI_IO0, GPIO_FN_A21, GPIO_FN_MISO_IO1, GPIO_FN_A22, GPIO_FN_IO2,
+	GPIO_FN_A23, GPIO_FN_IO3, GPIO_FN_A24, GPIO_FN_SPCLK, GPIO_FN_A25, GPIO_FN_SSL,
+
+	GPIO_FN_VI2_CLK, GPIO_FN_AVB_RX_CLK, GPIO_FN_VI2_CLKENB, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_VI2_HSYNC, GPIO_FN_AVB_RXD0, GPIO_FN_VI2_VSYNC, GPIO_FN_AVB_RXD1,
+	GPIO_FN_VI2_D0_C0, GPIO_FN_AVB_RXD2, GPIO_FN_VI2_D1_C1, GPIO_FN_AVB_RXD3,
+	GPIO_FN_VI2_D2_C2, GPIO_FN_AVB_RXD4, GPIO_FN_VI2_D3_C3, GPIO_FN_AVB_RXD5,
+	GPIO_FN_VI2_D4_C4, GPIO_FN_AVB_RXD6, GPIO_FN_VI2_D5_C5, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI2_D6_C6, GPIO_FN_AVB_RX_ER, GPIO_FN_VI2_D7_C7, GPIO_FN_AVB_COL,
+	GPIO_FN_VI2_D8_Y0, GPIO_FN_AVB_TXD3, GPIO_FN_VI2_D9_Y1, GPIO_FN_AVB_TX_EN,
+	GPIO_FN_VI2_D10_Y2, GPIO_FN_AVB_TXD0, GPIO_FN_VI2_D11_Y3, GPIO_FN_AVB_TXD1,
+	GPIO_FN_VI2_FIELD, GPIO_FN_AVB_TXD2,
+
+	GPIO_FN_VI3_CLK, GPIO_FN_AVB_TX_CLK, GPIO_FN_VI3_CLKENB, GPIO_FN_AVB_TXD4,
+	GPIO_FN_VI3_HSYNC, GPIO_FN_AVB_TXD5, GPIO_FN_VI3_VSYNC, GPIO_FN_AVB_TXD6,
+	GPIO_FN_VI3_D0_C0, GPIO_FN_AVB_TXD7, GPIO_FN_VI3_D1_C1, GPIO_FN_AVB_TX_ER,
+	GPIO_FN_VI3_D2_C2, GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI3_D3_C3, GPIO_FN_AVB_MDC,
+	GPIO_FN_VI3_D4_C4, GPIO_FN_AVB_MDIO, GPIO_FN_VI3_D5_C5, GPIO_FN_AVB_LINK,
+	GPIO_FN_VI3_D6_C6, GPIO_FN_AVB_MAGIC, GPIO_FN_VI3_D7_C7, GPIO_FN_AVB_PHY_INT,
+	GPIO_FN_VI3_D8_Y0, GPIO_FN_AVB_CRS, GPIO_FN_VI3_D9_Y1, GPIO_FN_AVB_GTXREFCLK,
+	GPIO_FN_VI3_D11_Y3,
+
+	GPIO_FN_VI4_CLKENB, GPIO_FN_VI0_D12_G4_Y4, GPIO_FN_VI4_HSYNC, GPIO_FN_VI0_D13_G5_Y5,
+	GPIO_FN_VI4_VSYNC, GPIO_FN_VI0_D14_G6_Y6, GPIO_FN_VI4_D0_C0, GPIO_FN_VI0_D15_G7_Y7,
+	GPIO_FN_VI4_D1_C1, GPIO_FN_VI0_D16_R0, GPIO_FN_VI1_D12_G4_Y4_0,
+	GPIO_FN_VI4_D2_C2, GPIO_FN_VI0_D17_R1, GPIO_FN_VI1_D13_G5_Y5_0,
+	GPIO_FN_VI4_D3_C3, GPIO_FN_VI0_D18_R2, GPIO_FN_VI1_D14_G6_Y6_0,
+	GPIO_FN_VI4_D4_C4, GPIO_FN_VI0_D19_R3, GPIO_FN_VI1_D15_G7_Y7_0,
+	GPIO_FN_VI4_D5_C5, GPIO_FN_VI0_D20_R4, GPIO_FN_VI2_D12_Y4,
+	GPIO_FN_VI4_D6_C6, GPIO_FN_VI0_D21_R5, GPIO_FN_VI2_D13_Y5,
+	GPIO_FN_VI4_D7_C7, GPIO_FN_VI0_D22_R6, GPIO_FN_VI2_D14_Y6,
+	GPIO_FN_VI4_D8_Y0, GPIO_FN_VI0_D23_R7, GPIO_FN_VI2_D15_Y7,
+	GPIO_FN_VI4_D9_Y1, GPIO_FN_VI3_D12_Y4, GPIO_FN_VI4_D10_Y2, GPIO_FN_VI3_D13_Y5,
+	GPIO_FN_VI4_D11_Y3, GPIO_FN_VI3_D14_Y6, GPIO_FN_VI4_FIELD, GPIO_FN_VI3_D15_Y7,
+
+	GPIO_FN_VI5_CLKENB, GPIO_FN_VI1_D12_G4_Y4_1, GPIO_FN_VI5_HSYNC, GPIO_FN_VI1_D13_G5_Y5_1,
+	GPIO_FN_VI5_VSYNC, GPIO_FN_VI1_D14_G6_Y6_1, GPIO_FN_VI5_D0_C0, GPIO_FN_VI1_D15_G7_Y7_1,
+	GPIO_FN_VI5_D1_C1, GPIO_FN_VI1_D16_R0, GPIO_FN_VI5_D2_C2, GPIO_FN_VI1_D17_R1,
+	GPIO_FN_VI5_D3_C3, GPIO_FN_VI1_D18_R2, GPIO_FN_VI5_D4_C4, GPIO_FN_VI1_D19_R3,
+	GPIO_FN_VI5_D5_C5, GPIO_FN_VI1_D20_R4, GPIO_FN_VI5_D6_C6, GPIO_FN_VI1_D21_R5,
+	GPIO_FN_VI5_D7_C7, GPIO_FN_VI1_D22_R6, GPIO_FN_VI5_D8_Y0, GPIO_FN_VI1_D23_R7,
+
+	GPIO_FN_MSIOF0_SCK, GPIO_FN_HSCK0, GPIO_FN_MSIOF0_SYNC, GPIO_FN_HCTS0,
+	GPIO_FN_MSIOF0_TXD, GPIO_FN_HTX0, GPIO_FN_MSIOF0_RXD, GPIO_FN_HRX0,
+	GPIO_FN_MSIOF1_SCK, GPIO_FN_HSCK1, GPIO_FN_MSIOF1_SYNC, GPIO_FN_HRTS1,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_HTX1, GPIO_FN_MSIOF1_RXD, GPIO_FN_HRX1,
+	GPIO_FN_DRACK0, GPIO_FN_SCK2, GPIO_FN_DACK0, GPIO_FN_TX2,
+	GPIO_FN_DREQ0, GPIO_FN_RX2, GPIO_FN_DACK1, GPIO_FN_SCK3,
+	GPIO_FN_TX3, GPIO_FN_DREQ1, GPIO_FN_RX3,
+
+	GPIO_FN_PWM0, GPIO_FN_TCLK1, GPIO_FN_FSO_CFE_0,
+	GPIO_FN_PWM1, GPIO_FN_TCLK2, GPIO_FN_FSO_CFE_1,
+	GPIO_FN_PWM2, GPIO_FN_TCLK3, GPIO_FN_FSO_TOE,
+	GPIO_FN_PWM3, GPIO_FN_PWM4, GPIO_FN_SSI_SCK3, GPIO_FN_TPU0TO0,
+	GPIO_FN_SSI_WS3, GPIO_FN_TPU0TO1, GPIO_FN_SSI_SDATA3, GPIO_FN_TPU0TO2,
+	GPIO_FN_SSI_SCK4, GPIO_FN_TPU0TO3, GPIO_FN_SSI_WS4,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_AUDIO_CLKOUT,
+	GPIO_FN_AUDIO_CLKA, GPIO_FN_AUDIO_CLKB,
+};
+
+#endif /* __ASM_R8A7792_GPIO_H__ */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-rmobile/include/mach/r8a7792.h
new file mode 100644
index 00000000000..be57d3c788d
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7792.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7792.h
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+*/
+
+#ifndef __ASM_ARCH_R8A7792_H
+#define __ASM_ARCH_R8A7792_H
+
+#include "rcar-base.h"
+
+/* SH-I2C */
+#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
+#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00400801
+#define MSTP1_BITS	0x9B6F987F
+#define MSTP2_BITS	0x108CE100
+#define MSTP3_BITS	0x20004010
+#define MSTP4_BITS	0x80000184
+#define MSTP5_BITS	0x44C00004
+#define MSTP7_BITS	0x01BF0000
+#define MSTP8_BITS	0x1FE01FB0
+#define MSTP9_BITS	0xFE2BFFB2
+#define MSTP10_BITS	0x00001820
+#define MSTP11_BITS	0x00000008
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1
+
+#endif /* __ASM_ARCH_R8A7792_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h
index f9a29fc144f..f9a29fc144f 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7793.h b/arch/arm/mach-rmobile/include/mach/r8a7793.h
index 3efc62a1a90..3efc62a1a90 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7793.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7793.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h
index 8a002a89187..8a002a89187 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7794.h b/arch/arm/mach-rmobile/include/mach/r8a7794.h
index ea7dc4c0730..ea7dc4c0730 100644
--- a/arch/arm/include/asm/arch-rmobile/r8a7794.h
+++ b/arch/arm/mach-rmobile/include/mach/r8a7794.h
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
new file mode 100644
index 00000000000..63e156da273
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7795-gpio.h
@@ -0,0 +1,988 @@
+/*
+ * arch/arm/include/asm/arch-rcar_gen3/r8a7795-gpio.h
+ *	This file defines pin function control of gpio.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __ASM_R8A7795_GPIO_H__
+#define __ASM_R8A7795_GPIO_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+	GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+	GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
+	GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+
+	/* GPSR0 */
+	GPIO_GFN_D15,
+	GPIO_GFN_D14,
+	GPIO_GFN_D13,
+	GPIO_GFN_D12,
+	GPIO_GFN_D11,
+	GPIO_GFN_D10,
+	GPIO_GFN_D9,
+	GPIO_GFN_D8,
+	GPIO_GFN_D7,
+	GPIO_GFN_D6,
+	GPIO_GFN_D5,
+	GPIO_GFN_D4,
+	GPIO_GFN_D3,
+	GPIO_GFN_D2,
+	GPIO_GFN_D1,
+	GPIO_GFN_D0,
+
+	/* GPSR1 */
+	GPIO_GFN_EX_WAIT0_A,
+	GPIO_GFN_WE1x,
+	GPIO_GFN_WE0x,
+	GPIO_GFN_RD_WRx,
+	GPIO_GFN_RDx,
+	GPIO_GFN_BSx,
+	GPIO_GFN_CS1x_A26,
+	GPIO_GFN_CS0x,
+	GPIO_GFN_A19,
+	GPIO_GFN_A18,
+	GPIO_GFN_A17,
+	GPIO_GFN_A16,
+	GPIO_GFN_A15,
+	GPIO_GFN_A14,
+	GPIO_GFN_A13,
+	GPIO_GFN_A12,
+	GPIO_GFN_A11,
+	GPIO_GFN_A10,
+	GPIO_GFN_A9,
+	GPIO_GFN_A8,
+	GPIO_GFN_A7,
+	GPIO_GFN_A6,
+	GPIO_GFN_A5,
+	GPIO_GFN_A4,
+	GPIO_GFN_A3,
+	GPIO_GFN_A2,
+	GPIO_GFN_A1,
+	GPIO_GFN_A0,
+
+	/* GPSR2 */
+	GPIO_GFN_AVB_AVTP_CAPTURE_A,
+	GPIO_GFN_AVB_AVTP_MATCH_A,
+	GPIO_GFN_AVB_LINK,
+	GPIO_GFN_AVB_PHY_INT,
+	GPIO_GFN_AVB_MAGIC,
+	GPIO_GFN_AVB_MDC,
+	GPIO_GFN_PWM2_A,
+	GPIO_GFN_PWM1_A,
+	GPIO_GFN_PWM0,
+	GPIO_GFN_IRQ5,
+	GPIO_GFN_IRQ4,
+	GPIO_GFN_IRQ3,
+	GPIO_GFN_IRQ2,
+	GPIO_GFN_IRQ1,
+	GPIO_GFN_IRQ0,
+
+	/* GPSR3 */
+	GPIO_GFN_SD1_WP,
+	GPIO_GFN_SD1_CD,
+	GPIO_GFN_SD0_WP,
+	GPIO_GFN_SD0_CD,
+	GPIO_GFN_SD1_DAT3,
+	GPIO_GFN_SD1_DAT2,
+	GPIO_GFN_SD1_DAT1,
+	GPIO_GFN_SD1_DAT0,
+	GPIO_GFN_SD1_CMD,
+	GPIO_GFN_SD1_CLK,
+	GPIO_GFN_SD0_DAT3,
+	GPIO_GFN_SD0_DAT2,
+	GPIO_GFN_SD0_DAT1,
+	GPIO_GFN_SD0_DAT0,
+	GPIO_GFN_SD0_CMD,
+	GPIO_GFN_SD0_CLK,
+
+	/* GPSR4 */
+	GPIO_FN_SD3_DS,
+	GPIO_GFN_SD3_DAT7,
+	GPIO_GFN_SD3_DAT6,
+	GPIO_GFN_SD3_DAT5,
+	GPIO_GFN_SD3_DAT4,
+	GPIO_FN_SD3_DAT3,
+	GPIO_FN_SD3_DAT2,
+	GPIO_FN_SD3_DAT1,
+	GPIO_FN_SD3_DAT0,
+	GPIO_FN_SD3_CMD,
+	GPIO_FN_SD3_CLK,
+	GPIO_GFN_SD2_DS,
+	GPIO_GFN_SD2_DAT3,
+	GPIO_GFN_SD2_DAT2,
+	GPIO_GFN_SD2_DAT1,
+	GPIO_GFN_SD2_DAT0,
+	GPIO_FN_SD2_CMD,
+	GPIO_GFN_SD2_CLK,
+
+	/* GPSR5 */
+	GPIO_GFN_MLB_DAT,
+	GPIO_GFN_MLB_SIG,
+	GPIO_GFN_MLB_CLK,
+	GPIO_FN_MSIOF0_RXD,
+	GPIO_GFN_MSIOF0_SS2,
+	GPIO_FN_MSIOF0_TXD,
+	GPIO_GFN_MSIOF0_SS1,
+	GPIO_GFN_MSIOF0_SYNC,
+	GPIO_FN_MSIOF0_SCK,
+	GPIO_GFN_HRTS0x,
+	GPIO_GFN_HCTS0x,
+	GPIO_GFN_HTX0,
+	GPIO_GFN_HRX0,
+	GPIO_GFN_HSCK0,
+	GPIO_GFN_RX2_A,
+	GPIO_GFN_TX2_A,
+	GPIO_GFN_SCK2,
+	GPIO_GFN_RTS1x_TANS,
+	GPIO_GFN_CTS1x,
+	GPIO_GFN_TX1_A,
+	GPIO_GFN_RX1_A,
+	GPIO_GFN_RTS0x_TANS,
+	GPIO_GFN_CTS0x,
+	GPIO_GFN_TX0,
+	GPIO_GFN_RX0,
+	GPIO_GFN_SCK0,
+
+	/* GPSR6 */
+	GPIO_GFN_USB31_OVC,
+	GPIO_GFN_USB31_PWEN,
+	GPIO_GFN_USB30_OVC,
+	GPIO_GFN_USB30_PWEN,
+	GPIO_GFN_USB1_OVC,
+	GPIO_GFN_USB1_PWEN,
+	GPIO_GFN_USB0_OVC,
+	GPIO_GFN_USB0_PWEN,
+	GPIO_GFN_AUDIO_CLKB_B,
+	GPIO_GFN_AUDIO_CLKA_A,
+	GPIO_GFN_SSI_SDATA9_A,
+	GPIO_GFN_SSI_SDATA8,
+	GPIO_GFN_SSI_SDATA7,
+	GPIO_GFN_SSI_WS78,
+	GPIO_GFN_SSI_SCK78,
+	GPIO_GFN_SSI_SDATA6,
+	GPIO_GFN_SSI_WS6,
+	GPIO_GFN_SSI_SCK6,
+	GPIO_FN_SSI_SDATA5,
+	GPIO_FN_SSI_WS5,
+	GPIO_FN_SSI_SCK5,
+	GPIO_GFN_SSI_SDATA4,
+	GPIO_GFN_SSI_WS4,
+	GPIO_GFN_SSI_SCK4,
+	GPIO_GFN_SSI_SDATA3,
+	GPIO_GFN_SSI_WS34,
+	GPIO_GFN_SSI_SCK34,
+	GPIO_GFN_SSI_SDATA2_A,
+	GPIO_GFN_SSI_SDATA1_A,
+	GPIO_GFN_SSI_SDATA0,
+	GPIO_GFN_SSI_WS0129,
+	GPIO_GFN_SSI_SCK0129,
+
+	/* GPSR7 */
+	GPIO_FN_HDMI1_CEC,
+	GPIO_FN_HDMI0_CEC,
+	GPIO_FN_AVS2,
+	GPIO_FN_AVS1,
+
+	/* IPSR0 */
+	GPIO_IFN_AVB_MDC,
+	GPIO_FN_MSIOF2_SS2_C,
+	GPIO_IFN_AVB_MAGIC,
+	GPIO_FN_MSIOF2_S1_C,
+	GPIO_FN_SCK4_A,
+	GPIO_IFN_AVB_PHY_INT,
+	GPIO_FN_MSIOF2_SYNC_C,
+	GPIO_FN_RX4_A,
+	GPIO_IFN_AVB_LINK,
+	GPIO_FN_MSIOF2_SCK_C,
+	GPIO_FN_TX4_A,
+	GPIO_IFN_AVB_AVTP_MATCH_A,
+	GPIO_FN_MSIOF2_RXD_C,
+	GPIO_FN_CTS4x_A,
+	GPIO_IFN_AVB_AVTP_CAPTURE_A,
+	GPIO_FN_MSIOF2_TXD_C,
+	GPIO_FN_RTS4x_TANS_A,
+	GPIO_IFN_IRQ0,
+	GPIO_FN_QPOLB,
+	GPIO_FN_DU_CDE,
+	GPIO_FN_VI4_DATA0_B,
+	GPIO_FN_CAN0_TX_B,
+	GPIO_FN_CANFD0_TX_B,
+	GPIO_IFN_IRQ1,
+	GPIO_FN_QPOLA,
+	GPIO_FN_DU_DISP,
+	GPIO_FN_VI4_DATA1_B,
+	GPIO_FN_CAN0_RX_B,
+	GPIO_FN_CANFD0_RX_B,
+
+	/* IPSR1 */
+	GPIO_IFN_IRQ2,
+	GPIO_FN_QCPV_QDE,
+	GPIO_FN_DU_EXODDF_DU_ODDF_DISP_CDE,
+	GPIO_FN_VI4_DATA2_B,
+	GPIO_FN_PWM3_B,
+	GPIO_IFN_IRQ3,
+	GPIO_FN_QSTVB_QVE,
+	GPIO_FN_A25,
+	GPIO_FN_DU_DOTCLKOUT1,
+	GPIO_FN_VI4_DATA3_B,
+	GPIO_FN_PWM4_B,
+	GPIO_IFN_IRQ4,
+	GPIO_FN_QSTH_QHS,
+	GPIO_FN_A24,
+	GPIO_FN_DU_EXHSYNC_DU_HSYNC,
+	GPIO_FN_VI4_DATA4_B,
+	GPIO_FN_PWM5_B,
+	GPIO_IFN_IRQ5,
+	GPIO_FN_QSTB_QHE,
+	GPIO_FN_A23,
+	GPIO_FN_DU_EXVSYNC_DU_VSYNC,
+	GPIO_FN_VI4_DATA5_B,
+	GPIO_FN_PWM6_B,
+	GPIO_IFN_PWM0,
+	GPIO_FN_AVB_AVTP_PPS,
+	GPIO_FN_A22,
+	GPIO_FN_VI4_DATA6_B,
+	GPIO_FN_IECLK_B,
+	GPIO_IFN_PWM1_A,
+	GPIO_FN_A21,
+	GPIO_FN_HRX3_D,
+	GPIO_FN_VI4_DATA7_B,
+	GPIO_FN_IERX_B,
+	GPIO_IFN_PWM2_A,
+	GPIO_FN_PWMFSW0,
+	GPIO_FN_A20,
+	GPIO_FN_HTX3_D,
+	GPIO_FN_IETX_B,
+	GPIO_IFN_A0,
+	GPIO_FN_LCDOUT16,
+	GPIO_FN_MSIOF3_SYNC_B,
+	GPIO_FN_VI4_DATA8,
+	GPIO_FN_DU_DB0,
+	GPIO_FN_PWM3_A,
+
+	/* IPSR2 */
+	GPIO_IFN_A1,
+	GPIO_FN_LCDOUT17,
+	GPIO_FN_MSIOF3_TXD_B,
+	GPIO_FN_VI4_DATA9,
+	GPIO_FN_DU_DB1,
+	GPIO_FN_PWM4_A,
+	GPIO_IFN_A2,
+	GPIO_FN_LCDOUT18,
+	GPIO_FN_MSIOF3_SCK_B,
+	GPIO_FN_VI4_DATA10,
+	GPIO_FN_DU_DB2,
+	GPIO_FN_PWM5_A,
+	GPIO_IFN_A3,
+	GPIO_FN_LCDOUT19,
+	GPIO_FN_MSIOF3_RXD_B,
+	GPIO_FN_VI4_DATA11,
+	GPIO_FN_DU_DB3,
+	GPIO_FN_PWM6_A,
+	GPIO_IFN_A4,
+	GPIO_FN_LCDOUT20,
+	GPIO_FN_MSIOF3_SS1_B,
+	GPIO_FN_VI4_DATA12,
+	GPIO_FN_VI5_DATA12,
+	GPIO_FN_DU_DB4,
+	GPIO_IFN_A5,
+	GPIO_FN_LCDOUT21,
+	GPIO_FN_MSIOF3_SS2_B,
+	GPIO_FN_SCK4_B,
+	GPIO_FN_VI4_DATA13,
+	GPIO_FN_VI5_DATA13,
+	GPIO_FN_DU_DB5,
+	GPIO_IFN_A6,
+	GPIO_FN_LCDOUT22,
+	GPIO_FN_MSIOF2_SS1_A,
+	GPIO_FN_RX4_B,
+	GPIO_FN_VI4_DATA14,
+	GPIO_FN_VI5_DATA14,
+	GPIO_FN_DU_DB6,
+	GPIO_IFN_A7,
+	GPIO_FN_LCDOUT23,
+	GPIO_FN_MSIOF2_SS2_A,
+	GPIO_FN_TX4_B,
+	GPIO_FN_VI4_DATA15,
+	GPIO_FN_V15_DATA15,
+	GPIO_FN_DU_DB7,
+	GPIO_IFN_A8,
+	GPIO_FN_RX3_B,
+	GPIO_FN_MSIOF2_SYNC_A,
+	GPIO_FN_HRX4_B,
+	GPIO_FN_SDA6_A,
+	GPIO_FN_AVB_AVTP_MATCH_B,
+	GPIO_FN_PWM1_B,
+
+	/* IPSR3 */
+	GPIO_IFN_A9,
+	GPIO_FN_MSIOF2_SCK_A,
+	GPIO_FN_CTS4x_B,
+	GPIO_FN_VI5_VSYNCx,
+	GPIO_IFN_A10,
+	GPIO_FN_MSIOF2_RXD_A,
+	GPIO_FN_RTS4n_TANS_B,
+	GPIO_FN_VI5_HSYNCx,
+	GPIO_IFN_A11,
+	GPIO_FN_TX3_B,
+	GPIO_FN_MSIOF2_TXD_A,
+	GPIO_FN_HTX4_B,
+	GPIO_FN_HSCK4,
+	GPIO_FN_VI5_FIELD,
+	GPIO_FN_SCL6_A,
+	GPIO_FN_AVB_AVTP_CAPTURE_B,
+	GPIO_FN_PWM2_B,
+	GPIO_FN_SPV_EVEN,
+	GPIO_IFN_A12,
+	GPIO_FN_LCDOUT12,
+	GPIO_FN_MSIOF3_SCK_C,
+	GPIO_FN_HRX4_A,
+	GPIO_FN_VI5_DATA8,
+	GPIO_FN_DU_DG4,
+	GPIO_IFN_A13,
+	GPIO_FN_LCDOUT13,
+	GPIO_FN_MSIOF3_SYNC_C,
+	GPIO_FN_HTX4_A,
+	GPIO_FN_VI5_DATA9,
+	GPIO_FN_DU_DG5,
+	GPIO_IFN_A14,
+	GPIO_FN_LCDOUT14,
+	GPIO_FN_MSIOF3_RXD_C,
+	GPIO_FN_HCTS4x,
+	GPIO_FN_VI5_DATA10,
+	GPIO_FN_DU_DG6,
+	GPIO_IFN_A15,
+	GPIO_FN_LCDOUT15,
+	GPIO_FN_MSIOF3_TXD_C,
+	GPIO_FN_HRTS4x,
+	GPIO_FN_VI5_DATA11,
+	GPIO_FN_DU_DG7,
+	GPIO_IFN_A16,
+	GPIO_FN_LCDOUT8,
+	GPIO_FN_VI4_FIELD,
+	GPIO_FN_DU_DG0,
+
+	/* IPSR4 */
+	GPIO_IFN_A17,
+	GPIO_FN_LCDOUT9,
+	GPIO_FN_VI4_VSYNCx,
+	GPIO_FN_DU_DG1,
+	GPIO_IFN_A18,
+	GPIO_FN_LCDOUT10,
+	GPIO_FN_VI4_HSYNCx,
+	GPIO_FN_DU_DG2,
+	GPIO_IFN_A19,
+	GPIO_FN_LCDOUT11,
+	GPIO_FN_VI4_CLKENB,
+	GPIO_FN_DU_DG3,
+	GPIO_IFN_CS0x,
+	GPIO_FN_VI5_CLKENB,
+	GPIO_IFN_CS1x_A26,
+	GPIO_FN_VI5_CLK,
+	GPIO_FN_EX_WAIT0_B,
+	GPIO_IFN_BSx,
+	GPIO_FN_QSTVA_QVS,
+	GPIO_FN_MSIOF3_SCK_D,
+	GPIO_FN_SCK3,
+	GPIO_FN_HSCK3,
+	GPIO_FN_CAN1_TX,
+	GPIO_FN_CANFD1_TX,
+	GPIO_FN_IETX_A,
+	GPIO_IFN_RDx,
+	GPIO_FN_MSIOF3_SYNC_D,
+	GPIO_FN_RX3_A,
+	GPIO_FN_HRX3_A,
+	GPIO_FN_CAN0_TX_A,
+	GPIO_FN_CANFD0_TX_A,
+	GPIO_IFN_RD_WRx,
+	GPIO_FN_MSIOF3_RXD_D,
+	GPIO_FN_TX3_A,
+	GPIO_FN_HTX3_A,
+	GPIO_FN_CAN0_RX_A,
+	GPIO_FN_CANFD0_RX_A,
+
+	/* IPSR5 */
+	GPIO_IFN_WE0x,
+	GPIO_FN_MSIIOF3_TXD_D,
+	GPIO_FN_CTS3x,
+	GPIO_FN_HCTS3x,
+	GPIO_FN_SCL6_B,
+	GPIO_FN_CAN_CLK,
+	GPIO_FN_IECLK_A,
+	GPIO_IFN_WE1x,
+	GPIO_FN_MSIOF3_SS1_D,
+	GPIO_FN_RTS3x_TANS,
+	GPIO_FN_HRTS3x,
+	GPIO_FN_SDA6_B,
+	GPIO_FN_CAN1_RX,
+	GPIO_FN_CANFD1_RX,
+	GPIO_FN_IERX_A,
+	GPIO_IFN_EX_WAIT0_A,
+	GPIO_FN_QCLK,
+	GPIO_FN_VI4_CLK,
+	GPIO_FN_DU_DOTCLKOUT0,
+	GPIO_IFN_D0,
+	GPIO_FN_MSIOF2_SS1_B,
+	GPIO_FN_MSIOF3_SCK_A,
+	GPIO_FN_VI4_DATA16,
+	GPIO_FN_VI5_DATA0,
+	GPIO_IFN_D1,
+	GPIO_FN_MSIOF2_SS2_B,
+	GPIO_FN_MSIOF3_SYNC_A,
+	GPIO_FN_VI4_DATA17,
+	GPIO_FN_VI5_DATA1,
+	GPIO_IFN_D2,
+	GPIO_FN_MSIOF3_RXD_A,
+	GPIO_FN_VI4_DATA18,
+	GPIO_FN_VI5_DATA2,
+	GPIO_IFN_D3,
+	GPIO_FN_MSIOF3_TXD_A,
+	GPIO_FN_VI4_DATA19,
+	GPIO_FN_VI5_DATA3,
+	GPIO_IFN_D4,
+	GPIO_FN_MSIOF2_SCK_B,
+	GPIO_FN_VI4_DATA20,
+	GPIO_FN_VI5_DATA4,
+
+	/* IPSR6 */
+	GPIO_IFN_D5,
+	GPIO_FN_MSIOF2_SYNC_B,
+	GPIO_FN_VI4_DATA21,
+	GPIO_FN_VI5_DATA5,
+	GPIO_IFN_D6,
+	GPIO_FN_MSIOF2_RXD_B,
+	GPIO_FN_VI4_DATA22,
+	GPIO_FN_VI5_DATA6,
+	GPIO_IFN_D7,
+	GPIO_FN_MSIOF2_TXD_B,
+	GPIO_FN_VI4_DATA23,
+	GPIO_FN_VI5_DATA7,
+	GPIO_IFN_D8,
+	GPIO_FN_LCDOUT0,
+	GPIO_FN_MSIOF2_SCK_D,
+	GPIO_FN_SCK4_C,
+	GPIO_FN_VI4_DATA0_A,
+	GPIO_FN_DU_DR0,
+	GPIO_IFN_D9,
+	GPIO_FN_LCDOUT1,
+	GPIO_FN_MSIOF2_SYNC_D,
+	GPIO_FN_VI4_DATA1_A,
+	GPIO_FN_DU_DR1,
+	GPIO_IFN_D10,
+	GPIO_FN_LCDOUT2,
+	GPIO_FN_MSIOF2_RXD_D,
+	GPIO_FN_HRX3_B,
+	GPIO_FN_VI4_DATA2_A,
+	GPIO_FN_CTS4x_C,
+	GPIO_FN_DU_DR2,
+	GPIO_IFN_D11,
+	GPIO_FN_LCDOUT3,
+	GPIO_FN_MSIOF2_TXD_D,
+	GPIO_FN_HTX3_B,
+	GPIO_FN_VI4_DATA3_A,
+	GPIO_FN_RTS4x_TANS_C,
+	GPIO_FN_DU_DR3,
+	GPIO_IFN_D12,
+	GPIO_FN_LCDOUT4,
+	GPIO_FN_MSIOF2_SS1_D,
+	GPIO_FN_RX4_C,
+	GPIO_FN_VI4_DATA4_A,
+	GPIO_FN_DU_DR4,
+
+	/* IPSR7 */
+	GPIO_IFN_D13,
+	GPIO_FN_LCDOUT5,
+	GPIO_FN_MSIOF2_SS2_D,
+	GPIO_FN_TX4_C,
+	GPIO_FN_VI4_DATA5_A,
+	GPIO_FN_DU_DR5,
+	GPIO_IFN_D14,
+	GPIO_FN_LCDOUT6,
+	GPIO_FN_MSIOF3_SS1_A,
+	GPIO_FN_HRX3_C,
+	GPIO_FN_VI4_DATA6_A,
+	GPIO_FN_DU_DR6,
+	GPIO_FN_SCL6_C,
+	GPIO_IFN_D15,
+	GPIO_FN_LCDOUT7,
+	GPIO_FN_MSIOF3_SS2_A,
+	GPIO_FN_HTX3_C,
+	GPIO_FN_VI4_DATA7_A,
+	GPIO_FN_DU_DR7,
+	GPIO_FN_SDA6_C,
+	GPIO_FN_FSCLKST,
+	GPIO_IFN_SD0_CLK,
+	GPIO_FN_MSIOF1_SCK_E,
+	GPIO_FN_STP_OPWM_0_B,
+	GPIO_IFN_SD0_CMD,
+	GPIO_FN_MSIOF1_SYNC_E,
+	GPIO_FN_STP_IVCXO27_0_B,
+	GPIO_IFN_SD0_DAT0,
+	GPIO_FN_MSIOF1_RXD_E,
+	GPIO_FN_TS_SCK0_B,
+	GPIO_FN_STP_ISCLK_0_B,
+	GPIO_IFN_SD0_DAT1,
+	GPIO_FN_MSIOF1_TXD_E,
+	GPIO_FN_TS_SPSYNC0_B,
+	GPIO_FN_STP_ISSYNC_0_B,
+
+	/* IPSR8 */
+	GPIO_IFN_SD0_DAT2,
+	GPIO_FN_MSIOF1_SS1_E,
+	GPIO_FN_TS_SDAT0_B,
+	GPIO_FN_STP_ISD_0_B,
+	GPIO_IFN_SD0_DAT3,
+	GPIO_FN_MSIOF1_SS2_E,
+	GPIO_FN_TS_SDEN0_B,
+	GPIO_FN_STP_ISEN_0_B,
+	GPIO_IFN_SD1_CLK,
+	GPIO_FN_MSIOF1_SCK_G,
+	GPIO_FN_SIM0_CLK_A,
+
+	GPIO_IFN_SD1_CMD,
+	GPIO_FN_MSIOF1_SYNC_G,
+	GPIO_FN_SIM0_D_A,
+	GPIO_FN_STP_IVCXO27_1_B,
+
+	GPIO_IFN_SD1_DAT0,
+	GPIO_FN_SD2_DAT4,
+	GPIO_FN_MSIOF1_RXD_G,
+	GPIO_FN_TS_SCK1_B,
+	GPIO_FN_STP_ISCLK_1_B,
+
+	GPIO_IFN_SD1_DAT1,
+	GPIO_FN_SD2_DAT5,
+	GPIO_FN_MSIOF1_TXD_G,
+	GPIO_FN_TS_SPSYNC1_B,
+	GPIO_FN_STP_ISSYNC_1_B,
+
+	GPIO_IFN_SD1_DAT2,
+	GPIO_FN_SD2_DAT6,
+	GPIO_FN_MSIOF1_SS1_G,
+	GPIO_FN_TS_SDAT1_B,
+	GPIO_FN_STP_IOD_1_B,
+	GPIO_IFN_SD1_DAT3,
+	GPIO_FN_SD2_DAT7,
+	GPIO_FN_MSIOF1_SS2_G,
+	GPIO_FN_TS_SDEN1_B,
+	GPIO_FN_STP_ISEN_1_B,
+
+	/* IPSR9 */
+	GPIO_IFN_SD2_CLK,
+	GPIO_FN_SCKZ_A,
+	GPIO_IFN_SD2_DAT0,
+	GPIO_FN_MTSx_A,
+	GPIO_IFN_SD2_DAT1,
+	GPIO_FN_STMx_A,
+	GPIO_IFN_SD2_DAT2,
+	GPIO_FN_MDATA_A,
+	GPIO_IFN_SD2_DAT3,
+	GPIO_FN_SDATA_A,
+	GPIO_IFN_SD2_DS,
+	GPIO_FN_SATA_DEVSLP_B,
+	GPIO_FN_VSP_A,
+	GPIO_IFN_SD3_DAT4,
+	GPIO_FN_SD2_CD_A,
+	GPIO_IFN_SD3_DAT5,
+	GPIO_FN_SD2_WP_A,
+
+	/* IPSR10 */
+	GPIO_IFN_SD3_DAT6,
+	GPIO_FN_SD3_CD,
+	GPIO_IFN_SD3_DAT7,
+	GPIO_FN_SD3_WP,
+	GPIO_IFN_SD0_CD,
+	GPIO_FN_SCL2_B,
+	GPIO_FN_SIM0_RST_A,
+	GPIO_IFN_SD0_WP,
+	GPIO_FN_SDA2_B,
+	GPIO_IFN_SD1_CD,
+	GPIO_FN_SIM0_CLK_B,
+	GPIO_IFN_SD1_WP,
+	GPIO_FN_SIM0_D_B,
+	GPIO_IFN_SCK0,
+	GPIO_FN_HSCK1_B,
+	GPIO_FN_MSIOF1_SS2_B,
+	GPIO_FN_AUDIO_CLKC_B,
+	GPIO_FN_SDA2_A,
+	GPIO_FN_SIM0_RST_B,
+	GPIO_FN_STP_OPWM__C,
+	GPIO_FN_RIF0_CLK_B,
+	GPIO_FN_ADICHS2,
+	GPIO_IFN_RX0,
+	GPIO_FN_HRX1_B,
+	GPIO_FN_TS_SCK0_C,
+	GPIO_FN_STP_ISCLK_0_C,
+	GPIO_FN_RIF0_D0_B,
+
+	/* IPSR11 */
+	GPIO_IFN_TX0,
+	GPIO_FN_HTX1_B,
+	GPIO_FN_TS_SPSYNC0_C,
+	GPIO_FN_STP_ISSYNC_0_C,
+	GPIO_FN_RIF0_D1_B,
+	GPIO_IFN_CTS0x,
+	GPIO_FN_HCTS1x_B,
+	GPIO_FN_MSIOF1_SYNC_B,
+	GPIO_FN_TS_SPSYNC1_C,
+	GPIO_FN_STP_ISSYNC_1_C,
+	GPIO_FN_RIF1_SYNC_B,
+	GPIO_FN_AUDIO_CLKOUT_C,
+	GPIO_FN_ADICS_SAMP,
+	GPIO_IFN_RTS0x_TANS,
+	GPIO_FN_HRTS1x_B,
+	GPIO_FN_MSIOF1_SS1_B,
+	GPIO_FN_AUDIO_CLKA_B,
+	GPIO_FN_SCL2_A,
+	GPIO_FN_STP_IVCXO27_1_C,
+	GPIO_FN_RIF0_SYNC_B,
+	GPIO_FN_ADICHS1,
+	GPIO_IFN_RX1_A,
+	GPIO_FN_HRX1_A,
+	GPIO_FN_TS_SDAT0_C,
+	GPIO_FN_STP_IDS_0_C,
+	GPIO_FN_RIF1_CLK_C,
+	GPIO_IFN_TX1_A,
+	GPIO_FN_HTX1_A,
+	GPIO_FN_TS_SDEN0_C,
+	GPIO_FN_STP_ISEN_0_C,
+	GPIO_FN_RIF1_D0_C,
+	GPIO_IFN_CTS1x,
+	GPIO_FN_HCTS1x_A,
+	GPIO_FN_MSIOF1_RXD_B,
+	GPIO_FN_TS_SDEN1_C,
+	GPIO_FN_STP_ISEN_1_C,
+	GPIO_FN_RIF1_D0_B,
+	GPIO_FN_ADIDATA,
+	GPIO_IFN_RTS1x_TANS,
+	GPIO_FN_HRTS1x_A,
+	GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_TS_SDAT1_C,
+	GPIO_FN_STP_ISD_1_C,
+	GPIO_FN_RIF1_D1_B,
+	GPIO_FN_ADICHS0,
+	GPIO_IFN_SCK2,
+	GPIO_FN_SCIF_CLK_B,
+	GPIO_FN_MSIOF1_SCK_B,
+	GPIO_FN_TS_SCK1_C,
+	GPIO_FN_STP_ISCLK_1_C,
+	GPIO_FN_RIF1_CLK_B,
+	GPIO_FN_ADICLK,
+
+	/* IPSR12 */
+	GPIO_IFN_TX2_A,
+	GPIO_FN_SD2_CD_B,
+	GPIO_FN_SCL1_A,
+	GPIO_FN_RSD_CLK_B,
+	GPIO_FN_FMCLK_A,
+	GPIO_FN_RIF1_D1_C,
+	GPIO_FN_FSO_CFE_0_B,
+	GPIO_IFN_RX2_A,
+	GPIO_FN_SD2_WP_B,
+	GPIO_FN_SDA1_A,
+	GPIO_FN_RDS_DATA_B,
+	GPIO_FN_RMIN_A,
+	GPIO_FN_RIF1_SYNC_C,
+	GPIO_FN_FSO_CEF_1_B,
+	GPIO_IFN_HSCK0,
+	GPIO_FN_MSIOF1_SCK_D,
+	GPIO_FN_AUDIO_CLKB_A,
+	GPIO_FN_SSI_SDATA1_B,
+	GPIO_FN_TS_SCK0_D,
+	GPIO_FN_STP_ISCLK_0_D,
+	GPIO_FN_RIF0_CLK_C,
+	GPIO_FN_AD_CLK,
+	GPIO_IFN_HRX0,
+	GPIO_FN_MSIOF1_RXD_D,
+	GPIO_FN_SS1_SDATA2_B,
+	GPIO_FN_TS_SDEN0_D,
+	GPIO_FN_STP_ISEN_0_D,
+	GPIO_FN_RIF0_D0_C,
+	GPIO_FN_AD_DI,
+	GPIO_IFN_HTX0,
+	GPIO_FN_MSIOF1_TXD_D,
+	GPIO_FN_SSI_SDATA9_B,
+	GPIO_FN_TS_SDAT0_D,
+	GPIO_FN_STP_ISD_0_D,
+	GPIO_FN_RIF0_D1_C,
+	GPIO_FN_AD_DO,
+	GPIO_IFN_HCTS0x,
+	GPIO_FN_RX2_B,
+	GPIO_FN_MSIOF1_SYNC_D,
+	GPIO_FN_SSI_SCK9_A,
+	GPIO_FN_TS_SPSYNC0_D,
+	GPIO_FN_STP_ISSYNC_0_D,
+	GPIO_FN_RIF0_SYNC_C,
+	GPIO_FN_AUDIO_CLKOUT1_A,
+	GPIO_FN_AD_NSCx,
+	GPIO_IFN_HRTS0x,
+	GPIO_FN_TX2_B,
+	GPIO_FN_MSIOF1_SS1_D,
+	GPIO_FN_SSI_WS9_A,
+	GPIO_FN_STP_IVCXO27_0_D,
+	GPIO_FN_BPFCLK_A,
+	GPIO_FN_AUDIO_CLKOUT2_A,
+	GPIO_IFN_MSIOF0_SYNC,
+	GPIO_FN_AUDIO_CLKOUT_A,
+
+	/* IPSR13 */
+	GPIO_IFN_MSIOF0_SS1,
+	GPIO_FN_RX5,
+	GPIO_FN_AUDIO_CLKA_C,
+	GPIO_FN_SSI_SCK2_A,
+	GPIO_FN_RDS_CLK_A,
+	GPIO_FN_STP_IVCXO27_0_C,
+	GPIO_FN_AUDIO_CLKOUT3_A,
+	GPIO_FN_TCLK1_B,
+	GPIO_IFN_MSIOF0_SS2,
+	GPIO_FN_TX5,
+	GPIO_FN_MSIOF1_SS2_D,
+	GPIO_FN_AUDIO_CLKC_A,
+	GPIO_FN_SSI_WS2_A,
+	GPIO_FN_RDS_DATA_A,
+	GPIO_FN_STP_OPWM_0_D,
+	GPIO_FN_AUDIO_CLKOUT_D,
+	GPIO_FN_SPEEDIN_B,
+	GPIO_IFN_MLB_CLK,
+	GPIO_FN_MSIOF1_SCK_F,
+	GPIO_FN_SCL1_B,
+	GPIO_IFN_MLB_SIG,
+	GPIO_FN_RX1_B,
+	GPIO_FN_MSIOF1_SYNC_F,
+	GPIO_FN_SDA1_B,
+	GPIO_IFN_MLB_DAT,
+	GPIO_FN_TX1_B,
+	GPIO_FN_MSIOF1_RXD_F,
+	GPIO_IFN_SSI_SCK0129,
+	GPIO_FN_MSIOF1_TXD_F,
+	GPIO_FN_MOUT0,
+	GPIO_IFN_SSI_WS0129,
+	GPIO_FN_MSIOF1_SS1_F,
+	GPIO_FN_MOUT1,
+	GPIO_IFN_SSI_SDATA0,
+	GPIO_FN_MSIOF1_SS2_F,
+	GPIO_FN_MOUT2,
+
+	/* IPSR14 */
+	GPIO_IFN_SSI_SDATA1_A,
+	GPIO_FN_MOUT5,
+	GPIO_IFN_SSI_SDATA2_A,
+	GPIO_FN_SSI_SCK1_B,
+	GPIO_FN_MOUT6,
+	GPIO_IFN_SSI_SCK34,
+	GPIO_FN_MSIOF1_SS1_A,
+	GPIO_FN_STP_OPWM_0_A,
+	GPIO_IFN_SSI_WS34,
+	GPIO_FN_HCTS2x_A,
+	GPIO_FN_MSIOF1_SS2_A,
+	GPIO_FN_STP_IVCXO27_0_A,
+	GPIO_IFN_SSI_SDATA3,
+	GPIO_FN_HRTS2x_A,
+	GPIO_FN_MSIOF1_TXD_A,
+	GPIO_FN_TS_SCK0_A,
+	GPIO_FN_STP_ISCLK_0_A,
+	GPIO_FN_RIF0_D1_A,
+	GPIO_FN_RIF2_D0_A,
+	GPIO_IFN_SSI_SCK4,
+	GPIO_FN_HRX2_A,
+	GPIO_FN_MSIOF1_SCK_A,
+	GPIO_FN_TS_SDAT0_A,
+	GPIO_FN_STP_ISD_0_A,
+	GPIO_FN_RIF0_CLK_A,
+	GPIO_FN_RIF2_CLK_A,
+	GPIO_IFN_SSI_WS4,
+	GPIO_FN_HTX2_A,
+	GPIO_FN_MSIOF1_SYNC_A,
+	GPIO_FN_TS_SDEN0_A,
+	GPIO_FN_STP_ISEN_0_A,
+	GPIO_FN_RIF0_SYNC_A,
+	GPIO_FN_RIF2_SYNC_A,
+	GPIO_IFN_SSI_SDATA4,
+	GPIO_FN_HSCK2_A,
+	GPIO_FN_MSIOF1_RXD_A,
+	GPIO_FN_TS_SPSYNC0_A,
+	GPIO_FN_STP_ISSYNC_0_A,
+	GPIO_FN_RIF0_D0_A,
+	GPIO_FN_RIF2_D1_A,
+
+	/* IPSR15 */
+	GPIO_IFN_SSI_SCK6,
+	GPIO_FN_USB2_PWEN,
+	GPIO_FN_SIM0_RST_D,
+	GPIO_FN_RDS_CLK_C,
+	GPIO_IFN_SSI_WS6,
+	GPIO_FN_USB2_OVC,
+	GPIO_FN_SIM0_D_D,
+	GPIO_IFN_SSI_SDATA6,
+	GPIO_FN_SIM0_CLK_D,
+	GPIO_FN_RSD_DATA_C,
+	GPIO_FN_SATA_DEVSLP_A,
+	GPIO_IFN_SSI_SCK78,
+	GPIO_FN_HRX2_B,
+	GPIO_FN_MSIOF1_SCK_C,
+	GPIO_FN_TS_SCK1_A,
+	GPIO_FN_STP_ISCLK_1_A,
+	GPIO_FN_RIF1_CLK_A,
+	GPIO_FN_RIF3_CLK_A,
+	GPIO_IFN_SSI_WS78,
+	GPIO_FN_HTX2_B,
+	GPIO_FN_MSIOF1_SYNC_C,
+	GPIO_FN_TS_SDT1_A,
+	GPIO_FN_STP_ISD_1_A,
+	GPIO_FN_RIF1_SYNC_A,
+	GPIO_FN_RIF3_SYNC_A,
+	GPIO_IFN_SSI_SDATA7,
+	GPIO_FN_HCTS2x_B,
+	GPIO_FN_MSIOF1_RXD_C,
+	GPIO_FN_TS_SDEN1_A,
+	GPIO_FN_STP_IEN_1_A,
+	GPIO_FN_RIF1_D0_A,
+	GPIO_FN_RIF3_D0_A,
+	GPIO_FN_TCLK2_A,
+	GPIO_IFN_SSI_SDATA8,
+	GPIO_FN_HRTS2x_B,
+	GPIO_FN_MSIOF1_TXD_C,
+	GPIO_FN_TS_SPSYNC1_A,
+	GPIO_FN_STP_ISSYNC_1_A,
+	GPIO_FN_RIF1_D1_A,
+	GPIO_FN_EIF3_D1_A,
+	GPIO_IFN_SSI_SDATA9_A,
+	GPIO_FN_HSCK2_B,
+	GPIO_FN_MSIOF1_SS1_C,
+	GPIO_FN_HSCK1_A,
+	GPIO_FN_SSI_WS1_B,
+	GPIO_FN_SCK1,
+	GPIO_FN_STP_IVCXO27_1_A,
+	GPIO_FN_SCK5,
+
+	/* IPSR16 */
+	GPIO_IFN_AUDIO_CLKA_A,
+	GPIO_FN_CC5_OSCOUT,
+	GPIO_IFN_AUDIO_CLKB_B,
+	GPIO_FN_SCIF_CLK_A,
+	GPIO_FN_DVC_MUTE,
+	GPIO_FN_STP_IVCXO27_1_D,
+	GPIO_FN_REMOCON_A,
+	GPIO_FN_TCLK1_A,
+	GPIO_FN_VSP_B,
+	GPIO_IFN_USB0_PWEN,
+	GPIO_FN_SIM0_RST_C,
+	GPIO_FN_TS_SCK1_D,
+	GPIO_FN_STP_ISCLK_1_D,
+	GPIO_FN_BPFCLK_B,
+	GPIO_FN_RIF3_CLK_B,
+	GPIO_FN_SCKZ_B,
+	GPIO_IFN_USB0_OVC,
+	GPIO_FN_SIM0_D_C,
+	GPIO_FN_TS_SDAT1_D,
+	GPIO_FN_STP_ISD_1_D,
+	GPIO_FN_RIF3_SYNC_B,
+	GPIO_FN_VSP_C,
+	GPIO_IFN_USB1_PWEN,
+	GPIO_FN_SIM0_CLK_C,
+	GPIO_FN_SSI_SCK1_A,
+	GPIO_FN_TS_SCK0_E,
+	GPIO_FN_STP_ISCLK_0_E,
+	GPIO_FN_FMCLK_B,
+	GPIO_FN_RIF2_CLK_B,
+	GPIO_FN_MTSx_B,
+	GPIO_FN_SPEEDIN_A,
+	GPIO_FN_VSP_D,
+	GPIO_IFN_USB1_OVC,
+	GPIO_FN_MSIOF1_SS2_C,
+	GPIO_FN_SSI_WS1_A,
+	GPIO_FN_TS_SDAT0_E,
+	GPIO_FN_STP_ISD_0_E,
+	GPIO_FN_FMIN_B,
+	GPIO_FN_RIF2_SYNC_B,
+	GPIO_FN_STMx_B,
+	GPIO_FN_REMOCON_B,
+	GPIO_IFN_USB30_PWEN,
+	GPIO_FN_AUDIO_CLKOUT_B,
+	GPIO_FN_SSI_SCK2_B,
+	GPIO_FN_TS_SDEN1_D,
+	GPIO_FN_STP_ISEN_1_D,
+	GPIO_FN_STP_OPWM_0_E,
+	GPIO_FN_RIF3_D0_B,
+	GPIO_FN_MDATA_B,
+	GPIO_FN_TCLK2_B,
+	GPIO_FN_TPU0TO0,
+	GPIO_IFN_USB30_OVC,
+	GPIO_FN_AUDIO_CLKOUT1_B,
+	GPIO_FN_SSI_WS2_B,
+	GPIO_FN_TS_SPSYNC1_D,
+	GPIO_FN_STP_ISSYNC_1_D,
+	GPIO_FN_STP_IVCXO27_0_E,
+	GPIO_FN_RIF3_D1_B,
+	GPIO_FN_SDATA_B,
+	GPIO_FN_RSO_TOE_B,
+	GPIO_FN_TPU0TO1,
+
+	/* IPSR17 */
+	GPIO_IFN_USB31_PWEN,
+	GPIO_FN_AUDIO_CLKOUT2_B,
+	GPIO_FN_SI_SCK9_B,
+	GPIO_FN_TS_SDEN0_E,
+	GPIO_FN_STP_ISEN_0_E,
+	GPIO_FN_RIF2_D0_B,
+	GPIO_FN_TPU0TO2,
+	GPIO_IFN_USB31_OVC,
+	GPIO_FN_AUDIO_CLKOUT3_B,
+	GPIO_FN_SSI_WS9_B,
+	GPIO_FN_TS_SPSYNC0_E,
+	GPIO_FN_STP_ISSYNC_0_E,
+	GPIO_FN_RIF2_D1_B,
+	GPIO_FN_TPU0TO3,
+};
+
+#endif /* __ASM_R8A7795_GPIO_H__ */
diff --git a/arch/arm/mach-rmobile/include/mach/r8a7795.h b/arch/arm/mach-rmobile/include/mach/r8a7795.h
new file mode 100644
index 00000000000..2d004b6a540
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/r8a7795.h
@@ -0,0 +1,36 @@
+/*
+ * arch/arm/mach-rmobile/include/mach/r8a7795.h
+ *	This file defines registers and value for r8a7795.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_R8A7795_H
+#define __ASM_ARCH_R8A7795_H
+
+#include "rcar-gen3-base.h"
+
+/* Module stop control/status register bits */
+#define MSTP0_BITS	0x00640800
+#define MSTP1_BITS	0xF3EE9390
+#define MSTP2_BITS	0x340FAFDC
+#define MSTP3_BITS	0xD80C7CDF
+#define MSTP4_BITS	0x80000184
+#define MSTP5_BITS	0x40BFFF46
+#define MSTP6_BITS	0xE5FBEECF
+#define MSTP7_BITS	0x39FFFF0E
+#define MSTP8_BITS	0x01F19FF4
+#define MSTP9_BITS	0xFFDFFFFF
+#define MSTP10_BITS	0xFFFEFFE0
+#define MSTP11_BITS	0x00000000
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000	/* either MMC0 */
+#define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000	/* either MMC1 */
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 4
+
+#endif /* __ASM_ARCH_R8A7795_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h b/arch/arm/mach-rmobile/include/mach/rcar-base.h
index 53ead265bd0..709bc7515e8 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-base.h
@@ -10,7 +10,7 @@
 #define __ASM_ARCH_RCAR_BASE_H
 
 /*
- * R-Car (R8A7790/R8A7791/R8A7793/R8A7794) I/O Addresses
+ * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
  */
 #define RWDT_BASE		0xE6020000
 #define SWDT_BASE		0xE6030000
@@ -142,6 +142,12 @@
 
 #define SYS_AXI_SYX64TO128_BASE	0xFF800300
 #define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
 #define SYS_AXI_G2D_BASE	0xFF800540
 #define SYS_AXI_IMP0_BASE	0xFF800580
 #define SYS_AXI_IMP1_BASE	0xFF8005C0
@@ -154,30 +160,49 @@
 #define SYS_AXI_MMUR_BASE	0xFF800780
 #define SYS_AXI_MMUS0_BASE	0xFF8007C0
 #define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MPXM_BASE	0xFF800840
 #define SYS_AXI_MTSB0_BASE	0xFF800880
 #define SYS_AXI_MTSB1_BASE	0xFF8008C0
 #define SYS_AXI_PCI_BASE	0xFF800900
 #define SYS_AXI_RTX_BASE	0xFF800940
-#define SYS_AXI_SDS0_BASE	0xFF800A80
-#define SYS_AXI_SDS1_BASE	0xFF800AC0
-#define SYS_AXI_USB20_BASE	0xFF800C00
-#define SYS_AXI_USB21_BASE	0xFF800C40
-#define SYS_AXI_USB22_BASE	0xFF800C80
-#define SYS_AXI_USB30_BASE	0xFF800CC0
-#define SYS_AXI_AX2M_BASE	0xFF800380
-#define SYS_AXI_CC50_BASE	0xFF8003C0
-#define SYS_AXI_CCI_BASE	0xFF800440
-#define SYS_AXI_CS_BASE		0xFF800480
-#define SYS_AXI_DDM_BASE	0xFF8004C0
-#define SYS_AXI_ETH_BASE	0xFF800500
-#define SYS_AXI_MPXM_BASE	0xFF800840
 #define SYS_AXI_SAT0_BASE	0xFF800980
 #define SYS_AXI_SAT1_BASE	0xFF8009C0
 #define SYS_AXI_SDM0_BASE	0xFF800A00
 #define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
 #define SYS_AXI_TRAB_BASE	0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
 #define SYS_AXI_UDM0_BASE	0xFF800B80
 #define SYS_AXI_UDM1_BASE	0xFF800BC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_ADM_BASE	0xFF800D00
+#define SYS_AXI_ADS_BASE	0xFF800D40
+#define SYS_AXI_SYX_BASE	0xFF800FB8
+
+#define SYS_AXI_AXI64TO128W_BASE	0xFF801300
+#define SYS_AXI_AVBW_BASE	0xFF801340
+#define SYS_AXI_CC50W_BASE	0xFF8013C0
+#define SYS_AXI_CCIW_BASE	0xFF801440
+#define SYS_AXI_CSW_BASE	0xFF801480
+#define SYS_AXI_G2DW_BASE	0xFF801540
+#define SYS_AXI_IMUX0W_BASE	0xFF801600
+#define SYS_AXI_IMUX1W_BASE	0xFF801640
+#define SYS_AXI_IMUX2W_BASE	0xFF801680
+#define SYS_AXI_LBSW_BASE	0xFF8016C0
+#define SYS_AXI_RTXW_BASE	0xFF801940
+#define SYS_AXI_SDM0W_BASE	0xFF801A00
+#define SYS_AXI_SDM1W_BASE	0xFF801A40
+#define SYS_AXI_SDS0W_BASE	0xFF801A80
+#define SYS_AXI_SDS1W_BASE	0xFF801AC0
+#define SYS_AXI_TRABW_BASE	0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
+#define SYS_AXI_UDM0W_BASE	0xFF801B80
+#define SYS_AXI_UDM1W_BASE	0xFF801BC0
+#define SYS_AXI_ADMW_BASE	0xFF801D00
+#define SYS_AXI_ADSW_BASE	0xFF801D40
+#define SYS_AXI_SYXW_BASE	0xFF801FB8
 
 #define RT_AXI_SHX_BASE		0xFF810100
 #define RT_AXI_DBG_BASE		0xFF810140 /* R8A7791 only */
@@ -186,6 +211,11 @@
 #define RT_AXI_RTX64TO128_BASE	0xFF810200
 #define RT_AXI_STPRO_BASE	0xFF810240
 #define RT_AXI_SY2RT_BASE	0xFF810280 /* R8A7791 only */
+#define RT_AXI_RT_BASE		0xFF810FC0
+#define RT_AXI_SHXW_BASE	0xFF811100
+#define RT_AXI_DBGW_BASE	0xFF811140
+#define RT_AXI_RTX64TO128W_BASE	0xFF811200
+#define RT_AXI_RTW_BASE		0xFF811FC0
 
 #define MP_AXI_ADSP_BASE	0xFF820100
 #define MP_AXI_ASDS0_BASE	0xFF8201C0
@@ -197,8 +227,16 @@
 
 #define SYS_AXI256_AXI128TO256_BASE	0xFF860100
 #define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_AXM_BASE	0xFF860140
 #define SYS_AXI256_MPX_BASE	0xFF860180
 #define SYS_AXI256_MXI_BASE	0xFF8601C0
+#define SYS_AXI256_IMP0_BASE	0xFF860580
+#define SYS_AXI256_SY2_BASE	0xFF860FC0
+#define SYS_AXI256_AXI128TO256W_BASE	0xFF861100
+#define SYS_AXI256_AXMW_BASE	0xFF861140
+#define SYS_AXI256_MXIW_BASE	0xFF8611C0
+#define SYS_AXI256_IMP0W_BASE	0xFF861580
+#define SYS_AXI256_SY2W_BASE	0xFF861FC0
 
 #define CCI_AXI_MMUS0_BASE	0xFF880100
 #define CCI_AXI_SYX2_BASE	0xFF880140
@@ -227,9 +265,6 @@
 #define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
 #define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
 #define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
-#define MEDIA_AXI_VIN0W_BASE	0xFE966900
-#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
-#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
 #define MEDIA_AXI_FDP0R_BASE	0xFE964D40
 #define MEDIA_AXI_FDP0W_BASE	0xFE966D40
 #define MEDIA_AXI_IMSR_BASE	0xFE964D80
@@ -242,12 +277,6 @@
 #define MEDIA_AXI_IMRW_BASE	0xFE967180
 #define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
 #define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
-#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
-#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
-#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
-#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
-#define MEDIA_AXI_DU0R_BASE	0xFE965580
-#define MEDIA_AXI_DU0W_BASE	0xFE967580
 #define MEDIA_AXI_DU1R_BASE	0xFE9655C0
 #define MEDIA_AXI_DU1W_BASE	0xFE9675C0
 #define MEDIA_AXI_VCP0CR_BASE	0xFE965900
@@ -261,8 +290,66 @@
 #define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
 #define MEDIA_AXI_VPC1R_BASE	0xFE965D80
 
+#if defined (CONFIG_R8A7792)
+#define MEDIA_AXI_VCTU0R_BASE	0xFE964500 /* R8A7792 */
+#define MEDIA_AXI_VCTU0W_BASE	0xFE966500
+#define MEDIA_AXI_VDCTU0R_BASE	0xFE964540
+#define MEDIA_AXI_VDCTU0W_BASE	0xFE966540
+#define MEDIA_AXI_VDCTU1R_BASE	0xFE964580
+#define MEDIA_AXI_VDCTU1W_BASE	0xFE966580
+#define MEDIA_AXI_VIN0W_BASE	0xFE967580
+#define MEDIA_AXI_VIN1W_BASE	0xFE966D80
+#define MEDIA_AXI_RDRW_BASE	0xFE9675C0
+#define MEDIA_AXI_IMS01R_BASE	0xFE965500
+#define MEDIA_AXI_IMS01W_BASE	0xFE967500
+#define MEDIA_AXI_IMS23R_BASE	0xFE965540 /* FIXME */
+#define MEDIA_AXI_IMS23W_BASE	0xFE967540
+#define MEDIA_AXI_IMS45R_BASE	0xFE964D00
+#define MEDIA_AXI_IMS45W_BASE	0xFE966D00
+#define MEDIA_AXI_ROTCE4R_BASE	0xFE965100
+#define MEDIA_AXI_ROTCE4W_BASE	0xFE967100
+#define MEDIA_AXI_ROTVLC4R_BASE	0xFE965140
+#define MEDIA_AXI_ROTVLC4W_BASE	0xFE965140
+#define MEDIA_AXI_VSPD0R_BASE	0xFE964900
+#define MEDIA_AXI_VSPD0W_BASE	0xFE966900
+#define MEDIA_AXI_VSPD1R_BASE	0xFE964940
+#define MEDIA_AXI_VSPD1W_BASE	0xFE966940
+#define MEDIA_AXI_DU0R_BASE	0xFE964980
+#define MEDIA_AXI_DU0W_BASE	0xFE966980
+#define MEDIA_AXI_VSP0R_BASE	0xFE9649C0
+#define MEDIA_AXI_VSP0W_BASE	0xFE9669C0
+#define MEDIA_AXI_ROTCE0R_BASE	0xFE965900
+#define MEDIA_AXI_ROTCE0W_BASE	0xFE967900
+#define MEDIA_AXI_ROTVLC0R_BASE	0xFE965940
+#define MEDIA_AXI_ROTVLC0W_BASE	0xFE967940
+#define MEDIA_AXI_ROTCE1R_BASE	0xFE965980
+#define MEDIA_AXI_ROTCE1W_BASE	0xFE967980
+#define MEDIA_AXI_ROTVLC1R_BASE	0xFE9659C0
+#define MEDIA_AXI_ROTVLC1W_BASE	0xFE9679C0
+#define MEDIA_AXI_ROTCE2R_BASE	0xFE965D00
+#define MEDIA_AXI_ROTCE2W_BASE	0xFE967D00
+#define MEDIA_AXI_ROTVLC2R_BASE	0xFE965D40
+#define MEDIA_AXI_ROTVLC2W_BASE	0xFE967D40
+#define MEDIA_AXI_ROTCE3R_BASE	0xFE965D80
+#define MEDIA_AXI_ROTCE3W_BASE	0xFE967D80
+#define MEDIA_AXI_ROTVLC3R_BASE	0xFE965DC0
+#define MEDIA_AXI_ROTVLC3W_BASE	0xFE967DC0
+#else	/* R8A7792 */
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#endif	/* R8A7792 */
+
+
 #define SYS_AXI_AVBDMSCR	0xFF802000
 #define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_AX2MDMSCR	0xFF802004
 #define SYS_AXI_CC50DMSCR	0xFF802008
 #define SYS_AXI_CC51DMSCR	0xFF80200C
 #define SYS_AXI_CCIDMSCR	0xFF802010
@@ -301,6 +388,7 @@
 #define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
 #define SYS_AXI_AVBSLVDMSCR	0xFF802108
 #define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_AX2SLVDMSCR	0xFF80210C
 #define SYS_AXI_ETHSLVDMSCR	0xFF802110
 #define SYS_AXI_GICSLVDMSCR	0xFF802114
 #define SYS_AXI_IMPSLVDMSCR	0xFF802118
@@ -318,6 +406,11 @@
 #define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
 #define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
 #define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAPC1SLVDMSCR	0xFF802154
+#define SYS_AXI_SAPC2SLVDMSCR	0xFF802158
+#define SYS_AXI_SAPC3SLVDMSCR	0xFF80215C
+#define SYS_AXI_SAPC65SLVDMSCR	0xFF802160
+#define SYS_AXI_SAPC8SLVDMSCR	0xFF802164
 #define SYS_AXI_SAT0SLVDMSCR	0xFF802168
 #define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
 #define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
@@ -325,8 +418,10 @@
 #define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
 #define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
 #define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_SGXSLV1SLVDMSCR	0xFF802184
 #define SYS_AXI_STBSLVDMSCR	0xFF802188
 #define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR	0xFF802190
 #define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
 #define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
 #define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
@@ -334,6 +429,32 @@
 #define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
 #define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
 #define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+#define SYS_AXI_UTLBDSSLVDMSCR	0xFF8021B0
+#define SYS_AXI_UTLBS0SLVDMSCR	0xFF8021B4
+#define SYS_AXI_UTLBS1SLVDMSCR	0xFF8021B8
+#define	SYS_AXI_ROT0DMSCR	0xFF802320
+#define	SYS_AXI_ROT1DMSCR	0xFF802324
+#define	SYS_AXI_ROT2DMSCR	0xFF802328
+#define	SYS_AXI_ROT3DMSCR	0xFF80232C
+#define	SYS_AXI_ROT4DMSCR	0xFF802330
+#define	SYS_AXI_IMUX3SLVDMSCR	0xFF802334
+#define	SYS_AXI_STBR0SLVDMSCR	0xFF803200
+#define	SYS_AXI_STBR0PSLVDMSCR	0xFF803204
+#define	SYS_AXI_STBR0XSLVDMSCR	0xFF803208
+#define	SYS_AXI_STBR1SLVDMSCR	0xFF803210
+#define	SYS_AXI_STBR1PSLVDMSCR	0xFF803214
+#define	SYS_AXI_STBR1XSLVDMSCR	0xFF803218
+#define	SYS_AXI_STBR2SLVDMSCR	0xFF803220
+#define	SYS_AXI_STBR2PSLVDMSCR	0xFF803224
+#define	SYS_AXI_STBR2XSLVDMSCR	0xFF803228
+#define	SYS_AXI_STBR3SLVDMSCR	0xFF803230
+#define	SYS_AXI_STBR3PSLVDMSCR	0xFF803234
+#define	SYS_AXI_STBR3XSLVDMSCR	0xFF803238
+#define	SYS_AXI_STBR4SLVDMSCR	0xFF803240
+#define	SYS_AXI_STBR4PSLVDMSCR	0xFF803244
+#define	SYS_AXI_STBR4XSLVDMSCR	0xFF803248
+#define	SYS_AXI_ADM_DMSCR	0xFF803260
+#define	SYS_AXI_ADS_DMSCR	0xFF803264
 
 #define RT_AXI_CBMDMSCR		0xFF812000
 #define RT_AXI_DBDMSCR		0xFF812004
@@ -380,9 +501,86 @@
 #define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
 #define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
 
+#define	DM_AXI_DMAXICONF	0xFF850000
+#define	DM_AXI_DMAPBCONF	0xFF850004
+#define	DM_AXI_DMADMCONF	0xFF850020
+#define	DM_AXI_DMSDM0CONF	0xFF850024
+#define	DM_AXI_DMSDM1CONF	0xFF850028
+#define	DM_AXI_DMQSPAPSLVCONF	0xFF850030
+#define	DM_AXI_RAPD4SLVCONF	0xFF850034
+#define	DM_AXI_SAPD4SLVCONF	0xFF85003C
+#define	DM_AXI_SAPD5SLVCONF	0xFF850040
+#define	DM_AXI_SAPD6SLVCONF	0xFF850044
+#define	DM_AXI_SAPD65DSLVCONF	0xFF850048
+#define	DM_AXI_SDAP0SLVCONF	0xFF85004C
+#define	DM_AXI_MAPD2SLVCONF	0xFF850050
+#define	DM_AXI_MAPD3SLVCONF	0xFF850054
+#define	DM_AXI_DMXXDEFAULTSLAVESLVCONF	0xFF850058
+#define	DM_AXI_DMADMRQOSCONF	0xFF850100
+#define	DM_AXI_DMADMRQOSCTSET0	0xFF850104
+#define	DM_AXI_DMADMRQOSREQCTR	0xFF850114
+#define	DM_AXI_DMADMRQOSQON	0xFF850124
+#define	DM_AXI_DMADMRQOSIN	0xFF850128
+#define	DM_AXI_DMADMRQOSSTAT	0xFF85012C
+#define	DM_AXI_DMSDM0RQOSCONF	0xFF850140
+#define	DM_AXI_DMSDM0RQOSCTSET0	0xFF850144
+#define	DM_AXI_DMSDM0RQOSREQCTR	0xFF850154
+#define	DM_AXI_DMSDM0RQOSQON	0xFF850164
+#define	DM_AXI_DMSDM0RQOSIN	0xFF850168
+#define	DM_AXI_DMSDM0RQOSSTAT	0xFF85016C
+#define	DM_AXI_DMSDM1RQOSCONF	0xFF850180
+#define	DM_AXI_DMSDM1RQOSCTSET0	0xFF850184
+#define	DM_AXI_DMSDM1RQOSREQCTR	0xFF850194
+#define	DM_AXI_DMSDM1RQOSQON	0xFF8501A4
+#define	DM_AXI_DMSDM1RQOSIN	0xFF8501A8
+#define	DM_AXI_DMSDM1RQOSSTAT	0xFF8501AC
+#define	DM_AXI_DMRQOSCTSET1	0xFF850FC0
+#define	DM_AXI_DMRQOSCTSET2	0xFF850FC4
+#define	DM_AXI_DMRQOSCTSET3	0xFF850FC8
+#define	DM_AXI_DMRQOSTHRES0	0xFF850FCC
+#define	DM_AXI_DMRQOSTHRES1	0xFF850FD0
+#define	DM_AXI_DMRQOSTHRES2	0xFF850FD4
+#define	DM_AXI_DMADMWQOSCONF	0xFF851100
+#define	DM_AXI_DMADMWQOSCTSET0	0xFF851104
+#define	DM_AXI_DMADMWQOSREQCTR	0xFF851114
+#define	DM_AXI_DMADMWQOSQON	0xFF851124
+#define	DM_AXI_DMADMWQOSIN	0xFF851128
+#define	DM_AXI_DMADMWQOSSTAT	0xFF85112C
+#define	DM_AXI_DMSDM0WQOSCONF	0xFF851140
+#define	DM_AXI_DMSDM0WQOSCTSET0	0xFF851144
+#define	DM_AXI_DMSDM0WQOSREQCTR	0xFF851154
+#define	DM_AXI_DMSDM0WQOSQON	0xFF851164
+#define	DM_AXI_DMSDM0WQOSIN	0xFF851168
+#define	DM_AXI_DMSDM0WQOSSTAT	0xFF85116C
+#define	DM_AXI_DMSDM1WQOSCONF	0xFF851180
+#define	DM_AXI_DMSDM1WQOSCTSET0	0xFF851184
+#define	DM_AXI_DMSDM1WQOSREQCTR	0xFF851194
+#define	DM_AXI_DMSDM1WQOSQON	0xFF8511A4
+#define	DM_AXI_DMSDM1WQOSIN	0xFF8511A8
+#define	DM_AXI_DMSDM1WQOSSTAT	0xFF8511AC
+#define	DM_AXI_DMWQOSCTSET1	0xFF851FC0
+#define	DM_AXI_DMWQOSCTSET2	0xFF851FC4
+#define	DM_AXI_DMWQOSCTSET3	0xFF851FC8
+#define	DM_AXI_DMWQOSTHRES0	0xFF851FCC
+#define	DM_AXI_DMWQOSTHRES1	0xFF851FD0
+#define	DM_AXI_DMWQOSTHRES2	0xFF851FD4
+
 #define DM_AXI_RDMDMSCR		0xFF852000
 #define DM_AXI_SDM0DMSCR	0xFF852004
 #define DM_AXI_SDM1DMSCR	0xFF852008
+#if defined(CONFIG_R8A7792)
+#define	DM_AXI_DMQSPAPSLVDMSCR	0xFF852104
+#define	DM_AXI_RAPD4SLVDMSCR	0xFF852108
+#define	DM_AXI_SAPD4SLVDMSCR	0xFF852110
+#define	DM_AXI_SAPD5SLVDMSCR	0xFF852114
+#define	DM_AXI_SAPD6SLVDMSCR	0xFF852118
+#define	DM_AXI_SAPD65DSLVDMSCR	0xFF85211C
+#define	DM_AXI_SDAP0SLVDMSCR	0xFF852120
+#define	DM_AXI_MAPD2SLVDMSCR	0xFF852124
+#define	DM_AXI_MAPD3SLVDMSCR	0xFF852128
+#define	DM_AXI_DMXXDEFAULTSLAVESLVDMSCR	0xFF85212C
+#define	DM_AXI_DMXREGDMSENN	0xFF852200
+#else
 #define DM_AXI_MMAP0SLVDMSCR	0xFF852100
 #define DM_AXI_MMAP1SLVDMSCR	0xFF852104
 #define DM_AXI_QSPAPSLVDMSCR	0xFF852108
@@ -396,6 +594,7 @@
 #define DM_AXI_SDAP1SLVDMSCR	0xFF852128
 #define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
 #define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+#endif
 
 #define SYS_AXI256_SYXDMSCR	0xFF862000
 #define SYS_AXI256_MPXDMSCR	0xFF862004
@@ -407,6 +606,16 @@
 #define SYS_AXI256_S3CSLVDMSCR	0xFF862110
 
 #define MXT_SYXDMSCR		0xFF872000
+#if defined(CONFIG_R8A7792)
+#define	MXT_IMRSLVDMSCR		0xFF872110
+#define	MXT_VINSLVDMSCR		0xFF872114
+#define	MXT_VSP1SLVDMSCR	0xFF87211C
+#define	MXT_VSPD0SLVDMSCR	0xFF872120
+#define	MXT_VSPD1SLVDMSCR	0xFF872124
+#define	MXT_MAP1SLVDMSCR	0xFF872128
+#define	MXT_MAP2SLVDMSCR	0xFF87212C
+#define	MXT_MAP2BSLVDMSCR	0xFF872134
+#else	/* R8A7792 */
 #define MXT_CMM0SLVDMSCR	0xFF872100
 #define MXT_CMM1SLVDMSCR	0xFF872104
 #define MXT_CMM2SLVDMSCR	0xFF872108
@@ -421,6 +630,58 @@
 #define MXT_VSPD1SLVDMSCR	0xFF87212C
 #define MXT_MAP1SLVDMSCR	0xFF872130
 #define MXT_MAP2SLVDMSCR	0xFF872134
+#endif	/* R8A7792 */
+
+/* DMS Register (MXI) */
+#if defined(CONFIG_R8A7792)
+#define	MXI_JPURDMSCR		0xFE964200
+#define	MXI_JPUWDMSCR		0xFE966200
+#define	MXI_VCTU0RDMSCR		0xFE964600
+#define	MXI_VCTU0WDMSCR		0xFE966600
+#define	MXI_VDCTU0RDMSCR	0xFE964604
+#define	MXI_VDCTU0WDMSCR	0xFE966604
+#define	MXI_VDCTU1RDMSCR	0xFE964608
+#define	MXI_VDCTU1WDMSCR	0xFE966608
+#define	MXI_VIN0WDMSCR		0xFE967608
+#define	MXI_VIN1WDMSCR		0xFE966E08
+#define	MXI_RDRWDMSCR		0xFE96760C
+#define	MXI_IMS01RDMSCR		0xFE965600
+#define	MXI_IMS01WDMSCR		0xFE967600
+#define	MXI_IMS23RDMSCR		0xFE965604
+#define	MXI_IMS23WDMSCR		0xFE967604
+#define	MXI_IMS45RDMSCR		0xFE964E00
+#define	MXI_IMS45WDMSCR		0xFE966E00
+#define	MXI_IMRRDMSCR		0xFE964E04
+#define	MXI_IMRWDMSCR		0xFE966E04
+#define	MXI_ROTCE4RDMSCR	0xFE965200
+#define	MXI_ROTCE4WDMSCR	0xFE967200
+#define	MXI_ROTVLC4RDMSCR	0xFE965204
+#define	MXI_ROTVLC4WDMSCR	0xFE967204
+#define	MXI_VSPD0RDMSCR		0xFE964A00
+#define	MXI_VSPD0WDMSCR		0xFE966A00
+#define	MXI_VSPD1RDMSCR		0xFE964A04
+#define	MXI_VSPD1WDMSCR		0xFE966A04
+#define	MXI_DU0RDMSCR		0xFE964A08
+#define	MXI_DU0WDMSCR		0xFE966A08
+#define	MXI_VSP0RDMSCR		0xFE964A0C
+#define	MXI_VSP0WDMSCR		0xFE966A0C
+#define	MXI_ROTCE0RDMSCR	0xFE965A00
+#define	MXI_ROTCE0WDMSCR	0xFE967A00
+#define	MXI_ROTVLC0RDMSCR	0xFE965A04
+#define	MXI_ROTVLC0WDMSCR	0xFE967A04
+#define	MXI_ROTCE1RDMSCR	0xFE965A08
+#define	MXI_ROTCE1WDMSCR	0xFE967A08
+#define	MXI_ROTVLC1RDMSCR	0xFE965A0C
+#define	MXI_ROTVLC1WDMSCR	0xFE967A0C
+#define	MXI_ROTCE2RDMSCR	0xFE965E00
+#define	MXI_ROTCE2WDMSCR	0xFE967E00
+#define	MXI_ROTVLC2RDMSCR	0xFE965E04
+#define	MXI_ROTVLC2WDMSCR	0xFE967E04
+#define	MXI_ROTCE3RDMSCR	0xFE965E08
+#define	MXI_ROTCE3WDMSCR	0xFE967E08
+#define	MXI_ROTVLC3RDMSCR	0xFE965E0C
+#define	MXI_ROTVLC3WDMSCR	0xFE967E0C
+#endif	/* R8A7792 */
 
 #define CCI_AXI_MMUS0DMSCR	0xFF882000
 #define CCI_AXI_SYX2DMSCR	0xFF882004
@@ -597,6 +858,81 @@ struct rcar_dbsc3 {
 	u32 dbwt0cnf2;
 	u32 dbwt0cnf3;
 	u32 dbwt0cnf4;
+	u32 dummy17[27];	/* 0x394 .. 0x3FC */
+	u32 dbeccmode;
+	u32 dummy18[3];		/* 0x404 .. 0x40C */
+	u32 dbeccarea0;
+	u32 dbeccarea1;
+	u32 dbeccarea2;
+	u32 dbeccarea3;
+	u32 dummy19[4];		/* 0x420 .. 0x42C */
+	u32 dbeccintenable;
+	u32 dbeccintdetect;
+	u32 dummy20[22];	/* 0x438 .. 0x48C */
+	u32 dbeccmodulcnt;
+	u32 dummy21[27];	/* 0x494 .. 0x4FC */
+	u32 dbschecnt0;
+	u32 dummy22[63];	/* 0x504 .. 0x5FC */
+	u32 dbreradr0;
+	u32 dbreblane0;
+	u32 dbrerid0;
+	u32 dbrerinfo0;
+	u32 dbureradr0;
+	u32 dbureblane0;
+	u32 dburerid0;
+	u32 dburerinfo0;
+	u32 dbreradr1;
+	u32 dbreblane1;
+	u32 dbrerid1;
+	u32 dbrerinfo1;
+	u32 dbureradr1;
+	u32 dbureblane1;
+	u32 dburerid1;
+	u32 dburerinfo1;
+	u32 dbreradr2;
+	u32 dbreblane2;
+	u32 dbrerid2;
+	u32 dbrerinfo2;
+	u32 dbureradr2;
+	u32 dbureblane2;
+	u32 dburerid2;
+	u32 dburerinfo2;
+	u32 dbreradr3;
+	u32 dbreblane3;
+	u32 dbrerid3;
+	u32 dbrerinfo3;
+	u32 dbureradr3;
+	u32 dbureblane3;
+	u32 dburerid3;
+	u32 dburerinfo3;
+	u32 dummy23[160];	/* 0x680 .. 0x8FC */
+	u32 dbpccr;
+	u32 dbpeier;
+	u32 dbpeisr;
+	u32 dummy24;
+	u32 dbwdpesr0;
+	u32 dbwspesr0;
+	u32 dbpwear0;
+	u32 dbpweid0;
+	u32 dbpweinfo0;
+	u32 dummy25[3];		/* 0x924 .. 0x92C */
+	u32 dbwdpesr1;
+	u32 dbwspesr1;
+	u32 dbpwear1;
+	u32 dbpweid1;
+	u32 dbpweinfo1;
+	u32 dummy26[3];		/* 0x944 .. 0x94C */
+	u32 dbwdpesr2;
+	u32 dbwspesr2;
+	u32 dbpwear2;
+	u32 dbpweid2;
+	u32 dbpweinfo2;
+	u32 dummy27[3];		/* 0x964 .. 0x96C */
+	u32 dbwdpesr3;
+	u32 dbwspesr3;
+	u32 dbpwear3;
+	u32 dbpweid3;
+	u32 dbpweinfo3;
 };
 
 /* GPIO */
@@ -678,6 +1014,10 @@ struct rcar_mxi {
 	u32 dummy2;	/* 0x3C */
 	u32 mxrtcr;
 	u32 mxwtcr;
+	u32 mxaxirtcr;	/* R8a7792 only */
+	u32 mxaxiwtcr;
+	u32 mxs3crtcr;
+	u32 mxs3cwtcr;
 };
 
 struct rcar_mxi_qos {
@@ -699,6 +1039,7 @@ struct rcar_axi_qos {
 	u32 qosthres1;
 	u32 qosthres2;
 	u32 qosqon;
+	u32 qosin;
 };
 
 #endif
diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
new file mode 100644
index 00000000000..fbd87c4a01f
--- /dev/null
+++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
@@ -0,0 +1,100 @@
+/*
+ * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN3_BASE_H
+#define __ASM_ARCH_RCAR_GEN3_BASE_H
+
+/*
+ * R-Car (R8A7750) I/O Addresses
+ */
+#define RWDT_BASE		0xE6020000
+#define SWDT_BASE		0xE6030000
+#define LBSC_BASE		0xEE220200
+#define TMU_BASE		0xE61E0000
+#define GPIO5_BASE		0xE6055000
+
+/* SCIF */
+#define SCIF0_BASE		0xE6E60000
+#define SCIF1_BASE		0xE6E68000
+#define SCIF2_BASE		0xE6E88000
+#define SCIF3_BASE		0xE6C50000
+#define SCIF4_BASE		0xE6C40000
+#define SCIF5_BASE		0xE6F30000
+
+/* Module stop status register */
+#define MSTPSR0			0xE6150030
+#define MSTPSR1			0xE6150038
+#define MSTPSR2			0xE6150040
+#define MSTPSR3			0xE6150048
+#define MSTPSR4			0xE615004C
+#define MSTPSR5			0xE615003C
+#define MSTPSR6			0xE61501C0
+#define MSTPSR7			0xE61501C4
+#define MSTPSR8			0xE61509A0
+#define MSTPSR9			0xE61509A4
+#define MSTPSR10		0xE61509A8
+#define MSTPSR11		0xE61509AC
+
+/* Realtime module stop control register */
+#define RMSTPCR0		0xE6150110
+#define RMSTPCR1		0xE6150114
+#define RMSTPCR2		0xE6150118
+#define RMSTPCR3		0xE615011C
+#define RMSTPCR4		0xE6150120
+#define RMSTPCR5		0xE6150124
+#define RMSTPCR6		0xE6150128
+#define RMSTPCR7		0xE615012C
+#define RMSTPCR8		0xE6150980
+#define RMSTPCR9		0xE6150984
+#define RMSTPCR10		0xE6150988
+#define RMSTPCR11		0xE615098C
+
+/* System module stop control register */
+#define SMSTPCR0		0xE6150130
+#define SMSTPCR1		0xE6150134
+#define SMSTPCR2		0xE6150138
+#define SMSTPCR3		0xE615013C
+#define SMSTPCR4		0xE6150140
+#define SMSTPCR5		0xE6150144
+#define SMSTPCR6		0xE6150148
+#define SMSTPCR7		0xE615014C
+#define SMSTPCR8		0xE6150990
+#define SMSTPCR9		0xE6150994
+#define SMSTPCR10		0xE6150998
+#define SMSTPCR11		0xE615099C
+
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI0_BASE	0xEE100000
+#define CONFIG_SYS_SH_SDHI1_BASE	0xEE120000
+#define CONFIG_SYS_SH_SDHI2_BASE	0xEE140000
+#define CONFIG_SYS_SH_SDHI3_BASE	0xEE160000
+
+/* PFC */
+#define PFC_PUEN6       0xE6060418
+#define PUEN_USB1_OVC   (1 << 2)
+#define PUEN_USB1_PWEN  (1 << 1)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct rcar_rwdt {
+	u32 rwtcnt;
+	u32 rwtcsra;
+	u32 rwtcsrb;
+};
+
+/* SWDT */
+struct rcar_swdt {
+	u32 swtcnt;
+	u32 swtcsra;
+	u32 swtcsrb;
+};
+#endif
+
+#endif /* __ASM_ARCH_RCAR_GEN3_BASE_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
index 9a564f892c0..9a564f892c0 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-mstp.h
+++ b/arch/arm/mach-rmobile/include/mach/rcar-mstp.h
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index 65ee9eb5471..22d97b19ab9 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_ARCH_RMOBILE_H
 #define __ASM_ARCH_RMOBILE_H
 
-#if defined(CONFIG_RMOBILE)
+#if defined(CONFIG_ARCH_RMOBILE)
 #if defined(CONFIG_SH73A0)
 #include <asm/arch/sh73a0.h>
 #elif defined(CONFIG_R8A7740)
@@ -10,14 +10,18 @@
 #include <asm/arch/r8a7790.h>
 #elif defined(CONFIG_R8A7791)
 #include <asm/arch/r8a7791.h>
+#elif defined(CONFIG_R8A7792)
+#include <asm/arch/r8a7792.h>
 #elif defined(CONFIG_R8A7793)
 #include <asm/arch/r8a7793.h>
 #elif defined(CONFIG_R8A7794)
 #include <asm/arch/r8a7794.h>
+#elif defined(CONFIG_R8A7795)
+#include <asm/arch/r8a7795.h>
 #else
 #error "SOC Name not defined"
 #endif
-#endif /* CONFIG_RMOBILE */
+#endif /* CONFIG_ARCH_RMOBILE */
 
 #ifndef __ASSEMBLY__
 u32 rmobile_get_cpu_type(void);
diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h b/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h
index 398e2c10913..398e2c10913 100644
--- a/arch/arm/include/asm/arch-rmobile/sh73a0-gpio.h
+++ b/arch/arm/mach-rmobile/include/mach/sh73a0-gpio.h
diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/mach-rmobile/include/mach/sh73a0.h
index bdbb4086421..bdbb4086421 100644
--- a/arch/arm/include/asm/arch-rmobile/sh73a0.h
+++ b/arch/arm/mach-rmobile/include/mach/sh73a0.h
diff --git a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
index 057bf3f8bbf..057bf3f8bbf 100644
--- a/arch/arm/include/asm/arch-rmobile/sh_sdhi.h
+++ b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h
diff --git a/arch/arm/include/asm/arch-rmobile/sys_proto.h b/arch/arm/mach-rmobile/include/mach/sys_proto.h
index 326f6b14815..326f6b14815 100644
--- a/arch/arm/include/asm/arch-rmobile/sys_proto.h
+++ b/arch/arm/mach-rmobile/include/mach/sys_proto.h
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S b/arch/arm/mach-rmobile/lowlevel_init.S
index 0d654403eef..0d654403eef 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init.S
+++ b/arch/arm/mach-rmobile/lowlevel_init.S
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
index a5dbbea9e15..a5dbbea9e15 100644
--- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-rmobile/lowlevel_init_gen3.S
new file mode 100644
index 00000000000..88ff56ecbf8
--- /dev/null
+++ b/arch/arm/mach-rmobile/lowlevel_init_gen3.S
@@ -0,0 +1,76 @@
+/*
+ * arch/arm/cpu/armv8/rcar_gen3/lowlevel_init.S
+ *	This file is lowlevel initialize routine.
+ *
+ * (C) Copyright 2015 Renesas Electronics Corporation
+ *
+ * This file is based on the arch/arm/cpu/armv8/start.S
+ *
+ * (C) Copyright 2013
+ * David Feng <fenghua@phytium.com.cn>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+
+ENTRY(lowlevel_init)
+	mov	x29, lr			/* Save LR */
+
+#ifndef CONFIG_ARMV8_MULTIENTRY
+	/*
+	 * For single-entry systems the lowlevel init is very simple.
+	 */
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+
+#else /* CONFIG_ARMV8_MULTIENTRY is set */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+	branch_if_slave x0, 1f
+	ldr	x0, =GICD_BASE
+	bl	gic_init_secure
+1:
+#if defined(CONFIG_GICV3)
+	ldr	x0, =GICR_BASE
+	bl	gic_init_secure_percpu
+#elif defined(CONFIG_GICV2)
+	ldr	x0, =GICD_BASE
+	ldr	x1, =GICC_BASE
+	bl	gic_init_secure_percpu
+#endif
+#endif
+
+	branch_if_master x0, x1, 2f
+
+	/*
+	 * Slave should wait for master clearing spin table.
+	 * This sync prevent salves observing incorrect
+	 * value of spin table and jumping to wrong place.
+	 */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+	ldr	x0, =GICC_BASE
+#endif
+	bl	gic_wait_for_interrupt
+#endif
+
+	/*
+	 * All slaves will enter EL2 and optionally EL1.
+	 */
+	bl	armv8_switch_to_el2
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+	bl	armv8_switch_to_el1
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+	bl      s_init
+
+2:
+	mov	lr, x29			/* Restore LR */
+	ret
+ENDPROC(lowlevel_init)
diff --git a/arch/arm/mach-rmobile/memmap-r8a7795.c b/arch/arm/mach-rmobile/memmap-r8a7795.c
new file mode 100644
index 00000000000..c2c5e48aaf7
--- /dev/null
+++ b/arch/arm/mach-rmobile/memmap-r8a7795.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region r8a7795_mem_map[] = {
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = r8a7795_mem_map;
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c
index 5d42a68266b..5d42a68266b 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7740.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7740.c
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/mach-rmobile/pfc-r8a7790.c
index 580aba39e1f..580aba39e1f 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7790.c
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/mach-rmobile/pfc-r8a7790.h
index a13317be0b9..52f6d9e7cc1 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
+++ b/arch/arm/mach-rmobile/pfc-r8a7790.h
@@ -55,6 +55,54 @@
 	CPU_32_PORT(fn, pfx##_5_, sfx),				\
 	CPU_32_PORT(fn, pfx##_6_, sfx),				\
 	CPU_32_PORT1(fn, pfx##_7_, sfx)
+
+#elif defined(CONFIG_R8A7792)
+/*
+ * GP_0_0_DATA -> GP_11_29_DATA
+ * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31]
+ *  GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31])
+ */
+#define CPU_32_PORT0_28(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx),	\
+	PORT_1(fn, pfx##28, sfx)
+
+#define CPU_32_PORT0_22(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx)
+
+#define CPU_32_PORT0_27(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx),	\
+	PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx)
+
+#define CPU_32_PORT0_16(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), 					\
+	PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx),	\
+	PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx),	\
+	PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx),	\
+	PORT_1(fn, pfx##16, sfx)
+
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT0_28(fn, pfx##_0_, sfx),			\
+	CPU_32_PORT0_22(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),				\
+	CPU_32_PORT0_27(fn, pfx##_3_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_4_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_5_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_6_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_7_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_8_, sfx),			\
+	CPU_32_PORT0_16(fn, pfx##_9_, sfx),			\
+	CPU_32_PORT(fn, pfx##_10_, sfx),			\
+	CPU_32_PORT2(fn, pfx##_11_, sfx)
+
 #else
 #error "NO support"
 #endif
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/mach-rmobile/pfc-r8a7791.c
index 46d6e60c158..46d6e60c158 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7791.c
diff --git a/arch/arm/mach-rmobile/pfc-r8a7792.c b/arch/arm/mach-rmobile/pfc-r8a7792.c
new file mode 100644
index 00000000000..be29ee5528c
--- /dev/null
+++ b/arch/arm/mach-rmobile/pfc-r8a7792.c
@@ -0,0 +1,2302 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7792.c
+ *     This file is r8a7792 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3,
+	FN_IP0_4, FN_IP0_5, FN_IP0_6, FN_IP0_7,
+	FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15,
+	FN_IP0_16, FN_IP0_17, FN_IP0_18, FN_IP0_19,
+	FN_IP0_20, FN_IP0_21, FN_IP0_22, FN_IP0_23,
+	FN_IP1_0, FN_IP1_1, FN_IP1_2, FN_IP1_3,
+	FN_IP1_4,
+
+	/* GPSR1 */
+	FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8,
+	FN_IP1_9, FN_IP1_10, FN_IP1_11, FN_IP1_12,
+	FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
+	FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14, FN_DU1_DB5_C3_DATA15,
+	FN_DU1_DB6_C4, FN_DU1_DB7_C5, FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
+	FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
+
+	/* GPSR2 */
+	FN_D0, FN_D1, FN_D2, FN_D3,
+	FN_D4, FN_D5, FN_D6, FN_D7,
+	FN_D8, FN_D9, FN_D10, FN_D11,
+	FN_D12, FN_D13, FN_D14, FN_D15,
+	FN_A0, FN_A1, FN_A2, FN_A3,
+	FN_A4, FN_A5, FN_A6, FN_A7,
+	FN_A8, FN_A9, FN_A10, FN_A11,
+	FN_A12, FN_A13, FN_A14, FN_A15,
+
+	/* GPSR3 */
+	FN_A16, FN_A17, FN_A18, FN_A19,
+	FN_IP1_17, FN_IP1_18, FN_CS1_A26, FN_EX_CS0,
+	FN_EX_CS1, FN_EX_CS2, FN_EX_CS3, FN_EX_CS4,
+	FN_EX_CS5, FN_BS, FN_RD, FN_RD_WR,
+	FN_WE0, FN_WE1, FN_EX_WAIT0, FN_IRQ0,
+	FN_IRQ1, FN_IRQ2, FN_IRQ3, FN_IP1_19,
+	FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0,
+
+	/* GPSR4 */
+	FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC, FN_VI0_VSYNC,
+	FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
+	FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
+	FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
+	FN_VI0_FIELD,
+
+	/* GPSR5 */
+	FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC, FN_VI1_VSYNC,
+	FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
+	FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
+	FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
+	FN_VI1_FIELD,
+
+	/* GPSR6 */
+	FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3,
+	FN_IP2_4, FN_IP2_5, FN_IP2_6, FN_IP2_7,
+	FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11,
+	FN_IP2_12, FN_IP2_13, FN_IP2_14, FN_IP2_15,
+	FN_IP2_16,
+
+	/* GPSR7 */
+	FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3,
+	FN_IP3_4, FN_IP3_5, FN_IP3_6, FN_IP3_7,
+	FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11,
+	FN_IP3_12, FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14,
+	FN_VI3_FIELD,
+
+	/* GPSR8 */
+	FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2,
+	FN_IP4_4, FN_IP4_6_5, FN_IP4_8_7, FN_IP4_10_9,
+	FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15, FN_IP4_18_17,
+	FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
+
+	/* GPSR9 */
+	FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2,
+	FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
+	FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10,
+	FN_IP5_11, FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3,
+	FN_VI5_FIELD,
+
+	/* GPSR10 */
+	FN_IP6_0, FN_IP6_1, FN_HRTS0, FN_IP6_2,
+	FN_IP6_3, FN_IP6_4, FN_IP6_5, FN_HCTS1,
+	FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0,
+	FN_RTS0, FN_TX0, FN_RX0, FN_SCK1,
+	FN_CTS1, FN_RTS1, FN_TX1, FN_RX1,
+	FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+	FN_IP6_16, FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX,
+	FN_CAN0_RX, FN_CAN_CLK, FN_CAN1_TX, FN_CAN1_RX,
+
+	/* GPSR11 */
+	FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6,
+	FN_IP7_7, FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DAT0,
+	FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3, FN_SD0_CD,
+	FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
+	FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18,
+	FN_IP7_19, FN_IP7_20, FN_ADICLK, FN_ADICS_SAMP,
+	FN_ADIDATA, FN_ADICHS0, FN_ADICHS1, FN_ADICHS2,
+	FN_AVS1, FN_AVS2,
+
+	/* IPSR0 */
+	FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2, FN_DU0_DR3_Y5_DATA3,
+	FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5, FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7,
+	FN_DU0_DG0_DATA8, FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
+	FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14, FN_DU0_DG7_Y3_DATA15,
+	FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0, FN_DU0_DB3_C1,
+	FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4, FN_DU0_DB7_C5,
+
+	/* IPSR1 */
+	FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC, FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP,
+	FN_DU0_CDE, FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
+	FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5, FN_DU1_DG2_C6_DATA6,
+	FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8, FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10,
+	FN_DU1_DG7_Y3_DATA11, FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1,
+	FN_A22, FN_IO2, FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
+
+	/* IPSR2 */
+	FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
+	FN_VI2_HSYNC, FN_AVB_RXD0, FN_VI2_VSYNC, FN_AVB_RXD1,
+	FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
+	FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
+	FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
+	FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
+	FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
+	FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
+	FN_VI2_FIELD, FN_AVB_TXD2,
+
+	/* IPSR3 */
+	FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
+	FN_VI3_HSYNC, FN_AVB_TXD5, FN_VI3_VSYNC, FN_AVB_TXD6,
+	FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
+	FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
+	FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
+	FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
+	FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+	FN_VI3_D11_Y3,
+
+	/* IPSR4 */
+	FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
+	FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+	FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0,
+	FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0,
+	FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
+	FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
+	FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+	FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
+
+	/* IPSR5 */
+	FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1, FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
+	FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
+	FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
+	FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
+	FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
+	FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
+
+	/* IPSR6 */
+	FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0,
+	FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
+	FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1,
+	FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
+	FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2,
+	FN_DREQ0, FN_RX2, FN_DACK1, FN_SCK3,
+	FN_TX3, FN_DREQ1, FN_RX3,
+
+	/* IPSR7 */
+	FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
+	FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
+	FN_SSI_SCK3, FN_TPU0TO0, FN_SSI_WS3, FN_TPU0TO1,
+	FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
+	FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
+
+	FN_SEL_VI1_0, FN_SEL_VI1_1,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+	DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
+	DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
+	DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
+	DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, DU1_DISP_MARK, DU1_CDE_MARK,
+
+	D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
+	D6_MARK, D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK,
+	D12_MARK, D13_MARK, D14_MARK, D15_MARK, A0_MARK, A1_MARK,
+	A2_MARK, A3_MARK, A4_MARK, A5_MARK, A6_MARK, A7_MARK,
+	A8_MARK, A9_MARK, A10_MARK, A11_MARK, A12_MARK, A13_MARK,
+	A14_MARK, A15_MARK,
+
+	A16_MARK, A17_MARK, A18_MARK, A19_MARK,
+	CS1_A26_MARK, EX_CS0_MARK, EX_CS1_MARK, EX_CS2_MARK,
+	EX_CS3_MARK, EX_CS4_MARK, EX_CS5_MARK, BS_MARK,
+	RD_MARK, RD_WR_MARK, WE0_MARK, WE1_MARK, EX_WAIT0_MARK,
+	IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_MARK,
+
+	VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+	VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
+	VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK, VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
+	VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
+	VI0_FIELD_MARK,
+
+	VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_MARK,
+	VI1_VSYNC_MARK, VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
+	VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK,
+	VI1_D5_B5_C5_MARK, VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
+	VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK,
+	VI1_D11_G3_Y3_MARK, VI1_FIELD_MARK,
+
+	VI3_D10_Y2_MARK, VI3_FIELD_MARK,
+
+	VI4_CLK_MARK,
+
+	VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK, VI5_FIELD_MARK,
+
+	HRTS0_MARK, HCTS1_MARK, SCK0_MARK, CTS0_MARK, RTS0_MARK, TX0_MARK,
+	RX0_MARK, SCK1_MARK, CTS1_MARK, RTS1_MARK, TX1_MARK, RX1_MARK,
+	SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
+	CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
+
+	SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK,
+	SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+	SD0_CD_MARK, SD0_WP_MARK, ADICLK_MARK,
+	ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
+	ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
+
+	DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
+	DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
+	DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
+	DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
+	DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
+	DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
+	DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK,
+	DU0_DB5_C3_MARK, DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
+
+	DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+	DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
+	DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
+	DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
+	DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
+	DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
+	A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
+	A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
+
+	VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
+	VI2_HSYNC_MARK, AVB_RXD0_MARK, VI2_VSYNC_MARK, AVB_RXD1_MARK,
+	VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_RXD3_MARK,
+	VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
+	VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
+	VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
+	VI2_D8_Y0_MARK, AVB_TXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
+	VI2_D10_Y2_MARK, AVB_TXD0_MARK, VI2_D11_Y3_MARK, AVB_TXD1_MARK,
+	VI2_FIELD_MARK, AVB_TXD2_MARK,
+
+	VI3_CLK_MARK, AVB_TX_CLK_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
+	VI3_HSYNC_MARK, AVB_TXD5_MARK, VI3_VSYNC_MARK, AVB_TXD6_MARK,
+	VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
+	VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
+	VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
+	VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
+	VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
+	VI3_D11_Y3_MARK,
+
+	VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_MARK, VI0_D13_G5_Y5_MARK,
+	VI4_VSYNC_MARK, VI0_D14_G6_Y6_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK,
+	VI4_D1_C1_MARK, VI0_D16_R0_MARK, VI1_D12_G4_Y4_0_MARK,
+	VI4_D2_C2_MARK, VI0_D17_R1_MARK, VI1_D13_G5_Y5_0_MARK,
+	VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_0_MARK,
+	VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_0_MARK,
+	VI4_D5_C5_MARK, VI0_D20_R4_MARK, VI2_D12_Y4_MARK,
+	VI4_D6_C6_MARK, VI0_D21_R5_MARK, VI2_D13_Y5_MARK,
+	VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
+	VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK,
+	VI4_D9_Y1_MARK, VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK,
+	VI4_D11_Y3_MARK, VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
+
+	VI5_CLKENB_MARK, VI1_D12_G4_Y4_1_MARK, VI5_HSYNC_MARK, VI1_D13_G5_Y5_1_MARK,
+	VI5_VSYNC_MARK, VI1_D14_G6_Y6_1_MARK, VI5_D0_C0_MARK, VI1_D15_G7_Y7_1_MARK,
+	VI5_D1_C1_MARK, VI1_D16_R0_MARK, VI5_D2_C2_MARK, VI1_D17_R1_MARK,
+	VI5_D3_C3_MARK, VI1_D18_R2_MARK, VI5_D4_C4_MARK, VI1_D19_R3_MARK,
+	VI5_D5_C5_MARK, VI1_D20_R4_MARK, VI5_D6_C6_MARK, VI1_D21_R5_MARK,
+	VI5_D7_C7_MARK, VI1_D22_R6_MARK, VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
+
+	MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_MARK,
+	MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
+	MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_MARK,
+	MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
+	DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK,
+	DREQ0_MARK, RX2_MARK, DACK1_MARK, SCK3_MARK,
+	TX3_MARK, DREQ1_MARK, RX3_MARK,
+
+	PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK,
+	PWM1_MARK, TCLK2_MARK, FSO_CFE_1_MARK,
+	PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK,
+	PWM3_MARK, PWM4_MARK, SSI_SCK3_MARK, TPU0TO0_MARK,
+	SSI_WS3_MARK, TPU0TO1_MARK, SSI_SDATA3_MARK, TPU0TO2_MARK,
+	SSI_SCK4_MARK, TPU0TO3_MARK, SSI_WS4_MARK,
+	SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK,
+	AUDIO_CLKA_MARK, AUDIO_CLKB_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_DATA(DU1_DB2_C0_DATA12_MARK, FN_DU1_DB2_C0_DATA12),
+	PINMUX_DATA(DU1_DB3_C1_DATA13_MARK, FN_DU1_DB3_C1_DATA13),
+	PINMUX_DATA(DU1_DB4_C2_DATA14_MARK, FN_DU1_DB4_C2_DATA14),
+	PINMUX_DATA(DU1_DB5_C3_DATA15_MARK, FN_DU1_DB5_C3_DATA15),
+	PINMUX_DATA(DU1_DB6_C4_MARK, FN_DU1_DB6_C4),
+	PINMUX_DATA(DU1_DB7_C5_MARK, FN_DU1_DB7_C5),
+	PINMUX_DATA(DU1_EXHSYNC_DU1_HSYNC_MARK, FN_DU1_EXHSYNC_DU1_HSYNC),
+	PINMUX_DATA(DU1_EXVSYNC_DU1_VSYNC_MARK, FN_DU1_EXVSYNC_DU1_VSYNC),
+	PINMUX_DATA(DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE),
+	PINMUX_DATA(DU1_DISP_MARK, FN_DU1_DISP),
+	PINMUX_DATA(DU1_CDE_MARK, FN_DU1_CDE),
+
+	PINMUX_DATA(D0_MARK, FN_D0),
+	PINMUX_DATA(D1_MARK, FN_D1),
+	PINMUX_DATA(D2_MARK, FN_D2),
+	PINMUX_DATA(D3_MARK, FN_D3),
+	PINMUX_DATA(D4_MARK, FN_D4),
+	PINMUX_DATA(D5_MARK, FN_D5),
+	PINMUX_DATA(D6_MARK, FN_D6),
+	PINMUX_DATA(D7_MARK, FN_D7),
+	PINMUX_DATA(D8_MARK, FN_D8),
+	PINMUX_DATA(D9_MARK, FN_D9),
+	PINMUX_DATA(D10_MARK, FN_D10),
+	PINMUX_DATA(D11_MARK, FN_D11),
+	PINMUX_DATA(D12_MARK, FN_D12),
+	PINMUX_DATA(D13_MARK, FN_D13),
+	PINMUX_DATA(D14_MARK, FN_D14),
+	PINMUX_DATA(D15_MARK, FN_D15),
+	PINMUX_DATA(A0_MARK, FN_A0),
+	PINMUX_DATA(A1_MARK, FN_A1),
+	PINMUX_DATA(A2_MARK, FN_A2),
+	PINMUX_DATA(A3_MARK, FN_A3),
+	PINMUX_DATA(A4_MARK, FN_A4),
+	PINMUX_DATA(A5_MARK, FN_A5),
+	PINMUX_DATA(A6_MARK, FN_A6),
+	PINMUX_DATA(A7_MARK, FN_A7),
+	PINMUX_DATA(A8_MARK, FN_A8),
+	PINMUX_DATA(A9_MARK, FN_A9),
+	PINMUX_DATA(A10_MARK, FN_A10),
+	PINMUX_DATA(A11_MARK, FN_A11),
+	PINMUX_DATA(A12_MARK, FN_A12),
+	PINMUX_DATA(A13_MARK, FN_A13),
+	PINMUX_DATA(A14_MARK, FN_A14),
+	PINMUX_DATA(A15_MARK, FN_A15),
+
+	PINMUX_DATA(A16_MARK, FN_A16),
+	PINMUX_DATA(A17_MARK, FN_A17),
+	PINMUX_DATA(A18_MARK, FN_A18),
+	PINMUX_DATA(A19_MARK, FN_A19),
+	PINMUX_DATA(CS1_A26_MARK, FN_CS1_A26),
+	PINMUX_DATA(EX_CS0_MARK, FN_EX_CS0),
+	PINMUX_DATA(EX_CS1_MARK, FN_EX_CS1),
+	PINMUX_DATA(EX_CS2_MARK, FN_EX_CS2),
+	PINMUX_DATA(EX_CS3_MARK, FN_EX_CS3),
+	PINMUX_DATA(EX_CS4_MARK, FN_EX_CS4),
+	PINMUX_DATA(EX_CS5_MARK, FN_EX_CS5),
+	PINMUX_DATA(BS_MARK, FN_BS),
+	PINMUX_DATA(RD_MARK, FN_RD),
+	PINMUX_DATA(RD_WR_MARK, FN_RD_WR),
+	PINMUX_DATA(WE0_MARK, FN_WE0),
+	PINMUX_DATA(WE1_MARK, FN_WE1),
+	PINMUX_DATA(EX_WAIT0_MARK, FN_EX_WAIT0),
+	PINMUX_DATA(IRQ0_MARK, FN_IRQ0),
+	PINMUX_DATA(IRQ1_MARK, FN_IRQ1),
+	PINMUX_DATA(IRQ2_MARK, FN_IRQ2),
+	PINMUX_DATA(IRQ3_MARK, FN_IRQ3),
+	PINMUX_DATA(CS0_MARK, FN_CS0),
+
+	PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
+	PINMUX_DATA(VI0_CLKENB_MARK, FN_VI0_CLKENB),
+	PINMUX_DATA(VI0_HSYNC_MARK, FN_VI0_HSYNC),
+	PINMUX_DATA(VI0_VSYNC_MARK, FN_VI0_VSYNC),
+	PINMUX_DATA(VI0_D0_B0_C0_MARK, FN_VI0_D0_B0_C0),
+	PINMUX_DATA(VI0_D1_B1_C1_MARK, FN_VI0_D1_B1_C1),
+	PINMUX_DATA(VI0_D2_B2_C2_MARK, FN_VI0_D2_B2_C2),
+	PINMUX_DATA(VI0_D3_B3_C3_MARK, FN_VI0_D3_B3_C3),
+	PINMUX_DATA(VI0_D4_B4_C4_MARK, FN_VI0_D4_B4_C4),
+	PINMUX_DATA(VI0_D5_B5_C5_MARK, FN_VI0_D5_B5_C5),
+	PINMUX_DATA(VI0_D6_B6_C6_MARK, FN_VI0_D6_B6_C6),
+	PINMUX_DATA(VI0_D7_B7_C7_MARK, FN_VI0_D7_B7_C7),
+	PINMUX_DATA(VI0_D8_G0_Y0_MARK, FN_VI0_D8_G0_Y0),
+	PINMUX_DATA(VI0_D9_G1_Y1_MARK, FN_VI0_D9_G1_Y1),
+	PINMUX_DATA(VI0_D10_G2_Y2_MARK, FN_VI0_D10_G2_Y2),
+	PINMUX_DATA(VI0_D11_G3_Y3_MARK, FN_VI0_D11_G3_Y3),
+	PINMUX_DATA(VI0_FIELD_MARK, FN_VI0_FIELD),
+
+	PINMUX_DATA(VI1_CLK_MARK, FN_VI1_CLK),
+	PINMUX_DATA(VI1_CLKENB_MARK, FN_VI1_CLKENB),
+	PINMUX_DATA(VI1_HSYNC_MARK, FN_VI1_HSYNC),
+	PINMUX_DATA(VI1_VSYNC_MARK, FN_VI1_VSYNC),
+	PINMUX_DATA(VI1_D0_B0_C0_MARK, FN_VI1_D0_B0_C0),
+	PINMUX_DATA(VI1_D1_B1_C1_MARK, FN_VI1_D1_B1_C1),
+	PINMUX_DATA(VI1_D2_B2_C2_MARK, FN_VI1_D2_B2_C2),
+	PINMUX_DATA(VI1_D3_B3_C3_MARK, FN_VI1_D3_B3_C3),
+	PINMUX_DATA(VI1_D4_B4_C4_MARK, FN_VI1_D4_B4_C4),
+	PINMUX_DATA(VI1_D5_B5_C5_MARK, FN_VI1_D5_B5_C5),
+	PINMUX_DATA(VI1_D6_B6_C6_MARK, FN_VI1_D6_B6_C6),
+	PINMUX_DATA(VI1_D7_B7_C7_MARK, FN_VI1_D7_B7_C7),
+	PINMUX_DATA(VI1_D8_G0_Y0_MARK, FN_VI1_D8_G0_Y0),
+	PINMUX_DATA(VI1_D9_G1_Y1_MARK, FN_VI1_D9_G1_Y1),
+	PINMUX_DATA(VI1_D10_G2_Y2_MARK, FN_VI1_D10_G2_Y2),
+	PINMUX_DATA(VI1_D11_G3_Y3_MARK, FN_VI1_D11_G3_Y3),
+	PINMUX_DATA(VI1_FIELD_MARK, FN_VI1_FIELD),
+
+	PINMUX_DATA(VI3_D10_Y2_MARK, FN_VI3_D10_Y2),
+	PINMUX_DATA(VI3_FIELD_MARK, FN_VI3_FIELD),
+
+	PINMUX_DATA(VI4_CLK_MARK, FN_VI4_CLK),
+
+	PINMUX_DATA(VI5_CLK_MARK, FN_VI5_CLK),
+	PINMUX_DATA(VI5_D9_Y1_MARK, FN_VI5_D9_Y1),
+	PINMUX_DATA(VI5_D10_Y2_MARK, FN_VI5_D10_Y2),
+	PINMUX_DATA(VI5_D11_Y3_MARK, FN_VI5_D11_Y3),
+	PINMUX_DATA(VI5_FIELD_MARK, FN_VI5_FIELD),
+
+	PINMUX_DATA(HRTS0_MARK, FN_HRTS0),
+	PINMUX_DATA(HCTS1_MARK, FN_HCTS1),
+	PINMUX_DATA(SCK0_MARK, FN_SCK0),
+	PINMUX_DATA(CTS0_MARK, FN_CTS0),
+	PINMUX_DATA(RTS0_MARK, FN_RTS0),
+	PINMUX_DATA(TX0_MARK, FN_TX0),
+	PINMUX_DATA(RX0_MARK, FN_RX0),
+	PINMUX_DATA(SCK1_MARK, FN_SCK1),
+	PINMUX_DATA(CTS1_MARK, FN_CTS1),
+	PINMUX_DATA(RTS1_MARK, FN_RTS1),
+	PINMUX_DATA(TX1_MARK, FN_TX1),
+	PINMUX_DATA(RX1_MARK, FN_RX1),
+	PINMUX_DATA(SCIF_CLK_MARK, FN_SCIF_CLK),
+	PINMUX_DATA(CAN0_TX_MARK, FN_CAN0_TX),
+	PINMUX_DATA(CAN0_RX_MARK, FN_CAN0_RX),
+	PINMUX_DATA(CAN_CLK_MARK, FN_CAN_CLK),
+	PINMUX_DATA(CAN1_TX_MARK, FN_CAN1_TX),
+	PINMUX_DATA(CAN1_RX_MARK, FN_CAN1_RX),
+
+	PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK),
+	PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD),
+	PINMUX_DATA(SD0_DAT0_MARK, FN_SD0_DAT0),
+	PINMUX_DATA(SD0_DAT1_MARK, FN_SD0_DAT1),
+	PINMUX_DATA(SD0_DAT2_MARK, FN_SD0_DAT2),
+	PINMUX_DATA(SD0_DAT3_MARK, FN_SD0_DAT3),
+	PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD),
+	PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP),
+	PINMUX_DATA(ADICLK_MARK, FN_ADICLK),
+	PINMUX_DATA(ADICS_SAMP_MARK, FN_ADICS_SAMP),
+	PINMUX_DATA(ADIDATA_MARK, FN_ADIDATA),
+	PINMUX_DATA(ADICHS0_MARK, FN_ADICHS0),
+	PINMUX_DATA(ADICHS1_MARK, FN_ADICHS1),
+	PINMUX_DATA(ADICHS2_MARK, FN_ADICHS2),
+	PINMUX_DATA(AVS1_MARK, FN_AVS1),
+	PINMUX_DATA(AVS2_MARK, FN_AVS2),
+
+	PINMUX_IPSR_DATA(IP0_0, DU0_DR0_DATA0),
+	PINMUX_IPSR_DATA(IP0_1, DU0_DR1_DATA1),
+	PINMUX_IPSR_DATA(IP0_2, DU0_DR2_Y4_DATA2),
+	PINMUX_IPSR_DATA(IP0_3, DU0_DR3_Y5_DATA3),
+	PINMUX_IPSR_DATA(IP0_4, DU0_DR4_Y6_DATA4),
+	PINMUX_IPSR_DATA(IP0_5, DU0_DR5_Y7_DATA5),
+	PINMUX_IPSR_DATA(IP0_6, DU0_DR6_Y8_DATA6),
+	PINMUX_IPSR_DATA(IP0_7, DU0_DR7_Y9_DATA7),
+	PINMUX_IPSR_DATA(IP0_8, DU0_DG0_DATA8),
+	PINMUX_IPSR_DATA(IP0_9, DU0_DG1_DATA9),
+	PINMUX_IPSR_DATA(IP0_10, DU0_DG2_C6_DATA10),
+	PINMUX_IPSR_DATA(IP0_11, DU0_DG3_C7_DATA11),
+	PINMUX_IPSR_DATA(IP0_12, DU0_DG4_Y0_DATA12),
+	PINMUX_IPSR_DATA(IP0_13, DU0_DG5_Y1_DATA13),
+	PINMUX_IPSR_DATA(IP0_14, DU0_DG6_Y2_DATA14),
+	PINMUX_IPSR_DATA(IP0_15, DU0_DG7_Y3_DATA15),
+	PINMUX_IPSR_DATA(IP0_16, DU0_DB0),
+	PINMUX_IPSR_DATA(IP0_17, DU0_DB1),
+	PINMUX_IPSR_DATA(IP0_18, DU0_DB2_C0),
+	PINMUX_IPSR_DATA(IP0_19, DU0_DB3_C1),
+	PINMUX_IPSR_DATA(IP0_20, DU0_DB4_C2),
+	PINMUX_IPSR_DATA(IP0_21, DU0_DB5_C3),
+	PINMUX_IPSR_DATA(IP0_22, DU0_DB6_C4),
+	PINMUX_IPSR_DATA(IP0_23, DU0_DB7_C5),
+
+	PINMUX_IPSR_DATA(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
+	PINMUX_IPSR_DATA(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
+	PINMUX_IPSR_DATA(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+	PINMUX_IPSR_DATA(IP1_3, DU0_DISP),
+	PINMUX_IPSR_DATA(IP1_4, DU0_CDE),
+	PINMUX_IPSR_DATA(IP1_5, DU1_DR2_Y4_DATA0),
+	PINMUX_IPSR_DATA(IP1_6, DU1_DR3_Y5_DATA1),
+	PINMUX_IPSR_DATA(IP1_7, DU1_DR4_Y6_DATA2),
+	PINMUX_IPSR_DATA(IP1_8, DU1_DR5_Y7_DATA3),
+	PINMUX_IPSR_DATA(IP1_9, DU1_DR6_DATA4),
+	PINMUX_IPSR_DATA(IP1_10, DU1_DR7_DATA5),
+	PINMUX_IPSR_DATA(IP1_11, DU1_DG2_C6_DATA6),
+	PINMUX_IPSR_DATA(IP1_12, DU1_DG3_C7_DATA7),
+	PINMUX_IPSR_DATA(IP1_13, DU1_DG4_Y0_DATA8),
+	PINMUX_IPSR_DATA(IP1_14, DU1_DG5_Y1_DATA9),
+	PINMUX_IPSR_DATA(IP1_15, DU1_DG6_Y2_DATA10),
+	PINMUX_IPSR_DATA(IP1_16, DU1_DG7_Y3_DATA11),
+	PINMUX_IPSR_DATA(IP1_17, A20),
+	PINMUX_IPSR_DATA(IP1_17, MOSI_IO0),
+	PINMUX_IPSR_DATA(IP1_18, A21),
+	PINMUX_IPSR_DATA(IP1_18, MISO_IO1),
+	PINMUX_IPSR_DATA(IP1_19, A22),
+	PINMUX_IPSR_DATA(IP1_19, IO2),
+	PINMUX_IPSR_DATA(IP1_20, A23),
+	PINMUX_IPSR_DATA(IP1_20, IO3),
+	PINMUX_IPSR_DATA(IP1_21, A24),
+	PINMUX_IPSR_DATA(IP1_21, SPCLK),
+	PINMUX_IPSR_DATA(IP1_22, A25),
+	PINMUX_IPSR_DATA(IP1_22, SSL),
+
+	PINMUX_IPSR_DATA(IP2_0, VI2_CLK),
+	PINMUX_IPSR_DATA(IP2_0, AVB_RX_CLK),
+	PINMUX_IPSR_DATA(IP2_1, VI2_CLKENB),
+	PINMUX_IPSR_DATA(IP2_1, AVB_RX_DV),
+	PINMUX_IPSR_DATA(IP2_2, VI2_HSYNC),
+	PINMUX_IPSR_DATA(IP2_2, AVB_RXD0),
+	PINMUX_IPSR_DATA(IP2_3, VI2_VSYNC),
+	PINMUX_IPSR_DATA(IP2_3, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP2_4, VI2_D0_C0),
+	PINMUX_IPSR_DATA(IP2_4, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP2_5, VI2_D1_C1),
+	PINMUX_IPSR_DATA(IP2_5, AVB_RXD3),
+	PINMUX_IPSR_DATA(IP2_6, VI2_D2_C2),
+	PINMUX_IPSR_DATA(IP2_6, AVB_RXD4),
+	PINMUX_IPSR_DATA(IP2_7, VI2_D3_C3),
+	PINMUX_IPSR_DATA(IP2_7, AVB_RXD5),
+	PINMUX_IPSR_DATA(IP2_8, VI2_D4_C4),
+	PINMUX_IPSR_DATA(IP2_8, AVB_RXD6),
+	PINMUX_IPSR_DATA(IP2_9, VI2_D5_C5),
+	PINMUX_IPSR_DATA(IP2_9, AVB_RXD7),
+	PINMUX_IPSR_DATA(IP2_10, VI2_D6_C6),
+	PINMUX_IPSR_DATA(IP2_10, AVB_RX_ER),
+	PINMUX_IPSR_DATA(IP2_11, VI2_D7_C7),
+	PINMUX_IPSR_DATA(IP2_11, AVB_COL),
+	PINMUX_IPSR_DATA(IP2_12, VI2_D8_Y0),
+	PINMUX_IPSR_DATA(IP2_12, AVB_TXD3),
+	PINMUX_IPSR_DATA(IP2_13, VI2_D9_Y1),
+	PINMUX_IPSR_DATA(IP2_13, AVB_TX_EN),
+	PINMUX_IPSR_DATA(IP2_14, VI2_D10_Y2),
+	PINMUX_IPSR_DATA(IP2_14, AVB_TXD0),
+	PINMUX_IPSR_DATA(IP2_15, VI2_D11_Y3),
+	PINMUX_IPSR_DATA(IP2_15, AVB_TXD1),
+	PINMUX_IPSR_DATA(IP2_16, VI2_FIELD),
+	PINMUX_IPSR_DATA(IP2_16, AVB_TXD2),
+
+	PINMUX_IPSR_DATA(IP3_0, VI3_CLK),
+	PINMUX_IPSR_DATA(IP3_0, AVB_TX_CLK),
+	PINMUX_IPSR_DATA(IP3_1, VI3_CLKENB),
+	PINMUX_IPSR_DATA(IP3_1, AVB_TXD4),
+	PINMUX_IPSR_DATA(IP3_2, VI3_HSYNC),
+	PINMUX_IPSR_DATA(IP3_2, AVB_TXD5),
+	PINMUX_IPSR_DATA(IP3_3, VI3_VSYNC),
+	PINMUX_IPSR_DATA(IP3_3, AVB_TXD6),
+	PINMUX_IPSR_DATA(IP3_4, VI3_D0_C0),
+	PINMUX_IPSR_DATA(IP3_4, AVB_TXD7),
+	PINMUX_IPSR_DATA(IP3_5, VI3_D1_C1),
+	PINMUX_IPSR_DATA(IP3_5, AVB_TX_ER),
+	PINMUX_IPSR_DATA(IP3_6, VI3_D2_C2),
+	PINMUX_IPSR_DATA(IP3_6, AVB_GTX_CLK),
+	PINMUX_IPSR_DATA(IP3_7, VI3_D3_C3),
+	PINMUX_IPSR_DATA(IP3_7, AVB_MDC),
+	PINMUX_IPSR_DATA(IP3_8, VI3_D4_C4),
+	PINMUX_IPSR_DATA(IP3_8, AVB_MDIO),
+	PINMUX_IPSR_DATA(IP3_9, VI3_D5_C5),
+	PINMUX_IPSR_DATA(IP3_9, AVB_LINK),
+	PINMUX_IPSR_DATA(IP3_10, VI3_D6_C6),
+	PINMUX_IPSR_DATA(IP3_10, AVB_MAGIC),
+	PINMUX_IPSR_DATA(IP3_11, VI3_D7_C7),
+	PINMUX_IPSR_DATA(IP3_11, AVB_PHY_INT),
+	PINMUX_IPSR_DATA(IP3_12, VI3_D8_Y0),
+	PINMUX_IPSR_DATA(IP3_12, AVB_CRS),
+	PINMUX_IPSR_DATA(IP3_13, VI3_D9_Y1),
+	PINMUX_IPSR_DATA(IP3_13, AVB_GTXREFCLK),
+	PINMUX_IPSR_DATA(IP3_14, VI3_D11_Y3),
+
+	PINMUX_IPSR_DATA(IP4_0, VI4_CLKENB),
+	PINMUX_IPSR_DATA(IP4_0, VI0_D12_G4_Y4),
+	PINMUX_IPSR_DATA(IP4_1, VI4_HSYNC),
+	PINMUX_IPSR_DATA(IP4_1, VI0_D13_G5_Y5),
+	PINMUX_IPSR_DATA(IP4_3_2, VI4_VSYNC),
+	PINMUX_IPSR_DATA(IP4_3_2, VI0_D14_G6_Y6),
+	PINMUX_IPSR_DATA(IP4_4, VI4_D0_C0),
+	PINMUX_IPSR_DATA(IP4_4, VI0_D15_G7_Y7),
+	PINMUX_IPSR_DATA(IP4_6_5, VI4_D1_C1),
+	PINMUX_IPSR_DATA(IP4_6_5, VI0_D16_R0),
+	PINMUX_IPSR_MODSEL_DATA(IP4_6_5, VI1_D12_G4_Y4_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_8_7, VI4_D2_C2),
+	PINMUX_IPSR_DATA(IP4_8_7, VI0_D17_R1),
+	PINMUX_IPSR_MODSEL_DATA(IP4_8_7, VI1_D13_G5_Y5_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_10_9, VI4_D3_C3),
+	PINMUX_IPSR_DATA(IP4_10_9, VI0_D18_R2),
+	PINMUX_IPSR_MODSEL_DATA(IP4_10_9, VI1_D14_G6_Y6_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_12_11, VI4_D4_C4),
+	PINMUX_IPSR_DATA(IP4_12_11, VI0_D19_R3),
+	PINMUX_IPSR_MODSEL_DATA(IP4_12_11, VI1_D15_G7_Y7_0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP4_14_13, VI4_D5_C5),
+	PINMUX_IPSR_DATA(IP4_14_13, VI0_D20_R4),
+	PINMUX_IPSR_DATA(IP4_14_13, VI2_D12_Y4),
+	PINMUX_IPSR_DATA(IP4_16_15, VI4_D6_C6),
+	PINMUX_IPSR_DATA(IP4_16_15, VI0_D21_R5),
+	PINMUX_IPSR_DATA(IP4_16_15, VI2_D13_Y5),
+	PINMUX_IPSR_DATA(IP4_18_17, VI4_D7_C7),
+	PINMUX_IPSR_DATA(IP4_18_17, VI0_D22_R6),
+	PINMUX_IPSR_DATA(IP4_18_17, VI2_D14_Y6),
+	PINMUX_IPSR_DATA(IP4_20_19, VI4_D8_Y0),
+	PINMUX_IPSR_DATA(IP4_20_19, VI0_D23_R7),
+	PINMUX_IPSR_DATA(IP4_20_19, VI2_D15_Y7),
+	PINMUX_IPSR_DATA(IP4_21, VI4_D9_Y1),
+	PINMUX_IPSR_DATA(IP4_21, VI3_D12_Y4),
+	PINMUX_IPSR_DATA(IP4_22, VI4_D10_Y2),
+	PINMUX_IPSR_DATA(IP4_22, VI3_D13_Y5),
+	PINMUX_IPSR_DATA(IP4_23, VI4_D11_Y3),
+	PINMUX_IPSR_DATA(IP4_23, VI3_D14_Y6),
+	PINMUX_IPSR_DATA(IP4_24, VI4_FIELD),
+	PINMUX_IPSR_DATA(IP4_24, VI3_D15_Y7),
+
+	PINMUX_IPSR_DATA(IP5_0, VI5_CLKENB),
+	PINMUX_IPSR_MODSEL_DATA(IP5_0, VI1_D12_G4_Y4_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_1, VI5_HSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP5_1, VI1_D13_G5_Y5_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_2, VI5_VSYNC),
+	PINMUX_IPSR_MODSEL_DATA(IP5_2, VI1_D14_G6_Y6_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_3, VI5_D0_C0),
+	PINMUX_IPSR_MODSEL_DATA(IP5_3, VI1_D15_G7_Y7_1, SEL_VI1_1),
+	PINMUX_IPSR_DATA(IP5_4, VI5_D1_C1),
+	PINMUX_IPSR_DATA(IP5_4, VI1_D16_R0),
+	PINMUX_IPSR_DATA(IP5_5, VI5_D2_C2),
+	PINMUX_IPSR_DATA(IP5_5, VI1_D17_R1),
+	PINMUX_IPSR_DATA(IP5_6, VI5_D3_C3),
+	PINMUX_IPSR_DATA(IP5_6, VI1_D18_R2),
+	PINMUX_IPSR_DATA(IP5_7, VI5_D4_C4),
+	PINMUX_IPSR_DATA(IP5_7, VI1_D19_R3),
+	PINMUX_IPSR_DATA(IP5_8, VI5_D5_C5),
+	PINMUX_IPSR_DATA(IP5_8, VI1_D20_R4),
+	PINMUX_IPSR_DATA(IP5_9, VI5_D6_C6),
+	PINMUX_IPSR_DATA(IP5_9, VI1_D21_R5),
+	PINMUX_IPSR_DATA(IP5_10, VI5_D7_C7),
+	PINMUX_IPSR_DATA(IP5_10, VI1_D22_R6),
+	PINMUX_IPSR_DATA(IP5_11, VI5_D8_Y0),
+	PINMUX_IPSR_DATA(IP5_11, VI1_D23_R7),
+
+	PINMUX_IPSR_DATA(IP6_0, MSIOF0_SCK),
+	PINMUX_IPSR_DATA(IP6_0, HSCK0),
+	PINMUX_IPSR_DATA(IP6_1, MSIOF0_SYNC),
+	PINMUX_IPSR_DATA(IP6_1, HCTS0),
+	PINMUX_IPSR_DATA(IP6_2, MSIOF0_TXD),
+	PINMUX_IPSR_DATA(IP6_2, HTX0),
+	PINMUX_IPSR_DATA(IP6_3, MSIOF0_RXD),
+	PINMUX_IPSR_DATA(IP6_3, HRX0),
+	PINMUX_IPSR_DATA(IP6_4, MSIOF1_SCK),
+	PINMUX_IPSR_DATA(IP6_4, HSCK1),
+	PINMUX_IPSR_DATA(IP6_5, MSIOF1_SYNC),
+	PINMUX_IPSR_DATA(IP6_5, HRTS1),
+	PINMUX_IPSR_DATA(IP6_6, MSIOF1_TXD),
+	PINMUX_IPSR_DATA(IP6_6, HTX1),
+	PINMUX_IPSR_DATA(IP6_7, MSIOF1_RXD),
+	PINMUX_IPSR_DATA(IP6_7, HRX1),
+	PINMUX_IPSR_DATA(IP6_9_8, DRACK0),
+	PINMUX_IPSR_DATA(IP6_9_8, SCK2),
+	PINMUX_IPSR_DATA(IP6_11_10, DACK0),
+	PINMUX_IPSR_DATA(IP6_11_10, TX2),
+	PINMUX_IPSR_DATA(IP6_13_12, DREQ0),
+	PINMUX_IPSR_DATA(IP6_13_12, RX2),
+	PINMUX_IPSR_DATA(IP6_15_14, DACK1),
+	PINMUX_IPSR_DATA(IP6_15_14, SCK3),
+	PINMUX_IPSR_DATA(IP6_16, TX3),
+	PINMUX_IPSR_DATA(IP6_18_17, DREQ1),
+	PINMUX_IPSR_DATA(IP6_18_17, RX3),
+
+	PINMUX_IPSR_DATA(IP7_1_0, PWM0),
+	PINMUX_IPSR_DATA(IP7_1_0, TCLK1),
+	PINMUX_IPSR_DATA(IP7_1_0, FSO_CFE_0),
+	PINMUX_IPSR_DATA(IP7_3_2, PWM1),
+	PINMUX_IPSR_DATA(IP7_3_2, TCLK2),
+	PINMUX_IPSR_DATA(IP7_3_2, FSO_CFE_1),
+	PINMUX_IPSR_DATA(IP7_5_4, PWM2),
+	PINMUX_IPSR_DATA(IP7_5_4, TCLK3),
+	PINMUX_IPSR_DATA(IP7_5_4, FSO_TOE),
+	PINMUX_IPSR_DATA(IP7_6, PWM3),
+	PINMUX_IPSR_DATA(IP7_7, PWM4),
+	PINMUX_IPSR_DATA(IP7_9_8, SSI_SCK3),
+	PINMUX_IPSR_DATA(IP7_9_8, TPU0TO0),
+	PINMUX_IPSR_DATA(IP7_11_10, SSI_WS3),
+	PINMUX_IPSR_DATA(IP7_11_10, TPU0TO1),
+	PINMUX_IPSR_DATA(IP7_13_12, SSI_SDATA3),
+	PINMUX_IPSR_DATA(IP7_13_12, TPU0TO2),
+	PINMUX_IPSR_DATA(IP7_15_14, SSI_SCK4),
+	PINMUX_IPSR_DATA(IP7_15_14, TPU0TO3),
+	PINMUX_IPSR_DATA(IP7_16, SSI_WS4),
+	PINMUX_IPSR_DATA(IP7_17, SSI_SDATA4),
+	PINMUX_IPSR_DATA(IP7_18, AUDIO_CLKOUT),
+	PINMUX_IPSR_DATA(IP7_19, AUDIO_CLKA),
+	PINMUX_IPSR_DATA(IP7_20, AUDIO_CLKB),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	GPIO_FN(DU1_DB2_C0_DATA12), GPIO_FN(DU1_DB3_C1_DATA13),
+	GPIO_FN(DU1_DB4_C2_DATA14), GPIO_FN(DU1_DB5_C3_DATA15),
+	GPIO_FN(DU1_DB6_C4), GPIO_FN(DU1_DB7_C5),
+	GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC),
+	GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(DU1_DISP), GPIO_FN(DU1_CDE),
+
+	GPIO_FN(D0), GPIO_FN(D1), GPIO_FN(D2), GPIO_FN(D3),
+	GPIO_FN(D4), GPIO_FN(D5), GPIO_FN(D6), GPIO_FN(D7),
+	GPIO_FN(D8), GPIO_FN(D9), GPIO_FN(D10), GPIO_FN(D11),
+	GPIO_FN(D12), GPIO_FN(D13), GPIO_FN(D14), GPIO_FN(D15),
+	GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
+	GPIO_FN(A4), GPIO_FN(A5), GPIO_FN(A6), GPIO_FN(A7),
+	GPIO_FN(A8), GPIO_FN(A9), GPIO_FN(A10), GPIO_FN(A11),
+	GPIO_FN(A12), GPIO_FN(A13), GPIO_FN(A14), GPIO_FN(A15),
+
+	GPIO_FN(A16), GPIO_FN(A17), GPIO_FN(A18), GPIO_FN(A19),
+	GPIO_FN(CS1_A26), GPIO_FN(EX_CS0), GPIO_FN(EX_CS1), GPIO_FN(EX_CS2),
+	GPIO_FN(EX_CS3), GPIO_FN(EX_CS4), GPIO_FN(EX_CS5), GPIO_FN(BS),
+	GPIO_FN(RD), GPIO_FN(RD_WR), GPIO_FN(WE0), GPIO_FN(WE1),
+	GPIO_FN(EX_WAIT0), GPIO_FN(IRQ0), GPIO_FN(IRQ1), GPIO_FN(IRQ2),
+	GPIO_FN(IRQ3), GPIO_FN(CS0),
+
+	GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB), GPIO_FN(VI0_HSYNC),
+	GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_D0_B0_C0), GPIO_FN(VI0_D1_B1_C1),
+	GPIO_FN(VI0_D2_B2_C2), GPIO_FN(VI0_D3_B3_C3), GPIO_FN(VI0_D4_B4_C4),
+	GPIO_FN(VI0_D5_B5_C5), GPIO_FN(VI0_D6_B6_C6), GPIO_FN(VI0_D7_B7_C7),
+	GPIO_FN(VI0_D8_G0_Y0), GPIO_FN(VI0_D9_G1_Y1), GPIO_FN(VI0_D10_G2_Y2),
+	GPIO_FN(VI0_D11_G3_Y3), GPIO_FN(VI0_FIELD),
+
+	GPIO_FN(VI1_CLK), GPIO_FN(VI1_CLKENB), GPIO_FN(VI1_HSYNC),
+	GPIO_FN(VI1_VSYNC), GPIO_FN(VI1_D0_B0_C0), GPIO_FN(VI1_D1_B1_C1),
+	GPIO_FN(VI1_D2_B2_C2), GPIO_FN(VI1_D3_B3_C3), GPIO_FN(VI1_D4_B4_C4),
+	GPIO_FN(VI1_D5_B5_C5), GPIO_FN(VI1_D6_B6_C6), GPIO_FN(VI1_D7_B7_C7),
+	GPIO_FN(VI1_D8_G0_Y0), GPIO_FN(VI1_D9_G1_Y1), GPIO_FN(VI1_D10_G2_Y2),
+	GPIO_FN(VI1_D11_G3_Y3), GPIO_FN(VI1_FIELD),
+
+	GPIO_FN(VI3_D10_Y2), GPIO_FN(VI3_FIELD),
+
+	GPIO_FN(VI4_CLK),
+
+	GPIO_FN(VI5_CLK), GPIO_FN(VI5_D9_Y1), GPIO_FN(VI5_D10_Y2),
+	GPIO_FN(VI5_D11_Y3), GPIO_FN(VI5_FIELD),
+
+	GPIO_FN(HRTS0), GPIO_FN(HCTS1), GPIO_FN(SCK0), GPIO_FN(CTS0),
+	GPIO_FN(RTS0), GPIO_FN(TX0), GPIO_FN(RX0), GPIO_FN(SCK1),
+	GPIO_FN(CTS1), GPIO_FN(RTS1), GPIO_FN(TX1), GPIO_FN(RX1),
+	GPIO_FN(SCIF_CLK), GPIO_FN(CAN0_TX), GPIO_FN(CAN0_RX), GPIO_FN(CAN_CLK),
+	GPIO_FN(CAN1_TX), GPIO_FN(CAN1_RX),
+
+	GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), GPIO_FN(SD0_DAT0),
+	GPIO_FN(SD0_DAT1), GPIO_FN(SD0_DAT2), GPIO_FN(SD0_DAT3),
+	GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), GPIO_FN(ADICLK),
+	GPIO_FN(ADICS_SAMP), GPIO_FN(ADIDATA), GPIO_FN(ADICHS0),
+	GPIO_FN(ADICHS1), GPIO_FN(ADICHS2), GPIO_FN(AVS1),
+	GPIO_FN(AVS2),
+
+	GPIO_FN(DU0_DR0_DATA0), GPIO_FN(DU0_DR1_DATA1),
+	GPIO_FN(DU0_DR2_Y4_DATA2), GPIO_FN(DU0_DR3_Y5_DATA3),
+	GPIO_FN(DU0_DR4_Y6_DATA4), GPIO_FN(DU0_DR5_Y7_DATA5),
+	GPIO_FN(DU0_DR6_Y8_DATA6), GPIO_FN(DU0_DR7_Y9_DATA7),
+	GPIO_FN(DU0_DG0_DATA8), GPIO_FN(DU0_DG1_DATA9),
+	GPIO_FN(DU0_DG2_C6_DATA10), GPIO_FN(DU0_DG3_C7_DATA11),
+	GPIO_FN(DU0_DG4_Y0_DATA12), GPIO_FN(DU0_DG5_Y1_DATA13),
+	GPIO_FN(DU0_DG6_Y2_DATA14), GPIO_FN(DU0_DG7_Y3_DATA15),
+	GPIO_FN(DU0_DB0), GPIO_FN(DU0_DB1),
+	GPIO_FN(DU0_DB2_C0), GPIO_FN(DU0_DB3_C1), GPIO_FN(DU0_DB4_C2),
+	GPIO_FN(DU0_DB5_C3), GPIO_FN(DU0_DB6_C4), GPIO_FN(DU0_DB7_C5),
+
+	GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(DU0_EXVSYNC_DU0_VSYNC),
+	GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(DU0_DISP),
+	GPIO_FN(DU0_CDE), GPIO_FN(DU1_DR2_Y4_DATA0), GPIO_FN(DU1_DR3_Y5_DATA1),
+	GPIO_FN(DU1_DR4_Y6_DATA2), GPIO_FN(DU1_DR5_Y7_DATA3),
+	GPIO_FN(DU1_DR6_DATA4), GPIO_FN(DU1_DR7_DATA5),
+	GPIO_FN(DU1_DG2_C6_DATA6), GPIO_FN(DU1_DG3_C7_DATA7),
+	GPIO_FN(DU1_DG4_Y0_DATA8), GPIO_FN(DU1_DG5_Y1_DATA9),
+	GPIO_FN(DU1_DG6_Y2_DATA10), GPIO_FN(DU1_DG7_Y3_DATA11),
+	GPIO_FN(A20), GPIO_FN(MOSI_IO0), GPIO_FN(A21), GPIO_FN(MISO_IO1),
+	GPIO_FN(A22), GPIO_FN(IO2), GPIO_FN(A23), GPIO_FN(IO3),
+	GPIO_FN(A24), GPIO_FN(SPCLK), GPIO_FN(A25), GPIO_FN(SSL),
+
+	GPIO_FN(VI2_CLK), GPIO_FN(AVB_RX_CLK), GPIO_FN(VI2_CLKENB),
+	GPIO_FN(AVB_RX_DV), GPIO_FN(VI2_HSYNC), GPIO_FN(AVB_RXD0),
+	GPIO_FN(VI2_VSYNC), GPIO_FN(AVB_RXD1), GPIO_FN(VI2_D0_C0),
+	GPIO_FN(AVB_RXD2), GPIO_FN(VI2_D1_C1), GPIO_FN(AVB_RXD3),
+	GPIO_FN(VI2_D2_C2), GPIO_FN(AVB_RXD4), GPIO_FN(VI2_D3_C3),
+	GPIO_FN(AVB_RXD5), GPIO_FN(VI2_D4_C4), GPIO_FN(AVB_RXD6),
+	GPIO_FN(VI2_D5_C5), GPIO_FN(AVB_RXD7), GPIO_FN(VI2_D6_C6),
+	GPIO_FN(AVB_RX_ER), GPIO_FN(VI2_D7_C7), GPIO_FN(AVB_COL),
+	GPIO_FN(VI2_D8_Y0), GPIO_FN(AVB_TXD3), GPIO_FN(VI2_D9_Y1),
+	GPIO_FN(AVB_TX_EN), GPIO_FN(VI2_D10_Y2), GPIO_FN(AVB_TXD0),
+	GPIO_FN(VI2_D11_Y3), GPIO_FN(AVB_TXD1), GPIO_FN(VI2_FIELD),
+	GPIO_FN(AVB_TXD2),
+
+	GPIO_FN(VI3_CLK), GPIO_FN(AVB_TX_CLK), GPIO_FN(VI3_CLKENB),
+	GPIO_FN(AVB_TXD4), GPIO_FN(VI3_HSYNC), GPIO_FN(AVB_TXD5),
+	GPIO_FN(VI3_VSYNC), GPIO_FN(AVB_TXD6), GPIO_FN(VI3_D0_C0),
+	GPIO_FN(AVB_TXD7), GPIO_FN(VI3_D1_C1), GPIO_FN(AVB_TX_ER),
+	GPIO_FN(VI3_D2_C2), GPIO_FN(AVB_GTX_CLK), GPIO_FN(VI3_D3_C3),
+	GPIO_FN(AVB_MDC), GPIO_FN(VI3_D4_C4), GPIO_FN(AVB_MDIO),
+	GPIO_FN(VI3_D5_C5), GPIO_FN(AVB_LINK), GPIO_FN(VI3_D6_C6),
+	GPIO_FN(AVB_MAGIC), GPIO_FN(VI3_D7_C7), GPIO_FN(AVB_PHY_INT),
+	GPIO_FN(VI3_D8_Y0), GPIO_FN(AVB_CRS), GPIO_FN(VI3_D9_Y1),
+	GPIO_FN(AVB_GTXREFCLK), GPIO_FN(VI3_D11_Y3),
+
+	GPIO_FN(VI4_CLKENB), GPIO_FN(VI0_D12_G4_Y4), GPIO_FN(VI4_HSYNC),
+	GPIO_FN(VI0_D13_G5_Y5), GPIO_FN(VI4_VSYNC), GPIO_FN(VI0_D14_G6_Y6),
+	GPIO_FN(VI4_D0_C0), GPIO_FN(VI0_D15_G7_Y7), GPIO_FN(VI4_D1_C1),
+	GPIO_FN(VI0_D16_R0), GPIO_FN(VI1_D12_G4_Y4_0), GPIO_FN(VI4_D2_C2),
+	GPIO_FN(VI0_D17_R1), GPIO_FN(VI1_D13_G5_Y5_0), GPIO_FN(VI4_D3_C3),
+	GPIO_FN(VI0_D18_R2), GPIO_FN(VI1_D14_G6_Y6_0), GPIO_FN(VI4_D4_C4),
+	GPIO_FN(VI0_D19_R3), GPIO_FN(VI1_D15_G7_Y7_0), GPIO_FN(VI4_D5_C5),
+	GPIO_FN(VI0_D20_R4), GPIO_FN(VI2_D12_Y4), GPIO_FN(VI4_D6_C6),
+	GPIO_FN(VI0_D21_R5), GPIO_FN(VI2_D13_Y5), GPIO_FN(VI4_D7_C7),
+	GPIO_FN(VI0_D22_R6), GPIO_FN(VI2_D14_Y6), GPIO_FN(VI4_D8_Y0),
+	GPIO_FN(VI0_D23_R7), GPIO_FN(VI2_D15_Y7), GPIO_FN(VI4_D9_Y1),
+	GPIO_FN(VI3_D12_Y4), GPIO_FN(VI4_D10_Y2), GPIO_FN(VI3_D13_Y5),
+	GPIO_FN(VI4_D11_Y3), GPIO_FN(VI3_D14_Y6), GPIO_FN(VI4_FIELD),
+	GPIO_FN(VI3_D15_Y7),
+
+	GPIO_FN(VI5_CLKENB), GPIO_FN(VI1_D12_G4_Y4_1), GPIO_FN(VI5_HSYNC),
+	GPIO_FN(VI1_D13_G5_Y5_1), GPIO_FN(VI5_VSYNC), GPIO_FN(VI1_D14_G6_Y6_1),
+	GPIO_FN(VI5_D0_C0), GPIO_FN(VI1_D15_G7_Y7_1), GPIO_FN(VI5_D1_C1),
+	GPIO_FN(VI1_D16_R0), GPIO_FN(VI5_D2_C2), GPIO_FN(VI1_D17_R1),
+	GPIO_FN(VI5_D3_C3), GPIO_FN(VI1_D18_R2), GPIO_FN(VI5_D4_C4),
+	GPIO_FN(VI1_D19_R3), GPIO_FN(VI5_D5_C5), GPIO_FN(VI1_D20_R4),
+	GPIO_FN(VI5_D6_C6), GPIO_FN(VI1_D21_R5), GPIO_FN(VI5_D7_C7),
+	GPIO_FN(VI1_D22_R6), GPIO_FN(VI5_D8_Y0), GPIO_FN(VI1_D23_R7),
+
+	GPIO_FN(MSIOF0_SCK), GPIO_FN(HSCK0), GPIO_FN(MSIOF0_SYNC),
+	GPIO_FN(HCTS0), GPIO_FN(MSIOF0_TXD), GPIO_FN(HTX0),
+	GPIO_FN(MSIOF0_RXD), GPIO_FN(HRX0), GPIO_FN(MSIOF1_SCK),
+	GPIO_FN(HSCK1), GPIO_FN(MSIOF1_SYNC), GPIO_FN(HRTS1),
+	GPIO_FN(MSIOF1_TXD), GPIO_FN(HTX1), GPIO_FN(MSIOF1_RXD),
+	GPIO_FN(HRX1), GPIO_FN(DRACK0), GPIO_FN(SCK2),
+	GPIO_FN(DACK0), GPIO_FN(TX2), GPIO_FN(DREQ0),
+	GPIO_FN(RX2), GPIO_FN(DACK1), GPIO_FN(SCK3),
+	GPIO_FN(TX3), GPIO_FN(DREQ1), GPIO_FN(RX3),
+
+	GPIO_FN(PWM0), GPIO_FN(TCLK1), GPIO_FN(FSO_CFE_0),
+	GPIO_FN(PWM1), GPIO_FN(TCLK2), GPIO_FN(FSO_CFE_1),
+	GPIO_FN(PWM2), GPIO_FN(TCLK3), GPIO_FN(FSO_TOE),
+	GPIO_FN(PWM3), GPIO_FN(PWM4),
+	GPIO_FN(SSI_SCK3), GPIO_FN(TPU0TO0),
+	GPIO_FN(SSI_WS3), GPIO_FN(TPU0TO1),
+	GPIO_FN(SSI_SDATA3), GPIO_FN(TPU0TO2),
+	GPIO_FN(SSI_SCK4), GPIO_FN(TPU0TO3),
+	GPIO_FN(SSI_WS4), GPIO_FN(SSI_SDATA4),
+	GPIO_FN(AUDIO_CLKOUT), GPIO_FN(AUDIO_CLKA), GPIO_FN(AUDIO_CLKB),
+
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_0_28_FN, FN_IP1_4,
+		GP_0_27_FN, FN_IP1_3,
+		GP_0_26_FN, FN_IP1_2,
+		GP_0_25_FN, FN_IP1_1,
+		GP_0_24_FN, FN_IP1_0,
+		GP_0_23_FN, FN_IP0_23,
+		GP_0_22_FN, FN_IP0_22,
+		GP_0_21_FN, FN_IP0_21,
+		GP_0_20_FN, FN_IP0_20,
+		GP_0_19_FN, FN_IP0_19,
+		GP_0_18_FN, FN_IP0_18,
+		GP_0_17_FN, FN_IP0_17,
+		GP_0_16_FN, FN_IP0_16,
+		GP_0_15_FN, FN_IP0_15,
+		GP_0_14_FN, FN_IP0_14,
+		GP_0_13_FN, FN_IP0_13,
+		GP_0_12_FN, FN_IP0_12,
+		GP_0_11_FN, FN_IP0_11,
+		GP_0_10_FN, FN_IP0_10,
+		GP_0_9_FN, FN_IP0_9,
+		GP_0_8_FN, FN_IP0_8,
+		GP_0_7_FN, FN_IP0_7,
+		GP_0_6_FN, FN_IP0_6,
+		GP_0_5_FN, FN_IP0_5,
+		GP_0_4_FN, FN_IP0_4,
+		GP_0_3_FN, FN_IP0_3,
+		GP_0_2_FN, FN_IP0_2,
+		GP_0_1_FN, FN_IP0_1,
+		GP_0_0_FN, FN_IP0_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_22_FN, FN_DU1_CDE,
+		GP_1_21_FN, FN_DU1_DISP,
+		GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+		GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
+		GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
+		GP_1_17_FN, FN_DU1_DB7_C5,
+		GP_1_16_FN, FN_DU1_DB6_C4,
+		GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
+		GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
+		GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
+		GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
+		GP_1_11_FN, FN_IP1_16,
+		GP_1_10_FN, FN_IP1_15,
+		GP_1_9_FN, FN_IP1_14,
+		GP_1_8_FN, FN_IP1_13,
+		GP_1_7_FN, FN_IP1_12,
+		GP_1_6_FN, FN_IP1_11,
+		GP_1_5_FN, FN_IP1_10,
+		GP_1_4_FN, FN_IP1_9,
+		GP_1_3_FN, FN_IP1_8,
+		GP_1_2_FN, FN_IP1_7,
+		GP_1_1_FN, FN_IP1_6,
+		GP_1_0_FN, FN_IP1_5, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_A15,
+		GP_2_30_FN, FN_A14,
+		GP_2_29_FN, FN_A13,
+		GP_2_28_FN, FN_A12,
+		GP_2_27_FN, FN_A11,
+		GP_2_26_FN, FN_A10,
+		GP_2_25_FN, FN_A9,
+		GP_2_24_FN, FN_A8,
+		GP_2_23_FN, FN_A7,
+		GP_2_22_FN, FN_A6,
+		GP_2_21_FN, FN_A5,
+		GP_2_20_FN, FN_A4,
+		GP_2_19_FN, FN_A3,
+		GP_2_18_FN, FN_A2,
+		GP_2_17_FN, FN_A1,
+		GP_2_16_FN, FN_A0,
+		GP_2_15_FN, FN_D15,
+		GP_2_14_FN, FN_D14,
+		GP_2_13_FN, FN_D13,
+		GP_2_12_FN, FN_D12,
+		GP_2_11_FN, FN_D11,
+		GP_2_10_FN, FN_D10,
+		GP_2_9_FN, FN_D9,
+		GP_2_8_FN, FN_D8,
+		GP_2_7_FN, FN_D7,
+		GP_2_6_FN, FN_D6,
+		GP_2_5_FN, FN_D5,
+		GP_2_4_FN, FN_D4,
+		GP_2_3_FN, FN_D3,
+		GP_2_2_FN, FN_D2,
+		GP_2_1_FN, FN_D1,
+		GP_2_0_FN, FN_D0 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_3_27_FN, FN_CS0,
+		GP_3_26_FN, FN_IP1_22,
+		GP_3_25_FN, FN_IP1_21,
+		GP_3_24_FN, FN_IP1_20,
+		GP_3_23_FN, FN_IP1_19,
+		GP_3_22_FN, FN_IRQ3,
+		GP_3_21_FN, FN_IRQ2,
+		GP_3_20_FN, FN_IRQ1,
+		GP_3_19_FN, FN_IRQ0,
+		GP_3_18_FN, FN_EX_WAIT0,
+		GP_3_17_FN, FN_WE1,
+		GP_3_16_FN, FN_WE0,
+		GP_3_15_FN, FN_RD_WR,
+		GP_3_14_FN, FN_RD,
+		GP_3_13_FN, FN_BS,
+		GP_3_12_FN, FN_EX_CS5,
+		GP_3_11_FN, FN_EX_CS4,
+		GP_3_10_FN, FN_EX_CS3,
+		GP_3_9_FN, FN_EX_CS2,
+		GP_3_8_FN, FN_EX_CS1,
+		GP_3_7_FN, FN_EX_CS0,
+		GP_3_6_FN, FN_CS1_A26,
+		GP_3_5_FN, FN_IP1_18,
+		GP_3_4_FN, FN_IP1_17,
+		GP_3_3_FN, FN_A19,
+		GP_3_2_FN, FN_A18,
+		GP_3_1_FN, FN_A17,
+		GP_3_0_FN, FN_A16 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_16_FN, FN_VI0_FIELD,
+		GP_4_15_FN, FN_VI0_D11_G3_Y3,
+		GP_4_14_FN, FN_VI0_D10_G2_Y2,
+		GP_4_13_FN, FN_VI0_D9_G1_Y1,
+		GP_4_12_FN, FN_VI0_D8_G0_Y0,
+		GP_4_11_FN, FN_VI0_D7_B7_C7,
+		GP_4_10_FN, FN_VI0_D6_B6_C6,
+		GP_4_9_FN, FN_VI0_D5_B5_C5,
+		GP_4_8_FN, FN_VI0_D4_B4_C4,
+		GP_4_7_FN, FN_VI0_D3_B3_C3,
+		GP_4_6_FN, FN_VI0_D2_B2_C2,
+		GP_4_5_FN, FN_VI0_D1_B1_C1,
+		GP_4_4_FN, FN_VI0_D0_B0_C0,
+		GP_4_3_FN, FN_VI0_VSYNC,
+		GP_4_2_FN, FN_VI0_HSYNC,
+		GP_4_1_FN, FN_VI0_CLKENB,
+		GP_4_0_FN, FN_VI0_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_16_FN, FN_VI1_FIELD,
+		GP_5_15_FN, FN_VI1_D11_G3_Y3,
+		GP_5_14_FN, FN_VI1_D10_G2_Y2,
+		GP_5_13_FN, FN_VI1_D9_G1_Y1,
+		GP_5_12_FN, FN_VI1_D8_G0_Y0,
+		GP_5_11_FN, FN_VI1_D7_B7_C7,
+		GP_5_10_FN, FN_VI1_D6_B6_C6,
+		GP_5_9_FN, FN_VI1_D5_B5_C5,
+		GP_5_8_FN, FN_VI1_D4_B4_C4,
+		GP_5_7_FN, FN_VI1_D3_B3_C3,
+		GP_5_6_FN, FN_VI1_D2_B2_C2,
+		GP_5_5_FN, FN_VI1_D1_B1_C1,
+		GP_5_4_FN, FN_VI1_D0_B0_C0,
+		GP_5_3_FN, FN_VI1_VSYNC,
+		GP_5_2_FN, FN_VI1_HSYNC,
+		GP_5_1_FN, FN_VI1_CLKENB,
+		GP_5_0_FN, FN_VI1_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_16_FN, FN_IP2_16,
+		GP_6_15_FN, FN_IP2_15,
+		GP_6_14_FN, FN_IP2_14,
+		GP_6_13_FN, FN_IP2_13,
+		GP_6_12_FN, FN_IP2_12,
+		GP_6_11_FN, FN_IP2_11,
+		GP_6_10_FN, FN_IP2_10,
+		GP_6_9_FN, FN_IP2_9,
+		GP_6_8_FN, FN_IP2_8,
+		GP_6_7_FN, FN_IP2_7,
+		GP_6_6_FN, FN_IP2_6,
+		GP_6_5_FN, FN_IP2_5,
+		GP_6_4_FN, FN_IP2_4,
+		GP_6_3_FN, FN_IP2_3,
+		GP_6_2_FN, FN_IP2_2,
+		GP_6_1_FN, FN_IP2_1,
+		GP_6_0_FN, FN_IP2_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_16_FN, FN_VI3_FIELD,
+		GP_7_15_FN, FN_IP3_14,
+		GP_7_14_FN, FN_VI3_D10_Y2,
+		GP_7_13_FN, FN_IP3_13,
+		GP_7_12_FN, FN_IP3_12,
+		GP_7_11_FN, FN_IP3_11,
+		GP_7_10_FN, FN_IP3_10,
+		GP_7_9_FN, FN_IP3_9,
+		GP_7_8_FN, FN_IP3_8,
+		GP_7_7_FN, FN_IP3_7,
+		GP_7_6_FN, FN_IP3_6,
+		GP_7_5_FN, FN_IP3_5,
+		GP_7_4_FN, FN_IP3_4,
+		GP_7_3_FN, FN_IP3_3,
+		GP_7_2_FN, FN_IP3_2,
+		GP_7_1_FN, FN_IP3_1,
+		GP_7_0_FN, FN_IP3_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_8_16_FN, FN_IP4_24,
+		GP_8_15_FN, FN_IP4_23,
+		GP_8_14_FN, FN_IP4_22,
+		GP_8_13_FN, FN_IP4_21,
+		GP_8_12_FN, FN_IP4_20_19,
+		GP_8_11_FN, FN_IP4_18_17,
+		GP_8_10_FN, FN_IP4_16_15,
+		GP_8_9_FN, FN_IP4_14_13,
+		GP_8_8_FN, FN_IP4_12_11,
+		GP_8_7_FN, FN_IP4_10_9,
+		GP_8_6_FN, FN_IP4_8_7,
+		GP_8_5_FN, FN_IP4_6_5,
+		GP_8_4_FN, FN_IP4_4,
+		GP_8_3_FN, FN_IP4_3_2,
+		GP_8_2_FN, FN_IP4_1,
+		GP_8_1_FN, FN_IP4_0,
+		GP_8_0_FN, FN_VI4_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_9_16_FN, FN_VI5_FIELD,
+		GP_9_15_FN, FN_VI5_D11_Y3,
+		GP_9_14_FN, FN_VI5_D10_Y2,
+		GP_9_13_FN, FN_VI5_D9_Y1,
+		GP_9_12_FN, FN_IP5_11,
+		GP_9_11_FN, FN_IP5_10,
+		GP_9_10_FN, FN_IP5_9,
+		GP_9_9_FN, FN_IP5_8,
+		GP_9_8_FN, FN_IP5_7,
+		GP_9_7_FN, FN_IP5_6,
+		GP_9_6_FN, FN_IP5_5,
+		GP_9_5_FN, FN_IP5_4,
+		GP_9_4_FN, FN_IP5_3,
+		GP_9_3_FN, FN_IP5_2,
+		GP_9_2_FN, FN_IP5_1,
+		GP_9_1_FN, FN_IP5_0,
+		GP_9_0_FN, FN_VI5_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
+		GP_10_31_FN, FN_CAN1_RX,
+		GP_10_30_FN, FN_CAN1_TX,
+		GP_10_29_FN, FN_CAN_CLK,
+		GP_10_28_FN, FN_CAN0_RX,
+		GP_10_27_FN, FN_CAN0_TX,
+		GP_10_26_FN, FN_SCIF_CLK,
+		GP_10_25_FN, FN_IP6_18_17,
+		GP_10_24_FN, FN_IP6_16,
+		GP_10_23_FN, FN_IP6_15_14,
+		GP_10_22_FN, FN_IP6_13_12,
+		GP_10_21_FN, FN_IP6_11_10,
+		GP_10_20_FN, FN_IP6_9_8,
+		GP_10_19_FN, FN_RX1,
+		GP_10_18_FN, FN_TX1,
+		GP_10_17_FN, FN_RTS1,
+		GP_10_16_FN, FN_CTS1,
+		GP_10_15_FN, FN_SCK1,
+		GP_10_14_FN, FN_RX0,
+		GP_10_13_FN, FN_TX0,
+		GP_10_12_FN, FN_RTS0,
+		GP_10_11_FN, FN_CTS0,
+		GP_10_10_FN, FN_SCK0,
+		GP_10_9_FN, FN_IP6_7,
+		GP_10_8_FN, FN_IP6_6,
+		GP_10_7_FN, FN_HCTS1,
+		GP_10_6_FN, FN_IP6_5,
+		GP_10_5_FN, FN_IP6_4,
+		GP_10_4_FN, FN_IP6_3,
+		GP_10_3_FN, FN_IP6_2,
+		GP_10_2_FN, FN_HRTS0,
+		GP_10_1_FN, FN_IP6_1,
+		GP_10_0_FN, FN_IP6_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_11_29_FN, FN_AVS2,
+		GP_11_28_FN, FN_AVS1,
+		GP_11_27_FN, FN_ADICHS2,
+		GP_11_26_FN, FN_ADICHS1,
+		GP_11_25_FN, FN_ADICHS0,
+		GP_11_24_FN, FN_ADIDATA,
+		GP_11_23_FN, FN_ADICS_SAMP,
+		GP_11_22_FN, FN_ADICLK,
+		GP_11_21_FN, FN_IP7_20,
+		GP_11_20_FN, FN_IP7_19,
+		GP_11_19_FN, FN_IP7_18,
+		GP_11_18_FN, FN_IP7_17,
+		GP_11_17_FN, FN_IP7_16,
+		GP_11_16_FN, FN_IP7_15_14,
+		GP_11_15_FN, FN_IP7_13_12,
+		GP_11_14_FN, FN_IP7_11_10,
+		GP_11_13_FN, FN_IP7_9_8,
+		GP_11_12_FN, FN_SD0_WP,
+		GP_11_11_FN, FN_SD0_CD,
+		GP_11_10_FN, FN_SD0_DAT3,
+		GP_11_9_FN, FN_SD0_DAT2,
+		GP_11_8_FN, FN_SD0_DAT1,
+		GP_11_7_FN, FN_SD0_DAT0,
+		GP_11_6_FN, FN_SD0_CMD,
+		GP_11_5_FN, FN_SD0_CLK,
+		GP_11_4_FN, FN_IP7_7,
+		GP_11_3_FN, FN_IP7_6,
+		GP_11_2_FN, FN_IP7_5_4,
+		GP_11_1_FN, FN_IP7_3_2,
+		GP_11_0_FN, FN_IP7_1_0 }
+	},
+	/* IPSR0 */
+	{ PINMUX_CFG_REG("IPSR0", 0xE6060040, 32 ,1) {
+		/* IP0_31 [1] */
+		0, 0,
+		/* IP0_30 [1] */
+		0, 0,
+		/* IP0_29 [1] */
+		0, 0,
+		/* IP0_28 [1] */
+		0, 0,
+		/* IP0_27 [1] */
+		0, 0,
+		/* IP0_26 [1] */
+		0, 0,
+		/* IP0_25 [1] */
+		0, 0,
+		/* IP0_24 [1] */
+		0, 0,
+		/* IP0_23 [1] */
+		FN_DU0_DB7_C5, 0,
+		/* IP0_22 [1] */
+		FN_DU0_DB6_C4, 0,
+		/* IP0_21 [1] */
+		FN_DU0_DB5_C3, 0,
+		/* IP0_20 [1] */
+		FN_DU0_DB4_C2, 0,
+		/* IP0_19 [1] */
+		FN_DU0_DB3_C1, 0,
+		/* IP0_18 [1] */
+		FN_DU0_DB2_C0, 0,
+		/* IP0_17 [1] */
+		FN_DU0_DB1, 0,
+		/* IP0_16 [1] */
+		FN_DU0_DB0, 0,
+		/* IP0_15 [1] */
+		FN_DU0_DG7_Y3_DATA15, 0,
+		/* IP0_14 [1] */
+		FN_DU0_DG6_Y2_DATA14, 0,
+		/* IP0_13 [1] */
+		FN_DU0_DG5_Y1_DATA13, 0,
+		/* IP0_12 [1] */
+		FN_DU0_DG4_Y0_DATA12, 0,
+		/* IP0_11 [1] */
+		FN_DU0_DG3_C7_DATA11, 0,
+		/* IP0_10 [1] */
+		FN_DU0_DG2_C6_DATA10, 0,
+		/* IP0_9 [1] */
+		FN_DU0_DG1_DATA9, 0,
+		/* IP0_8 [1] */
+		FN_DU0_DG0_DATA8, 0,
+		/* IP0_7 [1] */
+		FN_DU0_DR7_Y9_DATA7, 0,
+		/* IP0_6 [1] */
+		FN_DU0_DR6_Y8_DATA6, 0,
+		/* IP0_5 [1] */
+		FN_DU0_DR5_Y7_DATA5, 0,
+		/* IP0_4 [1] */
+		FN_DU0_DR4_Y6_DATA4, 0,
+		/* IP0_3 [1] */
+		FN_DU0_DR3_Y5_DATA3, 0,
+		/* IP0_2 [1] */
+		FN_DU0_DR2_Y4_DATA2, 0,
+		/* IP0_1 [1] */
+		FN_DU0_DR1_DATA1, 0,
+		/* IP0_0 [1] */
+		FN_DU0_DR0_DATA0, 0, }
+	},
+	/* IPSR1 */
+	{ PINMUX_CFG_REG("IPSR1", 0xE6060044, 32, 1) {
+		/* IP1_31 [1] */
+		0, 0,
+		/* IP1_30 [1] */
+		0, 0,
+		/* IP1_29 [1] */
+		0, 0,
+		/* IP1_28 [1] */
+		0, 0,
+		/* IP1_27 [1] */
+		0, 0,
+		/* IP1_26 [1] */
+		0, 0,
+		/* IP1_25 [1] */
+		0, 0,
+		/* IP1_24 [1] */
+		0, 0,
+		/* IP1_23 [1] */
+		0, 0,
+		/* IP1_22 [1] */
+		FN_A25, FN_SSL,
+		/* IP1_21 [1] */
+		FN_A24, FN_SPCLK,
+		/* IP1_20 [1] */
+		FN_A23, FN_IO3,
+		/* IP1_19 [1] */
+		FN_A22, FN_IO2,
+		/* IP1_18 [1] */
+		FN_A21, FN_MISO_IO1,
+		/* IP1_17 [1] */
+		FN_A20, FN_MOSI_IO0,
+		/* IP1_16 [1] */
+		FN_DU1_DG7_Y3_DATA11, 0,
+		/* IP1_15 [1] */
+		FN_DU1_DG6_Y2_DATA10, 0,
+		/* IP1_14 [1] */
+		FN_DU1_DG5_Y1_DATA9, 0,
+		/* IP1_13 [1] */
+		FN_DU1_DG4_Y0_DATA8, 0,
+		/* IP1_12 [1] */
+		FN_DU1_DG3_C7_DATA7, 0,
+		/* IP1_11 [1] */
+		FN_DU1_DG2_C6_DATA6, 0,
+		/* IP1_10 [1] */
+		FN_DU1_DR7_DATA5, 0,
+		/* IP1_9 [1] */
+		FN_DU1_DR6_DATA4, 0,
+		/* IP1_8 [1] */
+		FN_DU1_DR5_Y7_DATA3, 0,
+		/* IP1_7 [1] */
+		FN_DU1_DR4_Y6_DATA2, 0,
+		/* IP1_6 [1] */
+		FN_DU1_DR3_Y5_DATA1, 0,
+		/* IP1_5 [1] */
+		FN_DU1_DR2_Y4_DATA0, 0,
+		/* IP1_4 [1] */
+		FN_DU0_CDE, 0,
+		/* IP1_3 [1] */
+		FN_DU0_DISP, 0,
+		/* IP1_2 [1] */
+		FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
+		/* IP1_1 [1] */
+		FN_DU0_EXVSYNC_DU0_VSYNC, 0,
+		/* IP1_0 [1] */
+		FN_DU0_EXHSYNC_DU0_HSYNC, 0, }
+	},
+	/* IPSR2 */
+	{ PINMUX_CFG_REG("IPSR2", 0xE6060048, 32, 1) {
+		/* IP2_31 [1] */
+		0, 0,
+		/* IP2_30 [1] */
+		0, 0,
+		/* IP2_29 [1] */
+		0, 0,
+		/* IP2_28 [1] */
+		0, 0,
+		/* IP2_27 [1] */
+		0, 0,
+		/* IP2_26 [1] */
+		0, 0,
+		/* IP2_25 [1] */
+		0, 0,
+		/* IP2_24 [1] */
+		0, 0,
+		/* IP2_23 [1] */
+		0, 0,
+		/* IP2_22 [1] */
+		0, 0,
+		/* IP2_21 [1] */
+		0, 0,
+		/* IP2_20 [1] */
+		0, 0,
+		/* IP2_19 [1] */
+		0, 0,
+		/* IP2_18 [1] */
+		0, 0,
+		/* IP2_17 [1] */
+		0, 0,
+		/* IP2_16 [1] */
+		FN_VI2_FIELD, FN_AVB_TXD2,
+		/* IP2_15 [1] */
+		FN_VI2_D11_Y3, FN_AVB_TXD1,
+		/* IP2_14 [1] */
+		FN_VI2_D10_Y2, FN_AVB_TXD0,
+		/* IP2_13 [1] */
+		FN_VI2_D9_Y1, FN_AVB_TX_EN,
+		/* IP2_12 [1] */
+		FN_VI2_D8_Y0, FN_AVB_TXD3,
+		/* IP2_11 [1] */
+		FN_VI2_D7_C7, FN_AVB_COL,
+		/* IP2_10 [1] */
+		FN_VI2_D6_C6, FN_AVB_RX_ER,
+		/* IP2_9 [1] */
+		FN_VI2_D5_C5, FN_AVB_RXD7,
+		/* IP2_8 [1] */
+		FN_VI2_D4_C4, FN_AVB_RXD6,
+		/* IP2_7 [1] */
+		FN_VI2_D3_C3, FN_AVB_RXD5,
+		/* IP2_6 [1] */
+		FN_VI2_D2_C2, FN_AVB_RXD4,
+		/* IP2_5 [1] */
+		FN_VI2_D1_C1, FN_AVB_RXD3,
+		/* IP2_4 [1] */
+		FN_VI2_D0_C0, FN_AVB_RXD2,
+		/* IP2_3 [1] */
+		FN_VI2_VSYNC, FN_AVB_RXD1,
+		/* IP2_2 [1] */
+		FN_VI2_HSYNC, FN_AVB_RXD0,
+		/* IP2_1 [1] */
+		FN_VI2_CLKENB, FN_AVB_RX_DV,
+		/* IP2_0 [1] */
+		FN_VI2_CLK, FN_AVB_RX_CLK, }
+	},
+	/* IPSR3 */
+	{ PINMUX_CFG_REG("IPSR3", 0xE606004C, 32, 1) {
+		/* IP3_31 [1] */
+		0, 0,
+		/* IP3_30 [1] */
+		0, 0,
+		/* IP3_29 [1] */
+		0, 0,
+		/* IP3_28 [1] */
+		0, 0,
+		/* IP3_27 [1] */
+		0, 0,
+		/* IP3_26 [1] */
+		0, 0,
+		/* IP3_25 [1] */
+		0, 0,
+		/* IP3_24 [1] */
+		0, 0,
+		/* IP3_23 [1] */
+		0, 0,
+		/* IP3_22 [1] */
+		0, 0,
+		/* IP3_21 [1] */
+		0, 0,
+		/* IP3_20 [1] */
+		0, 0,
+		/* IP3_19 [1] */
+		0, 0,
+		/* IP3_18 [1] */
+		0, 0,
+		/* IP3_17 [1] */
+		0, 0,
+		/* IP3_16 [1] */
+		0, 0,
+		/* IP3_15 [1] */
+		0, 0,
+		/* IP3_14 [1] */
+		FN_VI3_D11_Y3, 0,
+		/* IP3_13 [1] */
+		FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
+		/* IP3_12 [1] */
+		FN_VI3_D8_Y0, FN_AVB_CRS,
+		/* IP3_11 [1] */
+		FN_VI3_D7_C7, FN_AVB_PHY_INT,
+		/* IP3_10 [1] */
+		FN_VI3_D6_C6, FN_AVB_MAGIC,
+		/* IP3_9 [1] */
+		FN_VI3_D5_C5, FN_AVB_LINK,
+		/* IP3_8 [1] */
+		FN_VI3_D4_C4, FN_AVB_MDIO,
+		/* IP3_7 [1] */
+		FN_VI3_D3_C3, FN_AVB_MDC,
+		/* IP3_6 [1] */
+		FN_VI3_D2_C2, FN_AVB_GTX_CLK,
+		/* IP3_5 [1] */
+		FN_VI3_D1_C1, FN_AVB_TX_ER,
+		/* IP3_4 [1] */
+		FN_VI3_D0_C0, FN_AVB_TXD7,
+		/* IP3_3 [1] */
+		FN_VI3_VSYNC, FN_AVB_TXD6,
+		/* IP3_2 [1] */
+		FN_VI3_HSYNC, FN_AVB_TXD5,
+		/* IP3_1 [1] */
+		FN_VI3_CLKENB, FN_AVB_TXD4,
+		/* IP3_0 [1] */
+		FN_VI3_CLK, FN_AVB_TX_CLK,}
+	},
+	/* IPSR4 */
+	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
+			     1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 1, 2, 1, 1) {
+		/* IP4_31 [1] */
+		0, 0,
+		/* IP4_30 [1] */
+		0, 0,
+		/* IP4_29 [1] */
+		0, 0,
+		/* IP4_28 [1] */
+		0, 0,
+		/* IP4_27 [1] */
+		0, 0,
+		/* IP4_26 [1] */
+		0, 0,
+		/* IP4_25 [1] */
+		0, 0,
+		/* IP4_24 [1] */
+		FN_VI4_FIELD, FN_VI3_D15_Y7,
+		/* IP4_23 [1] */
+		FN_VI4_D11_Y3, FN_VI3_D14_Y6,
+		/* IP4_22 [1] */
+		FN_VI4_D10_Y2, FN_VI3_D13_Y5,
+		/* IP4_21 [1] */
+		FN_VI4_D9_Y1, FN_VI3_D12_Y4,
+		/* IP4_20_19 [2] */
+		FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
+		/* IP4_18_17 [2] */
+		FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
+		/* IP4_16_15 [2] */
+		FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
+		/* IP4_14_13 [2] */
+		FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
+		/* IP4_12_11 [2] */
+		FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7_0, 0,
+		/* IP4_10_9 [2] */
+		FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6_0, 0,
+		/* IP4_8_7 [2] */
+		FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5_0, 0,
+		/* IP4_6_5 [2] */
+		FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4_0, 0,
+		/* IP4_4 [1] */
+		FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
+		/* IP4_3_2 [2] */
+		FN_VI4_VSYNC, FN_VI0_D14_G6_Y6, 0, 0,
+		/* IP4_1 [1] */
+		FN_VI4_HSYNC, FN_VI0_D13_G5_Y5,
+		/* IP4_0 [1] */
+		FN_VI4_CLKENB, FN_VI0_D12_G4_Y4,}
+	},
+	/* IPSR5 */
+	{ PINMUX_CFG_REG("IPSR5", 0xE6060054, 32, 1) {
+		/* IP5_31 [1] */
+		0, 0,
+		/* IP5_30 [1] */
+		0, 0,
+		/* IP5_29 [1] */
+		0, 0,
+		/* IP5_28 [1] */
+		0, 0,
+		/* IP5_27 [1] */
+		0, 0,
+		/* IP5_26 [1] */
+		0, 0,
+		/* IP5_25 [1] */
+		0, 0,
+		/* IP5_24 [1] */
+		0, 0,
+		/* IP5_23 [1] */
+		0, 0,
+		/* IP5_22 [1] */
+		0, 0,
+		/* IP5_21 [1] */
+		0, 0,
+		/* IP5_20 [1] */
+		0, 0,
+		/* IP5_19 [1] */
+		0, 0,
+		/* IP5_18 [1] */
+		0, 0,
+		/* IP5_17 [1] */
+		0, 0,
+		/* IP5_16 [1] */
+		0, 0,
+		/* IP5_15 [1] */
+		0, 0,
+		/* IP5_14 [1] */
+		0, 0,
+		/* IP5_13 [1] */
+		0, 0,
+		/* IP5_12 [1] */
+		0, 0,
+		/* IP5_11 [1] */
+		FN_VI5_D8_Y0, FN_VI1_D23_R7,
+		/* IP5_10 [1] */
+		FN_VI5_D7_C7, FN_VI1_D22_R6,
+		/* IP5_9 [1] */
+		FN_VI5_D6_C6, FN_VI1_D21_R5,
+		/* IP5_8 [1] */
+		FN_VI5_D5_C5, FN_VI1_D20_R4,
+		/* IP5_7 [1] */
+		FN_VI5_D4_C4, FN_VI1_D19_R3,
+		/* IP5_6 [1] */
+		FN_VI5_D3_C3, FN_VI1_D18_R2,
+		/* IP5_5 [1] */
+		FN_VI5_D2_C2, FN_VI1_D17_R1,
+		/* IP5_4 [1] */
+		FN_VI5_D1_C1, FN_VI1_D16_R0,
+		/* IP5_3 [1] */
+		FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_1,
+		/* IP5_2 [1] */
+		FN_VI5_VSYNC, FN_VI1_D14_G6_Y6_1,
+		/* IP5_1 [1] */
+		FN_VI5_HSYNC, FN_VI1_D13_G5_Y5_1,
+		/* IP5_0 [1] */
+		FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_1,}
+	},
+	/* IPSR6 */
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     2, 1, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1) {
+		/* IP6_31 [1] */
+		0, 0,
+		/* IP6_30 [1] */
+		0, 0,
+		/* IP6_29 [1] */
+		0, 0,
+		/* IP6_28 [1] */
+		0, 0,
+		/* IP6_27 [1] */
+		0, 0,
+		/* IP6_26 [1] */
+		0, 0,
+		/* IP6_25 [1] */
+		0, 0,
+		/* IP6_24 [1] */
+		0, 0,
+		/* IP6_23 [1] */
+		0, 0,
+		/* IP6_22 [1] */
+		0, 0,
+		/* IP6_21 [1] */
+		0, 0,
+		/* IP6_20 [1] */
+		0, 0,
+		/* IP6_19 [1] */
+		0, 0,
+		/* IP6_18_17 [2] */
+		FN_DREQ1, FN_RX3, 0, 0,
+		/* IP6_16 [1] */
+		FN_TX3, 0,
+		/* IP6_15_14 [2] */
+		FN_DACK1, FN_SCK3, 0, 0,
+		/* IP6_13_12 [2] */
+		FN_DREQ0, FN_RX2, 0, 0,
+		/* IP6_11_10 [2] */
+		FN_DACK0, FN_TX2, 0, 0,
+		/* IP6_9_8 [2] */
+		FN_DRACK0, FN_SCK2, 0, 0,
+		/* IP6_7 [1] */
+		FN_MSIOF1_RXD, FN_HRX1,
+		/* IP6_6 [1] */
+		FN_MSIOF1_TXD, FN_HTX1,
+		/* IP6_5 [1] */
+		FN_MSIOF1_SYNC, FN_HRTS1,
+		/* IP6_4 [1] */
+		FN_MSIOF1_SCK, FN_HSCK1,
+		/* IP6_3 [1] */
+		FN_MSIOF0_RXD, FN_HRX0,
+		/* IP6_2 [1] */
+		FN_MSIOF0_TXD, FN_HTX0,
+		/* IP6_1 [1] */
+		FN_MSIOF0_SYNC, FN_HCTS0,
+		/* IP6_0 [1] */
+		FN_MSIOF0_SCK, FN_HSCK0, }
+	},
+	/* IPSR7 */
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
+			     1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+			     1, 1, 1, 1, 1, 2, 2, 2, 2, 1, 1, 2, 2, 2) {
+		/* IP7_31 [1] */
+		0, 0,
+		/* IP7_30 [1] */
+		0, 0,
+		/* IP7_29 [1] */
+		0, 0,
+		/* IP7_28 [1] */
+		0, 0,
+		/* IP7_27 [1] */
+		0, 0,
+		/* IP7_26 [1] */
+		0, 0,
+		/* IP7_25 [1] */
+		0, 0,
+		/* IP7_24 [1] */
+		0, 0,
+		/* IP7_23 [1] */
+		0, 0,
+		/* IP7_22 [1] */
+		0, 0,
+		/* IP7_21 [1] */
+		0, 0,
+		/* IP7_20 [1] */
+		FN_AUDIO_CLKB, 0,
+		/* IP7_19 [1] */
+		FN_AUDIO_CLKA, 0,
+		/* IP7_18 [1] */
+		FN_AUDIO_CLKOUT, 0,
+		/* IP7_17 [1] */
+		FN_SSI_SDATA4, 0,
+		/* IP7_16 [1] */
+		FN_SSI_WS4, 0,
+		/* IP7_15_14 [2] */
+		FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
+		/* IP7_13_12 [2] */
+		FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
+		/* IP7_11_10 [2] */
+		FN_SSI_WS3, FN_TPU0TO1, 0, 0,
+		/* IP7_9_8 [2] */
+		FN_SSI_SCK3, FN_TPU0TO0, 0, 0,
+		/* IP7_7 [1] */
+		FN_PWM4, 0,
+		/* IP7_6 [1] */
+		FN_PWM3, 0,
+		/* IP7_5_4 [2] */
+		FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
+		/* IP7_3_2 [2] */
+		FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
+		/* IP7_1_0 [2] */
+		FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0, }
+	},
+	/* MOD SEL */
+	{ PINMUX_CFG_REG("MOD_SEL", 0xE6060140, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		/* MOD_SEL [1] */
+		FN_SEL_VI1_0, FN_SEL_VI1_1, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_0_28_IN, GP_0_28_OUT,
+		GP_0_27_IN, GP_0_27_OUT,
+		GP_0_26_IN, GP_0_26_OUT,
+		GP_0_25_IN, GP_0_25_OUT,
+		GP_0_24_IN, GP_0_24_OUT,
+		GP_0_23_IN, GP_0_23_OUT,
+		GP_0_22_IN, GP_0_22_OUT,
+		GP_0_21_IN, GP_0_21_OUT,
+		GP_0_20_IN, GP_0_20_OUT,
+		GP_0_19_IN, GP_0_19_OUT,
+		GP_0_18_IN, GP_0_18_OUT,
+		GP_0_17_IN, GP_0_17_OUT,
+		GP_0_16_IN, GP_0_16_OUT,
+		GP_0_15_IN, GP_0_15_OUT,
+		GP_0_14_IN, GP_0_14_OUT,
+		GP_0_13_IN, GP_0_13_OUT,
+		GP_0_12_IN, GP_0_12_OUT,
+		GP_0_11_IN, GP_0_11_OUT,
+		GP_0_10_IN, GP_0_10_OUT,
+		GP_0_9_IN, GP_0_9_OUT,
+		GP_0_8_IN, GP_0_8_OUT,
+		GP_0_7_IN, GP_0_7_OUT,
+		GP_0_6_IN, GP_0_6_OUT,
+		GP_0_5_IN, GP_0_5_OUT,
+		GP_0_4_IN, GP_0_4_OUT,
+		GP_0_3_IN, GP_0_3_OUT,
+		GP_0_2_IN, GP_0_2_OUT,
+		GP_0_1_IN, GP_0_1_OUT,
+		GP_0_0_IN, GP_0_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_3_27_IN, GP_3_27_OUT,
+		GP_3_26_IN, GP_3_26_OUT,
+		GP_3_25_IN, GP_3_25_OUT,
+		GP_3_24_IN, GP_3_24_OUT,
+		GP_3_23_IN, GP_3_23_OUT,
+		GP_3_22_IN, GP_3_22_OUT,
+		GP_3_21_IN, GP_3_21_OUT,
+		GP_3_20_IN, GP_3_20_OUT,
+		GP_3_19_IN, GP_3_19_OUT,
+		GP_3_18_IN, GP_3_18_OUT,
+		GP_3_17_IN, GP_3_17_OUT,
+		GP_3_16_IN, GP_3_16_OUT,
+		GP_3_15_IN, GP_3_15_OUT,
+		GP_3_14_IN, GP_3_14_OUT,
+		GP_3_13_IN, GP_3_13_OUT,
+		GP_3_12_IN, GP_3_12_OUT,
+		GP_3_11_IN, GP_3_11_OUT,
+		GP_3_10_IN, GP_3_10_OUT,
+		GP_3_9_IN, GP_3_9_OUT,
+		GP_3_8_IN, GP_3_8_OUT,
+		GP_3_7_IN, GP_3_7_OUT,
+		GP_3_6_IN, GP_3_6_OUT,
+		GP_3_5_IN, GP_3_5_OUT,
+		GP_3_4_IN, GP_3_4_OUT,
+		GP_3_3_IN, GP_3_3_OUT,
+		GP_3_2_IN, GP_3_2_OUT,
+		GP_3_1_IN, GP_3_1_OUT,
+		GP_3_0_IN, GP_3_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_16_IN, GP_4_16_OUT,
+		GP_4_15_IN, GP_4_15_OUT,
+		GP_4_14_IN, GP_4_14_OUT,
+		GP_4_13_IN, GP_4_13_OUT,
+		GP_4_12_IN, GP_4_12_OUT,
+		GP_4_11_IN, GP_4_11_OUT,
+		GP_4_10_IN, GP_4_10_OUT,
+		GP_4_9_IN, GP_4_9_OUT,
+		GP_4_8_IN, GP_4_8_OUT,
+		GP_4_7_IN, GP_4_7_OUT,
+		GP_4_6_IN, GP_4_6_OUT,
+		GP_4_5_IN, GP_4_5_OUT,
+		GP_4_4_IN, GP_4_4_OUT,
+		GP_4_3_IN, GP_4_3_OUT,
+		GP_4_2_IN, GP_4_2_OUT,
+		GP_4_1_IN, GP_4_1_OUT,
+		GP_4_0_IN, GP_4_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_16_IN, GP_5_16_OUT,
+		GP_5_15_IN, GP_5_15_OUT,
+		GP_5_14_IN, GP_5_14_OUT,
+		GP_5_13_IN, GP_5_13_OUT,
+		GP_5_12_IN, GP_5_12_OUT,
+		GP_5_11_IN, GP_5_11_OUT,
+		GP_5_10_IN, GP_5_10_OUT,
+		GP_5_9_IN, GP_5_9_OUT,
+		GP_5_8_IN, GP_5_8_OUT,
+		GP_5_7_IN, GP_5_7_OUT,
+		GP_5_6_IN, GP_5_6_OUT,
+		GP_5_5_IN, GP_5_5_OUT,
+		GP_5_4_IN, GP_5_4_OUT,
+		GP_5_3_IN, GP_5_3_OUT,
+		GP_5_2_IN, GP_5_2_OUT,
+		GP_5_1_IN, GP_5_1_OUT,
+		GP_5_0_IN, GP_5_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055104, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_16_IN, GP_6_16_OUT,
+		GP_6_15_IN, GP_6_15_OUT,
+		GP_6_14_IN, GP_6_14_OUT,
+		GP_6_13_IN, GP_6_13_OUT,
+		GP_6_12_IN, GP_6_12_OUT,
+		GP_6_11_IN, GP_6_11_OUT,
+		GP_6_10_IN, GP_6_10_OUT,
+		GP_6_9_IN, GP_6_9_OUT,
+		GP_6_8_IN, GP_6_8_OUT,
+		GP_6_7_IN, GP_6_7_OUT,
+		GP_6_6_IN, GP_6_6_OUT,
+		GP_6_5_IN, GP_6_5_OUT,
+		GP_6_4_IN, GP_6_4_OUT,
+		GP_6_3_IN, GP_6_3_OUT,
+		GP_6_2_IN, GP_6_2_OUT,
+		GP_6_1_IN, GP_6_1_OUT,
+		GP_6_0_IN, GP_6_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055204, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_16_IN, GP_7_16_OUT,
+		GP_7_15_IN, GP_7_15_OUT,
+		GP_7_14_IN, GP_7_14_OUT,
+		GP_7_13_IN, GP_7_13_OUT,
+		GP_7_12_IN, GP_7_12_OUT,
+		GP_7_11_IN, GP_7_11_OUT,
+		GP_7_10_IN, GP_7_10_OUT,
+		GP_7_9_IN, GP_7_9_OUT,
+		GP_7_8_IN, GP_7_8_OUT,
+		GP_7_7_IN, GP_7_7_OUT,
+		GP_7_6_IN, GP_7_6_OUT,
+		GP_7_5_IN, GP_7_5_OUT,
+		GP_7_4_IN, GP_7_4_OUT,
+		GP_7_3_IN, GP_7_3_OUT,
+		GP_7_2_IN, GP_7_2_OUT,
+		GP_7_1_IN, GP_7_1_OUT,
+		GP_7_0_IN, GP_7_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL8", 0xE6055304, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_8_16_IN, GP_8_16_OUT,
+		GP_8_15_IN, GP_8_15_OUT,
+		GP_8_14_IN, GP_8_14_OUT,
+		GP_8_13_IN, GP_8_13_OUT,
+		GP_8_12_IN, GP_8_12_OUT,
+		GP_8_11_IN, GP_8_11_OUT,
+		GP_8_10_IN, GP_8_10_OUT,
+		GP_8_9_IN, GP_8_9_OUT,
+		GP_8_8_IN, GP_8_8_OUT,
+		GP_8_7_IN, GP_8_7_OUT,
+		GP_8_6_IN, GP_8_6_OUT,
+		GP_8_5_IN, GP_8_5_OUT,
+		GP_8_4_IN, GP_8_4_OUT,
+		GP_8_3_IN, GP_8_3_OUT,
+		GP_8_2_IN, GP_8_2_OUT,
+		GP_8_1_IN, GP_8_1_OUT,
+		GP_8_0_IN, GP_8_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL9", 0xE6055404, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_9_16_IN, GP_9_16_OUT,
+		GP_9_15_IN, GP_9_15_OUT,
+		GP_9_14_IN, GP_9_14_OUT,
+		GP_9_13_IN, GP_9_13_OUT,
+		GP_9_12_IN, GP_9_12_OUT,
+		GP_9_11_IN, GP_9_11_OUT,
+		GP_9_10_IN, GP_9_10_OUT,
+		GP_9_9_IN, GP_9_9_OUT,
+		GP_9_8_IN, GP_9_8_OUT,
+		GP_9_7_IN, GP_9_7_OUT,
+		GP_9_6_IN, GP_9_6_OUT,
+		GP_9_5_IN, GP_9_5_OUT,
+		GP_9_4_IN, GP_9_4_OUT,
+		GP_9_3_IN, GP_9_3_OUT,
+		GP_9_2_IN, GP_9_2_OUT,
+		GP_9_1_IN, GP_9_1_OUT,
+		GP_9_0_IN, GP_9_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL10", 0xE6055504, 32, 1) { GP_INOUTSEL(10) } },
+	{ PINMUX_CFG_REG("INOUTSEL11", 0xE6055604, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_11_29_IN, GP_11_29_OUT,
+		GP_11_28_IN, GP_11_28_OUT,
+		GP_11_27_IN, GP_11_27_OUT,
+		GP_11_26_IN, GP_11_26_OUT,
+		GP_11_25_IN, GP_11_25_OUT,
+		GP_11_24_IN, GP_11_24_OUT,
+		GP_11_23_IN, GP_11_23_OUT,
+		GP_11_22_IN, GP_11_22_OUT,
+		GP_11_21_IN, GP_11_21_OUT,
+		GP_11_20_IN, GP_11_20_OUT,
+		GP_11_19_IN, GP_11_19_OUT,
+		GP_11_18_IN, GP_11_18_OUT,
+		GP_11_17_IN, GP_11_17_OUT,
+		GP_11_16_IN, GP_11_16_OUT,
+		GP_11_15_IN, GP_11_15_OUT,
+		GP_11_14_IN, GP_11_14_OUT,
+		GP_11_13_IN, GP_11_13_OUT,
+		GP_11_12_IN, GP_11_12_OUT,
+		GP_11_11_IN, GP_11_11_OUT,
+		GP_11_10_IN, GP_11_10_OUT,
+		GP_11_9_IN, GP_11_9_OUT,
+		GP_11_8_IN, GP_11_8_OUT,
+		GP_11_7_IN, GP_11_7_OUT,
+		GP_11_6_IN, GP_11_6_OUT,
+		GP_11_5_IN, GP_11_5_OUT,
+		GP_11_4_IN, GP_11_4_OUT,
+		GP_11_3_IN, GP_11_3_OUT,
+		GP_11_2_IN, GP_11_2_OUT,
+		GP_11_1_IN, GP_11_1_OUT,
+		GP_11_0_IN, GP_11_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
+		0, 0, 0, GP_0_28_DATA,
+		GP_0_27_DATA, GP_0_26_DATA, GP_0_25_DATA, GP_0_24_DATA,
+		GP_0_23_DATA, GP_0_22_DATA, GP_0_21_DATA, GP_0_20_DATA,
+		GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA,
+		GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
+		GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
+		GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
+		GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
+		0, 0, 0, 0,
+		GP_3_27_DATA, GP_3_26_DATA, GP_3_25_DATA, GP_3_24_DATA,
+		GP_3_23_DATA, GP_3_22_DATA, GP_3_21_DATA, GP_3_20_DATA,
+		GP_3_19_DATA, GP_3_18_DATA, GP_3_17_DATA, GP_3_16_DATA,
+		GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
+		GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
+		GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
+		GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_4_16_DATA,
+		GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
+		GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
+		GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
+		GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_5_16_DATA,
+		GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT6", 0xE6055108, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_6_16_DATA,
+		GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA,
+		GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA,
+		GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
+		GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT7", 0xE6055208, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_7_16_DATA,
+		GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
+		GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
+		GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT8", 0xE6055308, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_8_16_DATA,
+		GP_8_15_DATA, GP_8_14_DATA, GP_8_13_DATA, GP_8_12_DATA,
+		GP_8_11_DATA, GP_8_10_DATA, GP_8_9_DATA, GP_8_8_DATA,
+		GP_8_7_DATA, GP_8_6_DATA, GP_8_5_DATA, GP_8_4_DATA,
+		GP_8_3_DATA, GP_8_2_DATA, GP_8_1_DATA, GP_8_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT9", 0xE6055408, 32) {
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, GP_9_16_DATA,
+		GP_9_15_DATA, GP_9_14_DATA, GP_9_13_DATA, GP_9_12_DATA,
+		GP_9_11_DATA, GP_9_10_DATA, GP_9_9_DATA, GP_9_8_DATA,
+		GP_9_7_DATA, GP_9_6_DATA, GP_9_5_DATA, GP_9_4_DATA,
+		GP_9_3_DATA, GP_9_2_DATA, GP_9_1_DATA, GP_9_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT10", 0xE6055508, 32) { GP_INDT(10) } },
+	{ PINMUX_DATA_REG("INDT11", 0xE6055608, 32) {
+		0, 0, GP_11_29_DATA, GP_11_28_DATA,
+		GP_11_27_DATA, GP_11_26_DATA, GP_11_25_DATA, GP_11_24_DATA,
+		GP_11_23_DATA, GP_11_22_DATA, GP_11_21_DATA, GP_11_20_DATA,
+		GP_11_19_DATA, GP_11_18_DATA, GP_11_17_DATA, GP_11_16_DATA,
+		GP_11_15_DATA, GP_11_14_DATA, GP_11_13_DATA, GP_11_12_DATA,
+		GP_11_11_DATA, GP_11_10_DATA, GP_11_9_DATA, GP_11_8_DATA,
+		GP_11_7_DATA, GP_11_6_DATA, GP_11_5_DATA, GP_11_4_DATA,
+		GP_11_3_DATA, GP_11_2_DATA, GP_11_1_DATA, GP_11_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7792_pinmux_info = {
+	.name = "r8a7792_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_AUDIO_CLKB,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7792_pinmux_init(void)
+{
+	register_pinmux(&r8a7792_pinmux_info);
+}
+
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c b/arch/arm/mach-rmobile/pfc-r8a7793.c
index 03c27ad7fef..03c27ad7fef 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7793.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7793.c
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c b/arch/arm/mach-rmobile/pfc-r8a7794.c
index 7ea5edc2e50..7ea5edc2e50 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
+++ b/arch/arm/mach-rmobile/pfc-r8a7794.c
diff --git a/arch/arm/mach-rmobile/pfc-r8a7795.c b/arch/arm/mach-rmobile/pfc-r8a7795.c
new file mode 100644
index 00000000000..65d66a08e2c
--- /dev/null
+++ b/arch/arm/mach-rmobile/pfc-r8a7795.c
@@ -0,0 +1,4844 @@
+/*
+ * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7795.c
+ *     This file is r8a7795 processor support - PFC hardware block.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)
+
+#define CPU_32_PORT2(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)
+
+#define CPU_32_PORT_28(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx),					\
+	PORT_10(fn, pfx##1, sfx),				\
+	PORT_1(fn, pfx##20, sfx),				\
+	PORT_1(fn, pfx##21, sfx),				\
+	PORT_1(fn, pfx##22, sfx),				\
+	PORT_1(fn, pfx##23, sfx),				\
+	PORT_1(fn, pfx##24, sfx),				\
+	PORT_1(fn, pfx##25, sfx),				\
+	PORT_1(fn, pfx##26, sfx),				\
+	PORT_1(fn, pfx##27, sfx)
+
+#define CPU_32_PORT_26(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx),					\
+	PORT_10(fn, pfx##1, sfx),				\
+	PORT_1(fn, pfx##20, sfx),				\
+	PORT_1(fn, pfx##21, sfx),				\
+	PORT_1(fn, pfx##22, sfx),				\
+	PORT_1(fn, pfx##23, sfx),				\
+	PORT_1(fn, pfx##24, sfx),				\
+	PORT_1(fn, pfx##25, sfx)
+
+#define CPU_32_PORT_18(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx),					\
+	PORT_1(fn, pfx##10, sfx),				\
+	PORT_1(fn, pfx##11, sfx),				\
+	PORT_1(fn, pfx##12, sfx),				\
+	PORT_1(fn, pfx##13, sfx),				\
+	PORT_1(fn, pfx##14, sfx),				\
+	PORT_1(fn, pfx##15, sfx),				\
+	PORT_1(fn, pfx##16, sfx),				\
+	PORT_1(fn, pfx##17, sfx)
+
+#define CPU_32_PORT_16(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx),					\
+	PORT_1(fn, pfx##10, sfx),				\
+	PORT_1(fn, pfx##11, sfx),				\
+	PORT_1(fn, pfx##12, sfx),				\
+	PORT_1(fn, pfx##13, sfx),				\
+	PORT_1(fn, pfx##14, sfx),				\
+	PORT_1(fn, pfx##15, sfx)
+
+#define CPU_32_PORT_15(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx),					\
+	PORT_1(fn, pfx##10, sfx),				\
+	PORT_1(fn, pfx##11, sfx),				\
+	PORT_1(fn, pfx##12, sfx),				\
+	PORT_1(fn, pfx##13, sfx),				\
+	PORT_1(fn, pfx##14, sfx)
+
+#define CPU_32_PORT_4(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##0, sfx),				\
+	PORT_1(fn, pfx##1, sfx),				\
+	PORT_1(fn, pfx##2, sfx),				\
+	PORT_1(fn, pfx##3, sfx)
+
+
+/* --gen3-- */
+/* GP_0_0_DATA -> GP_7_4_DATA */
+/* except for GP0[16] - [31],
+		GP1[28] - [31],
+		GP2[15] - [31],
+		GP3[16] - [31],
+		GP4[18] - [31],
+		GP5[26] - [31],
+		GP7[4] - [31] */
+
+#define CPU_ALL_PORT(fn, pfx, sfx)		\
+	CPU_32_PORT_16(fn, pfx##_0_, sfx),	\
+	CPU_32_PORT_28(fn, pfx##_1_, sfx),	\
+	CPU_32_PORT_15(fn, pfx##_2_, sfx),	\
+	CPU_32_PORT_16(fn, pfx##_3_, sfx),	\
+	CPU_32_PORT_18(fn, pfx##_4_, sfx),	\
+	CPU_32_PORT_26(fn, pfx##_5_, sfx),	\
+	CPU_32_PORT(fn, pfx##_6_, sfx),		\
+	CPU_32_PORT_4(fn, pfx##_7_, sfx)
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	GFN_D15,
+	GFN_D14,
+	GFN_D13,
+	GFN_D12,
+	GFN_D11,
+	GFN_D10,
+	GFN_D9,
+	GFN_D8,
+	GFN_D7,
+	GFN_D6,
+	GFN_D5,
+	GFN_D4,
+	GFN_D3,
+	GFN_D2,
+	GFN_D1,
+	GFN_D0,
+
+	/* GPSR1 */
+	GFN_EX_WAIT0_A,
+	GFN_WE1x,
+	GFN_WE0x,
+	GFN_RD_WRx,
+	GFN_RDx,
+	GFN_BSx,
+	GFN_CS1x_A26,
+	GFN_CS0x,
+	GFN_A19,
+	GFN_A18,
+	GFN_A17,
+	GFN_A16,
+	GFN_A15,
+	GFN_A14,
+	GFN_A13,
+	GFN_A12,
+	GFN_A11,
+	GFN_A10,
+	GFN_A9,
+	GFN_A8,
+	GFN_A7,
+	GFN_A6,
+	GFN_A5,
+	GFN_A4,
+	GFN_A3,
+	GFN_A2,
+	GFN_A1,
+	GFN_A0,
+
+	/* GPSR2 */
+	GFN_AVB_AVTP_CAPTURE_A,
+	GFN_AVB_AVTP_MATCH_A,
+	GFN_AVB_LINK,
+	GFN_AVB_PHY_INT,
+	GFN_AVB_MAGIC,
+	GFN_AVB_MDC,
+	GFN_PWM2_A,
+	GFN_PWM1_A,
+	GFN_PWM0,
+	GFN_IRQ5,
+	GFN_IRQ4,
+	GFN_IRQ3,
+	GFN_IRQ2,
+	GFN_IRQ1,
+	GFN_IRQ0,
+
+	/* GPSR3 */
+	GFN_SD1_WP,
+	GFN_SD1_CD,
+	GFN_SD0_WP,
+	GFN_SD0_CD,
+	GFN_SD1_DAT3,
+	GFN_SD1_DAT2,
+	GFN_SD1_DAT1,
+	GFN_SD1_DAT0,
+	GFN_SD1_CMD,
+	GFN_SD1_CLK,
+	GFN_SD0_DAT3,
+	GFN_SD0_DAT2,
+	GFN_SD0_DAT1,
+	GFN_SD0_DAT0,
+	GFN_SD0_CMD,
+	GFN_SD0_CLK,
+
+	/* GPSR4 */
+	FN_SD3_DS,
+	GFN_SD3_DAT7,
+	GFN_SD3_DAT6,
+	GFN_SD3_DAT5,
+	GFN_SD3_DAT4,
+	FN_SD3_DAT3,
+	FN_SD3_DAT2,
+	FN_SD3_DAT1,
+	FN_SD3_DAT0,
+	FN_SD3_CMD,
+	FN_SD3_CLK,
+	GFN_SD2_DS,
+	GFN_SD2_DAT3,
+	GFN_SD2_DAT2,
+	GFN_SD2_DAT1,
+	GFN_SD2_DAT0,
+	FN_SD2_CMD,
+	GFN_SD2_CLK,
+
+	/* GPSR5 */
+	GFN_MLB_DAT,
+	GFN_MLB_SIG,
+	GFN_MLB_CLK,
+	FN_MSIOF0_RXD,
+	GFN_MSIOF0_SS2,
+	FN_MSIOF0_TXD,
+	GFN_MSIOF0_SS1,
+	GFN_MSIOF0_SYNC,
+	FN_MSIOF0_SCK,
+	GFN_HRTS0x,
+	GFN_HCTS0x,
+	GFN_HTX0,
+	GFN_HRX0,
+	GFN_HSCK0,
+	GFN_RX2_A,
+	GFN_TX2_A,
+	GFN_SCK2,
+	GFN_RTS1x_TANS,
+	GFN_CTS1x,
+	GFN_TX1_A,
+	GFN_RX1_A,
+	GFN_RTS0x_TANS,
+	GFN_CTS0x,
+	GFN_TX0,
+	GFN_RX0,
+	GFN_SCK0,
+
+	/* GPSR6 */
+	GFN_USB31_OVC,
+	GFN_USB31_PWEN,
+	GFN_USB30_OVC,
+	GFN_USB30_PWEN,
+	GFN_USB1_OVC,
+	GFN_USB1_PWEN,
+	GFN_USB0_OVC,
+	GFN_USB0_PWEN,
+	GFN_AUDIO_CLKB_B,
+	GFN_AUDIO_CLKA_A,
+	GFN_SSI_SDATA9_A,
+	GFN_SSI_SDATA8,
+	GFN_SSI_SDATA7,
+	GFN_SSI_WS78,
+	GFN_SSI_SCK78,
+	GFN_SSI_SDATA6,
+	GFN_SSI_WS6,
+	GFN_SSI_SCK6,
+	FN_SSI_SDATA5,
+	FN_SSI_WS5,
+	FN_SSI_SCK5,
+	GFN_SSI_SDATA4,
+	GFN_SSI_WS4,
+	GFN_SSI_SCK4,
+	GFN_SSI_SDATA3,
+	GFN_SSI_WS34,
+	GFN_SSI_SCK34,
+	GFN_SSI_SDATA2_A,
+	GFN_SSI_SDATA1_A,
+	GFN_SSI_SDATA0,
+	GFN_SSI_WS0129,
+	GFN_SSI_SCK0129,
+
+	/* GPSR7 */
+	FN_HDMI1_CEC,
+	FN_HDMI0_CEC,
+	FN_AVS2,
+	FN_AVS1,
+
+	/* IPSR0 */
+	IFN_AVB_MDC,
+	FN_MSIOF2_SS2_C,
+	IFN_AVB_MAGIC,
+	FN_MSIOF2_S1_C,
+	FN_SCK4_A,
+	IFN_AVB_PHY_INT,
+	FN_MSIOF2_SYNC_C,
+	FN_RX4_A,
+	IFN_AVB_LINK,
+	FN_MSIOF2_SCK_C,
+	FN_TX4_A,
+	IFN_AVB_AVTP_MATCH_A,
+	FN_MSIOF2_RXD_C,
+	FN_CTS4x_A,
+	IFN_AVB_AVTP_CAPTURE_A,
+	FN_MSIOF2_TXD_C,
+	FN_RTS4x_TANS_A,
+	IFN_IRQ0,
+	FN_QPOLB,
+	FN_DU_CDE,
+	FN_VI4_DATA0_B,
+	FN_CAN0_TX_B,
+	FN_CANFD0_TX_B,
+	IFN_IRQ1,
+	FN_QPOLA,
+	FN_DU_DISP,
+	FN_VI4_DATA1_B,
+	FN_CAN0_RX_B,
+	FN_CANFD0_RX_B,
+
+	/* IPSR1 */
+	IFN_IRQ2,
+	FN_QCPV_QDE,
+	FN_DU_EXODDF_DU_ODDF_DISP_CDE,
+	FN_VI4_DATA2_B,
+	FN_PWM3_B,
+	IFN_IRQ3,
+	FN_QSTVB_QVE,
+	FN_A25,
+	FN_DU_DOTCLKOUT1,
+	FN_VI4_DATA3_B,
+	FN_PWM4_B,
+	IFN_IRQ4,
+	FN_QSTH_QHS,
+	FN_A24,
+	FN_DU_EXHSYNC_DU_HSYNC,
+	FN_VI4_DATA4_B,
+	FN_PWM5_B,
+	IFN_IRQ5,
+	FN_QSTB_QHE,
+	FN_A23,
+	FN_DU_EXVSYNC_DU_VSYNC,
+	FN_VI4_DATA5_B,
+	FN_PWM6_B,
+	IFN_PWM0,
+	FN_AVB_AVTP_PPS,
+	FN_A22,
+	FN_VI4_DATA6_B,
+	FN_IECLK_B,
+	IFN_PWM1_A,
+	FN_A21,
+	FN_HRX3_D,
+	FN_VI4_DATA7_B,
+	FN_IERX_B,
+	IFN_PWM2_A,
+	FN_PWMFSW0,
+	FN_A20,
+	FN_HTX3_D,
+	FN_IETX_B,
+	IFN_A0,
+	FN_LCDOUT16,
+	FN_MSIOF3_SYNC_B,
+	FN_VI4_DATA8,
+	FN_DU_DB0,
+	FN_PWM3_A,
+
+	/* IPSR2 */
+	IFN_A1,
+	FN_LCDOUT17,
+	FN_MSIOF3_TXD_B,
+	FN_VI4_DATA9,
+	FN_DU_DB1,
+	FN_PWM4_A,
+	IFN_A2,
+	FN_LCDOUT18,
+	FN_MSIOF3_SCK_B,
+	FN_VI4_DATA10,
+	FN_DU_DB2,
+	FN_PWM5_A,
+	IFN_A3,
+	FN_LCDOUT19,
+	FN_MSIOF3_RXD_B,
+	FN_VI4_DATA11,
+	FN_DU_DB3,
+	FN_PWM6_A,
+	IFN_A4,
+	FN_LCDOUT20,
+	FN_MSIOF3_SS1_B,
+	FN_VI4_DATA12,
+	FN_VI5_DATA12,
+	FN_DU_DB4,
+	IFN_A5,
+	FN_LCDOUT21,
+	FN_MSIOF3_SS2_B,
+	FN_SCK4_B,
+	FN_VI4_DATA13,
+	FN_VI5_DATA13,
+	FN_DU_DB5,
+	IFN_A6,
+	FN_LCDOUT22,
+	FN_MSIOF2_SS1_A,
+	FN_RX4_B,
+	FN_VI4_DATA14,
+	FN_VI5_DATA14,
+	FN_DU_DB6,
+	IFN_A7,
+	FN_LCDOUT23,
+	FN_MSIOF2_SS2_A,
+	FN_TX4_B,
+	FN_VI4_DATA15,
+	FN_V15_DATA15,
+	FN_DU_DB7,
+	IFN_A8,
+	FN_RX3_B,
+	FN_MSIOF2_SYNC_A,
+	FN_HRX4_B,
+	FN_SDA6_A,
+	FN_AVB_AVTP_MATCH_B,
+	FN_PWM1_B,
+
+	/* IPSR3 */
+	IFN_A9,
+	FN_MSIOF2_SCK_A,
+	FN_CTS4x_B,
+	FN_VI5_VSYNCx,
+	IFN_A10,
+	FN_MSIOF2_RXD_A,
+	FN_RTS4n_TANS_B,
+	FN_VI5_HSYNCx,
+	IFN_A11,
+	FN_TX3_B,
+	FN_MSIOF2_TXD_A,
+	FN_HTX4_B,
+	FN_HSCK4,
+	FN_VI5_FIELD,
+	FN_SCL6_A,
+	FN_AVB_AVTP_CAPTURE_B,
+	FN_PWM2_B,
+	FN_SPV_EVEN,
+	IFN_A12,
+	FN_LCDOUT12,
+	FN_MSIOF3_SCK_C,
+	FN_HRX4_A,
+	FN_VI5_DATA8,
+	FN_DU_DG4,
+	IFN_A13,
+	FN_LCDOUT13,
+	FN_MSIOF3_SYNC_C,
+	FN_HTX4_A,
+	FN_VI5_DATA9,
+	FN_DU_DG5,
+	IFN_A14,
+	FN_LCDOUT14,
+	FN_MSIOF3_RXD_C,
+	FN_HCTS4x,
+	FN_VI5_DATA10,
+	FN_DU_DG6,
+	IFN_A15,
+	FN_LCDOUT15,
+	FN_MSIOF3_TXD_C,
+	FN_HRTS4x,
+	FN_VI5_DATA11,
+	FN_DU_DG7,
+	IFN_A16,
+	FN_LCDOUT8,
+	FN_VI4_FIELD,
+	FN_DU_DG0,
+
+	/* IPSR4 */
+	IFN_A17,
+	FN_LCDOUT9,
+	FN_VI4_VSYNCx,
+	FN_DU_DG1,
+	IFN_A18,
+	FN_LCDOUT10,
+	FN_VI4_HSYNCx,
+	FN_DU_DG2,
+	IFN_A19,
+	FN_LCDOUT11,
+	FN_VI4_CLKENB,
+	FN_DU_DG3,
+	IFN_CS0x,
+	FN_VI5_CLKENB,
+	IFN_CS1x_A26,
+	FN_VI5_CLK,
+	FN_EX_WAIT0_B,
+	IFN_BSx,
+	FN_QSTVA_QVS,
+	FN_MSIOF3_SCK_D,
+	FN_SCK3,
+	FN_HSCK3,
+	FN_CAN1_TX,
+	FN_CANFD1_TX,
+	FN_IETX_A,
+	IFN_RDx,
+	FN_MSIOF3_SYNC_D,
+	FN_RX3_A,
+	FN_HRX3_A,
+	FN_CAN0_TX_A,
+	FN_CANFD0_TX_A,
+	IFN_RD_WRx,
+	FN_MSIOF3_RXD_D,
+	FN_TX3_A,
+	FN_HTX3_A,
+	FN_CAN0_RX_A,
+	FN_CANFD0_RX_A,
+
+	/* IPSR5 */
+	IFN_WE0x,
+	FN_MSIIOF3_TXD_D,
+	FN_CTS3x,
+	FN_HCTS3x,
+	FN_SCL6_B,
+	FN_CAN_CLK,
+	FN_IECLK_A,
+	IFN_WE1x,
+	FN_MSIOF3_SS1_D,
+	FN_RTS3x_TANS,
+	FN_HRTS3x,
+	FN_SDA6_B,
+	FN_CAN1_RX,
+	FN_CANFD1_RX,
+	FN_IERX_A,
+	IFN_EX_WAIT0_A,
+	FN_QCLK,
+	FN_VI4_CLK,
+	FN_DU_DOTCLKOUT0,
+	IFN_D0,
+	FN_MSIOF2_SS1_B,
+	FN_MSIOF3_SCK_A,
+	FN_VI4_DATA16,
+	FN_VI5_DATA0,
+	IFN_D1,
+	FN_MSIOF2_SS2_B,
+	FN_MSIOF3_SYNC_A,
+	FN_VI4_DATA17,
+	FN_VI5_DATA1,
+	IFN_D2,
+	FN_MSIOF3_RXD_A,
+	FN_VI4_DATA18,
+	FN_VI5_DATA2,
+	IFN_D3,
+	FN_MSIOF3_TXD_A,
+	FN_VI4_DATA19,
+	FN_VI5_DATA3,
+	IFN_D4,
+	FN_MSIOF2_SCK_B,
+	FN_VI4_DATA20,
+	FN_VI5_DATA4,
+
+	/* IPSR6 */
+	IFN_D5,
+	FN_MSIOF2_SYNC_B,
+	FN_VI4_DATA21,
+	FN_VI5_DATA5,
+	IFN_D6,
+	FN_MSIOF2_RXD_B,
+	FN_VI4_DATA22,
+	FN_VI5_DATA6,
+	IFN_D7,
+	FN_MSIOF2_TXD_B,
+	FN_VI4_DATA23,
+	FN_VI5_DATA7,
+	IFN_D8,
+	FN_LCDOUT0,
+	FN_MSIOF2_SCK_D,
+	FN_SCK4_C,
+	FN_VI4_DATA0_A,
+	FN_DU_DR0,
+	IFN_D9,
+	FN_LCDOUT1,
+	FN_MSIOF2_SYNC_D,
+	FN_VI4_DATA1_A,
+	FN_DU_DR1,
+	IFN_D10,
+	FN_LCDOUT2,
+	FN_MSIOF2_RXD_D,
+	FN_HRX3_B,
+	FN_VI4_DATA2_A,
+	FN_CTS4x_C,
+	FN_DU_DR2,
+	IFN_D11,
+	FN_LCDOUT3,
+	FN_MSIOF2_TXD_D,
+	FN_HTX3_B,
+	FN_VI4_DATA3_A,
+	FN_RTS4x_TANS_C,
+	FN_DU_DR3,
+	IFN_D12,
+	FN_LCDOUT4,
+	FN_MSIOF2_SS1_D,
+	FN_RX4_C,
+	FN_VI4_DATA4_A,
+	FN_DU_DR4,
+
+	/* IPSR7 */
+	IFN_D13,
+	FN_LCDOUT5,
+	FN_MSIOF2_SS2_D,
+	FN_TX4_C,
+	FN_VI4_DATA5_A,
+	FN_DU_DR5,
+	IFN_D14,
+	FN_LCDOUT6,
+	FN_MSIOF3_SS1_A,
+	FN_HRX3_C,
+	FN_VI4_DATA6_A,
+	FN_DU_DR6,
+	FN_SCL6_C,
+	IFN_D15,
+	FN_LCDOUT7,
+	FN_MSIOF3_SS2_A,
+	FN_HTX3_C,
+	FN_VI4_DATA7_A,
+	FN_DU_DR7,
+	FN_SDA6_C,
+	FN_FSCLKST,
+	IFN_SD0_CLK,
+	FN_MSIOF1_SCK_E,
+	FN_STP_OPWM_0_B,
+	IFN_SD0_CMD,
+	FN_MSIOF1_SYNC_E,
+	FN_STP_IVCXO27_0_B,
+	IFN_SD0_DAT0,
+	FN_MSIOF1_RXD_E,
+	FN_TS_SCK0_B,
+	FN_STP_ISCLK_0_B,
+	IFN_SD0_DAT1,
+	FN_MSIOF1_TXD_E,
+	FN_TS_SPSYNC0_B,
+	FN_STP_ISSYNC_0_B,
+
+	/* IPSR8 */
+	IFN_SD0_DAT2,
+	FN_MSIOF1_SS1_E,
+	FN_TS_SDAT0_B,
+	FN_STP_ISD_0_B,
+	IFN_SD0_DAT3,
+	FN_MSIOF1_SS2_E,
+	FN_TS_SDEN0_B,
+	FN_STP_ISEN_0_B,
+	IFN_SD1_CLK,
+	FN_MSIOF1_SCK_G,
+	FN_SIM0_CLK_A,
+
+	IFN_SD1_CMD,
+	FN_MSIOF1_SYNC_G,
+	FN_SIM0_D_A,
+	FN_STP_IVCXO27_1_B,
+
+	IFN_SD1_DAT0,
+	FN_SD2_DAT4,
+	FN_MSIOF1_RXD_G,
+	FN_TS_SCK1_B,
+	FN_STP_ISCLK_1_B,
+
+	IFN_SD1_DAT1,
+	FN_SD2_DAT5,
+	FN_MSIOF1_TXD_G,
+	FN_TS_SPSYNC1_B,
+	FN_STP_ISSYNC_1_B,
+
+	IFN_SD1_DAT2,
+	FN_SD2_DAT6,
+	FN_MSIOF1_SS1_G,
+	FN_TS_SDAT1_B,
+	FN_STP_IOD_1_B,
+	IFN_SD1_DAT3,
+	FN_SD2_DAT7,
+	FN_MSIOF1_SS2_G,
+	FN_TS_SDEN1_B,
+	FN_STP_ISEN_1_B,
+
+	/* IPSR9 */
+	IFN_SD2_CLK,
+	FN_SCKZ_A,
+	IFN_SD2_DAT0,
+	FN_MTSx_A,
+	IFN_SD2_DAT1,
+	FN_STMx_A,
+	IFN_SD2_DAT2,
+	FN_MDATA_A,
+	IFN_SD2_DAT3,
+	FN_SDATA_A,
+	IFN_SD2_DS,
+	FN_SATA_DEVSLP_B,
+	FN_VSP_A,
+	IFN_SD3_DAT4,
+	FN_SD2_CD_A,
+	IFN_SD3_DAT5,
+	FN_SD2_WP_A,
+
+	/* IPSR10 */
+	IFN_SD3_DAT6,
+	FN_SD3_CD,
+	IFN_SD3_DAT7,
+	FN_SD3_WP,
+	IFN_SD0_CD,
+	FN_SCL2_B,
+	FN_SIM0_RST_A,
+	IFN_SD0_WP,
+	FN_SDA2_B,
+	IFN_SD1_CD,
+	FN_SIM0_CLK_B,
+	IFN_SD1_WP,
+	FN_SIM0_D_B,
+	IFN_SCK0,
+	FN_HSCK1_B,
+	FN_MSIOF1_SS2_B,
+	FN_AUDIO_CLKC_B,
+	FN_SDA2_A,
+	FN_SIM0_RST_B,
+	FN_STP_OPWM__C,
+	FN_RIF0_CLK_B,
+	FN_ADICHS2,
+	IFN_RX0,
+	FN_HRX1_B,
+	FN_TS_SCK0_C,
+	FN_STP_ISCLK_0_C,
+	FN_RIF0_D0_B,
+
+	/* IPSR11 */
+	IFN_TX0,
+	FN_HTX1_B,
+	FN_TS_SPSYNC0_C,
+	FN_STP_ISSYNC_0_C,
+	FN_RIF0_D1_B,
+	IFN_CTS0x,
+	FN_HCTS1x_B,
+	FN_MSIOF1_SYNC_B,
+	FN_TS_SPSYNC1_C,
+	FN_STP_ISSYNC_1_C,
+	FN_RIF1_SYNC_B,
+	FN_AUDIO_CLKOUT_C,
+	FN_ADICS_SAMP,
+	IFN_RTS0x_TANS,
+	FN_HRTS1x_B,
+	FN_MSIOF1_SS1_B,
+	FN_AUDIO_CLKA_B,
+	FN_SCL2_A,
+	FN_STP_IVCXO27_1_C,
+	FN_RIF0_SYNC_B,
+	FN_ADICHS1,
+	IFN_RX1_A,
+	FN_HRX1_A,
+	FN_TS_SDAT0_C,
+	FN_STP_IDS_0_C,
+	FN_RIF1_CLK_C,
+	IFN_TX1_A,
+	FN_HTX1_A,
+	FN_TS_SDEN0_C,
+	FN_STP_ISEN_0_C,
+	FN_RIF1_D0_C,
+	IFN_CTS1x,
+	FN_HCTS1x_A,
+	FN_MSIOF1_RXD_B,
+	FN_TS_SDEN1_C,
+	FN_STP_ISEN_1_C,
+	FN_RIF1_D0_B,
+	FN_ADIDATA,
+	IFN_RTS1x_TANS,
+	FN_HRTS1x_A,
+	FN_MSIOF1_TXD_B,
+	FN_TS_SDAT1_C,
+	FN_STP_ISD_1_C,
+	FN_RIF1_D1_B,
+	FN_ADICHS0,
+	IFN_SCK2,
+	FN_SCIF_CLK_B,
+	FN_MSIOF1_SCK_B,
+	FN_TS_SCK1_C,
+	FN_STP_ISCLK_1_C,
+	FN_RIF1_CLK_B,
+	FN_ADICLK,
+
+	/* IPSR12 */
+	IFN_TX2_A,
+	FN_SD2_CD_B,
+	FN_SCL1_A,
+	FN_RSD_CLK_B,
+	FN_FMCLK_A,
+	FN_RIF1_D1_C,
+	FN_FSO_CFE_0_B,
+	IFN_RX2_A,
+	FN_SD2_WP_B,
+	FN_SDA1_A,
+	FN_RDS_DATA_B,
+	FN_RMIN_A,
+	FN_RIF1_SYNC_C,
+	FN_FSO_CEF_1_B,
+	IFN_HSCK0,
+	FN_MSIOF1_SCK_D,
+	FN_AUDIO_CLKB_A,
+	FN_SSI_SDATA1_B,
+	FN_TS_SCK0_D,
+	FN_STP_ISCLK_0_D,
+	FN_RIF0_CLK_C,
+	FN_AD_CLK,
+	IFN_HRX0,
+	FN_MSIOF1_RXD_D,
+	FN_SS1_SDATA2_B,
+	FN_TS_SDEN0_D,
+	FN_STP_ISEN_0_D,
+	FN_RIF0_D0_C,
+	FN_AD_DI,
+	IFN_HTX0,
+	FN_MSIOF1_TXD_D,
+	FN_SSI_SDATA9_B,
+	FN_TS_SDAT0_D,
+	FN_STP_ISD_0_D,
+	FN_RIF0_D1_C,
+	FN_AD_DO,
+	IFN_HCTS0x,
+	FN_RX2_B,
+	FN_MSIOF1_SYNC_D,
+	FN_SSI_SCK9_A,
+	FN_TS_SPSYNC0_D,
+	FN_STP_ISSYNC_0_D,
+	FN_RIF0_SYNC_C,
+	FN_AUDIO_CLKOUT1_A,
+	FN_AD_NSCx,
+	IFN_HRTS0x,
+	FN_TX2_B,
+	FN_MSIOF1_SS1_D,
+	FN_SSI_WS9_A,
+	FN_STP_IVCXO27_0_D,
+	FN_BPFCLK_A,
+	FN_AUDIO_CLKOUT2_A,
+	IFN_MSIOF0_SYNC,
+	FN_AUDIO_CLKOUT_A,
+
+	/* IPSR13 */
+	IFN_MSIOF0_SS1,
+	FN_RX5,
+	FN_AUDIO_CLKA_C,
+	FN_SSI_SCK2_A,
+	FN_RDS_CLK_A,
+	FN_STP_IVCXO27_0_C,
+	FN_AUDIO_CLKOUT3_A,
+	FN_TCLK1_B,
+	IFN_MSIOF0_SS2,
+	FN_TX5,
+	FN_MSIOF1_SS2_D,
+	FN_AUDIO_CLKC_A,
+	FN_SSI_WS2_A,
+	FN_RDS_DATA_A,
+	FN_STP_OPWM_0_D,
+	FN_AUDIO_CLKOUT_D,
+	FN_SPEEDIN_B,
+	IFN_MLB_CLK,
+	FN_MSIOF1_SCK_F,
+	FN_SCL1_B,
+	IFN_MLB_SIG,
+	FN_RX1_B,
+	FN_MSIOF1_SYNC_F,
+	FN_SDA1_B,
+	IFN_MLB_DAT,
+	FN_TX1_B,
+	FN_MSIOF1_RXD_F,
+	IFN_SSI_SCK0129,
+	FN_MSIOF1_TXD_F,
+	FN_MOUT0,
+	IFN_SSI_WS0129,
+	FN_MSIOF1_SS1_F,
+	FN_MOUT1,
+	IFN_SSI_SDATA0,
+	FN_MSIOF1_SS2_F,
+	FN_MOUT2,
+
+	/* IPSR14 */
+	IFN_SSI_SDATA1_A,
+	FN_MOUT5,
+	IFN_SSI_SDATA2_A,
+	FN_SSI_SCK1_B,
+	FN_MOUT6,
+	IFN_SSI_SCK34,
+	FN_MSIOF1_SS1_A,
+	FN_STP_OPWM_0_A,
+	IFN_SSI_WS34,
+	FN_HCTS2x_A,
+	FN_MSIOF1_SS2_A,
+	FN_STP_IVCXO27_0_A,
+	IFN_SSI_SDATA3,
+	FN_HRTS2x_A,
+	FN_MSIOF1_TXD_A,
+	FN_TS_SCK0_A,
+	FN_STP_ISCLK_0_A,
+	FN_RIF0_D1_A,
+	FN_RIF2_D0_A,
+	IFN_SSI_SCK4,
+	FN_HRX2_A,
+	FN_MSIOF1_SCK_A,
+	FN_TS_SDAT0_A,
+	FN_STP_ISD_0_A,
+	FN_RIF0_CLK_A,
+	FN_RIF2_CLK_A,
+	IFN_SSI_WS4,
+	FN_HTX2_A,
+	FN_MSIOF1_SYNC_A,
+	FN_TS_SDEN0_A,
+	FN_STP_ISEN_0_A,
+	FN_RIF0_SYNC_A,
+	FN_RIF2_SYNC_A,
+	IFN_SSI_SDATA4,
+	FN_HSCK2_A,
+	FN_MSIOF1_RXD_A,
+	FN_TS_SPSYNC0_A,
+	FN_STP_ISSYNC_0_A,
+	FN_RIF0_D0_A,
+	FN_RIF2_D1_A,
+
+	IFN_SSI_SCK6,
+	FN_USB2_PWEN,
+	FN_SIM0_RST_D,
+	FN_RDS_CLK_C,
+	IFN_SSI_WS6,
+	FN_USB2_OVC,
+	FN_SIM0_D_D,
+	IFN_SSI_SDATA6,
+	FN_SIM0_CLK_D,
+	FN_RSD_DATA_C,
+	FN_SATA_DEVSLP_A,
+	IFN_SSI_SCK78,
+	FN_HRX2_B,
+	FN_MSIOF1_SCK_C,
+	FN_TS_SCK1_A,
+	FN_STP_ISCLK_1_A,
+	FN_RIF1_CLK_A,
+	FN_RIF3_CLK_A,
+	IFN_SSI_WS78,
+	FN_HTX2_B,
+	FN_MSIOF1_SYNC_C,
+	FN_TS_SDT1_A,
+	FN_STP_ISD_1_A,
+	FN_RIF1_SYNC_A,
+	FN_RIF3_SYNC_A,
+	IFN_SSI_SDATA7,
+	FN_HCTS2x_B,
+	FN_MSIOF1_RXD_C,
+	FN_TS_SDEN1_A,
+	FN_STP_IEN_1_A,
+	FN_RIF1_D0_A,
+	FN_RIF3_D0_A,
+	FN_TCLK2_A,
+	IFN_SSI_SDATA8,
+	FN_HRTS2x_B,
+	FN_MSIOF1_TXD_C,
+	FN_TS_SPSYNC1_A,
+	FN_STP_ISSYNC_1_A,
+	FN_RIF1_D1_A,
+	FN_EIF3_D1_A,
+	IFN_SSI_SDATA9_A,
+	FN_HSCK2_B,
+	FN_MSIOF1_SS1_C,
+	FN_HSCK1_A,
+	FN_SSI_WS1_B,
+	FN_SCK1,
+	FN_STP_IVCXO27_1_A,
+	FN_SCK5,
+
+	/* IPSR16 */
+	IFN_AUDIO_CLKA_A,
+	FN_CC5_OSCOUT,
+	IFN_AUDIO_CLKB_B,
+	FN_SCIF_CLK_A,
+	FN_DVC_MUTE,
+	FN_STP_IVCXO27_1_D,
+	FN_REMOCON_A,
+	FN_TCLK1_A,
+	FN_VSP_B,
+	IFN_USB0_PWEN,
+	FN_SIM0_RST_C,
+	FN_TS_SCK1_D,
+	FN_STP_ISCLK_1_D,
+	FN_BPFCLK_B,
+	FN_RIF3_CLK_B,
+	FN_SCKZ_B,
+	IFN_USB0_OVC,
+	FN_SIM0_D_C,
+	FN_TS_SDAT1_D,
+	FN_STP_ISD_1_D,
+	FN_RIF3_SYNC_B,
+	FN_VSP_C,
+	IFN_USB1_PWEN,
+	FN_SIM0_CLK_C,
+	FN_SSI_SCK1_A,
+	FN_TS_SCK0_E,
+	FN_STP_ISCLK_0_E,
+	FN_FMCLK_B,
+	FN_RIF2_CLK_B,
+	FN_MTSx_B,
+	FN_SPEEDIN_A,
+	FN_VSP_D,
+	IFN_USB1_OVC,
+	FN_MSIOF1_SS2_C,
+	FN_SSI_WS1_A,
+	FN_TS_SDAT0_E,
+	FN_STP_ISD_0_E,
+	FN_FMIN_B,
+	FN_RIF2_SYNC_B,
+	FN_STMx_B,
+	FN_REMOCON_B,
+	IFN_USB30_PWEN,
+	FN_AUDIO_CLKOUT_B,
+	FN_SSI_SCK2_B,
+	FN_TS_SDEN1_D,
+	FN_STP_ISEN_1_D,
+	FN_STP_OPWM_0_E,
+	FN_RIF3_D0_B,
+	FN_MDATA_B,
+	FN_TCLK2_B,
+	FN_TPU0TO0,
+	IFN_USB30_OVC,
+	FN_AUDIO_CLKOUT1_B,
+	FN_SSI_WS2_B,
+	FN_TS_SPSYNC1_D,
+	FN_STP_ISSYNC_1_D,
+	FN_STP_IVCXO27_0_E,
+	FN_RIF3_D1_B,
+	FN_SDATA_B,
+	FN_RSO_TOE_B,
+	FN_TPU0TO1,
+
+	/* IPSR17 */
+	IFN_USB31_PWEN,
+	FN_AUDIO_CLKOUT2_B,
+	FN_SI_SCK9_B,
+	FN_TS_SDEN0_E,
+	FN_STP_ISEN_0_E,
+	FN_RIF2_D0_B,
+	FN_TPU0TO2,
+	IFN_USB31_OVC,
+	FN_AUDIO_CLKOUT3_B,
+	FN_SSI_WS9_B,
+	FN_TS_SPSYNC0_E,
+	FN_STP_ISSYNC_0_E,
+	FN_RIF2_D1_B,
+	FN_TPU0TO3,
+
+	/* MOD_SEL0 */
+	FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
+	FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
+	FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
+	FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
+	FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+	FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
+	FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
+	FN_SEL_MSIOF1_6,
+	FN_SEL_LBSC_0, FN_SEL_LBSC_1,
+	FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
+	FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+	FN_SEL_I2C6_2,
+	FN_SEL_I2C2_0, FN_SEL_I2C2_1,
+	FN_SEL_I2C1_0, FN_SEL_I2C1_1,
+	FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
+	FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
+	FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
+	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+	FN_SEL_FSO_1,
+	FN_SEL_FM_0, FN_SEL_FM_1,
+	FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
+	FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
+	FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
+	FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
+	FN_SEL_DRIF1_2,
+	FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
+	FN_SEL_DRIF0_2,
+	FN_SEL_CANFD_0, FN_SEL_CANFD_1,
+	FN_SEL_ADG_0, FN_SEL_ADG_1,
+	FN_SEL_ADG_2, FN_SEL_ADG_3,
+	FN_SEL_5LINE_0, FN_SEL_5LINE_1,
+
+	/* MOD_SEL1 */
+	FN_SEL_TSIF1_0,
+	FN_SEL_TSIF1_1,
+	FN_SEL_TSIF1_2,
+	FN_SEL_TSIF1_3,
+	FN_SEL_TSIF0_0,
+	FN_SEL_TSIF0_1,
+	FN_SEL_TSIF0_2,
+	FN_SEL_TSIF0_3,
+	FN_SEL_TSIF0_4,
+	FN_SEL_TIMER_TMU_0,
+	FN_SEL_TIMER_TMU_1,
+	FN_SEL_SSP1_1_0,
+	FN_SEL_SSP1_1_1,
+	FN_SEL_SSP1_1_2,
+	FN_SEL_SSP1_1_3,
+	FN_SEL_SSP1_0_0,
+	FN_SEL_SSP1_0_1,
+	FN_SEL_SSP1_0_2,
+	FN_SEL_SSP1_0_3,
+	FN_SEL_SSP1_0_4,
+	FN_SEL_SSI_0,
+	FN_SEL_SSI_1,
+	FN_SEL_SPEED_PULSE_IF_0,
+	FN_SEL_SPEED_PULSE_IF_1,
+	FN_SEL_SIMCARD_0,
+	FN_SEL_SIMCARD_1,
+	FN_SEL_SIMCARD_2,
+	FN_SEL_SIMCARD_3,
+	FN_SEL_SDHI2_0,
+	FN_SEL_SDHI2_1,
+	FN_SEL_SCIF4_0,
+	FN_SEL_SCIF4_1,
+	FN_SEL_SCIF4_2,
+	FN_SEL_SCIF3_0,
+	FN_SEL_SCIF3_1,
+	FN_SEL_SCIF2_0,
+	FN_SEL_SCIF2_1,
+	FN_SEL_SCIF1_0,
+	FN_SEL_SCIF1_1,
+	FN_SEL_SCIF_0,
+	FN_SEL_SCIF_1,
+	FN_SEL_REMOCON_0,
+	FN_SEL_REMOCON_1,
+	FN_SEL_RDS_0,
+	FN_SEL_RDS_1,
+	FN_SEL_RDS_2,
+	FN_SEL_RCAN_0,
+	FN_SEL_RCAN_1,
+	FN_SEL_PWM6_0,
+	FN_SEL_PWM6_1,
+	FN_SEL_PWM5_0,
+	FN_SEL_PWM5_1,
+	FN_SEL_PWM4_0,
+	FN_SEL_PWM4_1,
+	FN_SEL_PWM3_0,
+	FN_SEL_PWM3_1,
+	FN_SEL_PWM2_0,
+	FN_SEL_PWM2_1,
+	FN_SEL_PWM1_0,
+	FN_SEL_PWM1_1,
+
+	/* MOD_SEL2 */
+	FN_I2C_SEL_5_0,
+	FN_I2C_SEL_5_1,
+	FN_I2C_SEL_3_0,
+	FN_I2C_SEL_3_1,
+	FN_I2C_SEL_0_0,
+	FN_I2C_SEL_0_1,
+	FN_SEL_VSP_0,
+	FN_SEL_VSP_1,
+	FN_SEL_VSP_2,
+	FN_SEL_VSP_3,
+	FN_SEL_VIN4_0,
+	FN_SEL_VIN4_1,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	/* GPSR0 */
+	D15_GMARK,
+	D14_GMARK,
+	D13_GMARK,
+	D12_GMARK,
+	D11_GMARK,
+	D10_GMARK,
+	D9_GMARK,
+	D8_GMARK,
+	D7_GMARK,
+	D6_GMARK,
+	D5_GMARK,
+	D4_GMARK,
+	D3_GMARK,
+	D2_GMARK,
+	D1_GMARK,
+	D0_GMARK,
+
+	/* GPSR1 */
+	EX_WAIT0_A_GMARK,
+	WE1x_GMARK,
+	WE0x_GMARK,
+	RD_WRx_GMARK,
+	RDx_GMARK,
+	BSx_GMARK,
+	CS1x_A26_GMARK,
+	CS0x_GMARK,
+	A19_GMARK,
+	A18_GMARK,
+	A17_GMARK,
+	A16_GMARK,
+	A15_GMARK,
+	A14_GMARK,
+	A13_GMARK,
+	A12_GMARK,
+	A11_GMARK,
+	A10_GMARK,
+	A9_GMARK,
+	A8_GMARK,
+	A7_GMARK,
+	A6_GMARK,
+	A5_GMARK,
+	A4_GMARK,
+	A3_GMARK,
+	A2_GMARK,
+	A1_GMARK,
+	A0_GMARK,
+
+	/* GPSR2 */
+	AVB_AVTP_CAPTURE_A_GMARK,
+	AVB_AVTP_MATCH_A_GMARK,
+	AVB_LINK_GMARK,
+	AVB_PHY_INT_GMARK,
+	AVB_MAGIC_GMARK,
+	AVB_MDC_GMARK,
+	PWM2_A_GMARK,
+	PWM1_A_GMARK,
+	PWM0_GMARK,
+	IRQ5_GMARK,
+	IRQ4_GMARK,
+	IRQ3_GMARK,
+	IRQ2_GMARK,
+	IRQ1_GMARK,
+	IRQ0_GMARK,
+
+	/* GPSR3 */
+	SD1_WP_GMARK,
+	SD1_CD_GMARK,
+	SD0_WP_GMARK,
+	SD0_CD_GMARK,
+	SD1_DAT3_GMARK,
+	SD1_DAT2_GMARK,
+	SD1_DAT1_GMARK,
+	SD1_DAT0_GMARK,
+	SD1_CMD_GMARK,
+	SD1_CLK_GMARK,
+	SD0_DAT3_GMARK,
+	SD0_DAT2_GMARK,
+	SD0_DAT1_GMARK,
+	SD0_DAT0_GMARK,
+	SD0_CMD_GMARK,
+	SD0_CLK_GMARK,
+
+	/* GPSR4 */
+	SD3_DS_MARK,
+	SD3_DAT7_GMARK,
+	SD3_DAT6_GMARK,
+	SD3_DAT5_GMARK,
+	SD3_DAT4_GMARK,
+	SD3_DAT3_MARK,
+	SD3_DAT2_MARK,
+	SD3_DAT1_MARK,
+	SD3_DAT0_MARK,
+	SD3_CMD_MARK,
+	SD3_CLK_MARK,
+	SD2_DS_GMARK,
+	SD2_DAT3_GMARK,
+	SD2_DAT2_GMARK,
+	SD2_DAT1_GMARK,
+	SD2_DAT0_GMARK,
+	SD2_CMD_MARK,
+	SD2_CLK_GMARK,
+
+	/* GPSR5 */
+	MLB_DAT_GMARK,
+	MLB_SIG_GMARK,
+	MLB_CLK_GMARK,
+	MSIOF0_RXD_MARK,
+	MSIOF0_SS2_GMARK,
+	MSIOF0_TXD_MARK,
+	MSIOF0_SS1_GMARK,
+	MSIOF0_SYNC_GMARK,
+	MSIOF0_SCK_MARK,
+	HRTS0x_GMARK,
+	HCTS0x_GMARK,
+	HTX0_GMARK,
+	HRX0_GMARK,
+	HSCK0_GMARK,
+	RX2_A_GMARK,
+	TX2_A_GMARK,
+	SCK2_GMARK,
+	RTS1x_TANS_GMARK,
+	CTS1x_GMARK,
+	TX1_A_GMARK,
+	RX1_A_GMARK,
+	RTS0x_TANS_GMARK,
+	CTS0x_GMARK,
+	TX0_GMARK,
+	RX0_GMARK,
+	SCK0_GMARK,
+
+	/* GPSR6 */
+	USB31_OVC_GMARK,
+	USB31_PWEN_GMARK,
+	USB30_OVC_GMARK,
+	USB30_PWEN_GMARK,
+	USB1_OVC_GMARK,
+	USB1_PWEN_GMARK,
+	USB0_OVC_GMARK,
+	USB0_PWEN_GMARK,
+	AUDIO_CLKB_B_GMARK,
+	AUDIO_CLKA_A_GMARK,
+	SSI_SDATA9_A_GMARK,
+	SSI_SDATA8_GMARK,
+	SSI_SDATA7_GMARK,
+	SSI_WS78_GMARK,
+	SSI_SCK78_GMARK,
+	SSI_SDATA6_GMARK,
+	SSI_WS6_GMARK,
+	SSI_SCK6_GMARK,
+	SSI_SDATA5_MARK,
+	SSI_WS5_MARK,
+	SSI_SCK5_MARK,
+	SSI_SDATA4_GMARK,
+	SSI_WS4_GMARK,
+	SSI_SCK4_GMARK,
+	SSI_SDATA3_GMARK,
+	SSI_WS34_GMARK,
+	SSI_SCK34_GMARK,
+	SSI_SDATA2_A_GMARK,
+	SSI_SDATA1_A_GMARK,
+	SSI_SDATA0_GMARK,
+	SSI_WS0129_GMARK,
+	SSI_SCK0129_GMARK,
+
+	/* GPSR7 */
+	HDMI1_CEC_MARK,
+	HDMI0_CEC_MARK,
+	AVS2_MARK,
+	AVS1_MARK,
+
+	/* IPSR0 */
+	AVB_MDC_IMARK,
+	MSIOF2_SS2_C_MARK,
+	AVB_MAGIC_IMARK,
+	MSIOF2_S1_C_MARK,
+	SCK4_A_MARK,
+	AVB_PHY_INT_IMARK,
+	MSIOF2_SYNC_C_MARK,
+	RX4_A_MARK,
+	AVB_LINK_IMARK,
+	MSIOF2_SCK_C_MARK,
+	TX4_A_MARK,
+	AVB_AVTP_MATCH_A_IMARK,
+	MSIOF2_RXD_C_MARK,
+	CTS4x_A_MARK,
+	AVB_AVTP_CAPTURE_A_IMARK,
+	MSIOF2_TXD_C_MARK,
+	RTS4x_TANS_A_MARK,
+	IRQ0_IMARK,
+	QPOLB_MARK,
+	DU_CDE_MARK,
+	VI4_DATA0_B_MARK,
+	CAN0_TX_B_MARK,
+	CANFD0_TX_B_MARK,
+	IRQ1_IMARK,
+	QPOLA_MARK,
+	DU_DISP_MARK,
+	VI4_DATA1_B_MARK,
+	CAN0_RX_B_MARK,
+	CANFD0_RX_B_MARK,
+
+	/* IPSR1 */
+	IRQ2_IMARK,
+	QCPV_QDE_MARK,
+	DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
+	VI4_DATA2_B_MARK,
+	PWM3_B_MARK,
+	IRQ3_IMARK,
+	QSTVB_QVE_MARK,
+	A25_MARK,
+	DU_DOTCLKOUT1_MARK,
+	VI4_DATA3_B_MARK,
+	PWM4_B_MARK,
+	IRQ4_IMARK,
+	QSTH_QHS_MARK,
+	A24_MARK,
+	DU_EXHSYNC_DU_HSYNC_MARK,
+	VI4_DATA4_B_MARK,
+	PWM5_B_MARK,
+	IRQ5_IMARK,
+	QSTB_QHE_MARK,
+	A23_MARK,
+	DU_EXVSYNC_DU_VSYNC_MARK,
+	VI4_DATA5_B_MARK,
+	PWM6_B_MARK,
+	PWM0_IMARK,
+	AVB_AVTP_PPS_MARK,
+	A22_MARK,
+	VI4_DATA6_B_MARK,
+	IECLK_B_MARK,
+	PWM1_A_IMARK,
+	A21_MARK,
+	HRX3_D_MARK,
+	VI4_DATA7_B_MARK,
+	IERX_B_MARK,
+	PWM2_A_IMARK,
+	PWMFSW0_MARK,
+	A20_MARK,
+	HTX3_D_MARK,
+	IETX_B_MARK,
+	A0_IMARK,
+	LCDOUT16_MARK,
+	MSIOF3_SYNC_B_MARK,
+	VI4_DATA8_MARK,
+	DU_DB0_MARK,
+	PWM3_A_MARK,
+
+	/* IPSR2 */
+	A1_IMARK,
+	LCDOUT17_MARK,
+	MSIOF3_TXD_B_MARK,
+	VI4_DATA9_MARK,
+	DU_DB1_MARK,
+	PWM4_A_MARK,
+	A2_IMARK,
+	LCDOUT18_MARK,
+	MSIOF3_SCK_B_MARK,
+	VI4_DATA10_MARK,
+	DU_DB2_MARK,
+	PWM5_A_MARK,
+	A3_IMARK,
+	LCDOUT19_MARK,
+	MSIOF3_RXD_B_MARK,
+	VI4_DATA11_MARK,
+	DU_DB3_MARK,
+	PWM6_A_MARK,
+	A4_IMARK,
+	LCDOUT20_MARK,
+	MSIOF3_SS1_B_MARK,
+	VI4_DATA12_MARK,
+	VI5_DATA12_MARK,
+	DU_DB4_MARK,
+	A5_IMARK,
+	LCDOUT21_MARK,
+	MSIOF3_SS2_B_MARK,
+	SCK4_B_MARK,
+	VI4_DATA13_MARK,
+	VI5_DATA13_MARK,
+	DU_DB5_MARK,
+	A6_IMARK,
+	LCDOUT22_MARK,
+	MSIOF2_SS1_A_MARK,
+	RX4_B_MARK,
+	VI4_DATA14_MARK,
+	VI5_DATA14_MARK,
+	DU_DB6_MARK,
+	A7_IMARK,
+	LCDOUT23_MARK,
+	MSIOF2_SS2_A_MARK,
+	TX4_B_MARK,
+	VI4_DATA15_MARK,
+	V15_DATA15_MARK,
+	DU_DB7_MARK,
+	A8_IMARK,
+	RX3_B_MARK,
+	MSIOF2_SYNC_A_MARK,
+	HRX4_B_MARK,
+	SDA6_A_MARK,
+	AVB_AVTP_MATCH_B_MARK,
+	PWM1_B_MARK,
+
+	/* IPSR3 */
+	A9_IMARK,
+	MSIOF2_SCK_A_MARK,
+	CTS4x_B_MARK,
+	VI5_VSYNCx_MARK,
+	A10_IMARK,
+	MSIOF2_RXD_A_MARK,
+	RTS4n_TANS_B_MARK,
+	VI5_HSYNCx_MARK,
+	A11_IMARK,
+	TX3_B_MARK,
+	MSIOF2_TXD_A_MARK,
+	HTX4_B_MARK,
+	HSCK4_MARK,
+	VI5_FIELD_MARK,
+	SCL6_A_MARK,
+	AVB_AVTP_CAPTURE_B_MARK,
+	PWM2_B_MARK,
+	SPV_EVEN_MARK,
+	A12_IMARK,
+	LCDOUT12_MARK,
+	MSIOF3_SCK_C_MARK,
+	HRX4_A_MARK,
+	VI5_DATA8_MARK,
+	DU_DG4_MARK,
+	A13_IMARK,
+	LCDOUT13_MARK,
+	MSIOF3_SYNC_C_MARK,
+	HTX4_A_MARK,
+	VI5_DATA9_MARK,
+	DU_DG5_MARK,
+	A14_IMARK,
+	LCDOUT14_MARK,
+	MSIOF3_RXD_C_MARK,
+	HCTS4x_MARK,
+	VI5_DATA10_MARK,
+	DU_DG6_MARK,
+	A15_IMARK,
+	LCDOUT15_MARK,
+	MSIOF3_TXD_C_MARK,
+	HRTS4x_MARK,
+	VI5_DATA11_MARK,
+	DU_DG7_MARK,
+	A16_IMARK,
+	LCDOUT8_MARK,
+	VI4_FIELD_MARK,
+	DU_DG0_MARK,
+
+	/* IPSR4 */
+	A17_IMARK,
+	LCDOUT9_MARK,
+	VI4_VSYNCx_MARK,
+	DU_DG1_MARK,
+	A18_IMARK,
+	LCDOUT10_MARK,
+	VI4_HSYNCx_MARK,
+	DU_DG2_MARK,
+	A19_IMARK,
+	LCDOUT11_MARK,
+	VI4_CLKENB_MARK,
+	DU_DG3_MARK,
+	CS0x_IMARK,
+	VI5_CLKENB_MARK,
+	CS1x_A26_IMARK,
+	VI5_CLK_MARK,
+	EX_WAIT0_B_MARK,
+	BSx_IMARK,
+	QSTVA_QVS_MARK,
+	MSIOF3_SCK_D_MARK,
+	SCK3_MARK,
+	HSCK3_MARK,
+	CAN1_TX_MARK,
+	CANFD1_TX_MARK,
+	IETX_A_MARK,
+	RDx_IMARK,
+	MSIOF3_SYNC_D_MARK,
+	RX3_A_MARK,
+	HRX3_A_MARK,
+	CAN0_TX_A_MARK,
+	CANFD0_TX_A_MARK,
+	RD_WRx_IMARK,
+	MSIOF3_RXD_D_MARK,
+	TX3_A_MARK,
+	HTX3_A_MARK,
+	CAN0_RX_A_MARK,
+	CANFD0_RX_A_MARK,
+
+	/* IPSR5 */
+	WE0x_IMARK,
+	MSIIOF3_TXD_D_MARK,
+	CTS3x_MARK,
+	HCTS3x_MARK,
+	SCL6_B_MARK,
+	CAN_CLK_MARK,
+	IECLK_A_MARK,
+	WE1x_IMARK,
+	MSIOF3_SS1_D_MARK,
+	RTS3x_TANS_MARK,
+	HRTS3x_MARK,
+	SDA6_B_MARK,
+	CAN1_RX_MARK,
+	CANFD1_RX_MARK,
+	IERX_A_MARK,
+	EX_WAIT0_A_IMARK,
+	QCLK_MARK,
+	VI4_CLK_MARK,
+	DU_DOTCLKOUT0_MARK,
+	D0_IMARK,
+	MSIOF2_SS1_B_MARK,
+	MSIOF3_SCK_A_MARK,
+	VI4_DATA16_MARK,
+	VI5_DATA0_MARK,
+	D1_IMARK,
+	MSIOF2_SS2_B_MARK,
+	MSIOF3_SYNC_A_MARK,
+	VI4_DATA17_MARK,
+	VI5_DATA1_MARK,
+	D2_IMARK,
+	MSIOF3_RXD_A_MARK,
+	VI4_DATA18_MARK,
+	VI5_DATA2_MARK,
+	D3_IMARK,
+	MSIOF3_TXD_A_MARK,
+	VI4_DATA19_MARK,
+	VI5_DATA3_MARK,
+	D4_IMARK,
+	MSIOF2_SCK_B_MARK,
+	VI4_DATA20_MARK,
+	VI5_DATA4_MARK,
+
+	/* IPSR6 */
+	D5_IMARK,
+	MSIOF2_SYNC_B_MARK,
+	VI4_DATA21_MARK,
+	VI5_DATA5_MARK,
+	D6_IMARK,
+	MSIOF2_RXD_B_MARK,
+	VI4_DATA22_MARK,
+	VI5_DATA6_MARK,
+	D7_IMARK,
+	MSIOF2_TXD_B_MARK,
+	VI4_DATA23_MARK,
+	VI5_DATA7_MARK,
+	D8_IMARK,
+	LCDOUT0_MARK,
+	MSIOF2_SCK_D_MARK,
+	SCK4_C_MARK,
+	VI4_DATA0_A_MARK,
+	DU_DR0_MARK,
+	D9_IMARK,
+	LCDOUT1_MARK,
+	MSIOF2_SYNC_D_MARK,
+	VI4_DATA1_A_MARK,
+	DU_DR1_MARK,
+	D10_IMARK,
+	LCDOUT2_MARK,
+	MSIOF2_RXD_D_MARK,
+	HRX3_B_MARK,
+	VI4_DATA2_A_MARK,
+	CTS4x_C_MARK,
+	DU_DR2_MARK,
+	D11_IMARK,
+	LCDOUT3_MARK,
+	MSIOF2_TXD_D_MARK,
+	HTX3_B_MARK,
+	VI4_DATA3_A_MARK,
+	RTS4x_TANS_C_MARK,
+	DU_DR3_MARK,
+	D12_IMARK,
+	LCDOUT4_MARK,
+	MSIOF2_SS1_D_MARK,
+	RX4_C_MARK,
+	VI4_DATA4_A_MARK,
+	DU_DR4_MARK,
+
+	/* IPSR7 */
+	D13_IMARK,
+	LCDOUT5_MARK,
+	MSIOF2_SS2_D_MARK,
+	TX4_C_MARK,
+	VI4_DATA5_A_MARK,
+	DU_DR5_MARK,
+	D14_IMARK,
+	LCDOUT6_MARK,
+	MSIOF3_SS1_A_MARK,
+	HRX3_C_MARK,
+	VI4_DATA6_A_MARK,
+	DU_DR6_MARK,
+	SCL6_C_MARK,
+	D15_IMARK,
+	LCDOUT7_MARK,
+	MSIOF3_SS2_A_MARK,
+	HTX3_C_MARK,
+	VI4_DATA7_A_MARK,
+	DU_DR7_MARK,
+	SDA6_C_MARK,
+	FSCLKST_MARK,
+	SD0_CLK_IMARK,
+	MSIOF1_SCK_E_MARK,
+	STP_OPWM_0_B_MARK,
+	SD0_CMD_IMARK,
+	MSIOF1_SYNC_E_MARK,
+	STP_IVCXO27_0_B_MARK,
+	SD0_DAT0_IMARK,
+	MSIOF1_RXD_E_MARK,
+	TS_SCK0_B_MARK,
+	STP_ISCLK_0_B_MARK,
+	SD0_DAT1_IMARK,
+	MSIOF1_TXD_E_MARK,
+	TS_SPSYNC0_B_MARK,
+	STP_ISSYNC_0_B_MARK,
+
+	/* IPSR8 */
+	SD0_DAT2_IMARK,
+	MSIOF1_SS1_E_MARK,
+	TS_SDAT0_B_MARK,
+	STP_ISD_0_B_MARK,
+	SD0_DAT3_IMARK,
+	MSIOF1_SS2_E_MARK,
+	TS_SDEN0_B_MARK,
+	STP_ISEN_0_B_MARK,
+	SD1_CLK_IMARK,
+	MSIOF1_SCK_G_MARK,
+	SIM0_CLK_A_MARK,
+
+	SD1_CMD_IMARK,
+	MSIOF1_SYNC_G_MARK,
+	SIM0_D_A_MARK,
+	STP_IVCXO27_1_B_MARK,
+
+	SD1_DAT0_IMARK,
+	SD2_DAT4_MARK,
+	MSIOF1_RXD_G_MARK,
+	TS_SCK1_B_MARK,
+	STP_ISCLK_1_B_MARK,
+
+	SD1_DAT1_IMARK,
+	SD2_DAT5_MARK,
+	MSIOF1_TXD_G_MARK,
+	TS_SPSYNC1_B_MARK,
+	STP_ISSYNC_1_B_MARK,
+
+	SD1_DAT2_IMARK,
+	SD2_DAT6_MARK,
+	MSIOF1_SS1_G_MARK,
+	TS_SDAT1_B_MARK,
+	STP_IOD_1_B_MARK,
+	SD1_DAT3_IMARK,
+	SD2_DAT7_MARK,
+	MSIOF1_SS2_G_MARK,
+	TS_SDEN1_B_MARK,
+	STP_ISEN_1_B_MARK,
+
+	/* IPSR9 */
+	SD2_CLK_IMARK,
+	SCKZ_A_MARK,
+	SD2_DAT0_IMARK,
+	MTSx_A_MARK,
+	SD2_DAT1_IMARK,
+	STMx_A_MARK,
+	SD2_DAT2_IMARK,
+	MDATA_A_MARK,
+	SD2_DAT3_IMARK,
+	SDATA_A_MARK,
+	SD2_DS_IMARK,
+	SATA_DEVSLP_B_MARK,
+	VSP_A_MARK,
+	SD3_DAT4_IMARK,
+	SD2_CD_A_MARK,
+	SD3_DAT5_IMARK,
+	SD2_WP_A_MARK,
+
+	/* IPSR10 */
+	SD3_DAT6_IMARK,
+	SD3_CD_MARK,
+	SD3_DAT7_IMARK,
+	SD3_WP_MARK,
+	SD0_CD_IMARK,
+	SCL2_B_MARK,
+	SIM0_RST_A_MARK,
+	SD0_WP_IMARK,
+	SDA2_B_MARK,
+	SD1_CD_IMARK,
+	SIM0_CLK_B_MARK,
+	SD1_WP_IMARK,
+	SIM0_D_B_MARK,
+	SCK0_IMARK,
+	HSCK1_B_MARK,
+	MSIOF1_SS2_B_MARK,
+	AUDIO_CLKC_B_MARK,
+	SDA2_A_MARK,
+	SIM0_RST_B_MARK,
+	STP_OPWM__C_MARK,
+	RIF0_CLK_B_MARK,
+	ADICHS2_MARK,
+	RX0_IMARK,
+	HRX1_B_MARK,
+	TS_SCK0_C_MARK,
+	STP_ISCLK_0_C_MARK,
+	RIF0_D0_B_MARK,
+
+	/* IPSR11 */
+	TX0_IMARK,
+	HTX1_B_MARK,
+	TS_SPSYNC0_C_MARK,
+	STP_ISSYNC_0_C_MARK,
+	RIF0_D1_B_MARK,
+	CTS0x_IMARK,
+	HCTS1x_B_MARK,
+	MSIOF1_SYNC_B_MARK,
+	TS_SPSYNC1_C_MARK,
+	STP_ISSYNC_1_C_MARK,
+	RIF1_SYNC_B_MARK,
+	AUDIO_CLKOUT_C_MARK,
+	ADICS_SAMP_MARK,
+	RTS0x_TANS_IMARK,
+	HRTS1x_B_MARK,
+	MSIOF1_SS1_B_MARK,
+	AUDIO_CLKA_B_MARK,
+	SCL2_A_MARK,
+	STP_IVCXO27_1_C_MARK,
+	RIF0_SYNC_B_MARK,
+	ADICHS1_MARK,
+	RX1_A_IMARK,
+	HRX1_A_MARK,
+	TS_SDAT0_C_MARK,
+	STP_IDS_0_C_MARK,
+	RIF1_CLK_C_MARK,
+	TX1_A_IMARK,
+	HTX1_A_MARK,
+	TS_SDEN0_C_MARK,
+	STP_ISEN_0_C_MARK,
+	RIF1_D0_C_MARK,
+	CTS1x_IMARK,
+	HCTS1x_A_MARK,
+	MSIOF1_RXD_B_MARK,
+	TS_SDEN1_C_MARK,
+	STP_ISEN_1_C_MARK,
+	RIF1_D0_B_MARK,
+	ADIDATA_MARK,
+	RTS1x_TANS_IMARK,
+	HRTS1x_A_MARK,
+	MSIOF1_TXD_B_MARK,
+	TS_SDAT1_C_MARK,
+	STP_ISD_1_C_MARK,
+	RIF1_D1_B_MARK,
+	ADICHS0_MARK,
+	SCK2_IMARK,
+	SCIF_CLK_B_MARK,
+	MSIOF1_SCK_B_MARK,
+	TS_SCK1_C_MARK,
+	STP_ISCLK_1_C_MARK,
+	RIF1_CLK_B_MARK,
+	ADICLK_MARK,
+
+	/* IPSR12 */
+	TX2_A_IMARK,
+	SD2_CD_B_MARK,
+	SCL1_A_MARK,
+	RSD_CLK_B_MARK,
+	FMCLK_A_MARK,
+	RIF1_D1_C_MARK,
+	FSO_CFE_0_B_MARK,
+	RX2_A_IMARK,
+	SD2_WP_B_MARK,
+	SDA1_A_MARK,
+	RDS_DATA_B_MARK,
+	RMIN_A_MARK,
+	RIF1_SYNC_C_MARK,
+	FSO_CEF_1_B_MARK,
+	HSCK0_IMARK,
+	MSIOF1_SCK_D_MARK,
+	AUDIO_CLKB_A_MARK,
+	SSI_SDATA1_B_MARK,
+	TS_SCK0_D_MARK,
+	STP_ISCLK_0_D_MARK,
+	RIF0_CLK_C_MARK,
+	AD_CLK_MARK,
+	HRX0_IMARK,
+	MSIOF1_RXD_D_MARK,
+	SS1_SDATA2_B_MARK,
+	TS_SDEN0_D_MARK,
+	STP_ISEN_0_D_MARK,
+	RIF0_D0_C_MARK,
+	AD_DI_MARK,
+	HTX0_IMARK,
+	MSIOF1_TXD_D_MARK,
+	SSI_SDATA9_B_MARK,
+	TS_SDAT0_D_MARK,
+	STP_ISD_0_D_MARK,
+	RIF0_D1_C_MARK,
+	AD_DO_MARK,
+	HCTS0x_IMARK,
+	RX2_B_MARK,
+	MSIOF1_SYNC_D_MARK,
+	SSI_SCK9_A_MARK,
+	TS_SPSYNC0_D_MARK,
+	STP_ISSYNC_0_D_MARK,
+	RIF0_SYNC_C_MARK,
+	AUDIO_CLKOUT1_A_MARK,
+	AD_NSCx_MARK,
+	HRTS0x_IMARK,
+	TX2_B_MARK,
+	MSIOF1_SS1_D_MARK,
+	SSI_WS9_A_MARK,
+	STP_IVCXO27_0_D_MARK,
+	BPFCLK_A_MARK,
+	AUDIO_CLKOUT2_A_MARK,
+	MSIOF0_SYNC_IMARK,
+	AUDIO_CLKOUT_A_MARK,
+
+	/* IPSR13 */
+	MSIOF0_SS1_IMARK,
+	RX5_MARK,
+	AUDIO_CLKA_C_MARK,
+	SSI_SCK2_A_MARK,
+	RDS_CLK_A_MARK,
+	STP_IVCXO27_0_C_MARK,
+	AUDIO_CLKOUT3_A_MARK,
+	TCLK1_B_MARK,
+	MSIOF0_SS2_IMARK,
+	TX5_MARK,
+	MSIOF1_SS2_D_MARK,
+	AUDIO_CLKC_A_MARK,
+	SSI_WS2_A_MARK,
+	RDS_DATA_A_MARK,
+	STP_OPWM_0_D_MARK,
+	AUDIO_CLKOUT_D_MARK,
+	SPEEDIN_B_MARK,
+	MLB_CLK_IMARK,
+	MSIOF1_SCK_F_MARK,
+	SCL1_B_MARK,
+	MLB_SIG_IMARK,
+	RX1_B_MARK,
+	MSIOF1_SYNC_F_MARK,
+	SDA1_B_MARK,
+	MLB_DAT_IMARK,
+	TX1_B_MARK,
+	MSIOF1_RXD_F_MARK,
+	SSI_SCK0129_IMARK,
+	MSIOF1_TXD_F_MARK,
+	MOUT0_MARK,
+	SSI_WS0129_IMARK,
+	MSIOF1_SS1_F_MARK,
+	MOUT1_MARK,
+	SSI_SDATA0_IMARK,
+	MSIOF1_SS2_F_MARK,
+	MOUT2_MARK,
+
+	/* IPSR14 */
+	SSI_SDATA1_A_IMARK,
+	MOUT5_MARK,
+	SSI_SDATA2_A_IMARK,
+	SSI_SCK1_B_MARK,
+	MOUT6_MARK,
+	SSI_SCK34_IMARK,
+	MSIOF1_SS1_A_MARK,
+	STP_OPWM_0_A_MARK,
+	SSI_WS34_IMARK,
+	HCTS2x_A_MARK,
+	MSIOF1_SS2_A_MARK,
+	STP_IVCXO27_0_A_MARK,
+	SSI_SDATA3_IMARK,
+	HRTS2x_A_MARK,
+	MSIOF1_TXD_A_MARK,
+	TS_SCK0_A_MARK,
+	STP_ISCLK_0_A_MARK,
+	RIF0_D1_A_MARK,
+	RIF2_D0_A_MARK,
+	SSI_SCK4_IMARK,
+	HRX2_A_MARK,
+	MSIOF1_SCK_A_MARK,
+	TS_SDAT0_A_MARK,
+	STP_ISD_0_A_MARK,
+	RIF0_CLK_A_MARK,
+	RIF2_CLK_A_MARK,
+	SSI_WS4_IMARK,
+	HTX2_A_MARK,
+	MSIOF1_SYNC_A_MARK,
+	TS_SDEN0_A_MARK,
+	STP_ISEN_0_A_MARK,
+	RIF0_SYNC_A_MARK,
+	RIF2_SYNC_A_MARK,
+	SSI_SDATA4_IMARK,
+	HSCK2_A_MARK,
+	MSIOF1_RXD_A_MARK,
+	TS_SPSYNC0_A_MARK,
+	STP_ISSYNC_0_A_MARK,
+	RIF0_D0_A_MARK,
+	RIF2_D1_A_MARK,
+
+	SSI_SCK6_IMARK,
+	USB2_PWEN_MARK,
+	SIM0_RST_D_MARK,
+	RDS_CLK_C_MARK,
+	SSI_WS6_IMARK,
+	USB2_OVC_MARK,
+	SIM0_D_D_MARK,
+	SSI_SDATA6_IMARK,
+	SIM0_CLK_D_MARK,
+	RSD_DATA_C_MARK,
+	SATA_DEVSLP_A_MARK,
+	SSI_SCK78_IMARK,
+	HRX2_B_MARK,
+	MSIOF1_SCK_C_MARK,
+	TS_SCK1_A_MARK,
+	STP_ISCLK_1_A_MARK,
+	RIF1_CLK_A_MARK,
+	RIF3_CLK_A_MARK,
+	SSI_WS78_IMARK,
+	HTX2_B_MARK,
+	MSIOF1_SYNC_C_MARK,
+	TS_SDT1_A_MARK,
+	STP_ISD_1_A_MARK,
+	RIF1_SYNC_A_MARK,
+	RIF3_SYNC_A_MARK,
+	SSI_SDATA7_IMARK,
+	HCTS2x_B_MARK,
+	MSIOF1_RXD_C_MARK,
+	TS_SDEN1_A_MARK,
+	STP_IEN_1_A_MARK,
+	RIF1_D0_A_MARK,
+	RIF3_D0_A_MARK,
+	TCLK2_A_MARK,
+	SSI_SDATA8_IMARK,
+	HRTS2x_B_MARK,
+	MSIOF1_TXD_C_MARK,
+	TS_SPSYNC1_A_MARK,
+	STP_ISSYNC_1_A_MARK,
+	RIF1_D1_A_MARK,
+	EIF3_D1_A_MARK,
+	SSI_SDATA9_A_IMARK,
+	HSCK2_B_MARK,
+	MSIOF1_SS1_C_MARK,
+	HSCK1_A_MARK,
+	SSI_WS1_B_MARK,
+	SCK1_MARK,
+	STP_IVCXO27_1_A_MARK,
+	SCK5_MARK,
+
+	/* IPSR16 */
+	AUDIO_CLKA_A_IMARK,
+	CC5_OSCOUT_MARK,
+	AUDIO_CLKB_B_IMARK,
+	SCIF_CLK_A_MARK,
+	DVC_MUTE_MARK,
+	STP_IVCXO27_1_D_MARK,
+	REMOCON_A_MARK,
+	TCLK1_A_MARK,
+	VSP_B_MARK,
+	USB0_PWEN_IMARK,
+	SIM0_RST_C_MARK,
+	TS_SCK1_D_MARK,
+	STP_ISCLK_1_D_MARK,
+	BPFCLK_B_MARK,
+	RIF3_CLK_B_MARK,
+	SCKZ_B_MARK,
+	USB0_OVC_IMARK,
+	SIM0_D_C_MARK,
+	TS_SDAT1_D_MARK,
+	STP_ISD_1_D_MARK,
+	RIF3_SYNC_B_MARK,
+	VSP_C_MARK,
+	USB1_PWEN_IMARK,
+	SIM0_CLK_C_MARK,
+	SSI_SCK1_A_MARK,
+	TS_SCK0_E_MARK,
+	STP_ISCLK_0_E_MARK,
+	FMCLK_B_MARK,
+	RIF2_CLK_B_MARK,
+	MTSx_B_MARK,
+	SPEEDIN_A_MARK,
+	VSP_D_MARK,
+	USB1_OVC_IMARK,
+	MSIOF1_SS2_C_MARK,
+	SSI_WS1_A_MARK,
+	TS_SDAT0_E_MARK,
+	STP_ISD_0_E_MARK,
+	FMIN_B_MARK,
+	RIF2_SYNC_B_MARK,
+	STMx_B_MARK,
+	REMOCON_B_MARK,
+	USB30_PWEN_IMARK,
+	AUDIO_CLKOUT_B_MARK,
+	SSI_SCK2_B_MARK,
+	TS_SDEN1_D_MARK,
+	STP_ISEN_1_D_MARK,
+	STP_OPWM_0_E_MARK,
+	RIF3_D0_B_MARK,
+	MDATA_B_MARK,
+	TCLK2_B_MARK,
+	TPU0TO0_MARK,
+	USB30_OVC_IMARK,
+	AUDIO_CLKOUT1_B_MARK,
+	SSI_WS2_B_MARK,
+	TS_SPSYNC1_D_MARK,
+	STP_ISSYNC_1_D_MARK,
+	STP_IVCXO27_0_E_MARK,
+	RIF3_D1_B_MARK,
+	SDATA_B_MARK,
+	RSO_TOE_B_MARK,
+	TPU0TO1_MARK,
+
+	/* IPSR17 */
+	USB31_PWEN_IMARK,
+	AUDIO_CLKOUT2_B_MARK,
+	SI_SCK9_B_MARK,
+	TS_SDEN0_E_MARK,
+	STP_ISEN_0_E_MARK,
+	RIF2_D0_B_MARK,
+	TPU0TO2_MARK,
+	USB31_OVC_IMARK,
+	AUDIO_CLKOUT3_B_MARK,
+	SSI_WS9_B_MARK,
+	TS_SPSYNC0_E_MARK,
+	STP_ISSYNC_0_E_MARK,
+	RIF2_D1_B_MARK,
+	TPU0TO3_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	/* GPSR0 */
+	PINMUX_DATA(D15_GMARK, GFN_D15),
+	PINMUX_DATA(D14_GMARK, GFN_D14),
+	PINMUX_DATA(D13_GMARK, GFN_D13),
+	PINMUX_DATA(D12_GMARK, GFN_D12),
+	PINMUX_DATA(D11_GMARK, GFN_D11),
+	PINMUX_DATA(D10_GMARK, GFN_D10),
+	PINMUX_DATA(D9_GMARK, GFN_D9),
+	PINMUX_DATA(D8_GMARK, GFN_D8),
+	PINMUX_DATA(D7_GMARK, GFN_D7),
+	PINMUX_DATA(D6_GMARK, GFN_D6),
+	PINMUX_DATA(D5_GMARK, GFN_D5),
+	PINMUX_DATA(D4_GMARK, GFN_D4),
+	PINMUX_DATA(D3_GMARK, GFN_D3),
+	PINMUX_DATA(D2_GMARK, GFN_D2),
+	PINMUX_DATA(D1_GMARK, GFN_D1),
+	PINMUX_DATA(D0_GMARK, GFN_D0),
+
+	/* GPSR1 */
+	PINMUX_DATA(EX_WAIT0_A_GMARK, GFN_EX_WAIT0_A),
+	PINMUX_DATA(WE1x_GMARK, GFN_WE1x),
+	PINMUX_DATA(WE0x_GMARK, GFN_WE0x),
+	PINMUX_DATA(RD_WRx_GMARK, GFN_RD_WRx),
+	PINMUX_DATA(RDx_GMARK, GFN_RDx),
+	PINMUX_DATA(BSx_GMARK, GFN_BSx),
+	PINMUX_DATA(CS1x_A26_GMARK, GFN_CS1x_A26),
+	PINMUX_DATA(CS0x_GMARK, GFN_CS0x),
+	PINMUX_DATA(A19_GMARK, GFN_A19),
+	PINMUX_DATA(A18_GMARK, GFN_A18),
+	PINMUX_DATA(A17_GMARK, GFN_A17),
+	PINMUX_DATA(A16_GMARK, GFN_A16),
+	PINMUX_DATA(A15_GMARK, GFN_A15),
+	PINMUX_DATA(A14_GMARK, GFN_A14),
+	PINMUX_DATA(A13_GMARK, GFN_A13),
+	PINMUX_DATA(A12_GMARK, GFN_A12),
+	PINMUX_DATA(A11_GMARK, GFN_A11),
+	PINMUX_DATA(A10_GMARK, GFN_A10),
+	PINMUX_DATA(A9_GMARK, GFN_A9),
+	PINMUX_DATA(A8_GMARK, GFN_A8),
+	PINMUX_DATA(A7_GMARK, GFN_A7),
+	PINMUX_DATA(A6_GMARK, GFN_A6),
+	PINMUX_DATA(A5_GMARK, GFN_A5),
+	PINMUX_DATA(A4_GMARK, GFN_A4),
+	PINMUX_DATA(A3_GMARK, GFN_A3),
+	PINMUX_DATA(A2_GMARK, GFN_A2),
+	PINMUX_DATA(A1_GMARK, GFN_A1),
+	PINMUX_DATA(A0_GMARK, GFN_A0),
+
+	/* GPSR2 */
+	PINMUX_DATA(AVB_AVTP_CAPTURE_A_GMARK, GFN_AVB_AVTP_CAPTURE_A),
+	PINMUX_DATA(AVB_AVTP_MATCH_A_GMARK, GFN_AVB_AVTP_MATCH_A),
+	PINMUX_DATA(AVB_LINK_GMARK, GFN_AVB_LINK),
+	PINMUX_DATA(AVB_PHY_INT_GMARK, GFN_AVB_PHY_INT),
+	PINMUX_DATA(AVB_MAGIC_GMARK, GFN_AVB_MAGIC),
+	PINMUX_DATA(AVB_MDC_GMARK, GFN_AVB_MDC),
+	PINMUX_DATA(PWM2_A_GMARK, GFN_PWM2_A),
+	PINMUX_DATA(PWM1_A_GMARK, GFN_PWM1_A),
+	PINMUX_DATA(PWM0_GMARK, GFN_PWM0),
+	PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5),
+	PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4),
+	PINMUX_DATA(IRQ3_GMARK, GFN_IRQ3),
+	PINMUX_DATA(IRQ2_GMARK, GFN_IRQ2),
+	PINMUX_DATA(IRQ1_GMARK, GFN_IRQ1),
+	PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0),
+
+	/* GPSR3 */
+	PINMUX_DATA(SD1_WP_GMARK, GFN_SD1_WP),
+	PINMUX_DATA(SD1_CD_GMARK, GFN_SD1_CD),
+	PINMUX_DATA(SD0_WP_GMARK, GFN_SD0_WP),
+	PINMUX_DATA(SD0_CD_GMARK, GFN_SD0_CD),
+	PINMUX_DATA(SD1_DAT3_GMARK, GFN_SD1_DAT3),
+	PINMUX_DATA(SD1_DAT2_GMARK, GFN_SD1_DAT2),
+	PINMUX_DATA(SD1_DAT1_GMARK, GFN_SD1_DAT1),
+	PINMUX_DATA(SD1_DAT0_GMARK, GFN_SD1_DAT0),
+	PINMUX_DATA(SD1_CMD_GMARK, GFN_SD1_CMD),
+	PINMUX_DATA(SD1_CLK_GMARK, GFN_SD1_CLK),
+	PINMUX_DATA(SD0_DAT3_GMARK, GFN_SD0_DAT3),
+	PINMUX_DATA(SD0_DAT2_GMARK, GFN_SD0_DAT2),
+	PINMUX_DATA(SD0_DAT1_GMARK, GFN_SD0_DAT1),
+	PINMUX_DATA(SD0_DAT0_GMARK, GFN_SD0_DAT0),
+	PINMUX_DATA(SD0_CMD_GMARK, GFN_SD0_CMD),
+	PINMUX_DATA(SD0_CLK_GMARK, GFN_SD0_CLK),
+
+	/* GPSR4 */
+	PINMUX_DATA(SD3_DS_MARK, FN_SD3_DS),
+	PINMUX_DATA(SD3_DAT7_GMARK, GFN_SD3_DAT7),
+	PINMUX_DATA(SD3_DAT6_GMARK, GFN_SD3_DAT6),
+	PINMUX_DATA(SD3_DAT5_GMARK, GFN_SD3_DAT5),
+	PINMUX_DATA(SD3_DAT4_GMARK, GFN_SD3_DAT4),
+	PINMUX_DATA(SD3_DAT3_MARK, FN_SD3_DAT3),
+	PINMUX_DATA(SD3_DAT2_MARK, FN_SD3_DAT2),
+	PINMUX_DATA(SD3_DAT1_MARK, FN_SD3_DAT1),
+	PINMUX_DATA(SD3_DAT0_MARK, FN_SD3_DAT0),
+	PINMUX_DATA(SD3_CMD_MARK, FN_SD3_CMD),
+	PINMUX_DATA(SD3_CLK_MARK, FN_SD3_CLK),
+	PINMUX_DATA(SD2_DS_GMARK, GFN_SD2_DS),
+	PINMUX_DATA(SD2_DAT3_GMARK, GFN_SD2_DAT3),
+	PINMUX_DATA(SD2_DAT2_GMARK, GFN_SD2_DAT2),
+	PINMUX_DATA(SD2_DAT1_GMARK, GFN_SD2_DAT1),
+	PINMUX_DATA(SD2_DAT0_GMARK, GFN_SD2_DAT0),
+	PINMUX_DATA(SD2_CMD_MARK, FN_SD2_CMD),
+	PINMUX_DATA(SD2_CLK_GMARK, GFN_SD2_CLK),
+
+	/* GPSR5 */
+	PINMUX_DATA(MLB_DAT_GMARK, GFN_MLB_DAT),
+	PINMUX_DATA(MLB_SIG_GMARK, GFN_MLB_SIG),
+	PINMUX_DATA(MLB_CLK_GMARK, GFN_MLB_CLK),
+	PINMUX_DATA(MSIOF0_RXD_MARK, FN_MSIOF0_RXD),
+	PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2),
+	PINMUX_DATA(MSIOF0_TXD_MARK, FN_MSIOF0_TXD),
+	PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1),
+	PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC),
+	PINMUX_DATA(MSIOF0_SCK_MARK, FN_MSIOF0_SCK),
+	PINMUX_DATA(HRTS0x_GMARK, GFN_HRTS0x),
+	PINMUX_DATA(HCTS0x_GMARK, GFN_HCTS0x),
+	PINMUX_DATA(HTX0_GMARK, GFN_HTX0),
+	PINMUX_DATA(HRX0_GMARK, GFN_HRX0),
+	PINMUX_DATA(HSCK0_GMARK, GFN_HSCK0),
+	PINMUX_DATA(RX2_A_GMARK, GFN_RX2_A),
+	PINMUX_DATA(TX2_A_GMARK, GFN_TX2_A),
+	PINMUX_DATA(SCK2_GMARK, GFN_SCK2),
+	PINMUX_DATA(RTS1x_TANS_GMARK, GFN_RTS1x_TANS),
+	PINMUX_DATA(CTS1x_GMARK, GFN_CTS1x),
+	PINMUX_DATA(TX1_A_GMARK, GFN_TX1_A),
+	PINMUX_DATA(RX1_A_GMARK, GFN_RX1_A),
+	PINMUX_DATA(RTS0x_TANS_GMARK, GFN_RTS0x_TANS),
+	PINMUX_DATA(CTS0x_GMARK, GFN_CTS0x),
+	PINMUX_DATA(TX0_GMARK, GFN_TX0),
+	PINMUX_DATA(RX0_GMARK, GFN_RX0),
+	PINMUX_DATA(SCK0_GMARK, GFN_SCK0),
+
+	/* GPSR6 */
+	PINMUX_DATA(USB31_OVC_GMARK, GFN_USB31_OVC),
+	PINMUX_DATA(USB31_PWEN_GMARK, GFN_USB31_PWEN),
+	PINMUX_DATA(USB30_OVC_GMARK, GFN_USB30_OVC),
+	PINMUX_DATA(USB30_PWEN_GMARK, GFN_USB30_PWEN),
+	PINMUX_DATA(USB1_OVC_GMARK, GFN_USB1_OVC),
+	PINMUX_DATA(USB1_PWEN_GMARK, GFN_USB1_PWEN),
+	PINMUX_DATA(USB0_OVC_GMARK, GFN_USB0_OVC),
+	PINMUX_DATA(USB0_PWEN_GMARK, GFN_USB0_PWEN),
+	PINMUX_DATA(AUDIO_CLKB_B_GMARK, GFN_AUDIO_CLKB_B),
+	PINMUX_DATA(AUDIO_CLKA_A_GMARK, GFN_AUDIO_CLKA_A),
+	PINMUX_DATA(SSI_SDATA9_A_GMARK, GFN_SSI_SDATA9_A),
+	PINMUX_DATA(SSI_SDATA8_GMARK, GFN_SSI_SDATA8),
+	PINMUX_DATA(SSI_SDATA7_GMARK, GFN_SSI_SDATA7),
+	PINMUX_DATA(SSI_WS78_GMARK, GFN_SSI_WS78),
+	PINMUX_DATA(SSI_SCK78_GMARK, GFN_SSI_SCK78),
+	PINMUX_DATA(SSI_SDATA6_GMARK, GFN_SSI_SDATA6),
+	PINMUX_DATA(SSI_WS6_GMARK, GFN_SSI_WS6),
+	PINMUX_DATA(SSI_SCK6_GMARK, GFN_SSI_SCK6),
+	PINMUX_DATA(SSI_SDATA5_MARK, FN_SSI_SDATA5),
+	PINMUX_DATA(SSI_WS5_MARK, FN_SSI_WS5),
+	PINMUX_DATA(SSI_SCK5_MARK, FN_SSI_SCK5),
+	PINMUX_DATA(SSI_SDATA4_GMARK, GFN_SSI_SDATA4),
+	PINMUX_DATA(SSI_WS4_GMARK, GFN_SSI_WS4),
+	PINMUX_DATA(SSI_SCK4_GMARK, GFN_SSI_SCK4),
+	PINMUX_DATA(SSI_SDATA3_GMARK, GFN_SSI_SDATA3),
+	PINMUX_DATA(SSI_WS34_GMARK, GFN_SSI_WS34),
+	PINMUX_DATA(SSI_SCK34_GMARK, GFN_SSI_SCK34),
+	PINMUX_DATA(SSI_SDATA2_A_GMARK, GFN_SSI_SDATA2_A),
+	PINMUX_DATA(SSI_SDATA1_A_GMARK, GFN_SSI_SDATA1_A),
+	PINMUX_DATA(SSI_SDATA0_GMARK, GFN_SSI_SDATA0),
+	PINMUX_DATA(SSI_WS0129_GMARK, GFN_SSI_WS0129),
+	PINMUX_DATA(SSI_SCK0129_GMARK, GFN_SSI_SCK0129),
+
+	/* GPSR7 */
+	PINMUX_DATA(HDMI1_CEC_MARK, FN_HDMI1_CEC),
+	PINMUX_DATA(HDMI0_CEC_MARK, FN_HDMI0_CEC),
+	PINMUX_DATA(AVS2_MARK, FN_AVS2),
+	PINMUX_DATA(AVS1_MARK, FN_AVS1),
+
+	/* ipsr setting .. underconstruction */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+	/* GPSR0 */
+	GPIO_GFN(D15),
+	GPIO_GFN(D14),
+	GPIO_GFN(D13),
+	GPIO_GFN(D12),
+	GPIO_GFN(D11),
+	GPIO_GFN(D10),
+	GPIO_GFN(D9),
+	GPIO_GFN(D8),
+	GPIO_GFN(D7),
+	GPIO_GFN(D6),
+	GPIO_GFN(D5),
+	GPIO_GFN(D4),
+	GPIO_GFN(D3),
+	GPIO_GFN(D2),
+	GPIO_GFN(D1),
+	GPIO_GFN(D0),
+	/* GPSR1 */
+	GPIO_GFN(EX_WAIT0_A),
+	GPIO_GFN(WE1x),
+	GPIO_GFN(WE0x),
+	GPIO_GFN(RD_WRx),
+	GPIO_GFN(RDx),
+	GPIO_GFN(BSx),
+	GPIO_GFN(CS1x_A26),
+	GPIO_GFN(CS0x),
+	GPIO_GFN(A19),
+	GPIO_GFN(A18),
+	GPIO_GFN(A17),
+	GPIO_GFN(A16),
+	GPIO_GFN(A15),
+	GPIO_GFN(A14),
+	GPIO_GFN(A13),
+	GPIO_GFN(A12),
+	GPIO_GFN(A11),
+	GPIO_GFN(A10),
+	GPIO_GFN(A9),
+	GPIO_GFN(A8),
+	GPIO_GFN(A7),
+	GPIO_GFN(A6),
+	GPIO_GFN(A5),
+	GPIO_GFN(A4),
+	GPIO_GFN(A3),
+	GPIO_GFN(A2),
+	GPIO_GFN(A1),
+	GPIO_GFN(A0),
+
+	/* GPSR2 */
+	GPIO_GFN(AVB_AVTP_CAPTURE_A),
+	GPIO_GFN(AVB_AVTP_MATCH_A),
+	GPIO_GFN(AVB_LINK),
+	GPIO_GFN(AVB_PHY_INT),
+	GPIO_GFN(AVB_MAGIC),
+	GPIO_GFN(AVB_MDC),
+	GPIO_GFN(PWM2_A),
+	GPIO_GFN(PWM1_A),
+	GPIO_GFN(PWM0),
+	GPIO_GFN(IRQ5),
+	GPIO_GFN(IRQ4),
+	GPIO_GFN(IRQ3),
+	GPIO_GFN(IRQ2),
+	GPIO_GFN(IRQ1),
+	GPIO_GFN(IRQ0),
+
+	/* GPSR3 */
+	GPIO_GFN(SD1_WP),
+	GPIO_GFN(SD1_CD),
+	GPIO_GFN(SD0_WP),
+	GPIO_GFN(SD0_CD),
+	GPIO_GFN(SD1_DAT3),
+	GPIO_GFN(SD1_DAT2),
+	GPIO_GFN(SD1_DAT1),
+	GPIO_GFN(SD1_DAT0),
+	GPIO_GFN(SD1_CMD),
+	GPIO_GFN(SD1_CLK),
+	GPIO_GFN(SD0_DAT3),
+	GPIO_GFN(SD0_DAT2),
+	GPIO_GFN(SD0_DAT1),
+	GPIO_GFN(SD0_DAT0),
+	GPIO_GFN(SD0_CMD),
+	GPIO_GFN(SD0_CLK),
+
+	/* GPSR4 */
+	GPIO_FN(SD3_DS),
+	GPIO_GFN(SD3_DAT7),
+	GPIO_GFN(SD3_DAT6),
+	GPIO_GFN(SD3_DAT5),
+	GPIO_GFN(SD3_DAT4),
+	GPIO_FN(SD3_DAT3),
+	GPIO_FN(SD3_DAT2),
+	GPIO_FN(SD3_DAT1),
+	GPIO_FN(SD3_DAT0),
+	GPIO_FN(SD3_CMD),
+	GPIO_FN(SD3_CLK),
+	GPIO_GFN(SD2_DS),
+	GPIO_GFN(SD2_DAT3),
+	GPIO_GFN(SD2_DAT2),
+	GPIO_GFN(SD2_DAT1),
+	GPIO_GFN(SD2_DAT0),
+	GPIO_FN(SD2_CMD),
+	GPIO_GFN(SD2_CLK),
+
+	/* GPSR5 */
+	GPIO_GFN(MLB_DAT),
+	GPIO_GFN(MLB_SIG),
+	GPIO_GFN(MLB_CLK),
+	GPIO_FN(MSIOF0_RXD),
+	GPIO_GFN(MSIOF0_SS2),
+	GPIO_FN(MSIOF0_TXD),
+	GPIO_GFN(MSIOF0_SS1),
+	GPIO_GFN(MSIOF0_SYNC),
+	GPIO_FN(MSIOF0_SCK),
+	GPIO_GFN(HRTS0x),
+	GPIO_GFN(HCTS0x),
+	GPIO_GFN(HTX0),
+	GPIO_GFN(HRX0),
+	GPIO_GFN(HSCK0),
+	GPIO_GFN(RX2_A),
+	GPIO_GFN(TX2_A),
+	GPIO_GFN(SCK2),
+	GPIO_GFN(RTS1x_TANS),
+	GPIO_GFN(CTS1x),
+	GPIO_GFN(TX1_A),
+	GPIO_GFN(RX1_A),
+	GPIO_GFN(RTS0x_TANS),
+	GPIO_GFN(CTS0x),
+	GPIO_GFN(TX0),
+	GPIO_GFN(RX0),
+	GPIO_GFN(SCK0),
+
+	/* GPSR6 */
+	GPIO_GFN(USB31_OVC),
+	GPIO_GFN(USB31_PWEN),
+	GPIO_GFN(USB30_OVC),
+	GPIO_GFN(USB30_PWEN),
+	GPIO_GFN(USB1_OVC),
+	GPIO_GFN(USB1_PWEN),
+	GPIO_GFN(USB0_OVC),
+	GPIO_GFN(USB0_PWEN),
+	GPIO_GFN(AUDIO_CLKB_B),
+	GPIO_GFN(AUDIO_CLKA_A),
+	GPIO_GFN(SSI_SDATA9_A),
+	GPIO_GFN(SSI_SDATA8),
+	GPIO_GFN(SSI_SDATA7),
+	GPIO_GFN(SSI_WS78),
+	GPIO_GFN(SSI_SCK78),
+	GPIO_GFN(SSI_SDATA6),
+	GPIO_GFN(SSI_WS6),
+	GPIO_GFN(SSI_SCK6),
+	GPIO_FN(SSI_SDATA5),
+	GPIO_FN(SSI_WS5),
+	GPIO_FN(SSI_SCK5),
+	GPIO_GFN(SSI_SDATA4),
+	GPIO_GFN(SSI_WS4),
+	GPIO_GFN(SSI_SCK4),
+	GPIO_GFN(SSI_SDATA3),
+	GPIO_GFN(SSI_WS34),
+	GPIO_GFN(SSI_SCK34),
+	GPIO_GFN(SSI_SDATA2_A),
+	GPIO_GFN(SSI_SDATA1_A),
+	GPIO_GFN(SSI_SDATA0),
+	GPIO_GFN(SSI_WS0129),
+	GPIO_GFN(SSI_SCK0129),
+
+	/* GPSR7 */
+	GPIO_FN(HDMI1_CEC),
+	GPIO_FN(HDMI0_CEC),
+	GPIO_FN(AVS2),
+	GPIO_FN(AVS1),
+
+	/* IPSR0 */
+	GPIO_IFN(AVB_MDC),
+	GPIO_FN(MSIOF2_SS2_C),
+	GPIO_IFN(AVB_MAGIC),
+	GPIO_FN(MSIOF2_S1_C),
+	GPIO_FN(SCK4_A),
+	GPIO_IFN(AVB_PHY_INT),
+	GPIO_FN(MSIOF2_SYNC_C),
+	GPIO_FN(RX4_A),
+	GPIO_IFN(AVB_LINK),
+	GPIO_FN(MSIOF2_SCK_C),
+	GPIO_FN(TX4_A),
+	GPIO_IFN(AVB_AVTP_MATCH_A),
+	GPIO_FN(MSIOF2_RXD_C),
+	GPIO_FN(CTS4x_A),
+	GPIO_IFN(AVB_AVTP_CAPTURE_A),
+	GPIO_FN(MSIOF2_TXD_C),
+	GPIO_FN(RTS4x_TANS_A),
+	GPIO_IFN(IRQ0),
+	GPIO_FN(QPOLB),
+	GPIO_FN(DU_CDE),
+	GPIO_FN(VI4_DATA0_B),
+	GPIO_FN(CAN0_TX_B),
+	GPIO_FN(CANFD0_TX_B),
+	GPIO_IFN(IRQ1),
+	GPIO_FN(QPOLA),
+	GPIO_FN(DU_DISP),
+	GPIO_FN(VI4_DATA1_B),
+	GPIO_FN(CAN0_RX_B),
+	GPIO_FN(CANFD0_RX_B),
+
+	/* IPSR1 */
+	GPIO_IFN(IRQ2),
+	GPIO_FN(QCPV_QDE),
+	GPIO_FN(DU_EXODDF_DU_ODDF_DISP_CDE),
+	GPIO_FN(VI4_DATA2_B),
+	GPIO_FN(PWM3_B),
+	GPIO_IFN(IRQ3),
+	GPIO_FN(QSTVB_QVE),
+	GPIO_FN(A25),
+	GPIO_FN(DU_DOTCLKOUT1),
+	GPIO_FN(VI4_DATA3_B),
+	GPIO_FN(PWM4_B),
+	GPIO_IFN(IRQ4),
+	GPIO_FN(QSTH_QHS),
+	GPIO_FN(A24),
+	GPIO_FN(DU_EXHSYNC_DU_HSYNC),
+	GPIO_FN(VI4_DATA4_B),
+	GPIO_FN(PWM5_B),
+	GPIO_IFN(IRQ5),
+	GPIO_FN(QSTB_QHE),
+	GPIO_FN(A23),
+	GPIO_FN(DU_EXVSYNC_DU_VSYNC),
+	GPIO_FN(VI4_DATA5_B),
+	GPIO_FN(PWM6_B),
+	GPIO_IFN(PWM0),
+	GPIO_FN(AVB_AVTP_PPS),
+	GPIO_FN(A22),
+	GPIO_FN(VI4_DATA6_B),
+	GPIO_FN(IECLK_B),
+	GPIO_IFN(PWM1_A),
+	GPIO_FN(A21),
+	GPIO_FN(HRX3_D),
+	GPIO_FN(VI4_DATA7_B),
+	GPIO_FN(IERX_B),
+	GPIO_IFN(PWM2_A),
+	GPIO_FN(PWMFSW0),
+	GPIO_FN(A20),
+	GPIO_FN(HTX3_D),
+	GPIO_FN(IETX_B),
+	GPIO_IFN(A0),
+	GPIO_FN(LCDOUT16),
+	GPIO_FN(MSIOF3_SYNC_B),
+	GPIO_FN(VI4_DATA8),
+	GPIO_FN(DU_DB0),
+	GPIO_FN(PWM3_A),
+
+	/* IPSR2 */
+	GPIO_IFN(A1),
+	GPIO_FN(LCDOUT17),
+	GPIO_FN(MSIOF3_TXD_B),
+	GPIO_FN(VI4_DATA9),
+	GPIO_FN(DU_DB1),
+	GPIO_FN(PWM4_A),
+	GPIO_IFN(A2),
+	GPIO_FN(LCDOUT18),
+	GPIO_FN(MSIOF3_SCK_B),
+	GPIO_FN(VI4_DATA10),
+	GPIO_FN(DU_DB2),
+	GPIO_FN(PWM5_A),
+	GPIO_IFN(A3),
+	GPIO_FN(LCDOUT19),
+	GPIO_FN(MSIOF3_RXD_B),
+	GPIO_FN(VI4_DATA11),
+	GPIO_FN(DU_DB3),
+	GPIO_FN(PWM6_A),
+	GPIO_IFN(A4),
+	GPIO_FN(LCDOUT20),
+	GPIO_FN(MSIOF3_SS1_B),
+	GPIO_FN(VI4_DATA12),
+	GPIO_FN(VI5_DATA12),
+	GPIO_FN(DU_DB4),
+	GPIO_IFN(A5),
+	GPIO_FN(LCDOUT21),
+	GPIO_FN(MSIOF3_SS2_B),
+	GPIO_FN(SCK4_B),
+	GPIO_FN(VI4_DATA13),
+	GPIO_FN(VI5_DATA13),
+	GPIO_FN(DU_DB5),
+	GPIO_IFN(A6),
+	GPIO_FN(LCDOUT22),
+	GPIO_FN(MSIOF2_SS1_A),
+	GPIO_FN(RX4_B),
+	GPIO_FN(VI4_DATA14),
+	GPIO_FN(VI5_DATA14),
+	GPIO_FN(DU_DB6),
+	GPIO_IFN(A7),
+	GPIO_FN(LCDOUT23),
+	GPIO_FN(MSIOF2_SS2_A),
+	GPIO_FN(TX4_B),
+	GPIO_FN(VI4_DATA15),
+	GPIO_FN(V15_DATA15),
+	GPIO_FN(DU_DB7),
+	GPIO_IFN(A8),
+	GPIO_FN(RX3_B),
+	GPIO_FN(MSIOF2_SYNC_A),
+	GPIO_FN(HRX4_B),
+	GPIO_FN(SDA6_A),
+	GPIO_FN(AVB_AVTP_MATCH_B),
+	GPIO_FN(PWM1_B),
+
+	/* IPSR3 */
+	GPIO_IFN(A9),
+	GPIO_FN(MSIOF2_SCK_A),
+	GPIO_FN(CTS4x_B),
+	GPIO_FN(VI5_VSYNCx),
+	GPIO_IFN(A10),
+	GPIO_FN(MSIOF2_RXD_A),
+	GPIO_FN(RTS4n_TANS_B),
+	GPIO_FN(VI5_HSYNCx),
+	GPIO_IFN(A11),
+	GPIO_FN(TX3_B),
+	GPIO_FN(MSIOF2_TXD_A),
+	GPIO_FN(HTX4_B),
+	GPIO_FN(HSCK4),
+	GPIO_FN(VI5_FIELD),
+	GPIO_FN(SCL6_A),
+	GPIO_FN(AVB_AVTP_CAPTURE_B),
+	GPIO_FN(PWM2_B),
+	GPIO_FN(SPV_EVEN),
+	GPIO_IFN(A12),
+	GPIO_FN(LCDOUT12),
+	GPIO_FN(MSIOF3_SCK_C),
+	GPIO_FN(HRX4_A),
+	GPIO_FN(VI5_DATA8),
+	GPIO_FN(DU_DG4),
+	GPIO_IFN(A13),
+	GPIO_FN(LCDOUT13),
+	GPIO_FN(MSIOF3_SYNC_C),
+	GPIO_FN(HTX4_A),
+	GPIO_FN(VI5_DATA9),
+	GPIO_FN(DU_DG5),
+	GPIO_IFN(A14),
+	GPIO_FN(LCDOUT14),
+	GPIO_FN(MSIOF3_RXD_C),
+	GPIO_FN(HCTS4x),
+	GPIO_FN(VI5_DATA10),
+	GPIO_FN(DU_DG6),
+	GPIO_IFN(A15),
+	GPIO_FN(LCDOUT15),
+	GPIO_FN(MSIOF3_TXD_C),
+	GPIO_FN(HRTS4x),
+	GPIO_FN(VI5_DATA11),
+	GPIO_FN(DU_DG7),
+	GPIO_IFN(A16),
+	GPIO_FN(LCDOUT8),
+	GPIO_FN(VI4_FIELD),
+	GPIO_FN(DU_DG0),
+
+	/* IPSR4 */
+	GPIO_IFN(A17),
+	GPIO_FN(LCDOUT9),
+	GPIO_FN(VI4_VSYNCx),
+	GPIO_FN(DU_DG1),
+	GPIO_IFN(A18),
+	GPIO_FN(LCDOUT10),
+	GPIO_FN(VI4_HSYNCx),
+	GPIO_FN(DU_DG2),
+	GPIO_IFN(A19),
+	GPIO_FN(LCDOUT11),
+	GPIO_FN(VI4_CLKENB),
+	GPIO_FN(DU_DG3),
+	GPIO_IFN(CS0x),
+	GPIO_FN(VI5_CLKENB),
+	GPIO_IFN(CS1x_A26),
+	GPIO_FN(VI5_CLK),
+	GPIO_FN(EX_WAIT0_B),
+	GPIO_IFN(BSx),
+	GPIO_FN(QSTVA_QVS),
+	GPIO_FN(MSIOF3_SCK_D),
+	GPIO_FN(SCK3),
+	GPIO_FN(HSCK3),
+	GPIO_FN(CAN1_TX),
+	GPIO_FN(CANFD1_TX),
+	GPIO_FN(IETX_A),
+	GPIO_IFN(RDx),
+	GPIO_FN(MSIOF3_SYNC_D),
+	GPIO_FN(RX3_A),
+	GPIO_FN(HRX3_A),
+	GPIO_FN(CAN0_TX_A),
+	GPIO_FN(CANFD0_TX_A),
+	GPIO_IFN(RD_WRx),
+	GPIO_FN(MSIOF3_RXD_D),
+	GPIO_FN(TX3_A),
+	GPIO_FN(HTX3_A),
+	GPIO_FN(CAN0_RX_A),
+	GPIO_FN(CANFD0_RX_A),
+
+	/* IPSR5 */
+	GPIO_IFN(WE0x),
+	GPIO_FN(MSIIOF3_TXD_D),
+	GPIO_FN(CTS3x),
+	GPIO_FN(HCTS3x),
+	GPIO_FN(SCL6_B),
+	GPIO_FN(CAN_CLK),
+	GPIO_FN(IECLK_A),
+	GPIO_IFN(WE1x),
+	GPIO_FN(MSIOF3_SS1_D),
+	GPIO_FN(RTS3x_TANS),
+	GPIO_FN(HRTS3x),
+	GPIO_FN(SDA6_B),
+	GPIO_FN(CAN1_RX),
+	GPIO_FN(CANFD1_RX),
+	GPIO_FN(IERX_A),
+	GPIO_IFN(EX_WAIT0_A),
+	GPIO_FN(QCLK),
+	GPIO_FN(VI4_CLK),
+	GPIO_FN(DU_DOTCLKOUT0),
+	GPIO_IFN(D0),
+	GPIO_FN(MSIOF2_SS1_B),
+	GPIO_FN(MSIOF3_SCK_A),
+	GPIO_FN(VI4_DATA16),
+	GPIO_FN(VI5_DATA0),
+	GPIO_IFN(D1),
+	GPIO_FN(MSIOF2_SS2_B),
+	GPIO_FN(MSIOF3_SYNC_A),
+	GPIO_FN(VI4_DATA17),
+	GPIO_FN(VI5_DATA1),
+	GPIO_IFN(D2),
+	GPIO_FN(MSIOF3_RXD_A),
+	GPIO_FN(VI4_DATA18),
+	GPIO_FN(VI5_DATA2),
+	GPIO_IFN(D3),
+	GPIO_FN(MSIOF3_TXD_A),
+	GPIO_FN(VI4_DATA19),
+	GPIO_FN(VI5_DATA3),
+	GPIO_IFN(D4),
+	GPIO_FN(MSIOF2_SCK_B),
+	GPIO_FN(VI4_DATA20),
+	GPIO_FN(VI5_DATA4),
+
+	/* IPSR6 */
+	GPIO_IFN(D5),
+	GPIO_FN(MSIOF2_SYNC_B),
+	GPIO_FN(VI4_DATA21),
+	GPIO_FN(VI5_DATA5),
+	GPIO_IFN(D6),
+	GPIO_FN(MSIOF2_RXD_B),
+	GPIO_FN(VI4_DATA22),
+	GPIO_FN(VI5_DATA6),
+	GPIO_IFN(D7),
+	GPIO_FN(MSIOF2_TXD_B),
+	GPIO_FN(VI4_DATA23),
+	GPIO_FN(VI5_DATA7),
+	GPIO_IFN(D8),
+	GPIO_FN(LCDOUT0),
+	GPIO_FN(MSIOF2_SCK_D),
+	GPIO_FN(SCK4_C),
+	GPIO_FN(VI4_DATA0_A),
+	GPIO_FN(DU_DR0),
+	GPIO_IFN(D9),
+	GPIO_FN(LCDOUT1),
+	GPIO_FN(MSIOF2_SYNC_D),
+	GPIO_FN(VI4_DATA1_A),
+	GPIO_FN(DU_DR1),
+	GPIO_IFN(D10),
+	GPIO_FN(LCDOUT2),
+	GPIO_FN(MSIOF2_RXD_D),
+	GPIO_FN(HRX3_B),
+	GPIO_FN(VI4_DATA2_A),
+	GPIO_FN(CTS4x_C),
+	GPIO_FN(DU_DR2),
+	GPIO_IFN(D11),
+	GPIO_FN(LCDOUT3),
+	GPIO_FN(MSIOF2_TXD_D),
+	GPIO_FN(HTX3_B),
+	GPIO_FN(VI4_DATA3_A),
+	GPIO_FN(RTS4x_TANS_C),
+	GPIO_FN(DU_DR3),
+	GPIO_IFN(D12),
+	GPIO_FN(LCDOUT4),
+	GPIO_FN(MSIOF2_SS1_D),
+	GPIO_FN(RX4_C),
+	GPIO_FN(VI4_DATA4_A),
+	GPIO_FN(DU_DR4),
+
+	/* IPSR7 */
+	GPIO_IFN(D13),
+	GPIO_FN(LCDOUT5),
+	GPIO_FN(MSIOF2_SS2_D),
+	GPIO_FN(TX4_C),
+	GPIO_FN(VI4_DATA5_A),
+	GPIO_FN(DU_DR5),
+	GPIO_IFN(D14),
+	GPIO_FN(LCDOUT6),
+	GPIO_FN(MSIOF3_SS1_A),
+	GPIO_FN(HRX3_C),
+	GPIO_FN(VI4_DATA6_A),
+	GPIO_FN(DU_DR6),
+	GPIO_FN(SCL6_C),
+	GPIO_IFN(D15),
+	GPIO_FN(LCDOUT7),
+	GPIO_FN(MSIOF3_SS2_A),
+	GPIO_FN(HTX3_C),
+	GPIO_FN(VI4_DATA7_A),
+	GPIO_FN(DU_DR7),
+	GPIO_FN(SDA6_C),
+	GPIO_FN(FSCLKST),
+	GPIO_IFN(SD0_CLK),
+	GPIO_FN(MSIOF1_SCK_E),
+	GPIO_FN(STP_OPWM_0_B),
+	GPIO_IFN(SD0_CMD),
+	GPIO_FN(MSIOF1_SYNC_E),
+	GPIO_FN(STP_IVCXO27_0_B),
+	GPIO_IFN(SD0_DAT0),
+	GPIO_FN(MSIOF1_RXD_E),
+	GPIO_FN(TS_SCK0_B),
+	GPIO_FN(STP_ISCLK_0_B),
+	GPIO_IFN(SD0_DAT1),
+	GPIO_FN(MSIOF1_TXD_E),
+	GPIO_FN(TS_SPSYNC0_B),
+	GPIO_FN(STP_ISSYNC_0_B),
+
+	/* IPSR8 */
+	GPIO_IFN(SD0_DAT2),
+	GPIO_FN(MSIOF1_SS1_E),
+	GPIO_FN(TS_SDAT0_B),
+	GPIO_FN(STP_ISD_0_B),
+	GPIO_IFN(SD0_DAT3),
+	GPIO_FN(MSIOF1_SS2_E),
+	GPIO_FN(TS_SDEN0_B),
+	GPIO_FN(STP_ISEN_0_B),
+	GPIO_IFN(SD1_CLK),
+	GPIO_FN(MSIOF1_SCK_G),
+	GPIO_FN(SIM0_CLK_A),
+
+	GPIO_IFN(SD1_CMD),
+	GPIO_FN(MSIOF1_SYNC_G),
+	GPIO_FN(SIM0_D_A),
+	GPIO_FN(STP_IVCXO27_1_B),
+
+	GPIO_IFN(SD1_DAT0),
+	GPIO_FN(SD2_DAT4),
+	GPIO_FN(MSIOF1_RXD_G),
+	GPIO_FN(TS_SCK1_B),
+	GPIO_FN(STP_ISCLK_1_B),
+
+	GPIO_IFN(SD1_DAT1),
+	GPIO_FN(SD2_DAT5),
+	GPIO_FN(MSIOF1_TXD_G),
+	GPIO_FN(TS_SPSYNC1_B),
+	GPIO_FN(STP_ISSYNC_1_B),
+
+	GPIO_IFN(SD1_DAT2),
+	GPIO_FN(SD2_DAT6),
+	GPIO_FN(MSIOF1_SS1_G),
+	GPIO_FN(TS_SDAT1_B),
+	GPIO_FN(STP_IOD_1_B),
+	GPIO_IFN(SD1_DAT3),
+	GPIO_FN(SD2_DAT7),
+	GPIO_FN(MSIOF1_SS2_G),
+	GPIO_FN(TS_SDEN1_B),
+	GPIO_FN(STP_ISEN_1_B),
+
+	/* IPSR9 */
+	GPIO_IFN(SD2_CLK),
+	GPIO_FN(SCKZ_A),
+	GPIO_IFN(SD2_DAT0),
+	GPIO_FN(MTSx_A),
+	GPIO_IFN(SD2_DAT1),
+	GPIO_FN(STMx_A),
+	GPIO_IFN(SD2_DAT2),
+	GPIO_FN(MDATA_A),
+	GPIO_IFN(SD2_DAT3),
+	GPIO_FN(SDATA_A),
+	GPIO_IFN(SD2_DS),
+	GPIO_FN(SATA_DEVSLP_B),
+	GPIO_FN(VSP_A),
+	GPIO_IFN(SD3_DAT4),
+	GPIO_FN(SD2_CD_A),
+	GPIO_IFN(SD3_DAT5),
+	GPIO_FN(SD2_WP_A),
+
+	/* IPSR10 */
+	GPIO_IFN(SD3_DAT6),
+	GPIO_FN(SD3_CD),
+	GPIO_IFN(SD3_DAT7),
+	GPIO_FN(SD3_WP),
+	GPIO_IFN(SD0_CD),
+	GPIO_FN(SCL2_B),
+	GPIO_FN(SIM0_RST_A),
+	GPIO_IFN(SD0_WP),
+	GPIO_FN(SDA2_B),
+	GPIO_IFN(SD1_CD),
+	GPIO_FN(SIM0_CLK_B),
+	GPIO_IFN(SD1_WP),
+	GPIO_FN(SIM0_D_B),
+	GPIO_IFN(SCK0),
+	GPIO_FN(HSCK1_B),
+	GPIO_FN(MSIOF1_SS2_B),
+	GPIO_FN(AUDIO_CLKC_B),
+	GPIO_FN(SDA2_A),
+	GPIO_FN(SIM0_RST_B),
+	GPIO_FN(STP_OPWM__C),
+	GPIO_FN(RIF0_CLK_B),
+	GPIO_FN(ADICHS2),
+	GPIO_IFN(RX0),
+	GPIO_FN(HRX1_B),
+	GPIO_FN(TS_SCK0_C),
+	GPIO_FN(STP_ISCLK_0_C),
+	GPIO_FN(RIF0_D0_B),
+
+	/* IPSR11 */
+	GPIO_IFN(TX0),
+	GPIO_FN(HTX1_B),
+	GPIO_FN(TS_SPSYNC0_C),
+	GPIO_FN(STP_ISSYNC_0_C),
+	GPIO_FN(RIF0_D1_B),
+	GPIO_IFN(CTS0x),
+	GPIO_FN(HCTS1x_B),
+	GPIO_FN(MSIOF1_SYNC_B),
+	GPIO_FN(TS_SPSYNC1_C),
+	GPIO_FN(STP_ISSYNC_1_C),
+	GPIO_FN(RIF1_SYNC_B),
+	GPIO_FN(AUDIO_CLKOUT_C),
+	GPIO_FN(ADICS_SAMP),
+	GPIO_IFN(RTS0x_TANS),
+	GPIO_FN(HRTS1x_B),
+	GPIO_FN(MSIOF1_SS1_B),
+	GPIO_FN(AUDIO_CLKA_B),
+	GPIO_FN(SCL2_A),
+	GPIO_FN(STP_IVCXO27_1_C),
+	GPIO_FN(RIF0_SYNC_B),
+	GPIO_FN(ADICHS1),
+	GPIO_IFN(RX1_A),
+	GPIO_FN(HRX1_A),
+	GPIO_FN(TS_SDAT0_C),
+	GPIO_FN(STP_IDS_0_C),
+	GPIO_FN(RIF1_CLK_C),
+	GPIO_IFN(TX1_A),
+	GPIO_FN(HTX1_A),
+	GPIO_FN(TS_SDEN0_C),
+	GPIO_FN(STP_ISEN_0_C),
+	GPIO_FN(RIF1_D0_C),
+	GPIO_IFN(CTS1x),
+	GPIO_FN(HCTS1x_A),
+	GPIO_FN(MSIOF1_RXD_B),
+	GPIO_FN(TS_SDEN1_C),
+	GPIO_FN(STP_ISEN_1_C),
+	GPIO_FN(RIF1_D0_B),
+	GPIO_FN(ADIDATA),
+	GPIO_IFN(RTS1x_TANS),
+	GPIO_FN(HRTS1x_A),
+	GPIO_FN(MSIOF1_TXD_B),
+	GPIO_FN(TS_SDAT1_C),
+	GPIO_FN(STP_ISD_1_C),
+	GPIO_FN(RIF1_D1_B),
+	GPIO_FN(ADICHS0),
+	GPIO_IFN(SCK2),
+	GPIO_FN(SCIF_CLK_B),
+	GPIO_FN(MSIOF1_SCK_B),
+	GPIO_FN(TS_SCK1_C),
+	GPIO_FN(STP_ISCLK_1_C),
+	GPIO_FN(RIF1_CLK_B),
+	GPIO_FN(ADICLK),
+
+	/* IPSR12 */
+	GPIO_IFN(TX2_A),
+	GPIO_FN(SD2_CD_B),
+	GPIO_FN(SCL1_A),
+	GPIO_FN(RSD_CLK_B),
+	GPIO_FN(FMCLK_A),
+	GPIO_FN(RIF1_D1_C),
+	GPIO_FN(FSO_CFE_0_B),
+	GPIO_IFN(RX2_A),
+	GPIO_FN(SD2_WP_B),
+	GPIO_FN(SDA1_A),
+	GPIO_FN(RDS_DATA_B),
+	GPIO_FN(RMIN_A),
+	GPIO_FN(RIF1_SYNC_C),
+	GPIO_FN(FSO_CEF_1_B),
+	GPIO_IFN(HSCK0),
+	GPIO_FN(MSIOF1_SCK_D),
+	GPIO_FN(AUDIO_CLKB_A),
+	GPIO_FN(SSI_SDATA1_B),
+	GPIO_FN(TS_SCK0_D),
+	GPIO_FN(STP_ISCLK_0_D),
+	GPIO_FN(RIF0_CLK_C),
+	GPIO_FN(AD_CLK),
+	GPIO_IFN(HRX0),
+	GPIO_FN(MSIOF1_RXD_D),
+	GPIO_FN(SS1_SDATA2_B),
+	GPIO_FN(TS_SDEN0_D),
+	GPIO_FN(STP_ISEN_0_D),
+	GPIO_FN(RIF0_D0_C),
+	GPIO_FN(AD_DI),
+	GPIO_IFN(HTX0),
+	GPIO_FN(MSIOF1_TXD_D),
+	GPIO_FN(SSI_SDATA9_B),
+	GPIO_FN(TS_SDAT0_D),
+	GPIO_FN(STP_ISD_0_D),
+	GPIO_FN(RIF0_D1_C),
+	GPIO_FN(AD_DO),
+	GPIO_IFN(HCTS0x),
+	GPIO_FN(RX2_B),
+	GPIO_FN(MSIOF1_SYNC_D),
+	GPIO_FN(SSI_SCK9_A),
+	GPIO_FN(TS_SPSYNC0_D),
+	GPIO_FN(STP_ISSYNC_0_D),
+	GPIO_FN(RIF0_SYNC_C),
+	GPIO_FN(AUDIO_CLKOUT1_A),
+	GPIO_FN(AD_NSCx),
+	GPIO_IFN(HRTS0x),
+	GPIO_FN(TX2_B),
+	GPIO_FN(MSIOF1_SS1_D),
+	GPIO_FN(SSI_WS9_A),
+	GPIO_FN(STP_IVCXO27_0_D),
+	GPIO_FN(BPFCLK_A),
+	GPIO_FN(AUDIO_CLKOUT2_A),
+	GPIO_IFN(MSIOF0_SYNC),
+	GPIO_FN(AUDIO_CLKOUT_A),
+
+	/* IPSR13 */
+	GPIO_IFN(MSIOF0_SS1),
+	GPIO_FN(RX5),
+	GPIO_FN(AUDIO_CLKA_C),
+	GPIO_FN(SSI_SCK2_A),
+	GPIO_FN(RDS_CLK_A),
+	GPIO_FN(STP_IVCXO27_0_C),
+	GPIO_FN(AUDIO_CLKOUT3_A),
+	GPIO_FN(TCLK1_B),
+	GPIO_IFN(MSIOF0_SS2),
+	GPIO_FN(TX5),
+	GPIO_FN(MSIOF1_SS2_D),
+	GPIO_FN(AUDIO_CLKC_A),
+	GPIO_FN(SSI_WS2_A),
+	GPIO_FN(RDS_DATA_A),
+	GPIO_FN(STP_OPWM_0_D),
+	GPIO_FN(AUDIO_CLKOUT_D),
+	GPIO_FN(SPEEDIN_B),
+	GPIO_IFN(MLB_CLK),
+	GPIO_FN(MSIOF1_SCK_F),
+	GPIO_FN(SCL1_B),
+	GPIO_IFN(MLB_SIG),
+	GPIO_FN(RX1_B),
+	GPIO_FN(MSIOF1_SYNC_F),
+	GPIO_FN(SDA1_B),
+	GPIO_IFN(MLB_DAT),
+	GPIO_FN(TX1_B),
+	GPIO_FN(MSIOF1_RXD_F),
+	GPIO_IFN(SSI_SCK0129),
+	GPIO_FN(MSIOF1_TXD_F),
+	GPIO_FN(MOUT0),
+	GPIO_IFN(SSI_WS0129),
+	GPIO_FN(MSIOF1_SS1_F),
+	GPIO_FN(MOUT1),
+	GPIO_IFN(SSI_SDATA0),
+	GPIO_FN(MSIOF1_SS2_F),
+	GPIO_FN(MOUT2),
+
+	/* IPSR14 */
+	GPIO_IFN(SSI_SDATA1_A),
+	GPIO_FN(MOUT5),
+	GPIO_IFN(SSI_SDATA2_A),
+	GPIO_FN(SSI_SCK1_B),
+	GPIO_FN(MOUT6),
+	GPIO_IFN(SSI_SCK34),
+	GPIO_FN(MSIOF1_SS1_A),
+	GPIO_FN(STP_OPWM_0_A),
+	GPIO_IFN(SSI_WS34),
+	GPIO_FN(HCTS2x_A),
+	GPIO_FN(MSIOF1_SS2_A),
+	GPIO_FN(STP_IVCXO27_0_A),
+	GPIO_IFN(SSI_SDATA3),
+	GPIO_FN(HRTS2x_A),
+	GPIO_FN(MSIOF1_TXD_A),
+	GPIO_FN(TS_SCK0_A),
+	GPIO_FN(STP_ISCLK_0_A),
+	GPIO_FN(RIF0_D1_A),
+	GPIO_FN(RIF2_D0_A),
+	GPIO_IFN(SSI_SCK4),
+	GPIO_FN(HRX2_A),
+	GPIO_FN(MSIOF1_SCK_A),
+	GPIO_FN(TS_SDAT0_A),
+	GPIO_FN(STP_ISD_0_A),
+	GPIO_FN(RIF0_CLK_A),
+	GPIO_FN(RIF2_CLK_A),
+	GPIO_IFN(SSI_WS4),
+	GPIO_FN(HTX2_A),
+	GPIO_FN(MSIOF1_SYNC_A),
+	GPIO_FN(TS_SDEN0_A),
+	GPIO_FN(STP_ISEN_0_A),
+	GPIO_FN(RIF0_SYNC_A),
+	GPIO_FN(RIF2_SYNC_A),
+	GPIO_IFN(SSI_SDATA4),
+	GPIO_FN(HSCK2_A),
+	GPIO_FN(MSIOF1_RXD_A),
+	GPIO_FN(TS_SPSYNC0_A),
+	GPIO_FN(STP_ISSYNC_0_A),
+	GPIO_FN(RIF0_D0_A),
+	GPIO_FN(RIF2_D1_A),
+
+	GPIO_IFN(SSI_SCK6),
+	GPIO_FN(USB2_PWEN),
+	GPIO_FN(SIM0_RST_D),
+	GPIO_FN(RDS_CLK_C),
+	GPIO_IFN(SSI_WS6),
+	GPIO_FN(USB2_OVC),
+	GPIO_FN(SIM0_D_D),
+	GPIO_IFN(SSI_SDATA6),
+	GPIO_FN(SIM0_CLK_D),
+	GPIO_FN(RSD_DATA_C),
+	GPIO_FN(SATA_DEVSLP_A),
+	GPIO_IFN(SSI_SCK78),
+	GPIO_FN(HRX2_B),
+	GPIO_FN(MSIOF1_SCK_C),
+	GPIO_FN(TS_SCK1_A),
+	GPIO_FN(STP_ISCLK_1_A),
+	GPIO_FN(RIF1_CLK_A),
+	GPIO_FN(RIF3_CLK_A),
+	GPIO_IFN(SSI_WS78),
+	GPIO_FN(HTX2_B),
+	GPIO_FN(MSIOF1_SYNC_C),
+	GPIO_FN(TS_SDT1_A),
+	GPIO_FN(STP_ISD_1_A),
+	GPIO_FN(RIF1_SYNC_A),
+	GPIO_FN(RIF3_SYNC_A),
+	GPIO_IFN(SSI_SDATA7),
+	GPIO_FN(HCTS2x_B),
+	GPIO_FN(MSIOF1_RXD_C),
+	GPIO_FN(TS_SDEN1_A),
+	GPIO_FN(STP_IEN_1_A),
+	GPIO_FN(RIF1_D0_A),
+	GPIO_FN(RIF3_D0_A),
+	GPIO_FN(TCLK2_A),
+	GPIO_IFN(SSI_SDATA8),
+	GPIO_FN(HRTS2x_B),
+	GPIO_FN(MSIOF1_TXD_C),
+	GPIO_FN(TS_SPSYNC1_A),
+	GPIO_FN(STP_ISSYNC_1_A),
+	GPIO_FN(RIF1_D1_A),
+	GPIO_FN(EIF3_D1_A),
+	GPIO_IFN(SSI_SDATA9_A),
+	GPIO_FN(HSCK2_B),
+	GPIO_FN(MSIOF1_SS1_C),
+	GPIO_FN(HSCK1_A),
+	GPIO_FN(SSI_WS1_B),
+	GPIO_FN(SCK1),
+	GPIO_FN(STP_IVCXO27_1_A),
+	GPIO_FN(SCK5),
+
+	/* IPSR16 */
+	GPIO_IFN(AUDIO_CLKA_A),
+	GPIO_FN(CC5_OSCOUT),
+	GPIO_IFN(AUDIO_CLKB_B),
+	GPIO_FN(SCIF_CLK_A),
+	GPIO_FN(DVC_MUTE),
+	GPIO_FN(STP_IVCXO27_1_D),
+	GPIO_FN(REMOCON_A),
+	GPIO_FN(TCLK1_A),
+	GPIO_FN(VSP_B),
+	GPIO_IFN(USB0_PWEN),
+	GPIO_FN(SIM0_RST_C),
+	GPIO_FN(TS_SCK1_D),
+	GPIO_FN(STP_ISCLK_1_D),
+	GPIO_FN(BPFCLK_B),
+	GPIO_FN(RIF3_CLK_B),
+	GPIO_FN(SCKZ_B),
+	GPIO_IFN(USB0_OVC),
+	GPIO_FN(SIM0_D_C),
+	GPIO_FN(TS_SDAT1_D),
+	GPIO_FN(STP_ISD_1_D),
+	GPIO_FN(RIF3_SYNC_B),
+	GPIO_FN(VSP_C),
+	GPIO_IFN(USB1_PWEN),
+	GPIO_FN(SIM0_CLK_C),
+	GPIO_FN(SSI_SCK1_A),
+	GPIO_FN(TS_SCK0_E),
+	GPIO_FN(STP_ISCLK_0_E),
+	GPIO_FN(FMCLK_B),
+	GPIO_FN(RIF2_CLK_B),
+	GPIO_FN(MTSx_B),
+	GPIO_FN(SPEEDIN_A),
+	GPIO_FN(VSP_D),
+	GPIO_IFN(USB1_OVC),
+	GPIO_FN(MSIOF1_SS2_C),
+	GPIO_FN(SSI_WS1_A),
+	GPIO_FN(TS_SDAT0_E),
+	GPIO_FN(STP_ISD_0_E),
+	GPIO_FN(FMIN_B),
+	GPIO_FN(RIF2_SYNC_B),
+	GPIO_FN(STMx_B),
+	GPIO_FN(REMOCON_B),
+	GPIO_IFN(USB30_PWEN),
+	GPIO_FN(AUDIO_CLKOUT_B),
+	GPIO_FN(SSI_SCK2_B),
+	GPIO_FN(TS_SDEN1_D),
+	GPIO_FN(STP_ISEN_1_D),
+	GPIO_FN(STP_OPWM_0_E),
+	GPIO_FN(RIF3_D0_B),
+	GPIO_FN(MDATA_B),
+	GPIO_FN(TCLK2_B),
+	GPIO_FN(TPU0TO0),
+	GPIO_IFN(USB30_OVC),
+	GPIO_FN(AUDIO_CLKOUT1_B),
+	GPIO_FN(SSI_WS2_B),
+	GPIO_FN(TS_SPSYNC1_D),
+	GPIO_FN(STP_ISSYNC_1_D),
+	GPIO_FN(STP_IVCXO27_0_E),
+	GPIO_FN(RIF3_D1_B),
+	GPIO_FN(SDATA_B),
+	GPIO_FN(RSO_TOE_B),
+	GPIO_FN(TPU0TO1),
+
+	/* IPSR17 */
+	GPIO_IFN(USB31_PWEN),
+	GPIO_FN(AUDIO_CLKOUT2_B),
+	GPIO_FN(SI_SCK9_B),
+	GPIO_FN(TS_SDEN0_E),
+	GPIO_FN(STP_ISEN_0_E),
+	GPIO_FN(RIF2_D0_B),
+	GPIO_FN(TPU0TO2),
+	GPIO_IFN(USB31_OVC),
+	GPIO_FN(AUDIO_CLKOUT3_B),
+	GPIO_FN(SSI_WS9_B),
+	GPIO_FN(TS_SPSYNC0_E),
+	GPIO_FN(STP_ISSYNC_0_E),
+	GPIO_FN(RIF2_D1_B),
+	GPIO_FN(TPU0TO3),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	/* GPSR0(0xE6060100) md[3:1] controls initial value */
+	/*   md[3:1] .. 0     : 0x0000FFFF                  */
+	/*           .. other : 0x00000000                  */
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		GP_0_15_FN, GFN_D15,
+		GP_0_14_FN, GFN_D14,
+		GP_0_13_FN, GFN_D13,
+		GP_0_12_FN, GFN_D12,
+		GP_0_11_FN, GFN_D11,
+		GP_0_10_FN, GFN_D10,
+		GP_0_9_FN, GFN_D9,
+		GP_0_8_FN, GFN_D8,
+		GP_0_7_FN, GFN_D7,
+		GP_0_6_FN, GFN_D6,
+		GP_0_5_FN, GFN_D5,
+		GP_0_4_FN, GFN_D4,
+		GP_0_3_FN, GFN_D3,
+		GP_0_2_FN, GFN_D2,
+		GP_0_1_FN, GFN_D1,
+		GP_0_0_FN, GFN_D0 }
+	},
+	/* GPSR1(0xE6060104) is md[3:1] controls initial value */
+	/*   md[3:1] .. 0     : 0x0EFFFFFF                     */
+	/*           .. other : 0x00000000                     */
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_27_FN, GFN_EX_WAIT0_A,
+		GP_1_26_FN, GFN_WE1x,
+		GP_1_25_FN, GFN_WE0x,
+		GP_1_24_FN, GFN_RD_WRx,
+		GP_1_23_FN, GFN_RDx,
+		GP_1_22_FN, GFN_BSx,
+		GP_1_21_FN, GFN_CS1x_A26,
+		GP_1_20_FN, GFN_CS0x,
+		GP_1_19_FN, GFN_A19,
+		GP_1_18_FN, GFN_A18,
+		GP_1_17_FN, GFN_A17,
+		GP_1_16_FN, GFN_A16,
+		GP_1_15_FN, GFN_A15,
+		GP_1_14_FN, GFN_A14,
+		GP_1_13_FN, GFN_A13,
+		GP_1_12_FN, GFN_A12,
+		GP_1_11_FN, GFN_A11,
+		GP_1_10_FN, GFN_A10,
+		GP_1_9_FN, GFN_A9,
+		GP_1_8_FN, GFN_A8,
+		GP_1_7_FN, GFN_A7,
+		GP_1_6_FN, GFN_A6,
+		GP_1_5_FN, GFN_A5,
+		GP_1_4_FN, GFN_A4,
+		GP_1_3_FN, GFN_A3,
+		GP_1_2_FN, GFN_A2,
+		GP_1_1_FN, GFN_A1,
+		GP_1_0_FN, GFN_A0 }
+	},
+	/* GPSR2(0xE6060108) is md[3:1] controls               */
+	/*   md[3:1] .. 0     : 0x000003C0                     */
+	/*           .. other : 0x00000200                     */
+	{ PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		GP_2_14_FN, GFN_AVB_AVTP_CAPTURE_A,
+		GP_2_13_FN, GFN_AVB_AVTP_MATCH_A,
+		GP_2_12_FN, GFN_AVB_LINK,
+		GP_2_11_FN, GFN_AVB_PHY_INT,
+		GP_2_10_FN, GFN_AVB_MAGIC,
+		GP_2_9_FN, GFN_AVB_MDC,
+		GP_2_8_FN, GFN_PWM2_A,
+		GP_2_7_FN, GFN_PWM1_A,
+		GP_2_6_FN, GFN_PWM0,
+		GP_2_5_FN, GFN_IRQ5,
+		GP_2_4_FN, GFN_IRQ4,
+		GP_2_3_FN, GFN_IRQ3,
+		GP_2_2_FN, GFN_IRQ2,
+		GP_2_1_FN, GFN_IRQ1,
+		GP_2_0_FN, GFN_IRQ0 }
+	},
+
+	/* GPSR3 */
+	{ PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		GP_3_15_FN, GFN_SD1_WP,
+		GP_3_14_FN, GFN_SD1_CD,
+		GP_3_13_FN, GFN_SD0_WP,
+		GP_3_12_FN, GFN_SD0_CD,
+		GP_3_11_FN, GFN_SD1_DAT3,
+		GP_3_10_FN, GFN_SD1_DAT2,
+		GP_3_9_FN, GFN_SD1_DAT1,
+		GP_3_8_FN, GFN_SD1_DAT0,
+		GP_3_7_FN, GFN_SD1_CMD,
+		GP_3_6_FN, GFN_SD1_CLK,
+		GP_3_5_FN, GFN_SD0_DAT3,
+		GP_3_4_FN, GFN_SD0_DAT2,
+		GP_3_3_FN, GFN_SD0_DAT1,
+		GP_3_2_FN, GFN_SD0_DAT0,
+		GP_3_1_FN, GFN_SD0_CMD,
+		GP_3_0_FN, GFN_SD0_CLK }
+	},
+	/* GPSR4 */
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_17_FN, GPIO_FN_SD3_DS,
+		GP_4_16_FN, GFN_SD3_DAT7,
+
+		GP_4_15_FN, GFN_SD3_DAT6,
+		GP_4_14_FN, GFN_SD3_DAT5,
+		GP_4_13_FN, GFN_SD3_DAT4,
+		GP_4_12_FN, FN_SD3_DAT3,
+		GP_4_11_FN, FN_SD3_DAT2,
+		GP_4_10_FN, FN_SD3_DAT1,
+		GP_4_9_FN, FN_SD3_DAT0,
+		GP_4_8_FN, FN_SD3_CMD,
+		GP_4_7_FN, FN_SD3_CLK,
+		GP_4_6_FN, GFN_SD2_DS,
+		GP_4_5_FN, GFN_SD2_DAT3,
+		GP_4_4_FN, GFN_SD2_DAT2,
+		GP_4_3_FN, GFN_SD2_DAT1,
+		GP_4_2_FN, GFN_SD2_DAT0,
+		GP_4_1_FN, FN_SD2_CMD,
+		GP_4_0_FN, GFN_SD2_CLK }
+	},
+	/* GPSR5 */
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_25_FN, GFN_MLB_DAT,
+		GP_5_24_FN, GFN_MLB_SIG,
+
+		GP_5_23_FN, GFN_MLB_CLK,
+		GP_5_22_FN, FN_MSIOF0_RXD,
+		GP_5_21_FN, GFN_MSIOF0_SS2,
+		GP_5_20_FN, FN_MSIOF0_TXD,
+		GP_5_19_FN, GFN_MSIOF0_SS1,
+		GP_5_18_FN, GFN_MSIOF0_SYNC,
+		GP_5_17_FN, FN_MSIOF0_SCK,
+		GP_5_16_FN, GFN_HRTS0x,
+		GP_5_15_FN, GFN_HCTS0x,
+		GP_5_14_FN, GFN_HTX0,
+		GP_5_13_FN, GFN_HRX0,
+		GP_5_12_FN, GFN_HSCK0,
+		GP_5_11_FN, GFN_RX2_A,
+		GP_5_10_FN, GFN_TX2_A,
+		GP_5_9_FN, GFN_SCK2,
+		GP_5_8_FN, GFN_RTS1x_TANS,
+		GP_5_7_FN, GFN_CTS1x,
+		GP_5_6_FN, GFN_TX1_A,
+		GP_5_5_FN, GFN_RX1_A,
+		GP_5_4_FN, GFN_RTS0x_TANS,
+		GP_5_3_FN, GFN_CTS0x,
+		GP_5_2_FN, GFN_TX0,
+		GP_5_1_FN, GFN_RX0,
+		GP_5_0_FN, GFN_SCK0 }
+	},
+	/* GPSR6 */
+	{ PINMUX_CFG_REG("GPSR6", 0xE6060118, 32, 1) {
+		GP_6_31_FN, GFN_USB31_OVC,
+		GP_6_30_FN, GFN_USB31_PWEN,
+		GP_6_29_FN, GFN_USB30_OVC,
+		GP_6_28_FN, GFN_USB30_PWEN,
+		GP_6_27_FN, GFN_USB1_OVC,
+		GP_6_26_FN, GFN_USB1_PWEN,
+		GP_6_25_FN, GFN_USB0_OVC,
+		GP_6_24_FN, GFN_USB0_PWEN,
+		GP_6_23_FN, GFN_AUDIO_CLKB_B,
+		GP_6_22_FN, GFN_AUDIO_CLKA_A,
+		GP_6_21_FN, GFN_SSI_SDATA9_A,
+		GP_6_20_FN, GFN_SSI_SDATA8,
+		GP_6_19_FN, GFN_SSI_SDATA7,
+		GP_6_18_FN, GFN_SSI_WS78,
+		GP_6_17_FN, GFN_SSI_SCK78,
+		GP_6_16_FN, GFN_SSI_SDATA6,
+		GP_6_15_FN, GFN_SSI_WS6,
+		GP_6_14_FN, GFN_SSI_SCK6,
+		GP_6_13_FN, FN_SSI_SDATA5,
+		GP_6_12_FN, FN_SSI_WS5,
+		GP_6_11_FN, FN_SSI_SCK5,
+		GP_6_10_FN, GFN_SSI_SDATA4,
+		GP_6_9_FN, GFN_SSI_WS4,
+		GP_6_8_FN, GFN_SSI_SCK4,
+		GP_6_7_FN, GFN_SSI_SDATA3,
+		GP_6_6_FN, GFN_SSI_WS34,
+		GP_6_5_FN, GFN_SSI_SCK34,
+		GP_6_4_FN, GFN_SSI_SDATA2_A,
+		GP_6_3_FN, GFN_SSI_SDATA1_A,
+		GP_6_2_FN, GFN_SSI_SDATA0,
+		GP_6_1_FN, GFN_SSI_WS0129,
+		GP_6_0_FN, GFN_SSI_SCK0129 }
+	},
+	/* GPSR7 */
+	{ PINMUX_CFG_REG("GPSR7", 0xE606011C, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_3_FN, FN_HDMI1_CEC,
+		GP_7_2_FN, FN_HDMI0_CEC,
+		GP_7_1_FN, FN_AVS2,
+		GP_7_0_FN, FN_AVS1 }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR0_31_28 [4] */
+		IFN_IRQ1, FN_QPOLA, 0, FN_DU_DISP,
+		FN_VI4_DATA1_B, FN_CAN0_RX_B, FN_CANFD0_RX_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_27_24 [4] */
+		IFN_IRQ0, FN_QPOLB, 0, FN_DU_CDE,
+		FN_VI4_DATA0_B, FN_CAN0_TX_B, FN_CANFD0_TX_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_23_20 [4] */
+		IFN_AVB_AVTP_CAPTURE_A, 0, FN_MSIOF2_TXD_C, FN_RTS4x_TANS_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_19_16 [4] */
+		IFN_AVB_AVTP_MATCH_A, 0, FN_MSIOF2_RXD_C, FN_CTS4x_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_15_12 [4] */
+		IFN_AVB_LINK, 0, FN_MSIOF2_SCK_C, FN_TX4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_11_8 [4] */
+		IFN_AVB_PHY_INT, 0, FN_MSIOF2_SYNC_C, FN_RX4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_7_4 [4] */
+		IFN_AVB_MAGIC, 0, FN_MSIOF2_S1_C, FN_SCK4_A,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR0_3_0 [4] */
+		IFN_AVB_MDC, 0, FN_MSIOF2_SS2_C, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR1_31_28 [4] */
+		IFN_A0, FN_LCDOUT16, FN_MSIOF3_SYNC_B, 0,
+		FN_VI4_DATA8, 0, FN_DU_DB0, 0,
+		0, FN_PWM3_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_27_24 [4] */
+		IFN_PWM2_A, FN_PWMFSW0, FN_A20, FN_HTX3_D,
+		0, 0, 0, 0,
+		0, FN_IETX_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_23_20 [4] */
+		IFN_PWM1_A, 0, FN_A21, FN_HRX3_D,
+		FN_VI4_DATA7_B, 0, 0, 0,
+		0, FN_IERX_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_19_16 [4] */
+		IFN_PWM0, FN_AVB_AVTP_PPS, FN_A22, 0,
+		FN_VI4_DATA6_B, 0, 0, 0,
+		0, FN_IECLK_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_15_12 [4] */
+		IFN_IRQ5, FN_QSTB_QHE, FN_A23, FN_DU_EXVSYNC_DU_VSYNC,
+		FN_VI4_DATA5_B, 0, 0, 0,
+		0, FN_PWM6_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_11_8 [4] */
+		IFN_IRQ4, FN_QSTH_QHS, FN_A24, FN_DU_EXHSYNC_DU_HSYNC,
+		FN_VI4_DATA4_B, 0, 0, 0,
+		0, FN_PWM5_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_7_4 [4] */
+		IFN_IRQ3, FN_QSTVB_QVE, FN_A25, FN_DU_DOTCLKOUT1,
+		FN_VI4_DATA3_B, 0, 0,
+		0, FN_PWM4_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR1_3_0 [4] */
+		IFN_IRQ2, FN_QCPV_QDE, 0, FN_DU_EXODDF_DU_ODDF_DISP_CDE,
+		FN_VI4_DATA2_B, 0, 0, 0,
+		0, FN_PWM3_B, 0, 0,
+		0, 0, 0, 0
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR2_31_28 [4] */
+		IFN_A8, FN_RX3_B, FN_MSIOF2_SYNC_A, FN_HRX4_B,
+		0, 0, 0, FN_SDA6_A,
+		FN_AVB_AVTP_MATCH_B, FN_PWM1_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_27_24 [4] */
+		IFN_A7, FN_LCDOUT23, FN_MSIOF2_SS2_A, FN_TX4_B,
+		FN_VI4_DATA15, FN_V15_DATA15, FN_DU_DB7, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_23_20 [4] */
+		IFN_A6, FN_LCDOUT22, FN_MSIOF2_SS1_A, FN_RX4_B,
+		FN_VI4_DATA14, FN_VI5_DATA14, FN_DU_DB6, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_19_16 [4] */
+		IFN_A5, FN_LCDOUT21, FN_MSIOF3_SS2_B, FN_SCK4_B,
+		FN_VI4_DATA13, FN_VI5_DATA13, FN_DU_DB5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_15_12 [4] */
+		IFN_A4, FN_LCDOUT20, FN_MSIOF3_SS1_B, 0,
+		FN_VI4_DATA12, FN_VI5_DATA12, FN_DU_DB4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_11_8 [4] */
+		IFN_A3, FN_LCDOUT19, FN_MSIOF3_RXD_B, 0,
+		FN_VI4_DATA11, 0, FN_DU_DB3, 0,
+		0, FN_PWM6_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_7_4 [4] */
+		IFN_A2, FN_LCDOUT18, FN_MSIOF3_SCK_B, 0,
+		FN_VI4_DATA10, 0, FN_DU_DB2, 0,
+		0, FN_PWM5_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR2_3_0 [4] */
+		IFN_A1, FN_LCDOUT17, FN_MSIOF3_TXD_B, 0,
+		FN_VI4_DATA9, 0, FN_DU_DB1, 0,
+		0, FN_PWM4_A, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR3_31_28 [4] */
+		IFN_A16, FN_LCDOUT8, 0, 0,
+		FN_VI4_FIELD, 0, FN_DU_DG0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_27_24 [4] */
+		IFN_A15, FN_LCDOUT15, FN_MSIOF3_TXD_C, 0,
+		FN_HRTS4x, FN_VI5_DATA11, FN_DU_DG7, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_23_20 [4] */
+		IFN_A14, FN_LCDOUT14, FN_MSIOF3_RXD_C, 0,
+		FN_HCTS4x, FN_VI5_DATA10, FN_DU_DG6, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_19_16 [4] */
+		IFN_A13, FN_LCDOUT13, FN_MSIOF3_SYNC_C, 0,
+		FN_HTX4_A, FN_VI5_DATA9, FN_DU_DG5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_15_12 [4] */
+		IFN_A12, FN_LCDOUT12, FN_MSIOF3_SCK_C, 0,
+		FN_HRX4_A, FN_VI5_DATA8, FN_DU_DG4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_11_8 [4] */
+		IFN_A11, FN_TX3_B, FN_MSIOF2_TXD_A, FN_HTX4_B,
+		FN_HSCK4, FN_VI5_FIELD, 0, FN_SCL6_A,
+		FN_AVB_AVTP_CAPTURE_B, FN_PWM2_B, FN_SPV_EVEN, 0,
+		0, 0, 0, 0,
+		/* IPSR3_7_4 [4] */
+		IFN_A10, 0, FN_MSIOF2_RXD_A, FN_RTS4n_TANS_B,
+		0, FN_VI5_HSYNCx, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR3_3_0 [4] */
+		IFN_A9, 0, FN_MSIOF2_SCK_A, FN_CTS4x_B,
+		0, FN_VI5_VSYNCx, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR4_31_28 [4] */
+		IFN_RD_WRx, 0, FN_MSIOF3_RXD_D, FN_TX3_A,
+		FN_HTX3_A, 0, 0, 0,
+		FN_CAN0_RX_A, FN_CANFD0_RX_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_27_24 [4] */
+		IFN_RDx, 0, FN_MSIOF3_SYNC_D, FN_RX3_A,
+		FN_HRX3_A, 0, 0, 0,
+		FN_CAN0_TX_A, FN_CANFD0_TX_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_23_20 [4] */
+		IFN_BSx, FN_QSTVA_QVS, FN_MSIOF3_SCK_D, FN_SCK3,
+		FN_HSCK3, 0, 0, 0,
+		FN_CAN1_TX, FN_CANFD1_TX, FN_IETX_A, 0,
+		0, 0, 0, 0,
+		/* IPSR4_19_16 [4] */
+		IFN_CS1x_A26, 0, 0, 0,
+		0, FN_VI5_CLK, 0, FN_EX_WAIT0_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_15_12 [4] */
+		IFN_CS0x, 0, 0, 0,
+		0, FN_VI5_CLKENB, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_11_8 [4] */
+		IFN_A19, FN_LCDOUT11, 0, 0,
+		FN_VI4_CLKENB, 0, FN_DU_DG3, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_7_4 [4] */
+		IFN_A18, FN_LCDOUT10, 0, 0,
+		FN_VI4_HSYNCx, 0, FN_DU_DG2, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR4_3_0 [4] */
+		IFN_A17, FN_LCDOUT9, 0, 0,
+		FN_VI4_VSYNCx, 0, FN_DU_DG1, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR5_31_28 [4] */
+		IFN_D4, FN_MSIOF2_SCK_B, 0, 0,
+		FN_VI4_DATA20, FN_VI5_DATA4, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_27_24 [4] */
+		IFN_D3, 0, FN_MSIOF3_TXD_A, 0,
+		FN_VI4_DATA19, FN_VI5_DATA3, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_23_20 [4] */
+		IFN_D2, 0, FN_MSIOF3_RXD_A, 0,
+		FN_VI4_DATA18, FN_VI5_DATA2, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_19_16 [4] */
+		IFN_D1, FN_MSIOF2_SS2_B, FN_MSIOF3_SYNC_A, 0,
+		FN_VI4_DATA17, FN_VI5_DATA1, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_15_12 [4] */
+		IFN_D0, FN_MSIOF2_SS1_B, FN_MSIOF3_SCK_A, 0,
+		FN_VI4_DATA16, FN_VI5_DATA0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_11_8 [4] */
+		IFN_EX_WAIT0_A, FN_QCLK, 0, 0,
+		FN_VI4_CLK, 0, FN_DU_DOTCLKOUT0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR5_7_4 [4] */
+		IFN_WE1x, 0, FN_MSIOF3_SS1_D, FN_RTS3x_TANS,
+		FN_HRTS3x, 0, 0, FN_SDA6_B,
+		FN_CAN1_RX, FN_CANFD1_RX, FN_IERX_A, 0,
+		0, 0, 0, 0,
+		/* IPSR5_3_0 [4] */
+		IFN_WE0x, 0, FN_MSIIOF3_TXD_D, FN_CTS3x,
+		FN_HCTS3x, 0, 0, FN_SCL6_B,
+		FN_CAN_CLK, 0, FN_IECLK_A, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR6_31_28 [4] */
+		IFN_D12, FN_LCDOUT4, FN_MSIOF2_SS1_D, FN_RX4_C,
+		FN_VI4_DATA4_A, 0, FN_DU_DR4, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_27_24 [4] */
+		IFN_D11, FN_LCDOUT3, FN_MSIOF2_TXD_D, FN_HTX3_B,
+		FN_VI4_DATA3_A, FN_RTS4x_TANS_C, FN_DU_DR3, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_23_20 [4] */
+		IFN_D10, FN_LCDOUT2, FN_MSIOF2_RXD_D, FN_HRX3_B,
+		FN_VI4_DATA2_A, FN_CTS4x_C, FN_DU_DR2, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_19_16 [4] */
+		IFN_D9, FN_LCDOUT1, FN_MSIOF2_SYNC_D, 0,
+		FN_VI4_DATA1_A, 0, FN_DU_DR1, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_15_12 [4] */
+		IFN_D8, FN_LCDOUT0, FN_MSIOF2_SCK_D, FN_SCK4_C,
+		FN_VI4_DATA0_A, 0, FN_DU_DR0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_11_8 [4] */
+		IFN_D7, FN_MSIOF2_TXD_B, 0, 0,
+		FN_VI4_DATA23, FN_VI5_DATA7, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_7_4 [4] */
+		IFN_D6, FN_MSIOF2_RXD_B, 0, 0,
+		FN_VI4_DATA22, FN_VI5_DATA6, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR6_3_0 [4] */
+		IFN_D5, FN_MSIOF2_SYNC_B, 0, 0,
+		FN_VI4_DATA21, FN_VI5_DATA5, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR7_31_28 [4] */
+		IFN_SD0_DAT1, 0, FN_MSIOF1_TXD_E, 0,
+		0, FN_TS_SPSYNC0_B, FN_STP_ISSYNC_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_27_24 [4] */
+		IFN_SD0_DAT0, 0, FN_MSIOF1_RXD_E, 0,
+		0, FN_TS_SCK0_B, FN_STP_ISCLK_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_23_20 [4] */
+		IFN_SD0_CMD, 0, FN_MSIOF1_SYNC_E, 0,
+		0, 0, FN_STP_IVCXO27_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_19_16 [4] */
+		IFN_SD0_CLK, 0, FN_MSIOF1_SCK_E, 0,
+		0, 0, FN_STP_OPWM_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_15_12 [4] */
+		FN_FSCLKST, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_11_8 [4] */
+		IFN_D15, FN_LCDOUT7, FN_MSIOF3_SS2_A, FN_HTX3_C,
+		FN_VI4_DATA7_A, 0, FN_DU_DR7, FN_SDA6_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_7_4 [4] */
+		IFN_D14, FN_LCDOUT6, FN_MSIOF3_SS1_A, FN_HRX3_C,
+		FN_VI4_DATA6_A, 0, FN_DU_DR6, FN_SCL6_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR7_3_0 [4] */
+		IFN_D13, FN_LCDOUT5, FN_MSIOF2_SS2_D, FN_TX4_C,
+		FN_VI4_DATA5_A, 0, FN_DU_DR5, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR8_31_28 [4] */
+		IFN_SD1_DAT3, FN_SD2_DAT7, FN_MSIOF1_SS2_G, 0,
+		0, FN_TS_SDEN1_B, FN_STP_ISEN_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_27_24 [4] */
+		IFN_SD1_DAT2, FN_SD2_DAT6, FN_MSIOF1_SS1_G, 0,
+		0, FN_TS_SDAT1_B, FN_STP_IOD_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_23_20 [4] */
+		IFN_SD1_DAT1, FN_SD2_DAT5, FN_MSIOF1_TXD_G, 0,
+		0, FN_TS_SPSYNC1_B, FN_STP_ISSYNC_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_19_16 [4] */
+		IFN_SD1_DAT0, FN_SD2_DAT4, FN_MSIOF1_RXD_G, 0,
+		0, FN_TS_SCK1_B, FN_STP_ISCLK_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_15_12 [4] */
+		IFN_SD1_CMD, 0, FN_MSIOF1_SYNC_G, 0,
+		0, FN_SIM0_D_A, FN_STP_IVCXO27_1_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_11_8 [4] */
+		IFN_SD1_CLK, 0, FN_MSIOF1_SCK_G, 0,
+		0, FN_SIM0_CLK_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_7_4 [4] */
+		IFN_SD0_DAT3, 0, FN_MSIOF1_SS2_E, 0,
+		0, FN_TS_SDEN0_B, FN_STP_ISEN_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR8_3_0 [4] */
+		IFN_SD0_DAT2, 0, FN_MSIOF1_SS1_E, 0,
+		0, FN_TS_SDAT0_B, FN_STP_ISD_0_B, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR9_31_28 [4] */
+		IFN_SD3_DAT5, FN_SD2_WP_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_27_24 [4] */
+		IFN_SD3_DAT4, FN_SD2_CD_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_23_20 [4] */
+		IFN_SD2_DS, 0, 0, 0,
+		0, 0, 0, 0,
+		FN_SATA_DEVSLP_B, 0, 0, FN_VSP_A,
+		0, 0, 0, 0,
+		/* IPSR9_19_16 [4] */
+		IFN_SD2_DAT3, 0, 0, 0,
+		0, 0, 0, 0,
+		0, FN_SDATA_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_15_12 [4] */
+		IFN_SD2_DAT2, 0, 0, 0,
+		0, 0, 0, 0,
+		0, FN_MDATA_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_11_8 [4] */
+		IFN_SD2_DAT1, 0, 0, 0,
+		0, 0, 0, 0,
+		0, FN_STMx_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_7_4 [4] */
+		IFN_SD2_DAT0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, FN_MTSx_A, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR9_3_0 [4] */
+		IFN_SD2_CLK, 0, 0, 0,
+		0, 0, 0, 0,
+		0, FN_SCKZ_A, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR10_31_28 [4] */
+		IFN_RX0, FN_HRX1_B, 0, 0,
+		0, FN_TS_SCK0_C, FN_STP_ISCLK_0_C, FN_RIF0_D0_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_27_24 [4] */
+		IFN_SCK0, FN_HSCK1_B, FN_MSIOF1_SS2_B, FN_AUDIO_CLKC_B,
+		FN_SDA2_A, FN_SIM0_RST_B, FN_STP_OPWM__C, FN_RIF0_CLK_B,
+		0, FN_ADICHS2, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_23_20 [4] */
+		IFN_SD1_WP, 0, 0, 0,
+		0, FN_SIM0_D_B, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_19_16 [4] */
+		IFN_SD1_CD, 0, 0, 0,
+		0, FN_SIM0_CLK_B, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_15_12 [4] */
+		IFN_SD0_WP, 0, 0, 0,
+		FN_SDA2_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_11_8 [4] */
+		IFN_SD0_CD, 0, 0, 0,
+		FN_SCL2_B, FN_SIM0_RST_A, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_7_4 [4] */
+		IFN_SD3_DAT7, FN_SD3_WP, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR10_3_0 [4] */
+		IFN_SD3_DAT6, FN_SD3_CD, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606022C, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR11_31_28 [4] */
+		IFN_SCK2, FN_SCIF_CLK_B, FN_MSIOF1_SCK_B, 0,
+		0, FN_TS_SCK1_C, FN_STP_ISCLK_1_C, FN_RIF1_CLK_B,
+		0, FN_ADICLK, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_27_24 [4] */
+		IFN_RTS1x_TANS, FN_HRTS1x_A, FN_MSIOF1_TXD_B, 0,
+		0, FN_TS_SDAT1_C, FN_STP_ISD_1_C, FN_RIF1_D1_B,
+		0, FN_ADICHS0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_23_20 [4] */
+		IFN_CTS1x, FN_HCTS1x_A, FN_MSIOF1_RXD_B, 0,
+		0, FN_TS_SDEN1_C, FN_STP_ISEN_1_C, FN_RIF1_D0_B,
+		0, FN_ADIDATA, 0, 0,
+		/* IPSR11_19_16 [4] */
+		IFN_TX1_A, FN_HTX1_A, 0, 0,
+		0, FN_TS_SDEN0_C, FN_STP_ISEN_0_C, FN_RIF1_D0_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_15_12 [4] */
+		IFN_RX1_A, FN_HRX1_A, 0, 0,
+		0, FN_TS_SDAT0_C, FN_STP_IDS_0_C, FN_RIF1_CLK_C,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_11_8 [4] */
+		IFN_RTS0x_TANS, FN_HRTS1x_B, FN_MSIOF1_SS1_B, FN_AUDIO_CLKA_B,
+		FN_SCL2_A, 0, FN_STP_IVCXO27_1_C, FN_RIF0_SYNC_B,
+		0, FN_ADICHS1, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_7_4 [4] */
+		IFN_CTS0x, FN_HCTS1x_B, FN_MSIOF1_SYNC_B, 0,
+		0, FN_TS_SPSYNC1_C, FN_STP_ISSYNC_1_C, FN_RIF1_SYNC_B,
+		FN_AUDIO_CLKOUT_C, FN_ADICS_SAMP, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR11_3_0 [4] */
+		IFN_TX0, FN_HTX1_B, 0, 0,
+		0, FN_TS_SPSYNC0_C, FN_STP_ISSYNC_0_C, FN_RIF0_D1_B,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060230, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR12_31_28 [4] */
+		IFN_MSIOF0_SYNC, 0, 0, 0,
+		0, 0, 0, 0,
+		FN_AUDIO_CLKOUT_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_27_24 [4] */
+		IFN_HRTS0x, FN_TX2_B, FN_MSIOF1_SS1_D, 0,
+		FN_SSI_WS9_A, 0, FN_STP_IVCXO27_0_D, FN_BPFCLK_A,
+		FN_AUDIO_CLKOUT2_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_23_20 [4] */
+		IFN_HCTS0x, FN_RX2_B, FN_MSIOF1_SYNC_D, 0,
+		FN_SSI_SCK9_A, FN_TS_SPSYNC0_D, FN_STP_ISSYNC_0_D,
+		FN_RIF0_SYNC_C,
+		FN_AUDIO_CLKOUT1_A, FN_AD_NSCx, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_19_16 [4] */
+		IFN_HTX0, 0, FN_MSIOF1_TXD_D, 0,
+		FN_SSI_SDATA9_B, FN_TS_SDAT0_D, FN_STP_ISD_0_D, FN_RIF0_D1_C,
+		0, FN_AD_DO, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_15_12 [4] */
+		IFN_HRX0, 0, FN_MSIOF1_RXD_D, 0,
+		FN_SS1_SDATA2_B, FN_TS_SDEN0_D, FN_STP_ISEN_0_D, FN_RIF0_D0_C,
+		0, FN_AD_DI, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_11_8 [4] */
+		IFN_HSCK0, 0, FN_MSIOF1_SCK_D, FN_AUDIO_CLKB_A,
+		FN_SSI_SDATA1_B, FN_TS_SCK0_D, FN_STP_ISCLK_0_D, FN_RIF0_CLK_C,
+		0, FN_AD_CLK, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_7_4 [4] */
+		IFN_RX2_A, 0, 0, FN_SD2_WP_B,
+		FN_SDA1_A, FN_RDS_DATA_B, FN_RMIN_A, FN_RIF1_SYNC_C,
+		0, FN_FSO_CEF_1_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR12_3_0 [4] */
+		IFN_TX2_A, 0, 0, FN_SD2_CD_B,
+		FN_SCL1_A, FN_RSD_CLK_B, FN_FMCLK_A, FN_RIF1_D1_C,
+		0, FN_FSO_CFE_0_B, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR13", 0xE6060234, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR13_31_28 [4] */
+		IFN_SSI_SDATA0, 0, FN_MSIOF1_SS2_F, 0,
+		0, 0, 0, FN_MOUT2,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_27_24 [4] */
+		IFN_SSI_WS0129, 0, FN_MSIOF1_SS1_F, 0,
+		0, 0, 0, FN_MOUT1,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_23_20 [4] */
+		IFN_SSI_SCK0129, 0, FN_MSIOF1_TXD_F, 0,
+		0, 0, 0, FN_MOUT0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_19_16 [4] */
+		IFN_MLB_DAT, FN_TX1_B, FN_MSIOF1_RXD_F, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_15_12 [4] */
+		IFN_MLB_SIG, FN_RX1_B, FN_MSIOF1_SYNC_F, 0,
+		FN_SDA1_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_11_8 [4] */
+		IFN_MLB_CLK, 0, FN_MSIOF1_SCK_F, 0,
+		FN_SCL1_B, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR13_7_4 [4] */
+		IFN_MSIOF0_SS2, FN_TX5, FN_MSIOF1_SS2_D, FN_AUDIO_CLKC_A,
+		FN_SSI_WS2_A, FN_RDS_DATA_A, FN_STP_OPWM_0_D, 0,
+		FN_AUDIO_CLKOUT_D, 0, FN_SPEEDIN_B, 0,
+		/* IPSR13_3_0 [4] */
+		IFN_MSIOF0_SS1, FN_RX5, 0, FN_AUDIO_CLKA_C,
+		FN_SSI_SCK2_A, FN_RDS_CLK_A, FN_STP_IVCXO27_0_C, 0,
+		FN_AUDIO_CLKOUT3_A, 0, FN_TCLK1_B, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR14", 0xE6060238, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR14_31_28 [4] */
+		IFN_SSI_SDATA4, FN_HSCK2_A, FN_MSIOF1_RXD_A, 0,
+		0, FN_TS_SPSYNC0_A, FN_STP_ISSYNC_0_A, FN_RIF0_D0_A,
+		FN_RIF2_D1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_27_24 [4] */
+		IFN_SSI_WS4, FN_HTX2_A, FN_MSIOF1_SYNC_A, 0,
+		0, FN_TS_SDEN0_A, FN_STP_ISEN_0_A, FN_RIF0_SYNC_A,
+		FN_RIF2_SYNC_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_23_20 [4] */
+		IFN_SSI_SCK4, FN_HRX2_A, FN_MSIOF1_SCK_A, 0,
+		0, FN_TS_SDAT0_A, FN_STP_ISD_0_A, FN_RIF0_CLK_A,
+		FN_RIF2_CLK_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_19_16 [4] */
+		IFN_SSI_SDATA3, FN_HRTS2x_A, FN_MSIOF1_TXD_A, 0,
+		0, FN_TS_SCK0_A, FN_STP_ISCLK_0_A, FN_RIF0_D1_A,
+		FN_RIF2_D0_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_15_12 [4] */
+		IFN_SSI_WS34, FN_HCTS2x_A, FN_MSIOF1_SS2_A, 0,
+		0, 0, FN_STP_IVCXO27_0_A, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_11_8 [4] */
+		IFN_SSI_SCK34, 0, FN_MSIOF1_SS1_A, 0,
+		0, 0, FN_STP_OPWM_0_A, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_7_4 [4] */
+		IFN_SSI_SDATA2_A, 0, 0, 0,
+		FN_SSI_SCK1_B, 0, 0, FN_MOUT6,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR14_3_0 [4] */
+		IFN_SSI_SDATA1_A, 0, 0, 0,
+		0, 0, 0, FN_MOUT5,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR15", 0xE606023C, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR15_31_28 [4] */
+		IFN_SSI_SDATA9_A, FN_HSCK2_B, FN_MSIOF1_SS1_C, FN_HSCK1_A,
+		FN_SSI_WS1_B, FN_SCK1, FN_STP_IVCXO27_1_A, FN_SCK5,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_27_24 [4] */
+		IFN_SSI_SDATA8, FN_HRTS2x_B, FN_MSIOF1_TXD_C, 0,
+		0, FN_TS_SPSYNC1_A, FN_STP_ISSYNC_1_A, FN_RIF1_D1_A,
+		FN_EIF3_D1_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_23_20 [4] */
+		IFN_SSI_SDATA7, FN_HCTS2x_B, FN_MSIOF1_RXD_C, 0,
+		0, FN_TS_SDEN1_A, FN_STP_IEN_1_A, FN_RIF1_D0_A,
+		FN_RIF3_D0_A, 0, FN_TCLK2_A, 0,
+		/* IPSR15_19_16 [4] */
+		IFN_SSI_WS78, FN_HTX2_B, FN_MSIOF1_SYNC_C, 0,
+		0, FN_TS_SDT1_A, FN_STP_ISD_1_A, FN_RIF1_SYNC_A,
+		FN_RIF3_SYNC_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_15_12 [4] */
+		IFN_SSI_SCK78, FN_HRX2_B, FN_MSIOF1_SCK_C, 0,
+		0, FN_TS_SCK1_A, FN_STP_ISCLK_1_A, FN_RIF1_CLK_A,
+		FN_RIF3_CLK_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_11_8 [4] */
+		IFN_SSI_SDATA6, 0, 0, FN_SIM0_CLK_D,
+		0, 0, FN_RSD_DATA_C, 0,
+		FN_SATA_DEVSLP_A, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_7_4 [4] */
+		IFN_SSI_WS6, FN_USB2_OVC, 0, FN_SIM0_D_D,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR15_3_0 [4] */
+		IFN_SSI_SCK6, FN_USB2_PWEN, 0, FN_SIM0_RST_D,
+		0, 0, FN_RDS_CLK_C, 0,
+		0, 0, 0, 0,
+		0, 0, 0, 0,
+		}
+
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR16", 0xE6060240, 32,
+				4, 4, 4, 4, 4, 4, 4, 4) {
+		/* IPSR16_31_28 [4] */
+		IFN_USB30_OVC, 0, FN_AUDIO_CLKOUT1_B, 0,
+		FN_SSI_WS2_B, FN_TS_SPSYNC1_D, FN_STP_ISSYNC_1_D,
+		FN_STP_IVCXO27_0_E,
+		FN_RIF3_D1_B, FN_SDATA_B, FN_RSO_TOE_B, FN_TPU0TO1,
+		0, 0, 0, 0,
+		/* IPSR16_27_24 [4] */
+		IFN_USB30_PWEN, 0, 0, FN_AUDIO_CLKOUT_B,
+		FN_SSI_SCK2_B, FN_TS_SDEN1_D, FN_STP_ISEN_1_D, FN_STP_OPWM_0_E,
+		FN_RIF3_D0_B, FN_MDATA_B, FN_TCLK2_B, FN_TPU0TO0,
+		0, 0, 0, 0,
+		/* IPSR16_23_20 [4] */
+		IFN_USB1_OVC, 0, FN_MSIOF1_SS2_C, 0,
+		FN_SSI_WS1_A, FN_TS_SDAT0_E, FN_STP_ISD_0_E, FN_FMIN_B,
+		FN_RIF2_SYNC_B, FN_STMx_B, FN_REMOCON_B, 0,
+		0, 0, 0, 0,
+		/* IPSR16_19_16 [4] */
+		IFN_USB1_PWEN, 0, 0, FN_SIM0_CLK_C,
+		FN_SSI_SCK1_A, FN_TS_SCK0_E, FN_STP_ISCLK_0_E, FN_FMCLK_B,
+		FN_RIF2_CLK_B, FN_MTSx_B, FN_SPEEDIN_A, FN_VSP_D,
+		0, 0, 0, 0,
+		/* IPSR16_15_12 [4] */
+		IFN_USB0_OVC, 0, 0, FN_SIM0_D_C,
+		0, FN_TS_SDAT1_D, FN_STP_ISD_1_D, 0,
+		FN_RIF3_SYNC_B, 0, 0, FN_VSP_C,
+		0, 0, 0, 0,
+		/* IPSR16_11_8 [4] */
+		IFN_USB0_PWEN, 0, 0, FN_SIM0_RST_C,
+		0, FN_TS_SCK1_D, FN_STP_ISCLK_1_D, FN_BPFCLK_B,
+		FN_RIF3_CLK_B, FN_SCKZ_B, 0, 0,
+		0, 0, 0, 0,
+		/* IPSR16_7_4 [4] */
+		IFN_AUDIO_CLKB_B, FN_SCIF_CLK_A, 0, 0,
+		FN_DVC_MUTE, 0, FN_STP_IVCXO27_1_D, FN_REMOCON_A,
+		0, 0, FN_TCLK1_A, FN_VSP_B,
+		0, 0, 0, 0,
+		/* IPSR16_3_0 [4] */
+		IFN_AUDIO_CLKA_A, 0, 0, 0,
+		0, 0, 0, 0,
+		0, 0, 0, FN_CC5_OSCOUT,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR17", 0xE6060244, 32,
+				1, 1, 1, 1, 1, 1, 1, 1,
+				1, 1, 1, 1, 1, 1, 1, 1,
+				1, 1, 1, 1, 1, 1, 1, 1,
+				4, 4) {
+		/* reserved [31..24] */
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		/* reserved [23..16] */
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		/* reserved [15..8] */
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		/* IPSR17_7_4 [4] */
+		IFN_USB31_OVC, 0, 0, FN_AUDIO_CLKOUT3_B,
+		FN_SSI_WS9_B, FN_TS_SPSYNC0_E, FN_STP_ISSYNC_0_E, 0,
+		FN_RIF2_D1_B, 0, 0, FN_TPU0TO3,
+		0, 0, 0, 0,
+		/* IPSR17_3_0 [4] */
+		IFN_USB31_PWEN, 0, 0, FN_AUDIO_CLKOUT2_B,
+		FN_SI_SCK9_B, FN_TS_SDEN0_E, FN_STP_ISEN_0_E, 0,
+		FN_RIF2_D0_B, 0, 0, FN_TPU0TO2,
+		0, 0, 0, 0,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE6060500, 32,
+				1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2,
+				1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
+		/* RESERVED [1] */
+		0, 0,
+		/* SEL_MSIOF3 [2] */
+		FN_SEL_MSIOF3_0, FN_SEL_MSIOF3_1,
+		FN_SEL_MSIOF3_2, FN_SEL_MSIOF3_3,
+		/* SEL_MSIOF2 [2] */
+		FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1,
+		FN_SEL_MSIOF2_2, FN_SEL_MSIOF2_3,
+		/* SEL_MSIOF1 [3] */
+		FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
+		FN_SEL_MSIOF1_2, FN_SEL_MSIOF1_3,
+		FN_SEL_MSIOF1_4, FN_SEL_MSIOF1_5,
+		FN_SEL_MSIOF1_6, 0,
+		/* SEL_LBSC [1] */
+		FN_SEL_LBSC_0, FN_SEL_LBSC_1,
+		/* SEL_IEBUS [1] */
+		FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
+		/* SEL_I2C6 [2] */
+		FN_SEL_I2C6_0, FN_SEL_I2C6_1,
+		FN_SEL_I2C6_2, 0,
+		/* SEL_I2C2 [1] */
+		FN_SEL_I2C2_0, FN_SEL_I2C2_1,
+		/* SEL_I2C1 [1] */
+		FN_SEL_I2C1_0, FN_SEL_I2C1_1,
+		/* SEL_HSCIF4 [1] */
+		FN_SEL_HSCIF4_0, FN_SEL_HSCIF4_1,
+		/* SEL_HSCIF3 [2] */
+		FN_SEL_HSCIF3_0, FN_SEL_HSCIF3_1,
+		FN_SEL_HSCIF3_2, FN_SEL_HSCIF3_3,
+		/* SEL_HSCIF2 [1] */
+		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+		/* SEL_HSCIF1 [1] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+		/* SEL_FSO [1] */
+		0, FN_SEL_FSO_1,
+		/* SEL_FM [1] */
+		FN_SEL_FM_0, FN_SEL_FM_1,
+		/* SEL_ETHERAVB [1] */
+		FN_SEL_ETHERAVB_0, FN_SEL_ETHERAVB_1,
+		/* SEL_DRIF3 [1] */
+		FN_SEL_DRIF3_0, FN_SEL_DRIF3_1,
+		/* SEL_DRIF2 [1] */
+		FN_SEL_DRIF2_0, FN_SEL_DRIF2_1,
+		/* SEL_DRIF1 [2] */
+		FN_SEL_DRIF1_0, FN_SEL_DRIF1_1,
+		FN_SEL_DRIF1_2, 0,
+		/* SEL_DRIF0 [2] */
+		FN_SEL_DRIF0_0, FN_SEL_DRIF0_1,
+		FN_SEL_DRIF0_2, 0,
+		/* SEL_CANFD0 [1] */
+		FN_SEL_CANFD_0, FN_SEL_CANFD_1,
+		/* SEL_ADG [2] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1,
+		FN_SEL_ADG_2, FN_SEL_ADG_3,
+		/* SEL_5LINE [1] */
+		FN_SEL_5LINE_0, FN_SEL_5LINE_1,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE6060504, 32,
+				2, 3, 1, 2,
+				3, 1, 1, 2, 1,
+				2, 1, 1, 1, 1, 1, 2,
+				1, 1, 1, 1, 1, 1, 1) {
+		/* SEL_TSIF1 [2] */
+		FN_SEL_TSIF1_0,
+		FN_SEL_TSIF1_1,
+		FN_SEL_TSIF1_2,
+		FN_SEL_TSIF1_3,
+		/* SEL_TSIF0 [3] */
+		FN_SEL_TSIF0_0,
+		FN_SEL_TSIF0_1,
+		FN_SEL_TSIF0_2,
+		FN_SEL_TSIF0_3,
+		FN_SEL_TSIF0_4,
+		0,
+		0,
+		0,
+		/* SEL_TIMER_TMU [1] */
+		FN_SEL_TIMER_TMU_0,
+		FN_SEL_TIMER_TMU_1,
+		/* SEL_SSP1_1 [2] */
+		FN_SEL_SSP1_1_0,
+		FN_SEL_SSP1_1_1,
+		FN_SEL_SSP1_1_2,
+		FN_SEL_SSP1_1_3,
+		/* SEL_SSP1_0 [3] */
+		FN_SEL_SSP1_0_0,
+		FN_SEL_SSP1_0_1,
+		FN_SEL_SSP1_0_2,
+		FN_SEL_SSP1_0_3,
+		FN_SEL_SSP1_0_4,
+		0,
+		0,
+		0,
+		/* SEL_SSI [1] */
+		FN_SEL_SSI_0,
+		FN_SEL_SSI_1,
+		/* SEL_SPEED_PULSE_IF [1] */
+		FN_SEL_SPEED_PULSE_IF_0,
+		FN_SEL_SPEED_PULSE_IF_1,
+		/* SEL_SIMCARD [2] */
+		FN_SEL_SIMCARD_0,
+		FN_SEL_SIMCARD_1,
+		FN_SEL_SIMCARD_2,
+		FN_SEL_SIMCARD_3,
+		/* SEL_SDHI2 [1] */
+		FN_SEL_SDHI2_0,
+		FN_SEL_SDHI2_1,
+		/* SEL_SCIF4 [2] */
+		FN_SEL_SCIF4_0,
+		FN_SEL_SCIF4_1,
+		FN_SEL_SCIF4_2,
+		0,
+		/* SEL_SCIF3 [1] */
+		FN_SEL_SCIF3_0,
+		FN_SEL_SCIF3_1,
+		/* SEL_SCIF2 [1] */
+		FN_SEL_SCIF2_0,
+		FN_SEL_SCIF2_1,
+		/* SEL_SCIF1 [1] */
+		FN_SEL_SCIF1_0,
+		FN_SEL_SCIF1_1,
+		/* SEL_SCIF [1] */
+		FN_SEL_SCIF_0,
+		FN_SEL_SCIF_1,
+		/* SEL_REMOCON [1] */
+		FN_SEL_REMOCON_0,
+		FN_SEL_REMOCON_1,
+		/* SEL_RDS [2] */
+		FN_SEL_RDS_0,
+		FN_SEL_RDS_1,
+		FN_SEL_RDS_2,
+		0,
+		/* SEL_RCAN [1] */
+		FN_SEL_RCAN_0,
+		FN_SEL_RCAN_1,
+		/* SEL_PWM6 [1] */
+		FN_SEL_PWM6_0,
+		FN_SEL_PWM6_1,
+		/* SEL_PWM5 [1] */
+		FN_SEL_PWM5_0,
+		FN_SEL_PWM5_1,
+		/* SEL_PWM4 [1] */
+		FN_SEL_PWM4_0,
+		FN_SEL_PWM4_1,
+		/* SEL_PWM3 [1] */
+		FN_SEL_PWM3_0,
+		FN_SEL_PWM3_1,
+		/* SEL_PWM2 [1] */
+		FN_SEL_PWM2_0,
+		FN_SEL_PWM2_1,
+		/* SEL_PWM1 [1] */
+		FN_SEL_PWM1_0,
+		FN_SEL_PWM1_1,
+		}
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060508, 32,
+				1, 1, 1, 26, 2, 1) {
+		/* I2C_SEL_5 [1] */
+		FN_I2C_SEL_5_0,
+		FN_I2C_SEL_5_1,
+		/* I2C_SEL_3 [1] */
+		FN_I2C_SEL_3_0,
+		FN_I2C_SEL_3_1,
+		/* I2C_SEL_0 [1] */
+		FN_I2C_SEL_0_0,
+		FN_I2C_SEL_0_1,
+		/* reserved [26] */
+		/* SEL_VSP [2] */
+		FN_SEL_VSP_0,
+		FN_SEL_VSP_1,
+		FN_SEL_VSP_2,
+		FN_SEL_VSP_3,
+		/* SEL_VIN4 [1] */
+		FN_SEL_VIN4_0,
+		FN_SEL_VIN4_1,
+		}
+	},
+
+	/* under construction */
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		GP_0_15_IN, GP_0_15_OUT,
+		GP_0_14_IN, GP_0_14_OUT,
+		GP_0_13_IN, GP_0_13_OUT,
+		GP_0_12_IN, GP_0_12_OUT,
+		GP_0_11_IN, GP_0_11_OUT,
+		GP_0_10_IN, GP_0_10_OUT,
+		GP_0_9_IN, GP_0_9_OUT,
+		GP_0_8_IN, GP_0_8_OUT,
+		GP_0_7_IN, GP_0_7_OUT,
+		GP_0_6_IN, GP_0_6_OUT,
+		GP_0_5_IN, GP_0_5_OUT,
+		GP_0_4_IN, GP_0_4_OUT,
+		GP_0_3_IN, GP_0_3_OUT,
+		GP_0_2_IN, GP_0_2_OUT,
+		GP_0_1_IN, GP_0_1_OUT,
+		GP_0_0_IN, GP_0_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_27_IN, GP_1_27_OUT,
+		GP_1_26_IN, GP_1_26_OUT,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		GP_2_14_IN, GP_2_14_OUT,
+		GP_2_13_IN, GP_2_13_OUT,
+		GP_2_12_IN, GP_2_12_OUT,
+		GP_2_11_IN, GP_2_11_OUT,
+		GP_2_10_IN, GP_2_10_OUT,
+		GP_2_9_IN, GP_2_9_OUT,
+		GP_2_8_IN, GP_2_8_OUT,
+		GP_2_7_IN, GP_2_7_OUT,
+		GP_2_6_IN, GP_2_6_OUT,
+		GP_2_5_IN, GP_2_5_OUT,
+		GP_2_4_IN, GP_2_4_OUT,
+		GP_2_3_IN, GP_2_3_OUT,
+		GP_2_2_IN, GP_2_2_OUT,
+		GP_2_1_IN, GP_2_1_OUT,
+		GP_2_0_IN, GP_2_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		GP_3_15_IN, GP_3_15_OUT,
+		GP_3_14_IN, GP_3_14_OUT,
+		GP_3_13_IN, GP_3_13_OUT,
+		GP_3_12_IN, GP_3_12_OUT,
+		GP_3_11_IN, GP_3_11_OUT,
+		GP_3_10_IN, GP_3_10_OUT,
+		GP_3_9_IN, GP_3_9_OUT,
+		GP_3_8_IN, GP_3_8_OUT,
+		GP_3_7_IN, GP_3_7_OUT,
+		GP_3_6_IN, GP_3_6_OUT,
+		GP_3_5_IN, GP_3_5_OUT,
+		GP_3_4_IN, GP_3_4_OUT,
+		GP_3_3_IN, GP_3_3_OUT,
+		GP_3_2_IN, GP_3_2_OUT,
+		GP_3_1_IN, GP_3_1_OUT,
+		GP_3_0_IN, GP_3_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_4_17_IN, GP_4_17_OUT,
+		GP_4_16_IN, GP_4_16_OUT,
+
+		GP_4_15_IN, GP_4_15_OUT,
+		GP_4_14_IN, GP_4_14_OUT,
+		GP_4_13_IN, GP_4_13_OUT,
+		GP_4_12_IN, GP_4_12_OUT,
+		GP_4_11_IN, GP_4_11_OUT,
+		GP_4_10_IN, GP_4_10_OUT,
+		GP_4_9_IN, GP_4_9_OUT,
+		GP_4_8_IN, GP_4_8_OUT,
+		GP_4_7_IN, GP_4_7_OUT,
+		GP_4_6_IN, GP_4_6_OUT,
+		GP_4_5_IN, GP_4_5_OUT,
+		GP_4_4_IN, GP_4_4_OUT,
+		GP_4_3_IN, GP_4_3_OUT,
+		GP_4_2_IN, GP_4_2_OUT,
+		GP_4_1_IN, GP_4_1_OUT,
+		GP_4_0_IN, GP_4_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_5_25_IN, GP_5_25_OUT,
+		GP_5_24_IN, GP_5_24_OUT,
+
+		GP_5_23_IN, GP_5_23_OUT,
+		GP_5_22_IN, GP_5_22_OUT,
+		GP_5_21_IN, GP_5_21_OUT,
+		GP_5_20_IN, GP_5_20_OUT,
+		GP_5_19_IN, GP_5_19_OUT,
+		GP_5_18_IN, GP_5_18_OUT,
+		GP_5_17_IN, GP_5_17_OUT,
+		GP_5_16_IN, GP_5_16_OUT,
+
+		GP_5_15_IN, GP_5_15_OUT,
+		GP_5_14_IN, GP_5_14_OUT,
+		GP_5_13_IN, GP_5_13_OUT,
+		GP_5_12_IN, GP_5_12_OUT,
+		GP_5_11_IN, GP_5_11_OUT,
+		GP_5_10_IN, GP_5_10_OUT,
+		GP_5_9_IN, GP_5_9_OUT,
+		GP_5_8_IN, GP_5_8_OUT,
+		GP_5_7_IN, GP_5_7_OUT,
+		GP_5_6_IN, GP_5_6_OUT,
+		GP_5_5_IN, GP_5_5_OUT,
+		GP_5_4_IN, GP_5_4_OUT,
+		GP_5_3_IN, GP_5_3_OUT,
+		GP_5_2_IN, GP_5_2_OUT,
+		GP_5_1_IN, GP_5_1_OUT,
+		GP_5_0_IN, GP_5_0_OUT,
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) {
+		GP_INOUTSEL(6)
+		}
+	},
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_6_3_IN, GP_6_3_OUT,
+		GP_6_2_IN, GP_6_2_OUT,
+		GP_6_1_IN, GP_6_1_OUT,
+		GP_6_0_IN, GP_6_0_OUT,
+		}
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	/* use OUTDT registers? */
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA,
+		GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA,
+		GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA,
+		GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
+		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
+		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
+		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA,
+		GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA,
+		GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA,
+		GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, GP_4_17_DATA, GP_4_16_DATA,
+		GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA,
+		GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA,
+		GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA,
+		GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_5_25_DATA, GP_5_24_DATA,
+		GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA,
+		GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA,
+		GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA,
+		GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
+		GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
+		GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) {
+		GP_INDT(6) }
+	},
+	{ PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0, 0, 0, 0, 0,
+		0, 0, 0, 0,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+};
+
+static struct pinmux_info r8a7795_pinmux_info = {
+	.name = "r8a7795_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_TPU0TO3,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7795_pinmux_init(void)
+{
+	register_pinmux(&r8a7795_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c b/arch/arm/mach-rmobile/pfc-sh73a0.c
index 55dab7c1389..55dab7c1389 100644
--- a/arch/arm/cpu/armv7/rmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-rmobile/pfc-sh73a0.c
diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/mach-rmobile/timer.c
index 04700e7d34d..04700e7d34d 100644
--- a/arch/arm/cpu/armv7/rmobile/timer.c
+++ b/arch/arm/mach-rmobile/timer.c
diff --git a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
index 0e9c22296a3..28e61116a39 100644
--- a/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
+++ b/board/atmark-techno/armadillo-800eva/armadillo-800eva.c
@@ -315,7 +315,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 int board_late_init(void)
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index ea36fa4e192..a284721cfde 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -349,7 +349,7 @@ int board_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 int dram_init(void)
diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile
index 6904e39b128..22ab1f43d96 100644
--- a/board/renesas/alt/Makefile
+++ b/board/renesas/alt/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= alt.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= alt.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 3501a170442..a1a26a6d821 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -217,7 +217,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
index b6324c8fd7c..3323c3aee15 100644
--- a/board/renesas/alt/qos.c
+++ b/board/renesas/alt/qos.c
@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 /* QoS version 0.311 for ES1 and version 0.321 for ES2 */
 
 enum {
@@ -993,8 +993,8 @@ void qos_init(void)
 	writel(0x00000001, &axi_qos->qosthres2);
 	writel(0x00000001, &axi_qos->qosqon);
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/blanche/Kconfig b/board/renesas/blanche/Kconfig
new file mode 100644
index 00000000000..ac4730a62fe
--- /dev/null
+++ b/board/renesas/blanche/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BLANCHE
+
+config SYS_BOARD
+	default "blanche"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "blanche"
+
+endif
diff --git a/board/renesas/blanche/Makefile b/board/renesas/blanche/Makefile
new file mode 100644
index 00000000000..bdbfb291ecd
--- /dev/null
+++ b/board/renesas/blanche/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/blanche/Makefile
+#
+# Copyright (C) 2016 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= blanche.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c
new file mode 100644
index 00000000000..b2e2e3b0808
--- /dev/null
+++ b/board/renesas/blanche/blanche.c
@@ -0,0 +1,488 @@
+/*
+ * board/renesas/blanche/blanche.c
+ *     This file is blanche board support.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <asm/arch/mmc.h>
+#include <asm/arch/sh_sdhi.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include <mmc.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct pin_db {
+	u32	addr;	/* register address */
+	u32	mask;	/* mask value */
+	u32	val;	/* setting value */
+};
+
+#define	PMMR		0xE6060000
+#define	GPSR0		0xE6060004
+#define	GPSR1		0xE6060008
+#define	GPSR4		0xE6060014
+#define	GPSR5		0xE6060018
+#define	GPSR6		0xE606001C
+#define	GPSR7		0xE6060020
+#define	GPSR8		0xE6060024
+#define	GPSR9		0xE6060028
+#define	GPSR10		0xE606002C
+#define	GPSR11		0xE6060030
+#define	IPSR6		0xE6060058
+#define	PUPR2		0xE6060108
+#define	PUPR3		0xE606010C
+#define	PUPR4		0xE6060110
+#define	PUPR5		0xE6060114
+#define	PUPR7		0xE606011C
+#define	PUPR9		0xE6060124
+#define	PUPR10		0xE6060128
+#define	PUPR11		0xE606012C
+
+#define	CPG_PLL1CR	0xE6150028
+#define	CPG_PLL3CR	0xE61500DC
+
+#define	SetREG(x) \
+	writel((readl((x)->addr) & ~((x)->mask)) | ((x)->val), (x)->addr)
+
+#define	SetGuardREG(x)				\
+{ \
+	u32	val; \
+	val = (readl((x)->addr) & ~((x)->mask)) | ((x)->val); \
+	writel(~val, PMMR); \
+	writel(val, (x)->addr); \
+}
+
+struct pin_db	pin_guard[] = {
+	{ GPSR0,	0xFFFFFFFF,	0x0BFFFFFF },
+	{ GPSR1,	0xFFFFFFFF,	0x002FFFFF },
+	{ GPSR4,	0xFFFFFFFF,	0x00000FFF },
+	{ GPSR5,	0xFFFFFFFF,	0x00010FFF },
+	{ GPSR6,	0xFFFFFFFF,	0x00010FFF },
+	{ GPSR7,	0xFFFFFFFF,	0x00010FFF },
+	{ GPSR8,	0xFFFFFFFF,	0x00010FFF },
+	{ GPSR9,	0xFFFFFFFF,	0x00010FFF },
+	{ GPSR10,	0xFFFFFFFF,	0x04006000 },
+	{ GPSR11,	0xFFFFFFFF,	0x303FEFE0 },
+	{ IPSR6,	0xFFFFFFFF,	0x0002000E },
+};
+
+struct pin_db	pin_tbl[] = {
+	{ PUPR2,	0xFFFFFFFF,	0x00000000 },
+	{ PUPR3,	0xFFFFFFFF,	0x0803FF40 },
+	{ PUPR4,	0xFFFFFFFF,	0x0000FFFF },
+	{ PUPR5,	0xFFFFFFFF,	0x00010FFF },
+	{ PUPR7,	0xFFFFFFFF,	0x0001AFFF },
+	{ PUPR9,	0xFFFFFFFF,	0x0001CFFF },
+	{ PUPR10,	0xFFFFFFFF,	0xC0438001 },
+	{ PUPR11,	0xFFFFFFFF,	0x0FC00007 },
+};
+
+void pin_init(void)
+{
+	struct pin_db	*db;
+
+	for (db = pin_guard; db < &pin_guard[sizeof(pin_guard)/sizeof(struct pin_db)]; db++) {
+		SetGuardREG(db);
+	}
+	for (db = pin_tbl; db < &pin_tbl[sizeof(pin_tbl) /sizeof(struct pin_db)]; db++) {
+		SetREG(db);
+	}
+}
+
+#define s_init_wait(cnt) \
+		({	\
+			volatile u32 i = 0x10000 * cnt;	\
+			while (i > 0)	\
+				i--;	\
+		})
+
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+	u32 cpu_type;
+
+	cpu_type = rmobile_get_cpu_type();
+	if (cpu_type == 0x4A) {
+		writel(0x4D000000, CPG_PLL1CR);
+		writel(0x4F000000, CPG_PLL3CR);
+	}
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* SCIF Init */
+	pin_init();
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+	struct rcar_lbsc *lbsc = (struct rcar_lbsc *)LBSC_BASE;
+	struct rcar_dbsc3 *dbsc3_0 = (struct rcar_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x2A103320, &lbsc->cswcr0);
+	writel(0x2A103320, &lbsc->cswcr1);
+	writel(0x19102110, &lbsc->ecswcr0);
+	writel(0x19102110, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+
+	writel(0x21000000, &dbsc3_0->dbcmd);		/* opc=RstH (RESET => H) */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+	writel(0x10000000, &dbsc3_0->dbcmd);		/* opc=PDEn(CKE=L) */
+
+	/* Stop Auto-Calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* PLLCR: PLL Control Register */
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);	// > DDR1440
+
+	/* DXCCR: DATX8 Common Configuration Register */
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	/* DSGCR	:DDR System General Configuration Register */
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF00464DB, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000061, &dbsc3_0->dbpdrga);
+	writel(0x0000008D, &dbsc3_0->dbpdrgd);
+
+	/* Re-Execute ZQ calibration */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000073, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x0F030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+
+	writel(0x0000000B, &dbsc3_0->dbtr0);	// tCL=11
+	writel(0x00000008, &dbsc3_0->dbtr1);	// tCWL=8
+	writel(0x00000000, &dbsc3_0->dbtr2);	// tAL=0
+	writel(0x0000000B, &dbsc3_0->dbtr3);	// tRCD=11
+	writel(0x000C000B, &dbsc3_0->dbtr4);	// tRPA=12,tRP=11
+	writel(0x00000027, &dbsc3_0->dbtr5);	// tRC = 39
+	writel(0x0000001C, &dbsc3_0->dbtr6);	// tRAS = 28
+	writel(0x00000006, &dbsc3_0->dbtr7);	// tRRD = 6
+	writel(0x00000020, &dbsc3_0->dbtr8);	// tRFAW = 32
+	writel(0x00000008, &dbsc3_0->dbtr9);	// tRDPR = 8
+	writel(0x0000000C, &dbsc3_0->dbtr10);	// tWR = 12
+	writel(0x00000009, &dbsc3_0->dbtr11);	// tRDWR = 9
+	writel(0x00000012, &dbsc3_0->dbtr12);	// tWRRD = 18
+	writel(0x000000D0, &dbsc3_0->dbtr13);	// tRFC = 208
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);		/* DQL = 35, WDQL = 5 */
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082004, &dbsc3_0->dbadj2);		/* blanche QoS rev0.1 */
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);	/* 1600 */
+	writel(0x0000001F, &dbsc3_0->dbwt0cnf4);
+
+	while ((readl(&dbsc3_0->dbdfistat) & 0x00000001) != 0x00000001);
+	writel(0x00000011, &dbsc3_0->dbdficnt);
+
+	/* PGCR1	:PHY General Configuration Register 1 */
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C4E1, &dbsc3_0->dbpdrgd);		/* DDR3 */
+
+	/* PGCR2: PHY General Configuration Registers 2 */
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FCDB60, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	/* DTPR0	:DRAM Timing Parameters Register 0 */
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D9CBB66, &dbsc3_0->dbpdrgd);
+
+	/* DTPR1	:DRAM Timing Parameters Register 1 */
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868400, &dbsc3_0->dbpdrgd);
+
+	/* DTPR2	::DRAM Timing Parameters Register 2 */
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	/* MR0	:Mode Register 0 */
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	/* MR1	:Mode Register 1 */
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000004, &dbsc3_0->dbpdrgd);	/* DRAM Drv 40ohm */
+
+	/* MR2	:Mode Register 2 */
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);	/* CWL=8 */
+
+	/* VREF(ZQCAL) */
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x910035C7, &dbsc3_0->dbpdrgd);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* DRAM Init (set MRx etc) */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	/* CKE  = H */
+	writel(0x11000000, &dbsc3_0->dbcmd);		/* opc=PDXt(CKE=H) */
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* RAM ACC Training */
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	/* Bus control 0 */
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	/* DDR3 Calibration set */
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	/* DDR3 Calibration timing */
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	/* Refresh */
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+
+	/* PGSR0	:PHY General Status Registers 0 */
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	while ((readl(&dbsc3_0->dbpdrgd) & 0x00000001) != 0x00000001);
+
+	/* Enable Auto-Refresh */
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	/* Permit DDR-Access */
+	writel(0x00000001, &dbsc3_0->dbacen);
+
+	/* This locks the access to the PHY unit registers */
+	writel(0x00000000, &dbsc3_0->dbpdlck);
+#endif /* CONFIG_SYS_NO_FLASH */
+
+}
+
+#define TMU0_MSTP125	(1 << 25)
+#define SCIF0_MSTP721	(1 << 21)
+#define SDHI0_MSTP314	(1 << 14)
+#define QSPI_MSTP917	(1 << 17)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+	/* SCIF0 */
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+	/* SDHI0 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314);
+	/* QSPI */
+	mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7792_pinmux_init();
+
+	gpio_request(GPIO_FN_D0, NULL);
+	gpio_request(GPIO_FN_D1, NULL);
+	gpio_request(GPIO_FN_D2, NULL);
+	gpio_request(GPIO_FN_D3, NULL);
+	gpio_request(GPIO_FN_D4, NULL);
+	gpio_request(GPIO_FN_D5, NULL);
+	gpio_request(GPIO_FN_D6, NULL);
+	gpio_request(GPIO_FN_D7, NULL);
+	gpio_request(GPIO_FN_D8, NULL);
+	gpio_request(GPIO_FN_D9, NULL);
+	gpio_request(GPIO_FN_D10, NULL);
+	gpio_request(GPIO_FN_D11, NULL);
+	gpio_request(GPIO_FN_D12, NULL);
+	gpio_request(GPIO_FN_D13, NULL);
+	gpio_request(GPIO_FN_D14, NULL);
+	gpio_request(GPIO_FN_D15, NULL);
+	gpio_request(GPIO_FN_A0, NULL);
+	gpio_request(GPIO_FN_A1, NULL);
+	gpio_request(GPIO_FN_A2, NULL);
+	gpio_request(GPIO_FN_A3, NULL);
+	gpio_request(GPIO_FN_A4, NULL);
+	gpio_request(GPIO_FN_A5, NULL);
+	gpio_request(GPIO_FN_A6, NULL);
+	gpio_request(GPIO_FN_A7, NULL);
+	gpio_request(GPIO_FN_A8, NULL);
+	gpio_request(GPIO_FN_A9, NULL);
+	gpio_request(GPIO_FN_A10, NULL);
+	gpio_request(GPIO_FN_A11, NULL);
+	gpio_request(GPIO_FN_A12, NULL);
+	gpio_request(GPIO_FN_A13, NULL);
+	gpio_request(GPIO_FN_A14, NULL);
+	gpio_request(GPIO_FN_A15, NULL);
+	gpio_request(GPIO_FN_A16, NULL);
+	gpio_request(GPIO_FN_A17, NULL);
+	gpio_request(GPIO_FN_A18, NULL);
+	gpio_request(GPIO_FN_A19, NULL);
+#if defined(CONFIG_SYS_NO_FLASH)
+	gpio_request(GPIO_FN_MOSI_IO0, NULL);
+	gpio_request(GPIO_FN_MISO_IO1, NULL);
+	gpio_request(GPIO_FN_IO2, NULL);
+	gpio_request(GPIO_FN_IO3, NULL);
+	gpio_request(GPIO_FN_SPCLK, NULL);
+	gpio_request(GPIO_FN_SSL, NULL);
+#else	/* CONFIG_SYS_NO_FLASH */
+	gpio_request(GPIO_FN_A20, NULL);
+	gpio_request(GPIO_FN_A21, NULL);
+	gpio_request(GPIO_FN_A22, NULL);
+	gpio_request(GPIO_FN_A23, NULL);
+	gpio_request(GPIO_FN_A24, NULL);
+	gpio_request(GPIO_FN_A25, NULL);
+#endif	/* CONFIG_SYS_NO_FLASH */
+
+	gpio_request(GPIO_FN_CS1_A26, NULL);
+	gpio_request(GPIO_FN_EX_CS0, NULL);
+	gpio_request(GPIO_FN_EX_CS1, NULL);
+	gpio_request(GPIO_FN_BS, NULL);
+	gpio_request(GPIO_FN_RD, NULL);
+	gpio_request(GPIO_FN_WE0, NULL);
+	gpio_request(GPIO_FN_WE1, NULL);
+	gpio_request(GPIO_FN_EX_WAIT0, NULL);
+	gpio_request(GPIO_FN_IRQ0, NULL);
+	gpio_request(GPIO_FN_IRQ2, NULL);
+	gpio_request(GPIO_FN_IRQ3, NULL);
+	gpio_request(GPIO_FN_CS0, NULL);
+
+	/* Init timer */
+	timer_init();
+
+	return 0;
+}
+
+/*
+ Added for BLANCHE(R-CarV2H board)
+*/
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_SMC911X
+#define STR_ENV_ETHADDR	"ethaddr"
+
+	struct eth_device *dev;
+	uchar eth_addr[6];
+
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+
+	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
+		dev = eth_get_dev_by_index(0);
+		if (dev) {
+			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
+		} else {
+			printf("blanche: Couldn't get eth device\n");
+			rc = -1;
+		}
+	}
+
+#endif
+
+	return rc;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	int ret = -ENODEV;
+
+#ifdef CONFIG_SH_SDHI
+	gpio_request(GPIO_FN_SD0_DAT0, NULL);
+	gpio_request(GPIO_FN_SD0_DAT1, NULL);
+	gpio_request(GPIO_FN_SD0_DAT2, NULL);
+	gpio_request(GPIO_FN_SD0_DAT3, NULL);
+	gpio_request(GPIO_FN_SD0_CLK, NULL);
+	gpio_request(GPIO_FN_SD0_CMD, NULL);
+	gpio_request(GPIO_FN_SD0_CD, NULL);
+
+	gpio_request(GPIO_GP_11_12, NULL);
+	gpio_direction_output(GPIO_GP_11_12, 1);	/* power on */
+
+
+	ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0,
+			   SH_SDHI_QUIRK_16BIT_BUF);
+
+	if (ret)
+		return ret;
+#endif
+	return ret;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void reset_cpu(ulong addr)
+{
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF0_BASE,
+	.type = PORT_SCIF,
+	.clk = 14745600,
+	.clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(blanche_serials) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c
new file mode 100644
index 00000000000..f1327f6075c
--- /dev/null
+++ b/board/renesas/blanche/qos.c
@@ -0,0 +1,1366 @@
+/*
+ * board/renesas/blanche/qos.c
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct rcar_s3c *s3c;
+	struct rcar_s3c_qos *s3c_qos;
+	struct rcar_dbsc3_qos *qos_addr;
+	struct rcar_mxi *mxi;
+	struct rcar_mxi_qos *mxi_qos;
+	struct rcar_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20082004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct rcar_s3c *)S3C_BASE;
+	// writel(0x00000000, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F1F0C0C, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000204B, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FC4, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x0000205A, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct rcar_mxi *)MXI_BASE;
+	writel(0x00000100, &mxi->mxaxirtcr);
+	writel(0xFF530100, &mxi->mxaxiwtcr);
+	writel(0x00000100, &mxi->mxs3crtcr);
+	writel(0xFF530100, &mxi->mxs3cwtcr);
+	writel(0x004000C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->du0);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADM_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AXI64TO128W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVBW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_G2DW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2W_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBSW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTXBW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRABW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADMW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_ADSW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYXW_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000211B, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256W_AXI128TO256_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXMW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXIW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_IMP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00000001, &axi_qos->qosqon);
+	writel(0x00000005, &axi_qos->qosin);
+
+	axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SY2W_BASE;
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RT_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_SHXW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_DBGW_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002055, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00000000, &axi_qos->qosreqctr);
+	writel(0x00000000, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)RT_AXI_RTW_BASE;
+	writel(0x00002001, &axi_qos->qosctset1);
+	writel(0x00002001, &axi_qos->qosctset2);
+	writel(0x00002001, &axi_qos->qosctset3);
+	writel(0x00000000, &axi_qos->qosthres0);
+	writel(0x00000000, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000000A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002018, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x0000205F, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002008, &axi_qos->qosctset0);
+	writel(0x00002041, &axi_qos->qosctset1);
+	writel(0x00002023, &axi_qos->qosctset2);
+	writel(0x0000200A, &axi_qos->qosctset3);
+	writel(0x00000010, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000102, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002259, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VDCTU1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002046, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_RDRW_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D0, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS01W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS23W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x0000000C, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMS45W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x000000C0, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002069, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC4W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002034, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x000020D3, &axi_qos->qosctset0);
+	writel(0x00000008, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000101, &axi_qos->qosconf);
+	writel(0x00002006, &axi_qos->qosctset0);
+	writel(0x00000018, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000201A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002042, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC0W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC1W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC2W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x0000204C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTCE3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002200, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3R_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_ROTVLC3W_BASE;
+	writel(0x00000100, &axi_qos->qosconf);
+	writel(0x00002455, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002050, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00002014, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* DMS Register(SYS-AXI) */
+	writel(0x00000000, SYS_AXI_AVBDMSCR);
+	writel(0x00000000, SYS_AXI_AX2MDMSCR);
+	writel(0x00000000, SYS_AXI_CC50DMSCR);
+	writel(0x00000000, SYS_AXI_CCIDMSCR);
+	writel(0x00000000, SYS_AXI_CSDMSCR);
+	writel(0x00000000, SYS_AXI_G2DDMSCR);
+	writel(0x00000000, SYS_AXI_IMP1DMSCR);
+	writel(0x00000000, SYS_AXI_LBSMDMSCR);
+	writel(0x00000000, SYS_AXI_MMUDSDMSCR);
+	writel(0x00000000, SYS_AXI_MMUMXDMSCR);
+	writel(0x00000000, SYS_AXI_MMUS0DMSCR);
+	writel(0x00000000, SYS_AXI_MMUS1DMSCR);
+	writel(0x00000000, SYS_AXI_RTMXDMSCR);
+	writel(0x00000000, SYS_AXI_SDM0DMSCR);
+	writel(0x00000000, SYS_AXI_SDM1DMSCR);
+	writel(0x00000000, SYS_AXI_SDS0DMSCR);
+	writel(0x00000000, SYS_AXI_SDS1DMSCR);
+	writel(0x00000000, SYS_AXI_TRABDMSCR);
+	writel(0x00000000, SYS_AXI_X128TO64SLVDMSCR);
+	writel(0x00000000, SYS_AXI_X64TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI_AVBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_AX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_GICSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMPSLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_IMX2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_LBSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_MXTSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_QSAPBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_RTXSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC65SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SAPC8SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_SGXSLV1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STMSLVDMSCR);
+	writel(0x00000000, SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_TSPL2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBDSSLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_UTLBS1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_ROT0DMSCR);
+	writel(0x00000000, SYS_AXI_ROT1DMSCR);
+	writel(0x00000000, SYS_AXI_ROT2DMSCR);
+	writel(0x00000000, SYS_AXI_ROT3DMSCR);
+	writel(0x00000000, SYS_AXI_ROT4DMSCR);
+	writel(0x00000000, SYS_AXI_IMUX3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR0XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR1XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR2XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR3XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4SLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4PSLVDMSCR);
+	writel(0x00000000, SYS_AXI_STBR4XSLVDMSCR);
+	writel(0x00000000, SYS_AXI_ADM_DMSCR);
+	writel(0x00000000, SYS_AXI_ADS_DMSCR);
+
+	/* DMS Register(RT-AXI) */
+	writel(0x00000000, DM_AXI_DMAXICONF);
+	writel(0x00000019, DM_AXI_DMAPBCONF);
+	writel(0x00000000, DM_AXI_DMADMCONF);
+	writel(0x00000000, DM_AXI_DMSDM0CONF);
+	writel(0x00000000, DM_AXI_DMSDM1CONF);
+	writel(0x00000004, DM_AXI_DMQSPAPSLVCONF);
+	writel(0x00000004, DM_AXI_RAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD4SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD5SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD6SLVCONF);
+	writel(0x00000004, DM_AXI_SAPD65DSLVCONF);
+	writel(0x00000004, DM_AXI_SDAP0SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD2SLVCONF);
+	writel(0x00000004, DM_AXI_MAPD3SLVCONF);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVCONF);
+	writel(0x00000100, DM_AXI_DMADMRQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMRQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMRQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMRQOSQON);
+	writel(0x00000005, DM_AXI_DMADMRQOSIN);
+	writel(0x00000000, DM_AXI_DMADMRQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0RQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1RQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1RQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1RQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1RQOSSTAT);
+	writel(0x00002041, DM_AXI_DMRQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMRQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMRQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMRQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMRQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMRQOSTHRES2);
+	writel(0x00000100, DM_AXI_DMADMWQOSCONF);
+	writel(0x0000214C, DM_AXI_DMADMWQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMADMWQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMADMWQOSQON);
+	writel(0x00000005, DM_AXI_DMADMWQOSIN);
+	writel(0x00000000, DM_AXI_DMADMWQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM0WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM0WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM0WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM0WQOSSTAT);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSCONF);
+	writel(0x0000214C, DM_AXI_DMSDM1WQOSCTSET0);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSREQCTR);
+	writel(0x00000001, DM_AXI_DMSDM1WQOSQON);
+	writel(0x00000005, DM_AXI_DMSDM1WQOSIN);
+	writel(0x00000000, DM_AXI_DMSDM1WQOSSTAT);
+	writel(0x00002041, DM_AXI_DMWQOSCTSET1);
+	writel(0x00002023, DM_AXI_DMWQOSCTSET2);
+	writel(0x0000200A, DM_AXI_DMWQOSCTSET3);
+	writel(0x00002050, DM_AXI_DMWQOSTHRES0);
+	writel(0x00002032, DM_AXI_DMWQOSTHRES1);
+	writel(0x00002014, DM_AXI_DMWQOSTHRES2);
+	writel(0x00000000, DM_AXI_RDMDMSCR);
+	writel(0x00000000, DM_AXI_SDM0DMSCR);
+	writel(0x00000000, DM_AXI_SDM1DMSCR);
+	writel(0x00000000, DM_AXI_DMQSPAPSLVDMSCR);
+	writel(0x00000000, DM_AXI_RAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD4SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD5SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD6SLVDMSCR);
+	writel(0x00000000, DM_AXI_SAPD65DSLVDMSCR);
+	writel(0x00000000, DM_AXI_SDAP0SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD2SLVDMSCR);
+	writel(0x00000000, DM_AXI_MAPD3SLVDMSCR);
+	writel(0x00000000, DM_AXI_DMXXDEFAULTSLAVESLVDMSCR);
+	writel(0x00000001, DM_AXI_DMXREGDMSENN);
+
+	/* DMS Register(SYS-AXI256) */
+	writel(0x00000000, SYS_AXI256_SYXDMSCR);
+	writel(0x00000000, SYS_AXI256_MXIDMSCR);
+	writel(0x00000000, SYS_AXI256_X128TO256SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_X256TO128SLVDMSCR);
+	writel(0x00000000, SYS_AXI256_SYXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_CCXSLVDMSCR);
+	writel(0x00000000, SYS_AXI256_S3CSLVDMSCR);
+
+	/* DMS Register(MXT) */
+	writel(0x00000000, MXT_SYXDMSCR);
+	writel(0x00000000, MXT_IMRSLVDMSCR);
+	writel(0x00000000, MXT_VINSLVDMSCR);
+	writel(0x00000000, MXT_VPC1SLVDMSCR);
+	writel(0x00000000, MXT_VSPD0SLVDMSCR);
+	writel(0x00000000, MXT_VSPD1SLVDMSCR);
+	writel(0x00000000, MXT_MAP1SLVDMSCR);
+	writel(0x00000000, MXT_MAP2SLVDMSCR);
+	writel(0x00000000, MXT_MAP2BSLVDMSCR);
+
+	/* DMS Register(MXI) */
+	writel(0x00000002, MXI_JPURDMSCR);
+	writel(0x00000002, MXI_JPUWDMSCR);
+	writel(0x00000002, MXI_VCTU0RDMSCR);
+	writel(0x00000002, MXI_VCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU0RDMSCR);
+	writel(0x00000002, MXI_VDCTU0WDMSCR);
+	writel(0x00000002, MXI_VDCTU1RDMSCR);
+	writel(0x00000002, MXI_VDCTU1WDMSCR);
+	writel(0x00000002, MXI_VIN0WDMSCR);
+	writel(0x00000002, MXI_VIN1WDMSCR);
+	writel(0x00000002, MXI_RDRWDMSCR);
+	writel(0x00000002, MXI_IMS01RDMSCR);
+	writel(0x00000002, MXI_IMS01WDMSCR);
+	writel(0x00000002, MXI_IMS23RDMSCR);
+	writel(0x00000002, MXI_IMS23WDMSCR);
+	writel(0x00000002, MXI_IMS45RDMSCR);
+	writel(0x00000002, MXI_IMS45WDMSCR);
+	writel(0x00000002, MXI_IMRRDMSCR);
+	writel(0x00000002, MXI_IMRWDMSCR);
+	writel(0x00000002, MXI_ROTCE4RDMSCR);
+	writel(0x00000002, MXI_ROTCE4WDMSCR);
+	writel(0x00000002, MXI_ROTVLC4RDMSCR);
+	writel(0x00000002, MXI_ROTVLC4WDMSCR);
+	writel(0x00000002, MXI_VSPD0RDMSCR);
+	writel(0x00000002, MXI_VSPD0WDMSCR);
+	writel(0x00000002, MXI_VSPD1RDMSCR);
+	writel(0x00000002, MXI_VSPD1WDMSCR);
+	writel(0x00000002, MXI_DU0RDMSCR);
+	writel(0x00000002, MXI_DU0WDMSCR);
+	writel(0x00000002, MXI_VSP0RDMSCR);
+	writel(0x00000002, MXI_VSP0WDMSCR);
+	writel(0x00000002, MXI_ROTCE0RDMSCR);
+	writel(0x00000002, MXI_ROTCE0WDMSCR);
+	writel(0x00000002, MXI_ROTVLC0RDMSCR);
+	writel(0x00000002, MXI_ROTVLC0WDMSCR);
+	writel(0x00000002, MXI_ROTCE1RDMSCR);
+	writel(0x00000002, MXI_ROTCE1WDMSCR);
+	writel(0x00000002, MXI_ROTVLC1RDMSCR);
+	writel(0x00000002, MXI_ROTVLC1WDMSCR);
+	writel(0x00000002, MXI_ROTCE2RDMSCR);
+	writel(0x00000002, MXI_ROTCE2WDMSCR);
+	writel(0x00000002, MXI_ROTVLC2RDMSCR);
+	writel(0x00000002, MXI_ROTVLC2WDMSCR);
+	writel(0x00000002, MXI_ROTCE3RDMSCR);
+	writel(0x00000002, MXI_ROTCE3WDMSCR);
+	writel(0x00000002, MXI_ROTVLC3RDMSCR);
+	writel(0x00000002, MXI_ROTVLC3WDMSCR);
+
+	/* DMS Register(CCI-AXI) */
+	writel(0x00000000, CCI_AXI_MMUS0DMSCR);
+	writel(0x00000000, CCI_AXI_SYX2DMSCR);
+	writel(0x00000000, CCI_AXI_MMURDMSCR);
+	writel(0x00000000, CCI_AXI_MMUDSDMSCR);
+	writel(0x00000000, CCI_AXI_MMUMDMSCR);
+	writel(0x00000000, CCI_AXI_MXIDMSCR);
+	writel(0x00000000, CCI_AXI_MMUS1DMSCR);
+	writel(0x00000000, CCI_AXI_MMUMPDMSCR);
+	writel(0x00000000, CCI_AXI_DVMDMSCR);
+	writel(0x00000000, CCI_AXI_CCISLVDMSCR);
+
+	/* CC-AXI Function Register */
+	writel(0x00000011, CCI_AXI_IPMMUIDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMURDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS0DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUS1DVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUMPDVMCR);
+	writel(0x00000011, CCI_AXI_IPMMUDSDVMCR);
+	writel(0x0000F700, CCI_AXI_AX2ADDRMASK);
+
+}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/blanche/qos.h b/board/renesas/blanche/qos.h
new file mode 100644
index 00000000000..e3ecddfd28c
--- /dev/null
+++ b/board/renesas/blanche/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile
index 2dac748efbe..e09ae1e4143 100644
--- a/board/renesas/gose/Makefile
+++ b/board/renesas/gose/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= gose.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= gose.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c
index bace439235b..3a8bf862d5b 100644
--- a/board/renesas/gose/gose.c
+++ b/board/renesas/gose/gose.c
@@ -201,7 +201,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c
index 413ad1124bb..0317ea26c7d 100644
--- a/board/renesas/gose/qos.c
+++ b/board/renesas/gose/qos.c
@@ -13,7 +13,7 @@
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 /* QoS version 0.311 */
 enum {
 	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
@@ -1196,8 +1196,8 @@ void qos_init(void)
 	writel(0x00000001, &axi_qos->qosthres2);
 	writel(0x00000001, &axi_qos->qosqon);
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
index c10bba5682c..15f111c5041 100644
--- a/board/renesas/koelsch/Makefile
+++ b/board/renesas/koelsch/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= koelsch.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= koelsch.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 51e70e222de..b741e2e186c 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -222,7 +222,7 @@ int board_phy_config(struct phy_device *phydev)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
index 8cb2b48f574..16118d72a04 100644
--- a/board/renesas/koelsch/qos.c
+++ b/board/renesas/koelsch/qos.c
@@ -14,7 +14,7 @@
 #include <asm/arch/rmobile.h>
 
 /* QoS version 0.240 for ES1 and version 0.411 for ES2 */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 enum {
 	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
 	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -1384,8 +1384,8 @@ void qos_init(void)
 	writel(0x00000001, &axi_qos->qosthres2);
 	writel(0x00000001, &axi_qos->qosqon);
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
index 8d034611a47..0e44c69fd6a 100644
--- a/board/renesas/lager/Makefile
+++ b/board/renesas/lager/Makefile
@@ -6,4 +6,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= lager.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= lager.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 83260a1c1a4..6fed2f9796b 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -235,7 +235,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
index ae155512f58..25b8d0956a7 100644
--- a/board/renesas/lager/qos.c
+++ b/board/renesas/lager/qos.c
@@ -13,7 +13,7 @@
 #include <asm/arch/rmobile.h>
 
 /* QoS version 0.955 for ES1 and version 0.973 for ES2 */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 enum {
 	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
 	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -2426,8 +2426,8 @@ void qos_init(void)
 	else
 		qos_init_es1();
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/porter/Makefile b/board/renesas/porter/Makefile
index dbf32e9c540..09c07ef5d4a 100644
--- a/board/renesas/porter/Makefile
+++ b/board/renesas/porter/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= porter.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= porter.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c
index b5378defa86..f6467ee2d95 100644
--- a/board/renesas/porter/porter.c
+++ b/board/renesas/porter/porter.c
@@ -203,7 +203,7 @@ int board_phy_config(struct phy_device *phydev)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/porter/qos.c b/board/renesas/porter/qos.c
index 491d1bab86e..6b19c5e29cd 100644
--- a/board/renesas/porter/qos.c
+++ b/board/renesas/porter/qos.c
@@ -15,7 +15,7 @@
 #include <asm/arch/rmobile.h>
 
 /* QoS version 0.240 for ES1 and version 0.334 for ES2 */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 enum {
 	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
 	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -1305,8 +1305,8 @@ void qos_init(void)
 	writel(0x00000001, &axi_qos->qosthres2);
 	writel(0x00000001, &axi_qos->qosqon);
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/rcar-gen2-common/common.c b/board/renesas/rcar-common/common.c
index 0103f42bd5d..33c1726f186 100644
--- a/board/renesas/rcar-gen2-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -1,8 +1,9 @@
 /*
- * board/renesas/rcar-gen2-common/common.c
+ * board/renesas/rcar-common/common.c
  *
  * Copyright (C) 2013 Renesas Electronics Corporation
  * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  *
  * SPDX-License-Identifier: GPL-2.0
  */
@@ -29,7 +30,10 @@ static struct mstp_ctl mstptbl[] = {
 		RMSTPCR4, MSTP4_BITS, CONFIG_RMSTP4_ENA },
 	{ SMSTPCR5, MSTP5_BITS, CONFIG_SMSTP5_ENA,
 		RMSTPCR5, MSTP5_BITS, CONFIG_RMSTP5_ENA },
-	/* No MSTP6 */
+#ifdef CONFIG_RCAR_GEN3
+	{ SMSTPCR6, MSTP6_BITS, CONFIG_SMSTP6_ENA,
+		RMSTPCR6, MSTP6_BITS, CONFIG_RMSTP6_ENA },
+#endif
 	{ SMSTPCR7, MSTP7_BITS, CONFIG_SMSTP7_ENA,
 		RMSTPCR7, MSTP7_BITS, CONFIG_RMSTP7_ENA },
 	{ SMSTPCR8, MSTP8_BITS, CONFIG_SMSTP8_ENA,
@@ -51,9 +55,11 @@ void arch_preboot_os(void)
 
 	/* Stop module clock */
 	for (i = 0; i < ARRAY_SIZE(mstptbl); i++) {
-		mstp_setclrbits_le32(mstptbl[i].s_addr, mstptbl[i].s_dis,
+		mstp_setclrbits_le32((uintptr_t)mstptbl[i].s_addr,
+				     mstptbl[i].s_dis,
 				     mstptbl[i].s_ena);
-		mstp_setclrbits_le32(mstptbl[i].r_addr, mstptbl[i].r_dis,
+		mstp_setclrbits_le32((uintptr_t)mstptbl[i].r_addr,
+				     mstptbl[i].r_dis,
 				     mstptbl[i].r_ena);
 	}
 }
diff --git a/board/renesas/salvator-x/Kconfig b/board/renesas/salvator-x/Kconfig
new file mode 100644
index 00000000000..ed4c479f7ca
--- /dev/null
+++ b/board/renesas/salvator-x/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_SALVATOR_X
+
+config SYS_SOC
+	default "rmobile"
+
+config SYS_BOARD
+	default "salvator-x"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "salvator-x"
+
+endif
diff --git a/board/renesas/salvator-x/MAINTAINERS b/board/renesas/salvator-x/MAINTAINERS
new file mode 100644
index 00000000000..abd05c88e0e
--- /dev/null
+++ b/board/renesas/salvator-x/MAINTAINERS
@@ -0,0 +1,6 @@
+SALVATOR_X BOARD
+M:	Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+S:	Maintained
+F:	board/renesas/salvator-x/
+F:	include/configs/salvator-x.h
+F:	configs/salvator-x_defconfig
diff --git a/board/renesas/salvator-x/Makefile b/board/renesas/salvator-x/Makefile
new file mode 100644
index 00000000000..61b0d063e59
--- /dev/null
+++ b/board/renesas/salvator-x/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/salvator-x/Makefile
+#
+# Copyright (C) 2015 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y	:= salvator-x.o ../rcar-common/common.o
diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
new file mode 100644
index 00000000000..47242c60ddf
--- /dev/null
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -0,0 +1,120 @@
+/*
+ * board/renesas/salvator-x/salvator-x.c
+ *     This file is Salvator-X board support.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <dm.h>
+#include <dm/platform_data/serial_sh.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <asm/arch/rcar-mstp.h>
+#include <i2c.h>
+#include <mmc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CPGWPCR	0xE6150904
+#define CPGWPR  0xE615090C
+
+#define CLK2MHZ(clk)	(clk / 1000 / 1000)
+void s_init(void)
+{
+	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
+	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	writel(0xA5A50000, CPGWPCR);
+	writel(0xFFFFFFFF, CPGWPR);
+}
+
+#define GSX_MSTP112	(1 << 12)	/* 3DG */
+#define TMU0_MSTP125	(1 << 25)	/* secure */
+#define TMU1_MSTP124	(1 << 24)	/* non-secure */
+#define SCIF2_MSTP310	(1 << 10)	/* SCIF2 */
+
+int board_early_init_f(void)
+{
+	/* TMU0,1 */		/* which use ? */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125 | TMU1_MSTP124);
+	/* SCIF2 */
+	mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SCIF2_MSTP310);
+
+	return 0;
+}
+
+/* SYSC */
+/* R/- 32 Power status register 2(3DG) */
+#define	SYSC_PWRSR2	0xE6180100
+/* -/W 32 Power resume control register 2 (3DG) */
+#define	SYSC_PWRONCR2	0xE618010C
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
+
+	/* Init PFC controller */
+	r8a7795_pinmux_init();
+
+	/* GSX: force power and clock supply */
+	writel(0x0000001F, SYSC_PWRONCR2);
+	while (readl(SYSC_PWRSR2) != 0x000003E0)
+		mdelay(20);
+
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, GSX_MSTP112);
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RCAR_BOARD_STRING
+};
+
+#define RST_BASE	0xE6160000
+#define RST_CA57RESCNT	(RST_BASE + 0x40)
+#define RST_CA53RESCNT	(RST_BASE + 0x44)
+#define RST_RSTOUTCR	(RST_BASE + 0x58)
+#define RST_CODE	0xA5A5000F
+
+void reset_cpu(ulong addr)
+{
+	/* only CA57 ? */
+	writel(RST_CODE, RST_CA57RESCNT);
+}
+
+static const struct sh_serial_platdata serial_platdata = {
+	.base = SCIF2_BASE,
+	.type = PORT_SCIF,
+	.clk = 14745600,		/* 0xE10000 */
+	.clk_mode = EXT_CLK,
+};
+
+U_BOOT_DEVICE(salvator_x_scif2) = {
+	.name = "serial_sh",
+	.platdata = &serial_platdata,
+};
diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile
index e6eea6142ec..8916a8d961a 100644
--- a/board/renesas/silk/Makefile
+++ b/board/renesas/silk/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= silk.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= silk.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c
index 4f6e46ce527..f86fd01b67e 100644
--- a/board/renesas/silk/qos.c
+++ b/board/renesas/silk/qos.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>
 #include <asm/arch/rmobile.h>
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 /* QoS version 0.11 */
 
 enum {
@@ -944,8 +944,8 @@ void qos_init(void)
 	writel(0x00000001, &axi_qos->qosthres2);
 	writel(0x00000001, &axi_qos->qosqon);
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c
index 021baabc657..4ec3f92ca37 100644
--- a/board/renesas/silk/silk.c
+++ b/board/renesas/silk/silk.c
@@ -192,7 +192,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 void reset_cpu(ulong addr)
diff --git a/board/renesas/stout/Makefile b/board/renesas/stout/Makefile
index e78f80c3616..cb7c61d0203 100644
--- a/board/renesas/stout/Makefile
+++ b/board/renesas/stout/Makefile
@@ -8,4 +8,4 @@
 # SPDX-License-Identifier: GPL-2.0
 #
 
-obj-y	:= stout.o cpld.o qos.o ../rcar-gen2-common/common.o
+obj-y	:= stout.o cpld.o qos.o ../rcar-common/common.o
diff --git a/board/renesas/stout/qos.c b/board/renesas/stout/qos.c
index d49a0ab72b5..f29c5c99d52 100644
--- a/board/renesas/stout/qos.c
+++ b/board/renesas/stout/qos.c
@@ -15,7 +15,7 @@
 #include <asm/arch/rmobile.h>
 
 /* QoS version 0.955 for ES1 and version 0.973 for ES2 */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 enum {
 	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
 	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -2428,8 +2428,8 @@ void qos_init(void)
 	else
 		qos_init_es1();
 }
-#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
 void qos_init(void)
 {
 }
-#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
+#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */
diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c
index 7df73940915..672a730f074 100644
--- a/board/renesas/stout/stout.c
+++ b/board/renesas/stout/stout.c
@@ -217,7 +217,7 @@ int dram_init(void)
 }
 
 const struct rmobile_sysinfo sysinfo = {
-	CONFIG_RMOBILE_BOARD_STRING
+	CONFIG_ARCH_RMOBILE_BOARD_STRING
 };
 
 static const struct sh_serial_platdata serial_platdata = {
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index 661d5445456..15964c64d8c 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -1,37 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_ALT=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/armadillo-800eva_defconfig b/configs/armadillo-800eva_defconfig
index 9bae3c3efac..3bd4680a28a 100644
--- a/configs/armadillo-800eva_defconfig
+++ b/configs/armadillo-800eva_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
 CONFIG_TARGET_ARMADILLO_800EVA=y
 CONFIG_BOOTDELAY=3
 # CONFIG_CMD_BDI is not set
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
new file mode 100644
index 00000000000..90c888987ed
--- /dev/null
+++ b/configs/blanche_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_BLANCHE=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index f2075fe27db..461f2359f70 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -1,36 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_GOSE=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 217a868230b..665a43259e8 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -1,37 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_KOELSCH=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig
index 00a54416b57..f1ef1c49b30 100644
--- a/configs/kzm9g_defconfig
+++ b/configs/kzm9g_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
 CONFIG_TARGET_KZM9G=y
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="KZM-A9-GT# "
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 19dd1fe27ee..9bc893a1c7b 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -1,36 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_LAGER=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index a587ed5ab2c..acb039d9004 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -1,37 +1,28 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_PORTER=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/salvator-x_defconfig b/configs/salvator-x_defconfig
new file mode 100644
index 00000000000..e16acd3e560
--- /dev/null
+++ b/configs/salvator-x_defconfig
@@ -0,0 +1,12 @@
+CONFIG_ARM=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_RCAR_GEN3=y
+CONFIG_TARGET_SALVATOR_X=y
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index f5d7afde581..65a74f87ddd 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -1,37 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_SILK=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 9073c178755..1a0f09b5542 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -1,36 +1,27 @@
 CONFIG_ARM=y
-CONFIG_RMOBILE=y
+CONFIG_ARCH_RMOBILE=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_STOUT=y
 CONFIG_BOOTDELAY=3
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
+CONFIG_BOOTSTAGE_USER_COUNT=0x20
+CONFIG_BOOTSTAGE_STASH_ADDR=0x0
+CONFIG_BOOTSTAGE_STASH_SIZE=0x4096
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMI is not set
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
-# CONFIG_CMD_FPGA is not set
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_DHCP=y
 CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
-CONFIG_SH_SDHI=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_OF_LIBFDT=y
diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h
index 2f65f9d2640..445465ec487 100644
--- a/drivers/mmc/sh_mmcif.h
+++ b/drivers/mmc/sh_mmcif.h
@@ -196,7 +196,7 @@ struct sh_mmcif_regs {
 #define SOFT_RST_OFF		(0 << 31)
 
 #define CLKDEV_EMMC_DATA	52000000	/* 52MHz */
-#ifdef CONFIG_RMOBILE
+#ifdef CONFIG_ARCH_RMOBILE
 #define MMC_CLK_DIV_MIN(clk)	(clk / (1 << 9))
 #define MMC_CLK_DIV_MAX(clk)	(clk / (1 << 1))
 #else
diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c
index be6aeb1684f..ea82e2b449d 100644
--- a/drivers/mmc/sh_sdhi.c
+++ b/drivers/mmc/sh_sdhi.c
@@ -399,7 +399,6 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
 {
 	unsigned short i, j, cnt = 1;
 	unsigned short resp[8];
-	unsigned long *p1, *p2;
 
 	if (cmd->resp_type & MMC_RSP_136) {
 		cnt = 4;
@@ -418,27 +417,29 @@ static void sh_sdhi_get_response(struct sh_sdhi_host *host, struct mmc_cmd *cmd)
 			resp[i] |= (resp[j--] >> 8) & 0x00ff;
 		}
 		resp[0] = (resp[0] << 8) & 0xff00;
-
-		/* SDHI REGISTER SPECIFICATION */
-		p1 = ((unsigned long *)resp) + 3;
-
 	} else {
 		resp[0] = sh_sdhi_readw(host, SDHI_RSP00);
 		resp[1] = sh_sdhi_readw(host, SDHI_RSP01);
-
-		p1 = ((unsigned long *)resp);
 	}
 
-	p2 = (unsigned long *)cmd->response;
 #if defined(__BIG_ENDIAN_BITFIELD)
-	for (i = 0; i < cnt; i++) {
-		*p2++ = ((*p1 >> 16) & 0x0000ffff) |
-				((*p1 << 16) & 0xffff0000);
-		p1--;
+	if (cnt == 4) {
+		cmd->response[0] = (resp[6] << 16) | resp[7];
+		cmd->response[1] = (resp[4] << 16) | resp[5];
+		cmd->response[2] = (resp[2] << 16) | resp[3];
+		cmd->response[3] = (resp[0] << 16) | resp[1];
+	} else {
+		cmd->response[0] = (resp[0] << 16) | resp[1];
 	}
 #else
-	for (i = 0; i < cnt; i++)
-		*p2++ = *p1--;
+	if (cnt == 4) {
+		cmd->response[0] = (resp[7] << 16) | resp[6];
+		cmd->response[1] = (resp[5] << 16) | resp[4];
+		cmd->response[2] = (resp[3] << 16) | resp[2];
+		cmd->response[3] = (resp[1] << 16) | resp[0];
+	} else {
+		cmd->response[0] = (resp[1] << 16) | resp[0];
+	}
 #endif /* __BIG_ENDIAN_BITFIELD */
 }
 
diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h
index cbc29294355..348f544d0a2 100644
--- a/drivers/serial/serial_sh.h
+++ b/drivers/serial/serial_sh.h
@@ -225,7 +225,8 @@ struct uart_port {
 # define SCIF_ORER 0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x38	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
-	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
+	defined(CONFIG_R8A7792) || defined(CONFIG_R8A7793) || \
+	defined(CONFIG_R8A7794) || defined(CONFIG_R8A7795)
 # if defined(CONFIG_SCIF_A)
 #  define SCIF_ORER	0x0200
 # else
@@ -307,7 +308,7 @@ struct uart_port {
 /* SH7763 SCIF2 support */
 # define SCIF2_RFDC_MASK 0x001f
 # define SCIF2_TXROOM_MAX 16
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 # if defined(CONFIG_SCIF_A)
@@ -565,7 +566,7 @@ SCIF_FNS(SCFCR,  0x18, 16)
 SCIF_FNS(SCFDR,  0x1c, 16)
 SCIF_FNS(SCLSR,  0x24, 16)
 SCIF_FNS(DL,	 0x00,  0) /* dummy */
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 /* SCIFA and SCIF register offsets and size */
 SCIx_FNS(SCSMR,  0,  0, 0x00, 16, 0,  0, 0x00, 16, 0,  0)
@@ -761,7 +762,7 @@ static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 #elif defined(__H8300H__) || defined(__H8300S__)
 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
-#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || defined(CONFIG_R8A7792) || \
 	defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794)
 #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */
  #if defined(CONFIG_SCIF_A)
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 3a81c49b894..9955674afd1 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -12,17 +12,17 @@
 
 #undef DEBUG
 #define CONFIG_R8A7794
-#define CONFIG_RMOBILE_BOARD_STRING "Alt"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0x70000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE6304000
 #endif
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
 #else
 #define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
index 522b2871044..e9cab5c6953 100644
--- a/include/configs/armadillo-800eva.h
+++ b/include/configs/armadillo-800eva.h
@@ -11,7 +11,7 @@
 
 #undef DEBUG
 #define CONFIG_R8A7740
-#define CONFIG_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Armadillo-800EVA Board\n"
 #define CONFIG_SH_GPIO_PFC
 
 #include <asm/arch/rmobile.h>
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
new file mode 100755
index 00000000000..f094bbead61
--- /dev/null
+++ b/include/configs/blanche.h
@@ -0,0 +1,121 @@
+/*
+ * include/configs/blanche.h
+ *     This file is blanche board configuration.
+ *
+ * Copyright (C) 2016 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __BLANCHE_H
+#define __BLANCHE_H
+
+#undef DEBUG
+#define CONFIG_R8A7792
+#define CONFIG_RMOBILE_BOARD_STRING "Blanche"
+
+#include "rcar-gen2-common.h"
+
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE817FFFC
+#define STACK_AREA_SIZE			0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define RCAR_GEN2_SDRAM_BASE		0x40000000
+#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
+#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+
+#define CONFIG_SYS_MEMTEST_START	(RCAR_GEN2_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 504 * 1024 * 1024)
+
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+/* FLASH */
+/* #define CONFIG_SYS_NO_FLASH */	/* uncomment if use QSPI-FLASH */
+#if defined(CONFIG_SYS_NO_FLASH)
+#define CONFIG_SYS_TEXT_BASE	0x40000000
+#define CONFIG_SPI
+#define CONFIG_SH_QSPI
+#define CONFIG_SH_QSPI_BASE	0xE6B10000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+#undef  CONFIG_CMD_SF
+#undef  CONFIG_CMD_SPI
+#endif
+
+/* BLANCHE on board LANC: SMC89218 (ExCS0) */
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X                  1
+#define CONFIG_SMC911X_16_BIT           1
+#define CONFIG_SMC911X_BASE             0x18000000
+
+/* Board Clock */
+#define RMOBILE_XTAL_CLK	20000000u
+#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_SYS_TMU_CLK_DIV	4
+
+/* ENV setting */
+#if defined(CONFIG_SYS_NO_FLASH)
+#else
+#undef  CONFIG_ENV_IS_IN_SPI_FLASH
+#undef  CONFIG_ENV_ADDR
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+#endif
+
+/* USB */
+#undef CONFIG_CMD_USB
+
+#define CONFIG_GENERIC_MMC
+
+/* Module stop status bits */
+/* INTC-RT */
+#define CONFIG_SMSTP0_ENA	0x00400000
+/* SDHI0 */
+#define CONFIG_SMSTP3_ENA	0x00004000
+/* INTC-SYS, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+/* SCIF0 */
+#define CONFIG_SMSTP7_ENA	0x00200000
+/* QSPI */
+#define CONFIG_SMSTP9_ENA	0x00020000
+/* SYS-DMAC0 */
+#define CONFIG_RMSTP2_ENA	0x00080000
+
+/* SDHI */
+#define CONFIG_SH_SDHI_FREQ	97500000
+#define HAVE_BLOCK_DEVICE
+
+#endif	/* __BLANCHE_H */
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 230be3168ab..18eaf25e7bc 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -11,18 +11,18 @@
 
 #undef DEBUG
 #define CONFIG_R8A7793
-#define CONFIG_RMOBILE_BOARD_STRING "Gose"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Gose"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0x70000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE6304000
 #endif
 
 /* STACK */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
 #else
 #define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 121fe3f534f..b98fc298327 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -11,18 +11,18 @@
 
 #undef DEBUG
 #define CONFIG_R8A7791
-#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Koelsch"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0x70000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE6304000
 #endif
 
 /* STACK */
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
 #else
 #define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
index 1b4c7d43889..94f35161594 100644
--- a/include/configs/kzm9g.h
+++ b/include/configs/kzm9g.h
@@ -14,7 +14,7 @@
 
 #define CONFIG_SH73A0
 #define CONFIG_KZM_A9_GT
-#define CONFIG_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING	"KMC KZM-A9-GT"
 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
 
 #include <asm/arch/rmobile.h>
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 9971ad80824..3be1540d13f 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -12,11 +12,11 @@
 
 #undef DEBUG
 #define CONFIG_R8A7790
-#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0xB0000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE8080000
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 929eedee310..e3bf33cc149 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -13,17 +13,17 @@
 
 #undef DEBUG
 #define CONFIG_R8A7791
-#define CONFIG_RMOBILE_BOARD_STRING "Porter"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0x70000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE6304000
 #endif
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
 #else
 #define CONFIG_SYS_INIT_SP_ADDR		0xE633fffC
diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
new file mode 100644
index 00000000000..f9e5f59a52a
--- /dev/null
+++ b/include/configs/rcar-gen3-common.h
@@ -0,0 +1,98 @@
+/*
+ * include/configs/rcar-gen3-common.h
+ *	This file is R-Car Gen3 common configuration file.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __RCAR_GEN3_COMMON_H
+#define __RCAR_GEN3_COMMON_H
+
+#include <asm/arch/rmobile.h>
+
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FDT
+
+#define CONFIG_REMAKE_ELF
+
+/* boot option */
+#define CONFIG_SUPPORT_RAW_INITRD
+
+/* Support File sytems */
+#define CONFIG_FAT_WRITE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_FS_EXT4
+#define CONFIG_EXT4_WRITE
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SH_GPIO_PFC
+
+/* console */
+#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 38400 }
+
+/* MEMORY */
+#define CONFIG_SYS_TEXT_BASE		0x49000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7fff0)
+
+#define CONFIG_SYS_SDRAM_BASE		(0x48000000)
+#define CONFIG_SYS_SDRAM_SIZE		(1024u * 1024 * 1024 - 0x08000000)
+#define CONFIG_SYS_LOAD_ADDR		(0x48080000)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_EXTRA_ENV_SETTINGS	\
+	"fdt_high=0xffffffffffffffff\0"	\
+	"initrd_high=0xffffffffffffffff\0"
+
+#define CONFIG_BOOTARGS	\
+	"console=ttySC0,115200 rw root=/dev/nfs "	\
+	"nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
+
+#define CONFIG_BOOTCOMMAND	\
+	"tftp 0x48080000 Image; " \
+	"tftp 0x48000000 Image-r8a7795-salvator-x.dtb; " \
+	"booti 0x48080000 - 0x48000000"
+
+#endif	/* __RCAR_GEN3_COMMON_H */
diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h
new file mode 100644
index 00000000000..d1d615c8a76
--- /dev/null
+++ b/include/configs/salvator-x.h
@@ -0,0 +1,54 @@
+/*
+ * include/configs/salvator-x.h
+ *     This file is Salvator-X board configuration.
+ *
+ * Copyright (C) 2015 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __SALVATOR_X_H
+#define __SALVATOR_X_H
+
+#undef DEBUG
+
+#define CONFIG_RCAR_BOARD_STRING "Salvator-X"
+
+#include "rcar-gen3-common.h"
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF2
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/* [A] Hyper Flash */
+/* use to RPC(SPI Multi I/O Bus Controller) */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+
+/* Board Clock */
+/* XTAL_CLK : 33.33MHz */
+#define RCAR_XTAL_CLK		33333333u
+#define CONFIG_SYS_CLK_FREQ	RCAR_XTAL_CLK
+/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */
+/* CPclk 16.66MHz, S3D2 133.33MHz                          */
+#define CONFIG_CP_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_SYS_CLK_FREQ * 192 / 2)
+#define CONFIG_S3D2_CLK_FREQ	(266666666u/2)
+
+/* Generic Timer Definitions (use in assembler source) */
+#define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
+
+/* Generic Interrupt Controller Definitions */
+#define CONFIG_GICV2
+#define GICD_BASE	0xF1010000
+#define GICC_BASE	0xF1020000
+
+/* Module stop status bits */
+/* MFIS, SCIF1 */
+#define CONFIG_SMSTP2_ENA	0x00002040
+/* INTC-AP, IRQC */
+#define CONFIG_SMSTP4_ENA	0x00000180
+
+#endif /* __SALVATOR_X_H */
diff --git a/include/configs/silk.h b/include/configs/silk.h
index dca0623485c..8c4ee4f6ad0 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -13,17 +13,17 @@
 
 #undef DEBUG
 #define CONFIG_R8A7794
-#define CONFIG_RMOBILE_BOARD_STRING "Silk"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Silk"
 
 #include "rcar-gen2-common.h"
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0x70000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE6304000
 #endif
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
 #else
 #define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
diff --git a/include/configs/stout.h b/include/configs/stout.h
index d21c3cbdeb2..8833c50b42a 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -14,13 +14,13 @@
 
 #undef DEBUG
 #define CONFIG_R8A7790
-#define CONFIG_RMOBILE_BOARD_STRING "Stout"
+#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Stout"
 
 #include "rcar-gen2-common.h"
 
 /* #define CONFIG_BOARD_LATE_INIT */
 
-#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
 #define CONFIG_SYS_TEXT_BASE	0xB0000000
 #else
 #define CONFIG_SYS_TEXT_BASE	0xE8080000
diff --git a/include/sh_pfc.h b/include/sh_pfc.h
index 7f6548f0651..0692593d515 100644
--- a/include/sh_pfc.h
+++ b/include/sh_pfc.h
@@ -2,6 +2,7 @@
  * SuperH Pin Function Controller Support
  * Copy from Linux kernel. (include/linux/sh_pfc.h)
  *
+ * Copyright (C) 2015 Renesas Electronics Corporation
  * Copyright (c) 2008 Magnus Damm
  *
  * This file is subject to the terms and conditions of the GNU General Public
@@ -135,6 +136,8 @@ int unregister_pinmux(struct pinmux_info *pip);
 #define PORT_ALL(str)	CPU_ALL_PORT(_PORT_ALL, PORT, str)
 #define GPIO_PORT_ALL()	CPU_ALL_PORT(_GPIO_PORT, , unused)
 #define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
+#define GPIO_GFN(str) PINMUX_GPIO(GPIO_GFN_##str, str##_GMARK)
+#define GPIO_IFN(str) PINMUX_GPIO(GPIO_IFN_##str, str##_IMARK)
 
 /* helper macro for pinmux_enum_t */
 #define PORT_DATA_I(nr)	\
diff --git a/include/sh_tmu.h b/include/sh_tmu.h
index 97d578dd55a..aa60c98750a 100644
--- a/include/sh_tmu.h
+++ b/include/sh_tmu.h
@@ -47,7 +47,7 @@ struct tmu_regs {
 };
 #endif /* CONFIG_CPU_SH3 */
 
-#if defined(CONFIG_CPU_SH4) || defined(CONFIG_RMOBILE)
+#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
 struct tmu_regs {
 	u32 reserved;
 	u8  tstr;